Bus data transmission method for connecting CPLD and FPGA and bus

Abstract

The invention provides a bus data transmission method for connecting a CPLD (Complex Programmable Logic Device) and an FPGA (Field Programmable Gate Array) and a bus, which are characterized in that input signals are transmitted in the same channel in a time-division and time-division manner at a main equipment end according to time sequence characteristics of bus transmission, so that the problem of excessive requirements on the number of pins of the CPLD / FPGA in the prior art is solved, and the bus transmission efficiency is improved. Compared with the prior art, the design of the whole system has less demand on CPLD / FPGA IO interface resources, the reduced IO quantity can reach about 67%, the model of a smaller CPLD / FPGA chip can be selected, the area size and the cost of the whole design system are facilitated, and thus the integration level and the flexibility of the system are improved.

Description

Technical Field

[0001] The invention belongs to the field of bus design, and in particular relates to a bus data transmission method and a bus for connecting CPLD and FPGA. Background Art

[0002] In the past few decades, CPLD / FPGA has been widely used as a high-end chip in military industry, aerospace instruments, test equipment and other fields due to its programmability. In recent years, with the development of domestic CPLD / FPGA technology and the continuous introduction of product types, CPLD / FPGA chips will be used by more designers in various products. In order to achieve the flexibility and scalability of the system architecture in the design, the flexibility of the microprocessor and the high-speed and parallel data processing capabilities of FPGA are often used. Therefore, the system product architecture of microprocessor + CPLD + CPLD / FPGA is widely used; usually the EMIF bus of the microprocessor (traditionally collectively referred to as Local bus) is used. Traditional design architectures such as Figure 1 As shown in the figure, the microprocessor communicates with the CPLD, and the CPLD chip is mainly used for system configuration and EMIF bus expansion. Due to the characteristics of the CPLD (limited number of pins and logic resources), there will be many restrictions on the system when there are multiple FPGA architecture designs.

[0003] As FPGA technology continues to develop and processing power increases, system design will gradually become more complex and multifunctional. At the same time, there will be more and more interfaces for external communication, which will require more IO pins of CPLD / FPGA. At the same time, in the design, the chip area of ​​CPLD / FPGA itself, the number of IO interfaces, processing power and cost are often considered comprehensively. The EMIF (traditionally referred to as local bus) bus uses a parallel asynchronous bus to access data, which requires more IO interfaces of FPGA. When there are multiple FPGAs in the system design, the number of IO will increase exponentially, so the number of IO interfaces of CPLD is too high, resulting in too high cost of CPLD or no suitable model available. However, when choosing CPLD / FPGA chip models, the more IO interfaces, the better. Often, the number of IO ports, logic resources and product size of CPLD / FPGA will be considered comprehensively. Reducing the number of IO of CPLD / FPGA and choosing the appropriate CPLD / FPGA chip model are beneficial to the size and cost of the entire design system. Summary of the invention

[0004] The present invention mainly solves the problem of excessive consumption of the number of CPLD IO interfaces and FPGA IO interface resources when designing the bus interface of a system architecture of a microprocessor + CPLD + a single FPGA or multiple FPGAs, and provides a bus data transmission method and a bus for connecting CPLD and FPGA.

[0005] In order to solve the above technical problems, the technical solution adopted is: A bus data transmission method for connecting CPLD and FPGA, wherein one end of the bus is connected to the CPLD as a master device, and the other end is connected to the FPGA as a slave device. At the master device end, the control signal, address signal and data signal in the input signal are transmitted on the same bus channel in time and step according to the timing characteristics, wherein the time and step means that on the same transmission channel, another signal is sent after one to two clock cycles have passed since the previous signal was sent; The slave receives the data on the bus and reads or writes the data signal at the corresponding address according to the read enable or write enable signal in the control signal. The functions of controlling the time division and step division are realized through internal program programming at the CPLD end or the FPGA end respectively.

[0006] Furthermore, multiple FPGAs can be connected at the CPLD end, and the number of interfaces that can be instantiated by the CPLD internal program can be consistent with the number of FPGA devices required by the user.

[0007] Further, the input signal is a parallel signal, including a chip select signal, a write enable signal, a read enable signal, an address and a data signal, and the chip select signal refers to a signal for selecting a corresponding FPGA for connection; When a chip select signal is valid, the input signal sent from the CPLD end is input to the FPGA end corresponding to the corresponding chip select signal in time and steps; When transmitting in time and steps, the read enable signal or the write enable signal and part or all of the address signal are transmitted first; when the address line signal cannot be transmitted in one time, the remaining address signals continue to be transmitted on the same transmission channel; When the address signal transmission is completed, the signal receiving end determines whether the read enable signal or the write enable signal is valid. When the write enable signal is valid, the data signal in the input signal is transmitted to the bus and the data is passed to the slave device and written to the address bit corresponding to the address signal; When the read enable signal is valid, the data on the address bit corresponding to the address signal from the device end is transferred to the bus.

[0008] Furthermore, when the slave device receives a valid read enable signal, it reads data from the address bit corresponding to the address signal, and after the read data is ready, it sends a read data valid signal to the master device, and then sends the read data to the master device.

[0009] Furthermore, a buffer is provided at the master device end and the slave device end respectively, for caching the input signal from the master device end, and then transmitting the input signal from the buffer to the bus in time and step by step; at the slave device end, it is used to cache the received signal and then transmit it from the buffer to the corresponding address of the slave device end, and when the read enable signal is valid, the read data from the slave device end is cached and then written to the bus in steps and transmitted to the master device end.

[0010] Furthermore, the bit width of the bus is selected by the user according to the size and throughput of the data transmission.

[0011] The present invention also provides a bus for connecting CPLD and FPGA, wherein one end of the bus is connected to the CPLD as a master device, and the other end is connected to the FPGA as a slave device. At the signal input end, the control signal, address signal and data signal in the input signal are transmitted on the same bus channel in time and step according to the timing characteristics, wherein the time and step refers to sending another signal on the same bus transmission channel one to two clock cycles after the previous signal is sent; The slave receives the data on the bus and reads or writes the data signal at the corresponding address according to the read enable or write enable signal in the control signal. The functions of controlling the time division and step division are realized through internal program programming at the CPLD end or the FPGA end respectively.

[0012] By adopting the above technical solution, the present invention has the following beneficial effects: The present invention provides a bus data transmission method and bus for connecting CPLD and FPGA. According to the timing characteristics of the bus, the input signal is transmitted in the same transmission channel of the bus by programming at the master device end in time and step, thereby solving the problem of excessive requirements on the number of pins of CPLD / FPGA in the prior art. The design of the entire system makes the CPLD / FPGA require less IO interface resources, and the number of IOs can be reduced by about 67%. A smaller model of CPLD / FPGA chip can be selected, which is beneficial to the area size and cost of the entire design system, thereby improving the integration and flexibility of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a design diagram of the EMIF bus architecture in the prior art; Figure 2It is a schematic diagram of the asynchronous bus address / data line mixed write operation; Figure 3 It is a schematic diagram of the asynchronous bus address / data line mixed read operation; Figure 4 This is a bus design diagram of the present invention. DETAILED DESCRIPTION

[0014] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] In the prior art, the EMIF bus is as follows Figure 1 As shown, its timing characteristics are summarized as follows: EMIF (External Memory Interface) is the abbreviation of DSP or microprocessor external memory interface. Usually, the EMIF data bus width can be 8 bits, 16 bits and 32 bits. It is the interface for processors such as FPGA and DSP to exchange data with external memory. It provides control signals and data transmission signals to control the read and write operations of memory (FPGA registers, etc. are often regarded as memory).

[0016] Introduction to EMIF signals (example): EMIF_ALE: Address latch signal EMIFA_AD[15:0]: 16-bit wide data / address multiplexing signal EMIFA_A[12:0]: 13-bit wide address line EMIFA_BA[1:0]: 2-bit wide padding address line EMIFA_WE: Write enable signal (active low) EMIFA_OE: read enable signal (active low) EMIFA_CS[2:5]: 4 asynchronous memory chip select signals CS2, CS3, CS4, CS5 (4 chip select signals are used as examples, and the chip select signals of each processor are different). Usually each device selects one chip select signal. Users can select different chip select signals for different devices as needed.

[0017] The EMIF signal write timing diagram of a processor is as follows Figure 2 As shown: Write timing: The chip select signal (CSn) first changes from high to low (indicating the start of work), and then the address valid indication signal (ADV_B) changes from high to low to indicate that the address on the address and data multiplexing bus is valid at this time, usually maintaining one clock cycle; at the same time, the write signal (WE_B) changes from high to low to indicate that this is a write operation; after a period of time (usually the time can be configured by the driver), the address becomes valid and the address value is maintained for a period of time (usually the time can be configured by the driver), and the write data value begins to be transmitted on the address / data bus. After waiting for a period of time, the chip select signal and write enable signal become invalid, and a write operation is completed.

[0018] The EMIF signal read timing diagram of a processor is as follows Figure 3 As shown: Read timing: The chip select signal (CSn) first changes from high to low (indicating the start of work), and then the address valid indication signal (ADV_B) changes from high to low to indicate that the address on the address and data multiplexing bus is valid. It lasts for about one clock cycle, and the address valid becomes high, indicating that the read address transmission is completed. After waiting for a period of time (usually the time can be configured by the driver), the read signal (OE_B) changes from high to low to indicate that the read operation has started. At this time, the accessed slave device needs to prepare the data. After the read operation signal is maintained for a period of time, it changes from low to high, indicating that a read operation is completed.

[0019] Processors from different manufacturers or different batches of the same manufacturer may have slight differences in the total number of interface signals for this type of bus, and there may also be some differences in the signal names, but combined with timing analysis, it can be concluded that the final functions are the same, and the main function is to complete the data reading and writing functions; the signal lines that meet the functional requirements of the bus mainly include: chip select signal (CSn), address line signal (ADDR), data line signal (DATA), read and write signal selection signal (or read and write signals are independent) (RWn), read and write enable signal (OE), etc. Therefore, the key signals are mainly chip select signal (CSn), address line signal (ADDR), data line signal (DATA), read and write signal (RWn).

[0020] The characteristic of this type of bus is that it uses too many IOs. It can support synchronous and asynchronous parallel bus processing methods. Usually, asynchronous parallel bus processing methods are used more frequently, and the bus accesses a large amount of data. Regardless of whether the data is read or written, the microprocessor first transmits the address data on the address signal line through some auxiliary signal lines (such as: chip select signal (CSn) or address enable signal (ALE)), waits for a period of time, transmits the read or write control information, and then waits for a period of time to transmit the read or write data information. After the data is maintained for a period of time, the read and write flags, chip select signals and other signals end, and the data will be maintained for a period of time to ensure that the slave end (FPGA) or the master end (microprocessor) can obtain the data correctly and stably.

[0021] According to the above-mentioned characteristics of the EMIF bus, the shortcomings of the bus are improved, and a new bus is proposed that can save IO interface resources without affecting the access efficiency and bandwidth of the bus. It can solve the problem of insufficient FPGA and CPLD IO resources encountered in the design of such systems.

[0022] The technical solution provided by the present invention is described in detail below with reference to the accompanying drawings: Figure 4 A specific embodiment of a bus data transmission method for connecting a CPLD and an FPGA of the present application is shown, wherein one end of the bus is connected to a CPLD as a master device end, and the other end is connected to an FPGA as a slave device end, and at the master device end, a control signal, an address signal, and a data signal in an input signal are transmitted on the same bus channel in time and in steps according to a timing feature, wherein the time and in steps refers to sending another signal on the same transmission channel after a previous signal is sent with an interval of one to two clock cycles; The slave receives the data on the bus and reads or writes the data signal at the corresponding address according to the read enable or write enable signal in the control signal. The functions of controlling the time division and step division are realized through internal program programming at the CPLD end or the FPGA end respectively.

[0023] It can be seen from the previous timing characteristics analysis that in the prior art, the asynchronous parallel bus transmits signals on different signal channels in a time-sharing manner. Therefore, in order to save the number of IO channels, the present application transmits the input signal in a time-sharing and step-by-step manner, and transmits different signals on the same channel in a time-sharing manner, thereby achieving the purpose of saving bit lines.

[0024] In this embodiment, multiple FPGAs can be connected to the CPLD end, and the number of interfaces that can be instantiated by the CPLD internal program can be consistent with the number of FPGA devices required by the user; the corresponding bus width is selected according to the data signal width of the FPGA end to connect the CPLD. In this embodiment, the input signal is a parallel signal, including a chip select signal, a write enable signal, a read enable signal, an address and a data signal, wherein the chip select signal refers to a signal for selecting a corresponding FPGA for connection; when a certain chip select signal is valid, the input signal sent from the CPLD end is input to the FPGA end corresponding to the corresponding chip select signal in time-sharing and step-by-step manner; when transmitting in time-sharing and step-by-step manner, the read enable signal or the write enable signal and part or all of the address signal are transmitted first; when the address line signal cannot be transmitted in one time, the remaining address signals continue to be transmitted on the same transmission channel; when the address signal transmission is completed, the signal receiving end determines whether the read enable signal or the write enable signal is valid, and when the write enable signal is valid, the data signal in the input signal is transmitted to the bus and the data is passed to the slave device end and written to the address bit corresponding to the address signal; when the read enable signal is valid, the data on the address bit corresponding to the address signal of the slave device end is transmitted to the bus.

[0025] In this embodiment, a buffer is provided at the master device end and the slave device end respectively, for caching the input signal from the master device end, and then transmitting the input signal from the buffer to the bus in time and step by step; at the slave device end, it is used to cache the received signal and then transmit it from the buffer to the corresponding address of the slave device end, and when the read enable signal is valid, the read data of the slave device end is cached and then written to the bus in steps and transmitted to the master device end.

[0026] like Figure 4 As shown, multiple FPGAs can be connected to the CPLD end, and the number of interfaces that can be instantiated by the CPLD internal program can be consistent with the number of FPGA devices required by the user; there are as many newly designed buses connected to the CPLD as there are FPGAs from the device end, and which newly designed bus is connected to the CPLD and the FPGA is selected according to the chip select signal. The bit width of the bus is selected by the user according to the size and throughput of the data transmission. In this embodiment, the user can flexibly set the bidirectional data width through parameters. For example, if the data bit of the CPLD end is 32 bits, the user can select the bit width of the bus to be 8 bits or 16 bits according to the size of the data. When 8 bits are selected, 4 clock cycles are required for transmission, and when 16 bits are selected, two clock cycles are required for transmission.

[0027] In this embodiment, when the read enable signal is received from the slave device as valid, data is read from the address bit corresponding to the address signal, and after the read data is ready, a read data valid signal is sent to the master device, and then the read data is sent to the master device. Since the feedback time required for the read data from different slave devices may be inconsistent when reading data from the slave device, a bus read data valid signal is added in this embodiment to indicate that the data is valid when the mark reads data, and to provide an indication to the master device to prevent the master device from waiting all the time, to prevent the master device from freezing and data loss between devices. The new bus designed in this embodiment can make the data more efficient and stable during communication, thereby reducing the resource usage of the number of IO interfaces of CPLD (master device end) and FPGA (slave device end), saving costs.

[0028] If the CPLD data interface is 32 bits and the newly designed bus is 16 bits when the signal is input, or the CPLD data interface is 16 bits and the newly designed bus is 8 bits, because the data transmitted through the bus must be divided into two steps to obtain the data of the write operation, after the slave device end, when the write enable signal is valid, the data of the write operation is written to the address bit corresponding to the address signal in the input signal on the slave device end. When the read enable signal is valid, it is necessary to read the data from the corresponding address bit on the slave device end. After the read data is ready, first send a read data valid signal to the master device end, and then write the read data into the bus step by step according to the data length and transmit it to the master device end.

[0029] In this embodiment, the data transmission process is specifically as follows: 1. First, the parallel input signals are processed through the timing circuit. The input signals include chip select valid signal (cs_n), write valid signal (wr_n), read valid signal (rd_n), address (address), and write data (write_data). On the master device side, the input signal is first cached, and then the signal is programmed to be transmitted in time and step by step on the master device side; 2. According to the chip select signal, select the slave device corresponding to the chip select signal and connect it using the newly designed bus.

[0030] 3. Transmit the read enable signal or write enable signal and part (such as the upper 16-bit part of the address data line) or all of the address signal; when the address line signal cannot be transmitted in one go, continue to transmit the remaining address signals (such as the remaining lower 16-bit address line data) on the same transmission channel; if the new bus is designed to be 16 bits, it only needs to be completed in one step. If the new bus is designed to be 8 bits, the address signal needs to be written into the bus in two steps.

[0031] 4. When the address line data transmission is completed, determine whether the read enable or write enable signal is valid. When the write enable signal is valid, the data signal in the input signal is transferred to the bus in steps and the data is transferred to the address bit corresponding to the write address signal from the device end; if the data interface of the CPLD at the master device end is 32, the newly designed bus is designed to be 16 bits; if the data interface of the CPLD at the master device end is 16, the newly designed bus is designed to be 8 bits, both of which require two steps to transmit the data signal; if the data interface of the CPLD at the master device end is 8 bits, the newly designed bus is also 8 bits, only one step of data signal transmission is required; 5. When the read enable signal is valid, read the data at the address bit corresponding to the address signal of the slave device. When the read data is ready, cache the data at the address bit corresponding to the address signal of the slave device, send a read data valid signal to the master device, and then transfer the read data to the bus in steps. Also, according to the number of bits of the data interface of the slave device and the number of bits of the newly designed bus, choose how many steps to write the read data to the bus and transmit it to the master device.

[0032] The present invention analyzes the timing characteristics of bus transmission, and transmits the input signal on the same channel in time and step by step through internal program control at the master device end, thereby reducing the bit width of the bus, making full use of the rich logic resources of FPGA and CPLD, reducing the demand for chip IO pins, and reducing the overall area of ​​the chip, thereby saving hardware resources. The bandwidth requirements for all data reading and writing are met, and the bandwidth resources of the bus are effectively utilized, maintaining efficient performance.

[0033] The present invention also provides a bus for connecting CPLD and FPGA, wherein one end of the bus is connected to the CPLD as a master device, and the other end is connected to the FPGA as a slave device. At the signal input end, the control signal, address signal and data signal in the input signal are transmitted on the same bus channel in time and step according to the timing characteristics, wherein the time and step refers to sending another signal on the same bus transmission channel one to two clock cycles after the previous signal is sent; The slave receives the data on the bus and reads or writes the data signal at the corresponding address according to the read enable or write enable signal in the control signal. The functions of controlling the time division and step division are realized through internal program programming at the CPLD end or the FPGA end respectively.

[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A bus data transmission method for connecting CPLD and FPGA, wherein one end of the bus is connected to the CPLD as a master device, and the other end is connected to the FPGA as a slave device, characterized in that: At the master device end, the control signal, address signal and data signal in the input signal are transmitted on the same bus channel in time and step according to the timing characteristics, wherein the time and step means that on the same transmission channel, another signal is sent after one to two clock cycles have passed since the previous signal was sent; The slave receives the data on the bus and reads or writes the data signal at the corresponding address according to the read enable or write enable signal in the control signal. The functions of controlling the time division and step division are realized through internal program programming at the CPLD end or the FPGA end respectively.

2. A bus data transmission method for connecting CPLD and FPGA according to claim 1, characterized in that: Multiple FPGAs can be connected on the CPLD side, and the number of interfaces that can be instantiated by the CPLD internal program can be consistent with the number of FPGA devices required by the user.

3. A bus data transmission method for connecting CPLD and FPGA according to claim 2, characterized in that: The input signal is a parallel signal, including a chip select signal, a write enable signal, a read enable signal, an address and a data signal, wherein the chip select signal refers to a signal for selecting a corresponding FPGA for connection; When a chip select signal is valid, the input signal sent from the CPLD end is input to the FPGA end corresponding to the corresponding chip select signal in time and steps; When transmitting in time and steps, the read enable signal or the write enable signal and part or all of the address signal are transmitted first; when the address line signal cannot be transmitted in one time, the remaining address signals continue to be transmitted on the same transmission channel; When the address signal transmission is completed, the signal receiving end determines whether the read enable signal or the write enable signal is valid. When the write enable signal is valid, the data signal in the master device is transmitted to the bus and the data is passed to the slave device to be written to the corresponding address; When the read enable signal is valid, the data corresponding to the address from the device end is transferred to the bus.

4. A bus data transmission method for connecting CPLD and FPGA according to claim 3, characterized in that: When the read enable signal is received as valid from the slave device, data is read from the address bit corresponding to the address signal. After the read data is ready, a read data valid signal is sent to the master device, and then the read data is written to the bus and sent to the master device.

5. A bus data transmission method for connecting CPLD and FPGA according to claim 4, characterized in that: A buffer is provided at the master device end and the slave device end respectively, for buffering the input signal from the master device end, and then transmitting the input signal from the buffer to the bus in time and step; The slave device is used to cache the received signal and then transmit it from the buffer to the corresponding address of the slave device. When the read enable signal is valid, the read data from the slave device is cached and then written into the bus in steps and transmitted to the master device.

6. A bus data transmission method for connecting CPLD and FPGA according to any one of claims 1 to 5, characterized in that: The bus width is selected by the user based on the size and throughput of the data to be transferred.

7. A bus for connecting CPLD and FPGA, wherein one end of the bus is connected to the CPLD as a master device, and the other end is connected to the FPGA as a slave device, characterized in that: At the master device end, the control signal, address signal and data signal in the input signal are transmitted on the same bus channel in time and step according to the timing characteristics, wherein the time and step means that on the same bus transmission channel, another signal is sent after one to two clock cycles after the previous signal is sent; The slave receives the data on the bus and reads or writes the data signal at the corresponding address according to the read enable or write enable signal in the control signal. The functions of controlling the time division and step division are realized through internal program programming at the CPLD end or the FPGA end respectively.

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