Pixel driving circuit, control method and display panel
By setting specific transistors in the pulse amplitude modulation and pulse width modulation modules of the pixel driving circuit for threshold compensation, the problem of poor uniformity in direct display of low grayscale in MLED is solved, and a more uniform in-plane luminescence effect is achieved.
Patent Information
- Application Number
- CN202510172784.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-17
- Publication Date
- 2025-04-04
AI Technical Summary
MLED direct display has the problem of poor uniformity in low grayscale, and hybrid drive technology still finds it difficult to completely solve the problem of uneven in-plane light emission.
A pixel driving circuit is designed to provide threshold compensation to the second transistor by setting a fifth transistor in the pulse amplitude modulation module, and a ninth transistor and tenth transistor in the pulse width modulation module to provide threshold compensation to the seventh transistor, so that when the pixel driving circuit drives the light emitting tube, the current flowing through the driving tube is independent of its own threshold voltage.
The uniformity of in-plane luminescence is effectively improved, and the problem of in-plane luminescence unevenness caused by changes in the threshold voltage of the drive tube is prevented.
Smart Images
Figure CN119763486A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of display technology, and in particular to a pixel driving circuit, a control method and a display panel. Background Art
[0002] With the development of display technology, MLED (Mini / Micro LED) display technology has emerged. However, MLED direct display has the problem of poor low grayscale uniformity. In related technologies, a hybrid driving technology using pulse amplitude modulation (PAM) and pulse width modulation (PWM) has emerged to solve the problem of poor low grayscale uniformity. However, due to the in-plane performance differences caused by the process, and the changes in the threshold voltage of the in-plane driving transistor with long-term driving, it will still cause uneven light emission in the plane. Summary of the invention
[0003] Based on this, it is necessary to provide a pixel driving circuit, a control method and a display panel that can improve the uniformity of light emission in order to solve the above technical problems.
[0004] In a first aspect, the present application proposes a pixel driving circuit, comprising: a pulse amplitude modulation module, a pulse width modulation module and a switch module, wherein:
[0005] The pulse amplitude modulation module includes: a first transistor, a first end of the first transistor is used to receive a data signal, a second end of the first transistor is connected to a first node, and a control end of the first transistor is used to receive a pulse amplitude modulation signal; a second transistor, a control end of the second transistor is connected to a second node, a first end of the second transistor is used to receive a power supply voltage, and a second end of the second transistor is connected to a ground end; a third transistor, a first end of the third transistor is used to receive the data signal, a second end of the third transistor is connected to the second node, and a control end of the third transistor is used to receive a reset signal; a fourth transistor, a first end of the fourth transistor is used to receive a zero point voltage, a second end of the fourth transistor is connected to the first node, and a control end of the fourth transistor is used to receive a hold signal; a fifth transistor, a first end of the fifth transistor is connected to the second node, a second end of the fifth transistor is used to receive a power supply voltage, and a control end of the fifth transistor is used to receive a compensation signal; a first storage unit, a first end of the first storage unit is connected to the first node, and a second end of the first storage unit is connected to the second node; a second storage unit, a first end of the second storage unit is connected to the second node, and a second end of the second storage unit is connected to the ground end;
[0006] The pulse width modulation module includes: a sixth transistor, a first end of the sixth transistor is used to receive the data signal, a second end of the sixth transistor is connected to the third node, and a control end of the sixth transistor is used to receive the pulse width modulation signal; a seventh transistor, a control end of the seventh transistor is connected to the fourth node, a first end of the seventh transistor is connected to the second node, and a second end of the seventh transistor is used to receive the zero point voltage; an eighth transistor, a first end of the eighth transistor is used to receive the data signal, a second end of the eighth transistor is connected to the fourth node, and a control end of the eighth transistor is used to receive the reset signal; a ninth transistor, a first end of the ninth transistor is used to receive the zero point voltage, a second end of the ninth transistor is connected to the third node, and a control end of the ninth transistor is used to receive the compensation signal; a tenth transistor, a first end of the tenth transistor is connected to the second node, a second end of the tenth transistor is connected to the fourth node, and a control end of the tenth transistor is used to receive the compensation signal; a third storage unit, a first end of the third storage unit is connected to the third node, and a second end of the third storage unit is connected to the fourth node; a fourth storage unit, a first end of the fourth storage unit is connected to the third node, and a second end of the fourth storage unit is used to receive the scan signal;
[0007] The switch module includes: an eleventh transistor, a first end of the eleventh transistor is used to receive the power supply voltage, a second end of the eleventh transistor is connected to the first end of the second transistor, and a control end of the eleventh transistor is used to receive a switch signal; a twelfth transistor, a first end of the twelfth transistor is connected to the second node, a second end of the twelfth transistor is connected to the first end of the seventh transistor, and a control end of the twelfth transistor is used to receive the switch signal.
[0008] In one embodiment, the first storage unit includes: a first capacitor, and the second storage unit includes: a second capacitor, a first end of the first capacitor is connected to the first node, a second end of the first capacitor is connected to the second node, a first end of the second capacitor is connected to the second node, and a second end of the second capacitor is connected to the ground.
[0009] In one embodiment, the third storage unit includes: a third capacitor, and the fourth storage unit includes: a fourth capacitor, the first end of the third capacitor is connected to the third node, the second end of the third capacitor is connected to the fourth node, the first end of the fourth capacitor is connected to the third node, and the second end of the fourth capacitor is used to receive the scan signal.
[0010] In a second aspect, the present application further proposes a control method for a pixel driving circuit, which is applied to the pixel driving circuit described in the embodiment of the first aspect, and the method includes:
[0011] Obtain a control signal and control the working state of the pixel driving circuit based on the control signal; wherein the control signal includes: a data signal, a pulse amplitude modulation signal, a reset signal, a hold signal, a compensation signal, a pulse width modulation signal, a scanning signal, and a switch signal; the working state includes: a voltage reset stage, a compensation stage, a writing stage, and a light-emitting stage.
[0012] In one of the embodiments, in the voltage reset stage, the third transistor and the eighth transistor are controlled to be turned on for a first preset time based on the reset signal, the fourth transistor is controlled to be turned on based on the hold signal, and the first potential signal is written through the data signal;
[0013] The first transistor is turned off based on the pulse amplitude modulation signal, the sixth transistor is turned off based on the pulse width modulation signal, the fifth transistor, the ninth transistor and the tenth transistor are turned off based on the compensation signal, and the eleventh transistor and the twelfth transistor are turned off based on the switch signal.
[0014] In one embodiment, in the compensation stage, the fifth transistor, the ninth transistor and the tenth transistor are controlled to be turned on for a second preset time length based on the compensation signal, and the fourth transistor is controlled to be turned on for the second preset time length based on the holding signal;
[0015] The first transistor is turned off based on the pulse amplitude modulation signal, the sixth transistor is turned off based on the pulse width modulation signal, the third transistor and the eighth transistor are turned off based on the reset signal, and the eleventh transistor and the twelfth transistor are turned off based on the switch signal.
[0016] In one of the embodiments, in the compensation stage, the voltage difference between the second node and the first node is set to a first threshold, and the voltage difference between the third node and the fourth node is set to a second threshold; wherein the first threshold is the sum of the ground voltage and the threshold voltage of the second transistor, and the second threshold is the sum of the zero point voltage and the threshold voltage of the seventh transistor.
[0017] In one of the embodiments, the writing phase includes: a pulse width writing phase and a pulse amplitude writing phase;
[0018] In the pulse width writing phase, the sixth transistor is controlled to be turned on for a third preset time length based on the pulse width modulation signal, and a pulse width potential signal is written through the data signal, and the fourth storage unit is charged through the scanning signal, and the first transistor is controlled to be turned off based on the pulse amplitude modulation signal;
[0019] In the pulse amplitude writing stage, the first transistor is controlled to be turned on for a fourth preset time length based on the pulse amplitude modulation signal, and the pulse amplitude potential signal is written through the data signal, and the fourth storage unit is discharged through the scanning signal, and the sixth transistor is controlled to be turned off based on the pulse width modulation signal;
[0020] In the pulse width writing stage and the pulse amplitude writing stage, the third transistor and the eighth transistor are controlled to be turned off based on the reset signal, the fifth transistor, the ninth transistor and the tenth transistor are controlled to be turned off based on the compensation signal, the fourth transistor is controlled to be turned off based on the hold signal, and the eleventh transistor and the twelfth transistor are controlled to be turned off based on the switch signal.
[0021] In one of the embodiments, in the light emitting stage, the fourth storage unit is charged at a preset rate by the scanning signal, and the eleventh transistor and the twelfth transistor are controlled to turn on based on the switch signal;
[0022] The first transistor is controlled to be turned off based on the pulse amplitude modulation signal, the sixth transistor is controlled to be turned off based on the pulse width modulation signal, the third transistor and the eighth transistor are controlled to be turned off based on the reset signal, the fifth transistor, the ninth transistor and the tenth transistor are controlled to be turned off based on the compensation signal, and the fourth transistor is controlled to be turned off based on the hold signal.
[0023] In a third aspect, the present application further proposes a display panel, comprising a plurality of pixel driving circuits, wherein the pixel driving circuits are the pixel driving circuits described in the embodiment of the first aspect.
[0024] The pixel driving circuit, control method and display panel perform threshold compensation on the second transistor, i.e., the driving tube, by setting the fifth transistor in the pulse amplitude modulation module, and perform threshold compensation on the seventh transistor, i.e., the pull-down tube, by setting the ninth transistor and the tenth transistor in the pulse width modulation module, so that when the pixel driving circuit drives the light-emitting tube to emit light, the current flowing through the driving tube (the second transistor) has nothing to do with its own threshold voltage, thereby preventing the problem of uneven light emission within the surface caused by the change of the threshold voltage of the driving tube, and improving the uniformity of the light emission within the surface. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0026] Figure 1is a circuit diagram of a pixel driving circuit in one embodiment;
[0027] Figure 2 is a timing diagram of a control signal in one embodiment;
[0028] Figure 3 A schematic diagram of transistor switching in a voltage resetting stage in one embodiment;
[0029] Figure 4 A schematic diagram of turning on and off a transistor in a compensation stage in an embodiment;
[0030] Figure 5 A schematic diagram of turning on and off a transistor in a writing phase in one embodiment;
[0031] Figure 6 FIG. 1 is a schematic diagram of the on-off state of a transistor in a light-emitting stage in an embodiment.
[0032] Description of reference numerals:
[0033] A pulse amplitude modulation module 110 and a pulse width modulation module 120 . DETAILED DESCRIPTION
[0034] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.
[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0036] It can be understood that the terms "first", "second", etc. used in the present application can be used in this article to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element.
[0037] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.
[0038] In one embodiment, Figure 1As shown, a pixel driving circuit is provided, comprising: a pulse amplitude modulation module 110, a pulse width modulation module 120 and a switch module, wherein:
[0039] The pulse amplitude modulation module 110 includes: a first transistor T1, a first end of the first transistor T1 is used to receive a data signal Data, a second end of the first transistor T1 is connected to a first node P1, and a control end of the first transistor T1 is used to receive a pulse amplitude modulation signal SPAM; a second transistor T2, a control end of the second transistor T2 is connected to a second node P2, a first end of the second transistor T2 is used to receive a power supply voltage VDD, and a second end of the second transistor T2 is connected to a ground terminal VSS; a third transistor T3, a first end of the third transistor T3 is used to receive a data signal Data, a second end of the third transistor T3 is connected to a second node P2, and a control end of the third transistor T3 is used to receive a reset signal Res; Four transistors T4, the first end of the fourth transistor T4 is used to receive the zero-point voltage V0, the second end of the fourth transistor T4 is connected to the first node P1, and the control end of the fourth transistor T4 is used to receive the hold signal Hold; the fifth transistor T5, the first end of the fifth transistor T5 is connected to the second node P2, the second end of the fifth transistor T5 is used to receive the power supply voltage VDD, and the control end of the fifth transistor T5 is used to receive the compensation signal Comp; the first storage unit, the first end of the first storage unit is connected to the first node P1, and the second end of the first storage unit is connected to the second node P2; the second storage unit, the first end of the second storage unit is connected to the second node P2, and the second end of the second storage unit is connected to the ground terminal VSS.
[0040] The pulse width modulation module 120 includes: a sixth transistor T6, a first end of the sixth transistor T6 is used to receive the data signal Data, a second end of the sixth transistor T6 is connected to the third node P3, and a control end of the sixth transistor T6 is used to receive the pulse width modulation signal SPWM; a seventh transistor T7, a control end of the seventh transistor T7 is connected to the fourth node P4, a first end of the seventh transistor T7 is connected to the second node P2, and a second end of the seventh transistor T7 is used to receive the zero point voltage V0; an eighth transistor T8, a first end of the eighth transistor T8 is used to receive the data signal Data, a second end of the eighth transistor T8 is connected to the fourth node P4, and a control end of the eighth transistor T8 is used to receive the reset signal Res; a ninth transistor T9, a first end of the ninth transistor T9 is used to receive the zero-point voltage V0, a second end of the ninth transistor T9 is connected to the third node P3, and a control end of the ninth transistor T9 is used to receive the compensation signal Comp; a tenth transistor T10, a first end of the tenth transistor T10 is connected to the second node P2, a second end of the tenth transistor T10 is connected to the fourth node P4, and a control end of the tenth transistor T10 is used to receive the compensation signal Comp; a third storage unit, a first end of the third storage unit is connected to the third node P3, and a second end of the third storage unit is connected to the fourth node P4; a fourth storage unit, a first end of the fourth storage unit is connected to the third node P3, and a second end of the fourth storage unit is used to receive a scan signal Sweep.
[0041] The switch module includes: an eleventh transistor T11, a first end of the eleventh transistor T11 is used to receive a power supply voltage VDD, a second end of the eleventh transistor T11 is connected to a first end of the second transistor T2, and a control end of the eleventh transistor T11 is used to receive a switch signal EM; a twelfth transistor T12, a first end of the twelfth transistor T12 is connected to a second node P2, a second end of the twelfth transistor T12 is connected to a first end of the seventh transistor T7, and a control end of the twelfth transistor T12 is used to receive a switch signal EM.
[0042] It is understandable that the first storage unit, the second storage unit, the third storage unit and the fourth storage unit can be composed of one or more capacitors and can be set according to specific needs. The above pixel driving circuit performs threshold compensation on the second transistor T2, that is, the driving tube, by setting the fifth transistor T5 in the pulse amplitude modulation module 110, and performs threshold compensation on the seventh transistor T7, that is, the pull-down tube, by setting the ninth transistor T9 and the tenth transistor T10 in the pulse width modulation module 120, so that when the pixel driving circuit drives the light-emitting tube to emit light, the current flowing through the driving tube (the second transistor T2) has nothing to do with its own threshold voltage, thereby preventing the problem of uneven light emission in the plane caused by the change of the threshold voltage of the driving tube, and improving the uniformity of the light emission in the plane.
[0043] In one embodiment, Figure 1 As shown, the first storage unit includes: a first capacitor C1, and the second storage unit includes: a second capacitor C2, the first end of the first capacitor C1 is connected to the first node P1, the second end of the first capacitor C1 is connected to the second node P2, the first end of the second capacitor C2 is connected to the second node P2, and the second end of the second capacitor C2 is connected to the ground terminal VSS.
[0044] In one embodiment, Figure 1 As shown, the third storage unit includes: a third capacitor C3, and the fourth storage unit includes: a fourth capacitor C4. The first end of the third capacitor C3 is connected to the third node P3, the second end of the third capacitor C3 is connected to the fourth node P4, the first end of the fourth capacitor C4 is connected to the third node P3, and the second end of the fourth capacitor C4 is used to receive the scan signal Sweep.
[0045] In one embodiment, the present application also proposes a control method for a pixel driving circuit, which is illustrated by taking its application in the above-mentioned pixel driving circuit as an example. The control method includes: obtaining a control signal and controlling the working state of the pixel driving circuit based on the control signal; wherein the control signal includes: a data signal Data, a pulse amplitude modulation signal SPAM, a reset signal Res, a hold signal Hold, a compensation signal Comp, a pulse width modulation signal SPWM, a scanning signal Sweep, and a switching signal EM; the working states include: a voltage reset stage, a compensation stage, a writing stage, and a light-emitting stage.
[0046] Specifically, in the present embodiment, the opening or closing of transistors in the pixel driving circuit is controlled by controlling a plurality of different types of signals in the control signal, so that the pixel driving circuit is in different working states, and the threshold compensation is performed on the second transistor T2, i.e., the driving tube, by setting the fifth transistor T5 in the pulse amplitude modulation module 110, and the threshold compensation is performed on the seventh transistor T7, i.e., the pull-down tube, by setting the ninth transistor T9 and the tenth transistor T10 in the pulse width modulation module 120, so that when the pixel driving circuit drives the light-emitting tube to emit light, the current flowing through the driving tube (the second transistor T2) has nothing to do with its own threshold voltage, thereby preventing the problem of uneven light emission in the plane caused by the change of the threshold voltage of the driving tube, and improving the uniformity of the light emission in the plane.
[0047] In one embodiment, Figure 2 FIG. 1 is a signal timing diagram of a control signal in an embodiment, wherein the transistor in the pixel driving circuit is turned on when the control terminal receives a high level VGH, and is turned off when the control terminal receives a low level VGL. This control method can be used to control the working state of the pixel driving circuit, thereby completing the threshold compensation of the second transistor T2 and the seventh transistor T7.
[0048] In one embodiment, Figure 2 As shown, in the voltage reset stage, that is, the Reset stage in the figure, the third transistor T3 and the eighth transistor T8 are controlled to be turned on for a first preset time based on the reset signal Res, the fourth transistor T4 is controlled to be turned on based on the hold signal Hold, and the first potential signal Data_0 is written through the data signal Data; the first transistor T1 is controlled to be turned off based on the pulse amplitude modulation signal SPAM, the sixth transistor T6 is controlled to be turned off based on the pulse width modulation signal SPWM, the fifth transistor T5, the ninth transistor T9 and the tenth transistor T10 are controlled to be turned off based on the compensation signal Comp, and the eleventh transistor T11 and the twelfth transistor T12 are controlled to be turned off based on the switch signal EM.
[0049] Specifically, in this embodiment, Figure 3 As shown, when the reset signal Res and the hold signal Hold are at the high level VGH, the other control signals are at the low level VGL. At this time, the third transistor T3, the fourth transistor T4, and the eighth transistor T8 are turned on, the second node P2 is written with the first potential signal Data_0 through the third transistor T3, the fourth node P4 is written with the first potential signal Data_0 through the eighth transistor T8, and the first node P1 is written with the zero point voltage V0 through the fourth transistor T4, that is, 0V. At this time, the second transistor T2 and the seventh transistor T7 are turned on.
[0050] In one embodiment, Figure 2 As shown, in the compensation stage, that is, the Compensation stage in the figure, the fifth transistor T5, the ninth transistor T9 and the tenth transistor T10 are controlled to be turned on for the second preset time length based on the compensation signal Comp, and the fourth transistor T4 is controlled to be turned on for the second preset time length based on the hold signal Hold; the first transistor T1 is controlled to be turned off based on the pulse amplitude modulation signal SPAM, the sixth transistor T6 is controlled to be turned off based on the pulse width modulation signal SPWM, the third transistor T3 and the eighth transistor T8 are controlled to be turned off based on the reset signal Res, and the eleventh transistor T11 and the twelfth transistor T12 are controlled to be turned off based on the switch signal EM.
[0051] In one embodiment, in the compensation stage, the voltage difference between the second node P2 and the first node P1 is set to a first threshold, and the voltage difference between the third node P3 and the fourth node P4 is set to a second threshold; wherein the first threshold is the sum of the ground terminal VSS voltage and the threshold voltage of the second transistor T2, and the second threshold is the sum of the zero point voltage V0 and the threshold voltage of the seventh transistor T7.
[0052] Specifically, in this embodiment, Figure 4As shown, when the compensation signal Comp and the hold signal Hold are at the high level VGH, the fifth transistor T5, the ninth transistor T9, the tenth transistor T10 and the fourth transistor T4 are turned on. For the pulse amplitude modulation module 110, the voltage of the second node P2 is pulled down by the ground terminal VSS until the voltage VP2 of the second node P2=VSS+Vth_T2, wherein Vth_T2 is the threshold voltage of the second transistor T2. At this time, the voltage compensation of the second transistor T2 is completed, and the voltage of the first node P1 is maintained at the zero point voltage V0 when the fourth transistor T4 is turned on, that is, 0V. At this time, the voltage difference between the second node P2 and the first node P1 is the first threshold, that is, the sum of the ground terminal VSS voltage and the threshold voltage of the second transistor T2. For the pulse width modulation module 120, the fourth node P4 is pulled down by the zero point voltage V0 until the voltage VP4 of the fourth node P4=V0+Vth_T7, wherein Vth_T7 is the threshold voltage of the seventh transistor T7. At this time, the voltage compensation of the seventh transistor T7 is completed, and the voltage of the third node P3 is kept at the zero point voltage V0 when the ninth transistor T9 is turned on, that is, 0V. At this time, the voltage difference between the third node P3 and the fourth node P4 is the second threshold value, that is, the sum of the zero point voltage V0 and the threshold voltage of the seventh transistor T7. When the zero point voltage V0 is 0, the voltage difference between the third node P3 and the fourth node P4 is the threshold voltage Vth_T7 of the seventh transistor T7.
[0053] In one embodiment, Figure 2 As shown, the writing stage, i.e., the Writing stage in the figure, includes: a pulse width writing stage and a pulse amplitude writing stage; in the pulse width writing stage, the sixth transistor T6 is controlled to be turned on for a third preset time length based on the pulse width modulation signal SPWM, and the pulse width potential signal VPWM is written through the data signal Data, and the fourth storage unit is charged through the scanning signal Sweep, and the first transistor T1 is controlled to be turned off based on the pulse amplitude modulation signal SPAM; in the pulse amplitude writing stage, the first transistor T1 is controlled to be turned on for a fourth preset time length based on the pulse amplitude modulation signal SPAM, and the pulse amplitude potential signal VPAM is written through the data signal Data, and the fourth storage unit is discharged through the scanning signal Sweep, and the sixth transistor T6 is controlled to be turned off based on the pulse width modulation signal SPWM; in the pulse width writing stage and the pulse amplitude writing stage, the third transistor T3 and the eighth transistor T8 are controlled to be turned off based on the reset signal Res, the fifth transistor T5, the ninth transistor T9 and the tenth transistor T10 are controlled to be turned off based on the compensation signal Comp, the fourth transistor T4 is controlled to be turned off based on the hold signal Hold, and the eleventh transistor T11 and the twelfth transistor T12 are controlled to be turned off based on the switch signal EM.
[0054] Specifically, in this embodiment, Figure 5As shown, in the pulse width writing stage, when the pulse width modulation signal SPWM is at a high level VGH, the sixth transistor T6 is turned on. Since the data signal Data is written into the pulse width potential signal VPWM at this time, the voltage VP3 of the third node P3 is VPWM. At this time, the scanning signal Sweep charges the fourth storage unit, that is, the fourth capacitor C4, so that the voltage at the second end of the fourth capacitor C4 is Vsweep_0. Therefore, the voltage difference between the fourth storage unit, that is, the fourth capacitor C4, is VPWM-Vsweep_0. At this time, the voltage VP4 of the fourth node P4 is VPWM+Vth_T7. After the third preset time duration, the pulse width modulation signal SPWM becomes a low level VGL, and the sixth transistor T6 is turned off. Then the pulse amplitude modulation signal SPAM becomes a high level VGH, and the first transistor T1 is turned on. Since the data signal Data is written into the pulse amplitude potential signal VPAM at this time, the voltage VP1 of the first node P1 is VPAM, and the voltage VP2 of the second node P2 is raised to VP2=C1*VPAM / (C1+C2)+Vth_T2+VSS.
[0055] In one embodiment, in the light emitting stage, i.e., the Emitting stage in the figure, the fourth storage unit is charged at a preset rate through the scanning signal Sweep, and the eleventh transistor T11 and the twelfth transistor T12 are controlled to be turned on based on the switching signal EM; the first transistor T1 is controlled to be turned off based on the pulse amplitude modulation signal SPAM, the sixth transistor T6 is controlled to be turned off based on the pulse width modulation signal SPWM, the third transistor T3 and the eighth transistor T8 are controlled to be turned off based on the reset signal Res, the fifth transistor T5, the ninth transistor T9 and the tenth transistor T10 are controlled to be turned off based on the compensation signal Comp, and the fourth transistor T4 is controlled to be turned off based on the hold signal Hold.
[0056] Specifically, in this embodiment, Figure 6 As shown, in the light-emitting stage, the switch signal EM is at a high level VGH, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the current can flow through the light-emitting tube. At the same time, the current flows through the second transistor T2, and the power supply voltage is a high voltage, so that the second transistor T2 works in the saturation region. According to the saturation current formula of the transistor, the current I flowing through the second transistor T2 at this time is as follows:
[0057]
[0058] Among them, V g =VP2=C1*VPAM / (C1+C2)+Vth_T2+VSS, =VSS, then the current I flowing through the second transistor T2 is as follows:
[0059]
[0060] It can be seen from the above formula that the current I flowing through the second transistor T2 is independent of the threshold voltage Vth_T2 of the second transistor T2. When the threshold voltage of the second transistor T2 changes, the driving current does not change, thereby avoiding the problem of uneven in-plane luminescence caused by the change of the threshold voltage of the driving tube and improving the uniformity of the in-plane luminescence.
[0061] Since the scan signal Sweep charges the fourth storage unit at a preset rate, the voltage of the fourth node P4 will be gradually raised at this time. When the voltage of the fourth node P4 rises to a level that can turn on the seventh transistor T7, the voltage of the second node P2 will be pulled down to the zero point voltage V0 through the seventh transistor T7, thereby turning off the second transistor T2 and ending the light emission.
[0062] In one embodiment, the present application further proposes a display panel, including a plurality of pixel driving circuits, the pixel driving circuits being the pixel driving circuits in the above embodiment. Specifically, each pixel driving circuit is used to drive a light-emitting tube to emit light, and for each pixel driving circuit, a fifth transistor T5 is set in the pulse amplitude modulation module 110 to perform threshold compensation on the second transistor T2, i.e., the driving tube, and a ninth transistor T9 and a tenth transistor T10 are set in the pulse width modulation module 120 to perform threshold compensation on the seventh transistor T7, i.e., the pull-down tube, so that when the pixel driving circuit drives the light-emitting tube to emit light, the current flowing through the driving tube (the second transistor T2) has nothing to do with its own threshold voltage, thereby preventing the problem of uneven in-plane light emission caused by the change in the threshold voltage of the driving tube, and improving the uniformity of in-plane light emission.
[0063] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "specific embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
[0064] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0065] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.
Claims
1. A pixel driving circuit, characterized in that: include: A pulse amplitude modulation module, a pulse width modulation module and a switch module, wherein: The pulse amplitude modulation module includes: a first transistor, a first end of the first transistor is used to receive a data signal, a second end of the first transistor is connected to a first node, and a control end of the first transistor is used to receive a pulse amplitude modulation signal; a second transistor, a control end of the second transistor is connected to a second node, a first end of the second transistor is used to receive a power supply voltage, and a second end of the second transistor is connected to a ground end; a third transistor, a first end of the third transistor is used to receive the data signal, a second end of the third transistor is connected to the second node, and a control end of the third transistor is used to receive a reset signal; a fourth transistor, a first end of the fourth transistor is used to receive a zero point voltage, a second end of the fourth transistor is connected to the first node, and a control end of the fourth transistor is used to receive a hold signal; a fifth transistor, a first end of the fifth transistor is connected to the second node, a second end of the fifth transistor is used to receive a power supply voltage, and a control end of the fifth transistor is used to receive a compensation signal; a first storage unit, a first end of the first storage unit is connected to the first node, and a second end of the first storage unit is connected to the second node; a second storage unit, a first end of the second storage unit is connected to the second node, and a second end of the second storage unit is connected to the ground end; The pulse width modulation module includes: a sixth transistor, a first end of the sixth transistor is used to receive the data signal, a second end of the sixth transistor is connected to the third node, and a control end of the sixth transistor is used to receive the pulse width modulation signal; a seventh transistor, a control end of the seventh transistor is connected to the fourth node, a first end of the seventh transistor is connected to the second node, and a second end of the seventh transistor is used to receive the zero point voltage; an eighth transistor, a first end of the eighth transistor is used to receive the data signal, a second end of the eighth transistor is connected to the fourth node, and a control end of the eighth transistor is used to receive the reset signal; a ninth transistor, a first end of the ninth transistor is used to receive the zero point voltage, a second end of the ninth transistor is connected to the third node, and a control end of the ninth transistor is used to receive the compensation signal; a tenth transistor, a first end of the tenth transistor is connected to the second node, a second end of the tenth transistor is connected to the fourth node, and a control end of the tenth transistor is used to receive the compensation signal; a third storage unit, a first end of the third storage unit is connected to the third node, and a second end of the third storage unit is connected to the fourth node; a fourth storage unit, a first end of the fourth storage unit is connected to the third node, and a second end of the fourth storage unit is used to receive the scan signal; The switch module includes: an eleventh transistor, a first end of the eleventh transistor is used to receive the power supply voltage, a second end of the eleventh transistor is connected to the first end of the second transistor, and a control end of the eleventh transistor is used to receive a switch signal; a twelfth transistor, a first end of the twelfth transistor is connected to the second node, a second end of the twelfth transistor is connected to the first end of the seventh transistor, and a control end of the twelfth transistor is used to receive the switch signal.
2. The pixel driving circuit according to claim 1, characterized in that: The first storage unit includes: a first capacitor, and the second storage unit includes: a second capacitor, wherein the first end of the first capacitor is connected to the first node, the second end of the first capacitor is connected to the second node, the first end of the second capacitor is connected to the second node, and the second end of the second capacitor is connected to the ground.
3. The pixel driving circuit according to claim 1, characterized in that: The third storage unit includes: a third capacitor, and the fourth storage unit includes: a fourth capacitor, the first end of the third capacitor is connected to the third node, the second end of the third capacitor is connected to the fourth node, the first end of the fourth capacitor is connected to the third node, and the second end of the fourth capacitor is used to receive the scan signal.
4. A control method for a pixel driving circuit, characterized in that: Applied to the pixel driving circuit according to any one of claims 1 to 3, the method comprises: Obtain a control signal and control the working state of the pixel driving circuit based on the control signal; wherein the control signal includes: a data signal, a pulse amplitude modulation signal, a reset signal, a hold signal, a compensation signal, a pulse width modulation signal, a scanning signal, and a switch signal; the working state includes: a voltage reset stage, a compensation stage, a writing stage, and a light-emitting stage.
5. The control method of the pixel driving circuit according to claim 4, characterized in that: In the voltage reset phase, the third transistor and the eighth transistor are controlled to be turned on for a first preset time based on the reset signal, the fourth transistor is controlled to be turned on based on the hold signal, and the first potential signal is written through the data signal; The first transistor is turned off based on the pulse amplitude modulation signal, the sixth transistor is turned off based on the pulse width modulation signal, the fifth transistor, the ninth transistor and the tenth transistor are turned off based on the compensation signal, and the eleventh transistor and the twelfth transistor are turned off based on the switch signal.
6. The control method of the pixel driving circuit according to claim 4, characterized in that: In the compensation stage, the fifth transistor, the ninth transistor and the tenth transistor are controlled to be turned on for a second preset time length based on the compensation signal, and the fourth transistor is controlled to be turned on for the second preset time length based on the holding signal; The first transistor is turned off based on the pulse amplitude modulation signal, the sixth transistor is turned off based on the pulse width modulation signal, the third transistor and the eighth transistor are turned off based on the reset signal, and the eleventh transistor and the twelfth transistor are turned off based on the switch signal.
7. The control method of the pixel driving circuit according to claim 6, characterized in that: In the compensation stage, the voltage difference between the second node and the first node is set to a first threshold, and the voltage difference between the third node and the fourth node is set to a second threshold; wherein the first threshold is the sum of the ground voltage and the threshold voltage of the second transistor, and the second threshold is the sum of the zero point voltage and the threshold voltage of the seventh transistor.
8. The control method of the pixel driving circuit according to claim 4, characterized in that: The writing stage includes: a pulse width writing stage and a pulse amplitude writing stage; In the pulse width writing phase, the sixth transistor is controlled to be turned on for a third preset time length based on the pulse width modulation signal, and a pulse width potential signal is written through the data signal, and the fourth storage unit is charged through the scanning signal, and the first transistor is controlled to be turned off based on the pulse amplitude modulation signal; In the pulse amplitude writing stage, the first transistor is controlled to be turned on for a fourth preset time length based on the pulse amplitude modulation signal, and the pulse amplitude potential signal is written through the data signal, and the fourth storage unit is discharged through the scanning signal, and the sixth transistor is controlled to be turned off based on the pulse width modulation signal; In the pulse width writing stage and the pulse amplitude writing stage, the third transistor and the eighth transistor are controlled to be turned off based on the reset signal, the fifth transistor, the ninth transistor and the tenth transistor are controlled to be turned off based on the compensation signal, the fourth transistor is controlled to be turned off based on the hold signal, and the eleventh transistor and the twelfth transistor are controlled to be turned off based on the switch signal.
9. The control method of the pixel driving circuit according to claim 4, characterized in that: In the light emitting stage, the fourth storage unit is charged at a preset rate by the scanning signal, and the eleventh transistor and the twelfth transistor are controlled to turn on based on the switch signal; The first transistor is controlled to be turned off based on the pulse amplitude modulation signal, the sixth transistor is controlled to be turned off based on the pulse width modulation signal, the third transistor and the eighth transistor are controlled to be turned off based on the reset signal, the fifth transistor, the ninth transistor and the tenth transistor are controlled to be turned off based on the compensation signal, and the fourth transistor is controlled to be turned off based on the hold signal.
10. A display panel, characterized in that: The invention comprises a plurality of pixel driving circuits, wherein the pixel driving circuit is the pixel driving circuit according to any one of claims 1 to 3.