Gate driving circuit, gate driving circuit control method and display panel

Abstract

This application provides a gate driving circuit, a control method for the gate driving circuit, and a display panel. The gate driving circuit includes multiple cascaded shift registers. Each shift register includes a bidirectional selector, a latch, and a shift register unit connected in sequence. The latch includes a latching structure, a first switching module, and a second switching module electrically connected. A first scan signal output from a first scan line connected to the latching structure is used to control the voltage of a first node. The voltage of the first node controls the gate control signal of the shift register by controlling the on / off state of the first switching module. A second scan signal output from a second scan line connected to the second switching module controls the connection or disconnection of the shift register of the current stage with shift registers of other stages by controlling the on / off state of the second switching module. This gate driving circuit can realize the on / off state of any shift register on the display panel, thereby reducing the power consumption of the shift register.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a gate driving circuit, a control method for the gate driving circuit, and a display panel. Background Technology

[0002] When existing displays show only a portion of the screen, one area displays a black image while the other displays a normal image. In this case, all the drive circuits of the shift register units will be activated, meaning that the gate output signal terminals of all the shift register units will be turned on one by one. The power consumption of the drive circuits of the shift register units is relatively high. Summary of the Invention

[0003] The main objective of this application is to provide a gate driving circuit, a control method for the gate driving circuit, and a display panel, so as to at least solve the problem in the prior art where all the driving circuits of the shift register units work when the display screen only displays a part of the area, resulting in high power consumption.

[0004] To achieve the above objectives, according to one aspect of this application, a gate driving circuit is provided, comprising a plurality of cascaded shift registers that sequentially output gate control signals via gate control lines. Each shift register includes a bidirectional selector, a latch, and a shift register unit connected in sequence. The latch includes a latch structure, a first switching module, and a second switching module electrically connected. The control terminal of the latch structure is connected to a first scan line, and a first scan signal output by the first scan line is used to control the voltage of a first node, which is a node where the latch structure is connected to the first switching module. The voltage of the first node is used to control the gate control signal output by the shift register by controlling the on / off state of the first switching module. The shift register unit is electrically connected to the first switching module. The control terminal of the second switching module is connected to a second scan line, and a second scan signal output by the second scan line is used to control the connection or disconnection of the shift register of the current stage with shift registers of other stages by controlling the on / off state of the second switching module. The bidirectional selector is electrically connected to the second switching module.

[0005] According to another aspect of this application, a control method for a gate driving circuit is provided. The method is used to control any type of gate driving circuit. The method includes: generating a set of driving signals, the set of driving signals including multiple level signals, the multiple level signals including a first scan signal and a second scan signal; applying the first scan signal to a latch structure to control the voltage of a first node, and controlling the on / off state of a first switching module by controlling the voltage of the first node, thereby controlling the gate control signal output by the shift register; applying the second scan signal to a second switching module to control the connection or disconnection of the shift register of the current stage with shift registers of other stages by controlling the on / off state of the second switching module.

[0006] According to another aspect of this application, a display panel is provided, comprising: any of the gate driving circuits described above; a first scan signal generator configured to generate a first scan signal; and a second scan signal generator configured to generate a second scan signal.

[0007] Applying the technical solution of this application, the aforementioned gate driving circuit includes multiple cascaded shift registers. Each shift register includes a bidirectional selector, a latch, and a shift register unit connected in sequence. The latch includes a latching structure, a first switching module, and a second switching module electrically connected. The first scan signal output from the first scan line connected to the latching structure controls the voltage of the first node. The voltage of the first node controls the gate control signal of the shift register by controlling the on / off state of the first switching module. The second scan signal output from the second scan line connected to the second switching module controls the connection or disconnection of the shift register of the current stage with shift registers of other stages by controlling the on / off state of the second switching module. This gate driving circuit adds a latch to each shift register. Through the control signal line, the shift register unit can be triggered from any stage, thereby enabling the opening or closing of any stage of the shift register. When the screen displays a normal image area, the shift register unit operates, and the shift register is turned on and off sequentially. When the screen displays a black image area, the shift register unit does not operate, and the gate control signal is not output, thereby reducing the power consumption of the shift register unit. This solves the problem in the prior art where all the drive circuits of the shift register units operate when the screen only displays a part of the area, resulting in high power consumption. Attached Figure Description

[0008] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0009] Figure 1A schematic diagram of the first display area and the second display area in the display panel is shown;

[0010] Figure 2 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown;

[0011] Figure 3 A schematic diagram of a latching structure according to an embodiment of this application is shown;

[0012] Figure 4 A schematic diagram of another latching structure provided according to an embodiment of this application is shown;

[0013] Figure 5 A schematic diagram of another latching structure provided according to an embodiment of this application is shown;

[0014] Figure 6 A schematic diagram of another gate drive circuit provided according to an embodiment of this application is shown;

[0015] Figure 7 A schematic diagram of another gate drive circuit provided according to an embodiment of this application is shown;

[0016] Figure 8 A schematic flowchart of a control method for a gate drive circuit according to an embodiment of this application is shown.

[0017] Figure 9 The embodiments provided in this application are illustrated. Figure 1 (a) Timing diagram of each signal in the gate drive circuit during the first frame scan;

[0018] Figure 10 The embodiments provided in this application are illustrated. Figure 1 (a) Timing diagram of each signal in the gate drive circuit during the second frame scan;

[0019] Figure 11 The embodiments provided in this application are illustrated. Figure 1 (b) Timing diagram of each signal in the gate drive circuit during the first frame scan;

[0020] Figure 12 The embodiments provided in this application are illustrated. Figure 1 (b) Timing diagram of each signal in the gate drive circuit during the second frame scan;

[0021] Figure 13 The embodiments provided in this application are illustrated. Figure 1 (c) Timing diagram of each signal in the gate drive circuit during scanning;

[0022] Figure 14 A schematic diagram of another gate drive circuit provided according to an embodiment of this application is shown;

[0023] Figure 15 The embodiments provided in this application are illustrated. Figure 1 (d) Timing diagram of each signal in the gate drive circuit during the second frame scan;

[0024] Figure 16 A schematic diagram of the structure of a display panel provided according to an embodiment of this application is shown.

[0025] The above figures include the following reference numerals:

[0026] 01. Bidirectional selector; 02. Latch; 10. Latch structure; 11. First inverter; 12. First switching unit; 121. Third switching module; 122. Fourth switching module; 13. Latch substructure; 131. Second inverter; 132. Third inverter; 20. First switching module; 30. Second switching module; 03. Shift register unit; 04. Abnormal power failure controller; 05. Output buffer; M1. First transistor; M2. Second transistor; M3. Third transistor; M4. Fourth transistor; M5. Fifth transistor; M6. Sixth transistor; M7. Seventh transistor; M8. Eighth transistor; M9. First switching device; M10. Second switching device. Detailed Implementation

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] As described in the background section, Figure 1 This is a schematic diagram of the first and second display areas in the display panel, as shown below. Figure 1 As shown, the first display area is the area that displays a black image, and the second display area is the area that displays a normal image. When only part of the screen displays a normal image, all shift registers will be working, that is, all gate control signals will be turned on one by one, and the power consumption of the shift registers will be relatively large.

[0031] To address the problem in the prior art where all the drive circuits of the shift register units operate when only a portion of the display screen is shown, resulting in high power consumption, embodiments of this application provide a gate drive circuit, a control method for the gate drive circuit, and a display panel.

[0032] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0033] This application provides a gate driving circuit including multiple cascaded shift registers that sequentially output gate control signals via gate control lines. A bidirectional selector, also known as a bidirectional multiplexer or bidirectional switch, is an electronic circuit component that selectively connects or disconnects signal paths in two directions. It allows data or signals to flow bidirectionally between two different points, i.e., it can select from input A to output B, or from input B to output A. In this application, when the bidirectional selection switch is activated, the gate driving circuit is described by scanning from top to bottom, and will not be repeated in the subsequent description. A shift register unit is an electronic circuit component that moves data signals according to a specified direction and timing under the drive of a clock signal. In display technologies such as liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs), shift register units are used to generate row-by-row or column-by-column scan signals to control the refresh of display pixels. A latch is a basic digital circuit unit used to store one bit of binary digital information. In this solution, the latch is used to latch the signal of the first node N1. Figure 2 This is a schematic diagram of a gate driving circuit according to an embodiment of this application, as shown below. Figure 2 As shown,

[0034] This application provides a gate driving circuit, which includes multiple cascaded shift registers. Each shift register includes a bidirectional selector 01, a latch 02, and a shift register unit 03 connected in sequence. The latch 02 includes a latch structure 10, a first switch module 20, and a second switch module 30 electrically connected. The control terminal of the latch structure 10 is connected to a first scan line. The first scan signal select1 output by the first scan line is used to control the voltage of a first node N1. The first node N1 is a node where the latch structure 10 is connected to the first switch module 20. The voltage of the first node N1 is used to control the gate control signal Gout output by the shift register by controlling the conduction or disconnection of the first switch module 20. The shift register unit 03 is electrically connected to the first switch module 20. The control terminal of the second switch module 30 is connected to a second scan line. The second scan signal select2 output by the second scan line is used to control the connection or disconnection of the shift register of the current stage with the shift register of other stages by controlling the conduction or disconnection of the second switch module 30. The bidirectional selector 01 is electrically connected to the second switch module 30.

[0035] The gate driving circuit provided in this application, during normal operation, i.e. during frame scanning, after the first-stage shift register receives the second initial scan signal STV, it sequentially transmits signals through the bidirectional selector, latch, and shift register unit of the first-stage shift register to output the gate control signal, and transmits the first-stage gate control signal to the next-stage shift register for step-by-step scanning.

[0036] When you want to disable the previous shift registers and start working from a specific shift register, firstly, in the previous frame, control the first scan signal select1 to be high to transmit the high-level signal to the first node N1. Then, use a latch structure to latch the first node N1 of the shift register at that level to a high level. When the first node N1 is high, the first switch module 20 is turned on. Then, during the current frame scan, set STV to low. Since STV remains low, no initial scan signal is provided to the first-level shift register unit, so the gate drive circuit will not scan normally. At this time, because the first node N1 of that level is high, the high-level signal of the first initial scan signal STV' is provided to the shift register unit of that level, and the gate control signal will start scanning from that level. When you want to stop scanning at any level, control the high / low level of the second scan signal select2 to disconnect the connection between the upper and lower level shift registers. At this time, the shift register unit in the next level shift register will not receive the trigger signal from the previous level, thus stopping the subsequent gate control signal scanning. The technical solution of this application includes a gate driving circuit comprising multiple cascaded shift registers. Each shift register includes a bidirectional selector, a latch, and a shift register unit connected in sequence. The latch includes a latching structure, a first switching module, and a second switching module electrically connected. A first scan signal output from a first scan line connected to the latching structure controls the voltage of a first node. The voltage of the first node controls the gate control signal of the shift register by controlling the on / off state of the first switching module. A second scan signal output from a second scan line connected to the second switching module controls the connection or disconnection of the shift register of the current stage with shift registers of other stages by controlling the on / off state of the second switching module. This gate driving circuit adds a latch to each shift register. By controlling the signals of the relevant signal lines, the shift register unit can be triggered from any stage, thereby enabling or disabling any stage of the shift register.

[0037] In the normally black mode, i.e., when there is no gate drive signal input, the display panel displays a black screen. In the normally white mode, i.e., when there is no gate drive signal input, the display panel displays a white screen. This application describes the display panel in normally black mode. In the area displaying a normal image, the shift register unit operates, and the shift register is sequentially opened and closed; in the area displaying a black image, the shift register unit does not operate, and the gate control signal is not output, thereby reducing the power consumption of the shift register unit and solving the problem in the prior art where all the drive circuits of the shift register units operate when the display screen only displays a partial area, resulting in high power consumption.

[0038] In this embodiment, each shift register stage is equipped with a latch. By controlling the high and low levels of at least the first scan signal select1 and the second scan signal select2, the shift register unit can be triggered from any stage in the display panel, thereby enabling the opening or closing of any stage of the shift register.

[0039] Figure 1 A schematic diagram of a first display area and a second display area in a display panel is shown. In the embodiment, in the second display area where a normal image is displayed, the shift register unit is working, and the gate control signal is output step by step, and the corresponding gate line is turned on step by step; in the first display area where a black image is displayed, the shift register unit is not working, and the gate control signal is not output, thereby achieving the purpose of reducing the power consumption of the shift register. Figure 1 The document illustrates four embodiments of display panel screens, wherein... Figure 1 (a) Display a black screen in the upper half of the display panel (i.e., the rows corresponding to the first n-1 shift registers), and a normal screen in the lower half of the display panel (i.e., the rows corresponding to shift registers after the nth shift register). Figure 1 (b) Display a black screen in the upper area of ​​the display panel (i.e., the rows corresponding to the first n-1 shift registers), a normal screen in the middle area of ​​the display panel (i.e., the rows corresponding to the nth to mth shift registers), and a black screen in the lower area of ​​the display panel (i.e., the rows corresponding to the shift registers from the (m+1)th shift register onwards). Figure 1 (c) Display a normal image in the upper half of the display panel (i.e., the rows corresponding to the first m shift registers), and display a black image in the lower half of the display panel (i.e., the rows corresponding to the shift registers after the (m+1)th shift register). Figure 1 (d) The upper area of ​​the display panel (i.e., the rows corresponding to the first m shift registers) displays a normal image, the middle area of ​​the display panel (i.e., the rows corresponding to the (m+1)th to (n-1)th shift registers) displays a black image, and the lower area of ​​the display panel (i.e., the rows corresponding to the shift registers after the nth shift register) displays a normal image.

[0040] It should be noted that in this application, the first initial scan signal STV' is a high-level signal, and the second initial scan signal STV, the first scan signal select1, and the second scan signal select2 are all high-level signals. The application also describes the signal as having a high-level output from the shift register. Of course, these signals could also be low-level signals. This application only describes the signal as having a high-level signal, with the first initial scan signal STV', the second initial scan signal STV, the first scan signal select1, and the second scan signal select2 all having a high-level output from the shift register.

[0041] Additionally, the gate control signal Gout (high or low level) is provided to the gate line of the corresponding row. Generally, when Gout is high, the corresponding row driving transistor is turned on, and the data signal is applied to the pixel of that row. Gout can also be output as a low-level signal; in this case, the row driving transistor is not turned on. Of course, if the driving transistor is a P-type transistor, it will be turned on when Gout is low and off when it is high. This application describes the situation with Gout outputting a high level as the effective level.

[0042] Optional, Figure 9 The embodiments provided in this application are illustrated. Figure 1 (a) Timing diagram of each signal in the gate drive circuit during the first frame scan in case ; Reference Figure 1 , Figure 2 and Figure 9 When the display panel screen is Figure 1In the case of the display in (a), the first display area, i.e., the first n-1 rows of the display panel, displays a black screen, and the second display area, i.e., the normal screen starts from the nth row. That is, the first n-1 levels are set to display a black screen, i.e., the first n-1 levels of the shift register are not working, and the nth level starts to display a normal screen. During the first frame scan, the shift register scans normally. That is, the second initial scan signal STV first gives a high-level signal to the first-level shift register, driving the first-level shift register to scan normally. The gate control signal will output a high-level gate control signal from beginning to end, so that the corresponding row drive transistor is turned on, so that the data signal can be written. During the first frame scan, the second scan signal select2 is always high, ensuring that the second switch module 30 is always on, and ensuring that the shift register outputs the gate control signal Gout in sequence from level 1 to level n-1. Simultaneously, when the first frame signal scans to level n-1, the output of level n-1 shift register unit 03 is high, and the high-level signal is used as the input signal of the level n shift register. At this time, the first scan signal select1 is pulled high, and the output of the level n latch will be set high. At the same time, the first initial scan signal STV' is set high. When the output of the level n latch is high, the signal (ln) of the first node N1 of the level n shift register is high. When the signal (ln) of the first node N1 is high, the first switch module 20 is turned on, and the high level of the first initial scan signal STV' is input to the shift register unit 03. Before the gate control signal of the (n-1)th stage is pulled low, the first scan signal select1 is pulled low first. At this time, due to the action of latch structure 10, the signal (ln) of the first node N1 of the nth stage shift register will always be latched at a high level, while the potential of the first node N1 of the latch 02 of other shift registers is latched at a low level (e.g., ln+1, ln+2, where ln+1 is the signal of the first node N1 of the (n+1)th stage shift register, and ln+2 is the signal of the first node N1 of the (n+2)th stage shift register). Furthermore, when the gate control signal of the (n-1)th stage is pulled low, the first initial scan signal STV' is pulled low synchronously to ensure that the signal input to the shift register unit 03 of other stages is at a low level, preventing leakage of other shift registers that may be caused when the first initial scan signal STV' is at a high level.

[0043] Figure 10 For the embodiments provided in this application Figure 1 (a) Timing diagram of each signal in the gate drive circuit during the second frame scan, refer to Figure 1 , Figure 2 and Figure 10During the second frame scan, the second initial scan signal STV remains low, meaning it does not provide a drive signal to the first-stage shift register. Therefore, shift registers from the first stage to the (n-1)th stage are inactive, thus reducing the power consumption of the shift register unit. When the normal timing signal is used to scan to the (n-1)th stage, the first initial scan signal STV' becomes high. Since the signal (ln) of the first node N1 of the nth-stage shift register is always latched high, the high-level signal of the first initial scan signal STV' is transmitted through the first switching module 20 of the nth-stage shift register to the shift register unit 03 of the nth-stage shift register, triggering the shift register unit 03 of the nth stage. Furthermore, when scanning to the nth level shift register according to the normal timing signal, the second scan signal select2 is adjusted to a high level and applied to the second switch module 30 to control the second switch module 30 to conduct, thereby controlling the connection between the nth level shift register and the (n+1)th level shift register, so as to realize the shift register scanning step by step from the nth level.

[0044] In addition, such as Figure 9 As shown, both CLK and XCLK signals are clock signals used to control data shifting operations. Inputting the CLK signal to the odd-level shift register and the XCLK signal to the even-level shift register enables asynchronous operation of the shift registers, ensuring the correct generation and output of the scan signal.

[0045] Figure 11 For the embodiments provided in this application Figure 1 (b) Timing diagram of each signal in the gate drive circuit during the first frame scan. Figure 12 For the embodiments provided in this application Figure 1 (b) Timing diagram of each signal in the gate drive circuit during the second frame scan, as follows: Figure 2 , Figure 11 , Figure 12 As shown, when the display panel screen is Figure 1 In the case of displaying the image as shown in (b), the first n-1 rows of the display panel display a black image, rows n to m display a normal image, and rows m+1 onwards display a black image. That is, the process of controlling the first n-1 rows of the display panel to display a black image and then displaying a normal image starting from row n is the same as when the display panel image is... Figure 1In the case of the displayed image in (a), the process of controlling the first n-1 rows of the display panel to display a black image, and then displaying a normal image from the nth row onwards, is the same. However, to control the display of a black image after the (m+1)th row, it is only necessary to, based on the steps, during the second frame scan, when the gate control signal scans to the mth level, that is, before the mth level gate control signal starts outputting, change the second scan signal select2 control signal from high level to low level. Similarly, the (m+1)th level shift register unit will not be triggered, that is, the gate control signal stops outputting after the mth level outputs. This will control the display panel positions corresponding to the first n-1 levels of shift registers to display a black image, the display panel positions corresponding to the nth to mth levels of shift registers to display a normal image, and the shift register units from the nth to the mth levels to trigger normally. The display panel positions corresponding to the (m+1)th level and beyond of shift registers will display a black image, and the shift registers after the (m+1)th level will not operate.

[0046] In summary, the aforementioned shift register latches the first node N1 of the shift register to be scanned to a high-level signal through a latch, so that by controlling the high or low level of the first initial scan signal STV', the shift register at this level can be made to work or not work. It is possible to trigger the shift register unit from any level, thereby enabling the opening of any level of shift register.

[0047] In some embodiments of this application, Figure 3 This is a schematic diagram of a latching structure provided according to an embodiment of this application, as shown below. Figure 3 As shown, the latch structure includes: a first inverter 11, the input terminal of which is electrically connected to the first terminal of the second switch module; a first switch unit 12, the first terminal of which is electrically connected to the input terminal of the first inverter 11, the second terminal of which is electrically connected to the output terminal of the first inverter 11, and the third terminal of which is connected to the first scan line; and a latch substructure 13, the first terminal of which is electrically connected to the fourth terminal of the first switch unit 12 and the first node N1, and the second terminal of which is electrically connected to the fifth terminal of the first switch unit 12.

[0048] The input terminal of the first inverter 11 is... Figure 2 The connection point between the input terminal I of the latch structure, the first terminal of the latch substructure 13, and the fourth terminal of the first switching unit 12 is... Figure 2The output terminal O of the latch structure is connected to the third terminal of the first switching unit 12, which is connected to the first scan line for inputting the first scan signal select1. When the first scan signal select1 is high, the first switching unit 12 is turned on, transmitting the signal input at the input terminal I of the latch structure to the output terminal O. When the first scan signal select1 is low, the first switching unit 12 is turned off, disconnecting the connection between the input terminal I and the output terminal O of the latch structure. This prevents the signal at the input terminal I from affecting the signal at the output terminal O, thus achieving latching of the signal at the output terminal O.

[0049] In some embodiments, Figure 4 This is a schematic diagram of another latching structure provided according to an embodiment of this application, as shown below. Figure 4 As shown, the first switching unit includes: a third switching module 121, the control terminal of the third switching module 121 is connected to the first scan line, the first end of the third switching module 121 is electrically connected to the first end of the second switching module 30, and the second end of the third switching module 121 is electrically connected to the first end of the latch substructure 13; and a fourth switching module 122, the control terminal of the fourth switching module 122 is connected to the first scan line, the first end of the fourth switching module 122 is electrically connected to the output terminal of the first inverter 11, and the second end of the fourth switching module 122 is electrically connected to the second end of the latch substructure 13.

[0050] When the signal at input terminal I of the latch structure is a high-level signal and the first scan signal select1 is a high-level signal, the third switch module 121 and the fourth switch module 122 are turned on. The third switch module 121 transmits the high-level signal at input terminal I of the latch structure to the first node N1, i.e., the signal at point Q is a high-level signal. Furthermore, the high-level signal at input terminal I of the latch structure is inverted by the first inverter 11 and becomes a low-level signal, which is then transmitted to the fourth switch module 122. Point, that is The signal at the point is a low-level signal.

[0051] When the signal at input I of the latch structure is low and the first scan signal select1 is high, based on the same principle, the signal at point Q will also be low. The signal at the point is a high-level signal.

[0052] When the first scan signal select1 is low, the third switch module 121 and the fourth switch module 122 are disconnected. At this time, the signal at the input terminal I of the latch structure cannot affect point Q. The signal at the point, i.e. the signal at the input terminal I of the latch structure, cannot affect the signal at the first node N1. The state of the signal at the first node N1 is maintained, thus realizing the latching function.

[0053] In some embodiments, such as Figure 4 As shown, both the third switch module 121 and the fourth switch module 122 are N-type switching transistors.

[0054] In some embodiments, such as Figure 4 As shown, the latch substructure includes: a second inverter 131, the input terminal of which is electrically connected to the first node N1 and the second terminal of the third switch module 121 respectively, and the output terminal of the second inverter 131 is electrically connected to the first terminal of the fourth switch module 122; and a third inverter 132, the input terminal of which is electrically connected to the first terminal of the fourth switch module 122, and the output terminal of the third inverter 132 is electrically connected to the first node N1 and the second terminal of the third switch module 121 respectively.

[0055] In this case, if the signal at input I of the latch structure is a high-level signal and the first scan signal select1 is a high-level signal, then based on the principle, the signal at point Q is a high-level signal. The signal at the point is a low-level signal. The low-level signal at point Q is input to the second inverter 131, which inverts it to output a high-level signal, the same as the signal at point Q. The high and low-level signals at point Q are input to the third inverter 132, which inverts it to output a low-level signal, the same as the signal at point Q. The signals at the points are the same, thus achieving signal latching.

[0056] In some embodiments, Figure 5 This is a schematic diagram of another latching structure provided according to an embodiment of this application, as shown below. Figure 5 As shown, the first inverter, the second inverter, and the third inverter are each composed of an N-type transistor and a P-type transistor. The gate of the N-type transistor is electrically connected to the gate of the P-type transistor, and the first terminal of the N-type transistor is electrically connected to the second terminal of the P-type transistor.

[0057] In this circuit, the first transistor M1 and the second transistor M2 form the third inverter, the third transistor M3 and the fourth transistor M4 form the second inverter, the fifth transistor M5 and the sixth transistor M6 form the first inverter, the seventh transistor M7 is the third switching module, and the eighth transistor M8 is the fourth switching module. The first transistor M1, the third transistor M3, and the fifth transistor M5 are all P-type TFTs, and the second transistor M2, the fourth transistor M4, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 are all N-type TFTs.

[0058] In some embodiments, such as Figure 5 As shown, the first terminal of the P-type transistor is electrically connected to the first power supply line, and the second terminal of the N-type transistor is electrically connected to the second power supply line.

[0059] Specifically, the first power line is used to provide a first reference voltage signal VGH, and the second power line is used to provide a second reference voltage signal VGL.

[0060] Among them, such as Figure 5 As shown, when the signal at input terminal I of the latch structure is a high-level signal and the first scan signal select1 is a high-level signal, the seventh transistor M7 and the eighth transistor M8 are turned on. The seventh transistor M7 transmits the high-level signal at input terminal I of the latch structure to point Q, that is, the signal at point Q is a high-level signal. The high-level signal at point Q controls the third transistor M3 to turn off and the fourth transistor M4 to turn on. The fourth transistor M4 transmits the second reference voltage signal VGL to... At point 1, a high-level signal at input terminal I of the latch structure controls the fifth transistor M5 to turn off and the sixth transistor M6 to turn on. The sixth transistor M6 transmits the second reference voltage signal VGL to the eighth transistor M8, and the eighth transistor M8 transmits the second reference voltage signal VGL to... Point, pulled down from both directions simultaneously The potential at the point can be lowered more quickly. The potential of the point enables fast latching. Simultaneously, The low-level signal at point Q controls the first transistor M1 to turn on and the second transistor M2 to turn off. The first transistor M1 transmits the first reference voltage signal VGH to point Q. By simultaneously raising the potential of point Q from two directions, the potential of point Q can be raised more quickly, ensuring the high-level signal at point Q and realizing signal transmission and latching.

[0061] In some embodiments, Figure 6 This is a schematic diagram of another gate drive circuit provided according to an embodiment of this application, as shown below. Figure 6 As shown, the first switch module 20 includes: a first switch device M9, the control terminal of the first switch device M9 is electrically connected to the output terminal of the latch structure 10, the first terminal of the first switch device M9 is electrically connected to the first initial scan signal line, and the second terminal of the first switch device M9 is electrically connected to the input terminal of the shift register unit 03.

[0062] In some embodiments, such as Figure 6 As shown, the first switching device M9 is an N-type switching transistor.

[0063] Specifically, when the first node N1 (i.e., the output terminal of latch structure 10) is at a high level, the first switching device M9 is turned on, and the first switching device M9 transmits the first initial scan signal STV' to the input terminal of shift register unit 03. When the first node N1 (i.e., the output terminal of latch structure 10) is at a low level, the first switching device M9 is turned off.

[0064] In some embodiments, such as Figure 6 As shown, the second switch module includes: a second switch device M10, the control terminal of the second switch device M10 is connected to the second scan line, the first terminal of the second switch device M10 is electrically connected to the output terminal of the bidirectional selector 01, and the second terminal of the second switch device M10 is electrically connected to the input terminal of the latch structure 10.

[0065] In some embodiments, such as Figure 6 As shown, the second switching device M10 is an N-type switching transistor.

[0066] Specifically, when the second scan signal select2 output from the second scan line is high, the second switching device M10 is turned on, and the first switching device M10 transmits the signal from the output of the bidirectional selector 01 to the input of the shift register unit 03. When the second scan signal select2 is low, the second switching device M10 is turned off.

[0067] In some embodiments, Figure 7 This is a schematic diagram of another gate drive circuit provided according to an embodiment of this application, as shown below. Figure 7 As shown, the shift register also includes an abnormal power-off controller 04 and an output buffer 05, wherein the abnormal power-off controller is used to disconnect the shift register of the current stage in the event of an abnormality in the shift register of the current stage.

[0068] Embodiments of this application provide a control method for a gate drive circuit. Figure 8 This is a flowchart illustrating a control method for a gate driving circuit according to an embodiment of this application, as shown below. Figure 8 As shown, the method is used to control any type of gate drive circuit, and the method includes:

[0069] Step S101: Generate a drive signal set, which includes multiple level signals, including a first scan signal and a second scan signal;

[0070] Step S102: Apply the first scan signal to the latch structure to control the voltage of the first node, and control the conduction or disconnection of the first switch module by controlling the voltage of the first node, so as to control the gate control signal output by the shift register.

[0071] Step S103: Apply the second scan signal to the second switch module to control the connection or disconnection of the shift register of the current stage with the shift register of other stages by controlling the conduction or disconnection of the second switch module.

[0072] The gate drive circuit control method of this application first generates a drive signal set, which includes multiple level signals, including a first scan signal and a second scan signal. Then, the first scan signal is applied to the latch structure to control the voltage of the first node. By controlling the voltage of the first node, the first switching module is turned on or off, thereby controlling the gate control signal output by the shift register. Finally, the second scan signal is applied to the second switching module to control the connection or disconnection of the current stage shift register with other stage shift registers by controlling the on or off state of the second switching module. This method controls the signals input to the shift register unit by controlling the first and second scan signals input in each frame, thereby enabling triggering of the shift register unit from any stage, opening any stage shift register, and closing any stage shift register. When the screen displays a normal image area, the shift register unit operates, and the shift register is turned on and off sequentially. When the screen displays a black image area, the shift register unit does not operate, and the gate control signal is not output, thereby reducing the power consumption of the shift register unit. This solves the problem in the prior art where all the drive circuits of the shift register units operate when the screen only displays a part of the area, resulting in high power consumption.

[0073] In some embodiments, Figure 1 These are several schematic diagrams showing the positions of the first and second display areas of the display panel during the display process. The first and second display areas can alternate multiple times during the display process, which will not be elaborated upon here; only the following are examples. Figure 1 The following four scenarios will be used as examples for explanation.

[0074] Figure 9 For the embodiments provided in this application Figure 1 (a) Timing diagram of each signal in the gate drive circuit during the first frame scan, as shown below. Figure 1 (a) Figure 7 and Figure 9 As shown, the first display area of ​​the display panel, i.e., the first n-1 rows of the display panel, displays a black image, while the second display area, i.e., the rows after the nth row, displays a normal image when the gate drive circuit outputs an effective level signal (such as a high level signal). In this case, the method further includes the following steps:

[0075] In step S201, when the (n-1)th level shift register has no signal output (i.e., the display area of ​​the corresponding row is black) and the nth level shift register outputs a valid gate control signal (i.e., the display area of ​​the corresponding row displays a normal image), when the first frame scans to the (n-1)th level shift register, the first scan signal select1 is adjusted to a high level signal, and the first scan signal select1 is applied to the latch structure 10 to adjust the voltage of the first node N1 of the nth level shift register (e.g., ...). Figure 9 (As shown in ln) is latched to a high level, n≥2;

[0076] Specifically, such as Figure 7 and Figure 9 As shown, when the (n-1)th stage shift register has no signal output and the nth stage shift register outputs a valid gate control signal, it is necessary to control the shift register units of the first (n-1)th stage shift registers to be inactive, and start driving the current stage display from the nth stage shift register. Therefore, it is necessary to first set the voltage of the first node N1 (e.g., ...) in the first frame. Figure 9 The first node N1 (as shown in ln) is latched to a high level. In the second frame, when the first n-1 level shift registers are not working (i.e., the first n-1 level shift registers have no signal output), the high level signal of the first node N1 controls the first switch module to be turned on. By controlling the high and low levels of the first initial scan signal STV', it is possible to start scanning directly from the nth level shift register or not scan at all.

[0077] In some embodiments, such as Figure 7 and Figure 9 As shown, the multiple level signals also include a first initial scan signal STV', which is the signal output from the first initial scan signal line. The first initial scan signal line is electrically connected to the first terminal of the first switching module (ninth transistor M9). When there is no signal output from the (n-1)th stage shift register and the nth stage shift register outputs a valid gate control signal, when the first frame scans to the (n-1)th stage shift register, the first scan signal select1 is adjusted to a high level signal and applied to the latch structure 10 to latch the voltage of the first node N1 of the nth stage shift register to a high level. Specifically, the steps include the following:

[0078] In step S2011, when there is no signal output from the (n-1)th stage shift register and the nth stage shift register outputs a valid gate control signal, when the first frame scans to the (n-1)th stage shift register, both the first scan signal select1 and the first initial scan signal are adjusted to high level signals to pull the potential of the first node N1 to high level.

[0079] Specifically, such as Figure 7 and Figure 9As shown, when there is no signal output from the (n-1)th stage shift register and the nth stage shift register outputs a valid gate control signal, when the first frame is scanned to the (n-1)th stage shift register, the first scan signal select1 and the first initial scan signal are both adjusted to high level signals. At this time, the latch structure 10 transmits the high level signal of the first scan signal select1 to the first node N1. The ninth transistor M9 is turned on under the action of the high level signal of the first node N1 and transmits the first initial scan signal STV' to the input terminal of the shift register unit. At this time, the input terminal of the shift register unit is a high level signal.

[0080] Step S2012: After the potential of the first node N1 is pulled high, the first scan signal select1 is adjusted to a low level signal to latch the voltage of the first node N1 of the nth stage shift register to a high level.

[0081] Specifically, latching the voltage of the first node N1 of the nth-stage shift register to a high level can keep the ninth transistor M9 in the on state. Thus, by controlling the high and low levels of the first initial scan signal STV', the input signal of the shift register unit in the nth-stage shift register can be controlled.

[0082] In step S2013, after the voltage of the first node N1 is latched to a high level, the (n-1)th stage shift register outputs a high-level signal and adjusts the first initial scan signal STV' to a low-level signal.

[0083] Specifically, such as Figure 7 and Figure 9 As shown, since the voltage of the first node N1 is latched to a high level, the ninth transistor M9 is turned on. When the first initial scan signal is a low-level signal, the ninth transistor M9 transmits the low-level signal of the first initial scan signal STV' to the input of the shift register of the nth stage shift register. Since the second scan signal select2 is always at a high level during the first frame scan, the tenth transistor M10 is always turned on during the first frame scan. At this time, the low-level signal output by the (n-1)th stage shift register is transmitted to the input of the shift register of the nth stage shift register through the bidirectional selector and the tenth transistor M10, ensuring that the signal at the input of the shift register of the nth stage shift register is a low-level signal, thus realizing the step-by-step scanning of the first frame.

[0084] In some embodiments, such as Figure 7 and Figure 9As shown, the first n-1 levels are set to display a black screen, and the nth level onwards displays a normal screen. During the first frame scan, the second initial scan signal STV first gives a high-level signal to the first-level shift register, driving the first-level shift register to scan normally. The gate control signal will be output from beginning to end. The second scan signal select2 is always high, ensuring that the tenth transistor M10 is always turned on, and ensuring that the shift register unit outputs the gate control signal Gout in sequence from level 1 to level n. When the first frame signal reaches level n-1, the output of shift register unit 03 of level n-1 is high. The high-level signal output by shift register unit 03 of level n-1 is transmitted to the input of shift register unit 03 of level n through bidirectional selector 01 of shift register n and tenth transistor M10. At this time, the first scan signal select1 is pulled high, and the output of the latch of level n will be set high, that is, the signal of the first node N1 of shift register n is high. At the same time, the first initial scan signal STV' is set high. When the signal of the first node N1 of shift register n is high, the ninth transistor M9 is turned on, transmitting the high level of the first initial scan signal STV' to the input of shift register unit 03 of shift register n, ensuring that the signal input to the input of shift register unit 03 of shift register n is a high-level signal. Before the gate control signal of the (n-1)th stage is pulled low, the first scan signal select1 is pulled low. At this time, due to the action of latch structure 10, the voltage of the first node N1 of the nth stage will remain latched at a high level. Since the first scan signal select1 is always low when the signal is transmitted to the first (n-1)th stage shift register, the latches of the first (n-1)th stage shift registers do not latch the voltage. Therefore, the potential of the first node N1 of the first (n-1)th stage shift registers is low. During the period when the first scan signal select1 is high, the nth stage shift register has not yet transmitted a signal to the next stage shift register. Therefore, the shift registers after the (n+1)th stage have no input signal. In this case, even if the first scan signal select1 is high, no high-level signal can be transmitted to the first node N1 of the shift registers after the (n+1)th stage. Therefore, the potential of the first node N1 of the shift registers after the (n+1)th stage is also low. Therefore, except for the nth-stage shift register, the first node N1 of the latches in all other shift register stages is latched to a low potential, such as... Figure 9 As shown, Figure 9In the diagram, ln represents the potential of the first node N1 of the nth stage, ln+1 represents the potential of the first node N1 of the (n+1)th stage, and ln+2 represents the potential of the first node N1 of the (n+2)th stage. It can be seen that, except for the first node N1 of the nth stage, the potential of the first node N1 of the latches in all other shift register units is low. Furthermore, when the gate control signal of the (n-1)th stage is pulled low, the first initial scan signal STV' is synchronously pulled low, ensuring that the signal input to shift register unit 03 is at a low level.

[0085] Figure 12 For the embodiments provided in this application Figure 1 (b) The timing diagram of each signal in the gate drive circuit during the second frame scan, refer to Figure 7 and Figure 12 The multiple level signals also include a first initial scan signal STV', which is the signal output from the first initial scan signal line. The first initial scan signal line is electrically connected to the first terminal of the first switching module (ninth transistor M9). After latching the voltage of the first node of the nth stage shift register to a high level, the method further includes the following steps:

[0086] In step S301, when the second frame scans to the (n-1)th stage shift register, the first initial scan signal STV' is adjusted to a high level and applied to the first switching module (ninth transistor M9), so that the first initial scan signal STV' is transmitted through the first switching module (ninth transistor M9) to the input terminal of the shift register unit in the nth stage shift register.

[0087] In step S302, when the second frame is scanned to the nth level shift register, the second scan signal select2 is adjusted to a high level signal and applied to the second switching module (tenth transistor M10) to control the second switching module (tenth transistor M10) to be turned on.

[0088] Specifically, by controlling STV' to be a high-level signal, the first switching module (ninth transistor M9) can transmit the high-level signal of STV' to the input terminal of the shift register in the nth stage shift register, so that the shift register in the nth stage shift register starts to have a high-level input signal. Thus, even when the shift registers in the first n-1 stages of shift registers are not working, the nth stage shift register can still work normally.

[0089] Figure 12 For the embodiments provided in this application Figure 1 (b) Timing diagram of each signal in the gate drive circuit during the second frame scan, as follows: Figure 7 and Figure 12 As shown, Figure 12In this diagram, ln represents the potential of the first node N1 in the nth stage, ln+1 represents the potential of the first node N1 in the (n+1)th stage, and ln+2 represents the potential of the first node N1 in the (n+2)th stage. The shift registers in stages 1 to (n-1)th are inactive. Normal operation begins from the nth stage shift register, meaning the shift register unit in the nth stage outputs a valid signal (e.g., a high-level signal) to drive the current row display. Since ln is always high, the ninth transistor M9 is turned on. At this time, the input voltage of the shift register unit in the nth stage shift register is related to the first initial scan signal STV'. When the second frame scans to the (n-1)th stage shift register, the first initial scan signal STV' is high, and the ninth transistor M9 of the nth stage shift register transmits the first initial scan signal STV' to the input of the shift register unit in the nth stage shift register.

[0090] When scanning to the nth level shift register in the second frame, it is necessary to scan level by level starting from the nth level shift register. Therefore, when scanning to the nth level shift register in the second frame, the second scan signal needs to be adjusted to a high level signal and applied to the second switch module to control the second switch module to conduct, thereby controlling the connection between the nth level shift register and the (n+1)th level shift register, so as to realize the shift register scanning level by level starting from the nth level.

[0091] In some embodiments, after latching the voltage of the first node of the nth-stage shift register to a high level, when the second frame scans to the (n-1)th-stage shift register, the second scan signal select2 is adjusted to a low level and applied to the second switching module (tenth transistor M10) to control the second switching module (tenth transistor M10) to disconnect, thereby controlling the nth-stage shift register to disconnect from the (n-1)th-stage shift register, preventing the nth-stage gate control signal from being transmitted to the (n-1)th-stage shift register through the bidirectional selector of the nth-stage shift register.

[0092] When the second frame scan reaches the (n-1)th stage shift register, the first initial scan signal STV' is high. The ninth transistor M9 of the nth stage shift register transmits the first initial scan signal STV' to the input of the shift register cell of the nth stage shift register. If the second scan signal select2 is high, the second switching module (tenth transistor M10) may transmit the high-level signal at the input of the shift register cell to the gate signal output of the (n-1)th stage shift register through a bidirectional selector. This would result in the output of the (n-1)th stage shift register, which does not need to output a valid level signal. Therefore, adjusting the second scan signal select2 to low when the second frame scans to the (n-1)th stage shift register can control the second switching module (tenth transistor M10) to disconnect, thereby controlling the nth stage shift register to disconnect from the (n-1)th stage shift register, ensuring that the output of the (n-1)th stage shift register is not affected by the nth stage shift register.

[0093] In other embodiments, after latching the voltage of the first node of the nth-stage shift register to a high level, when the second frame is scanned to the nth-stage shift register, the first initial scan signal STV' is adjusted to a low level and applied to the first switching module (ninth transistor M9).

[0094] When scanning starts from the nth stage shift register, only a high-level drive signal needs to be provided to the nth stage shift register. That is, the first initial scan signal STV' is provided to the nth stage shift register to drive it. When scanning to the nth stage shift register in the second frame, the first initial scan signal STV' is low. If the first initial scan signal STV' remains high for a long time, since the ninth transistor M9 of each stage shift register is connected to the first initial scan signal line, leakage may occur in some cases. That is, the high level of the first initial scan signal STV' will leak to the shift register unit. If the ninth transistor M9 of a shift register other than the nth stage leaks, it will cause the shift register of the stage with leakage to work. To avoid leakage, the first initial scan signal is adjusted to a high level only when scanning to the (n-1)th stage shift register in the second frame, and the first initial scan signal STV' is adjusted to a low level when scanning to the nth stage shift register in the second frame.

[0095] In other embodiments, when the second frame scans to the (n-1)th level shift register, the second scan signal is adjusted to a low level and applied to the second switch module to control the second switch module to disconnect, thereby controlling the nth level shift register to disconnect from the (n-1)th level shift register; and when the second frame scans to the nth level shift register, the first initial scan signal is adjusted to a low level and applied to the first switch module.

[0096] During the second frame scan, since the voltage of the first node N1 of the nth-stage shift register is latched high, the ninth transistor M9 of the nth-stage shift register is turned on, adjusting the first initial scan signal STV' to a high level. The ninth transistor M9 of the nth-stage shift register transmits the first initial scan signal STV' to the input of the shift register unit of the nth-stage shift register to control the shift register unit of the nth-stage shift register to drive the current row display. At this time, the voltage at the input of the shift register unit of the nth-stage shift register is a high-level signal. If the second scan signal select2 is a high-level signal, the second switching module (tenth transistor M10) of the nth-stage shift register will transmit the high-level signal at the input of the shift register unit to the gate signal output of the (n-1)th-stage shift register through a bidirectional selector, which will affect the output of the (n-1)th-stage shift register. Therefore, by adjusting the second scan signal select2 to a low level during the second frame scan, the second switch module (tenth transistor M10) of the nth stage shift register can be disconnected, thereby disconnecting the nth stage shift register from the (n-1)th stage shift register and ensuring that the output of the (n-1)th stage shift register is not affected by the nth stage shift register.

[0097] In some embodiments of this application, such as Figure 7 and Figure 12 As shown, the multiple level signals also include a second initial scan signal STV, which is the signal output by the second initial scan signal line. The second initial scan signal line is electrically connected to the signal input terminal of the first-stage shift register. The second initial scan signal is used to drive the first-stage shift register. The method also includes: during the second frame scan, the second initial scan signal STV is always a low-level signal.

[0098] During the second frame scan, the second initial scan signal STV remains low, meaning it does not provide a drive signal to the first-stage shift register. Therefore, shift registers from the first stage to the (n-1)th stage are inactive, thus reducing power consumption of the shift register unit. When scanning to the (n-1)th stage according to the normal timing signal, the first initial scan signal STV' goes high. Since the voltage of the first node N1 of the nth-stage shift register is always latched high, the high-level signal of the first initial scan signal STV' is transmitted through the ninth transistor M9 of the nth-stage shift register to the shift register unit 03, triggering the nth-stage shift register unit 03. Specifically... Figure 12 As shown, G1 is the gate control signal output by the first-stage shift register, G2 is the gate control signal output by the second-stage shift register, ..., Gn-1 is the gate control signal output by the (n-1)th stage shift register, Gn is the gate control signal output by the nth stage shift register, Gn+1 is the gate control signal output by the (n+1)th stage shift register, and Gn+2 is the gate control signal output by the (n+2)th stage shift register. It can be seen that the first n-1 stages of shift registers do not output any signals, that is, the first-stage shift register to the (n-1)th stage shift register is not working, and it starts working from the nth stage shift register, thereby achieving the purpose of reducing the power consumption of the shift register unit.

[0099] In some embodiments, such as Figure 7 and Figure 12 As shown, when the m-th shift register outputs a valid gate control signal (i.e., the display area of ​​the corresponding row displays a normal image) and the (m+1)-th shift register has no signal output (i.e., the display area of ​​the corresponding row displays black), the second scan signal select2 is adjusted to a low level and applied to the second switch module (tenth transistor M10) to control the second switch module (tenth transistor M10) to disconnect, thereby controlling the m-th shift register to disconnect from the (m+1)-th shift register, where m≥2.

[0100] In some embodiments, m > n, such as Figure 1 (b) Figure 7 and Figure 12 As shown, the first n-1 rows of the display panel display a black screen (i.e., ... Figure 1 (b) The first display area in the upper region of the display panel, such as Figure 7 As shown in region A), rows n to m display the normal image (i.e. Figure 1 (b) The second display area of ​​the display panel, such as Figure 7 As shown in region B), a black screen is displayed after the (m+1)th row (i.e. Figure 1 (b) The first display area in the lower region of the display panel, such as Figure 7As shown in region C), the m-th shift register drives the display of this row, and the (m+1)-th shift register has no signal output. In this case, steps S201, S2011, S2012, S2013, S301, S302, S401, and S302 are used to control the first n-1 rows of the display panel to display a black image, and then the normal image is displayed starting from the n-th row, that is, the normal scanning starts from the n-th row. Then, when the second frame scans to the m-th shift register, the second scan signal select2 is adjusted to a low level and applied to the second switch module (tenth transistor M10) to control the second switch module (tenth transistor M10) to disconnect, thereby controlling the m-th shift register to disconnect from the (m+1)-th shift register.

[0101] Specifically, when the gate control signal reaches the m-th stage (i.e., when the m-th stage gate control signal is high), changing the second scan signal select2 from high to low will disconnect the connection between the m-th stage shift register and the (m+1)-th stage shift register. Therefore, the gate control signal output by the m-th stage shift register will not trigger the shift register of the (m+1)-th stage shift register; that is, the gate control signal stops scanning after the m-th stage output. Specifically... Figure 12 As shown, Gm is the gate control signal output by the m-th stage shift register, and Gm+1 is the gate control signal output by the (m+1)-th stage shift register. It can be seen that the shift register is scanned normally from the n-th stage to the m-th stage. After that, the second scan signal select2 changes from high level to low level, disconnecting the connection between the m-th stage shift register and the (m+1)-th stage shift register. The shift registers after the (m+1)-th stage have no signal input, that is, the shift registers after the (m+1)-th stage do not work and have no gate control signal output, thus achieving the purpose of reducing the power consumption of the shift register unit.

[0102] Figure 13 For the embodiments provided in this application Figure 1 (c) Timing diagram of each signal in the gate drive circuit during scanning, as shown Figure 1 (c) Figure 7 and Figure 13 As shown, the first m rows of the display panel show the normal image (i.e. Figure 1 (c) The second display area, such as Figure 7 As shown in region D), a black screen is displayed after the (m+1)th row (i.e. Figure 1 (c) The first display area, such as Figure 7As shown in region C, in this embodiment, the second initial scan signal STV first sends a high-level signal to the first-stage shift register, driving it to scan normally. The gate control signal is output stage by stage from beginning to end. The second scan signal select2 is always high, ensuring that the tenth transistor is always on. Then, when scanning to the m-th stage shift register, the second scan signal select2 is adjusted to a low-level signal and applied to the second switching module (tenth transistor M10) to control the second switching module (tenth transistor M10) to disconnect, thereby controlling the m-th stage shift register to disconnect from the (m+1)-th stage shift register. At this time, the (m+1)-th stage shift register has no input signal to drive it, so it does not work, and the corresponding row on the display panel displays a black screen.

[0103] In other embodiments, m+1 < n-1, Figure 14 This is a schematic diagram of another gate drive circuit provided according to an embodiment of this application. Figure 15 For the embodiments provided in this application Figure 1 (d) Timing diagram of each signal in the gate drive circuit during the second frame scan, as follows: Figure 1 (d) Figure 9 , Figure 14 and Figure 15 As shown, the first m rows of the display panel show the normal image (i.e. Figure 1 (d) The second display area in the upper region of the display panel, such as Figure 14 As shown in region A), rows m+1 to n-1 display a black screen (i.e., ...). Figure 1 (d) The first display area of ​​D, such as Figure 14 As shown in area B), the normal screen is displayed after the nth row (i.e. Figure 1 (d) The second display area in the lower region of the display panel, such as Figure 14 (As shown in region C). During the first frame scan, the signal of the first node N1 of the nth row shift register is latched to a high level in the same manner as above, as shown below. Figure 9 As shown in ln, the potential of the first node N1 of the first n-1 stage shift register cells is all low level, as... Figure 9 As shown in ln+1 and ln+2. Figure 15As shown, during the second frame scan, the second initial scan signal STV first sends a high-level signal to the first-stage shift register, driving it to scan normally. The gate control signal is output stage by stage from beginning to end. The second scan signal select2 remains high, ensuring that the tenth transistor is always on. Then, when scanning to the m-th stage shift register, the second scan signal select2 is adjusted to a low-level signal and applied to the second switching module (tenth transistor M10) to control the second switching module (tenth transistor M10) to disconnect, thereby disconnecting the m-th stage shift register from the (m+1)-th stage shift register. At this time, there is no signal input from the (m+1)-th to (n-1)-th stage shift registers, the shift registers are not working, and the corresponding rows on the display panel display a black screen. When the second frame is scanned to the (n-1)th stage shift register, the first initial scan signal STV' goes high. Since the voltage of the first node N1 of the nth stage shift register is always latched at a high level, the high-level signal of the first initial scan signal STV' will be transmitted through the ninth transistor M9 of the nth stage shift register to the shift register 03 of the nth stage shift register. The shift register 03 of the nth stage starts to be triggered, thereby realizing the output of gate control signals step by step from the nth stage.

[0104] Meanwhile, to prevent the tenth transistor M10 of the nth-stage shift register from transmitting the high-level signal at the input of the nth-stage shift register unit to the gate signal output of the (n-1)th-stage shift register through the bidirectional selector, thus affecting the output of the (n-1)th-stage shift register, the second scan signal select2 is adjusted to a low level when the second frame scans to the (n-1)th-stage shift register. This controls the second switch module (tenth transistor M10) to disconnect, thereby disconnecting the nth-stage shift register from the (n-1)th-stage shift register and ensuring that the output of the (n-1)th-stage shift register is not affected by the nth-stage shift register.

[0105] Embodiments of this application also provide a display panel. Figure 16 This is a schematic diagram of the structure of a display panel according to an embodiment of this application, such as... Figure 16 As shown, it includes: a gate drive circuit gr of any kind; a first scan signal generator configured to generate a first scan signal; and a second scan signal generator configured to generate a second scan signal.

[0106] The display panel includes a display area AA and a non-display area BB. The display area AA includes multiple gate lines G and multiple data lines S that are insulated from and intersect with the gate lines G. The non-display area BB includes a gate drive circuit gr provided in any embodiment of the present invention, wherein the gate signal output terminal of each shift register unit is electrically connected to a gate line G.

[0107] It should be noted that the gate drive circuit can be either single-sided or dual-sided. Figure 15 The diagram shown is only for dual-side drive; the specific drive method can be adjusted according to actual needs.

[0108] In specific implementations, this invention also provides a display device, which includes a display panel. The display device provided in this embodiment can be an array substrate or a terminal display device, such as a mobile phone, computer, television, or other display devices with display functions. This invention does not impose specific limitations on these. The display device provided in this embodiment has the beneficial effects of the gate driving circuit provided in this embodiment, and specific details can be found in the various embodiments. The specific description of the gate driving circuit will not be repeated here.

[0109] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0110] As can be seen from the above description, the embodiments of this application achieve the following technical effects:

[0111] 1) The technical solution of this application includes a gate driving circuit comprising multiple cascaded shift registers. Each shift register includes a bidirectional selector, a latch, and a shift register unit connected in sequence. The latch includes a latching structure, a first switching module, and a second switching module electrically connected. The first scan signal output from the first scan line connected to the latching structure controls the voltage of the first node. The voltage of the first node controls the gate control signal of the shift register by controlling the on / off state of the first switching module. The second scan signal output from the second scan line connected to the second switching module controls the connection or disconnection of the shift register of the current stage with shift registers of other stages by controlling the on / off state of the second switching module. This gate driving circuit adds a latch to each shift register. Through the control signal line, the shift register unit can be triggered from any stage, thereby enabling the opening or closing of any stage of the shift register. When the screen displays a normal image area, the shift register unit is active, and the shift register is turned on and off sequentially. When the screen displays a black image area, the shift register unit is not active, and the gate control signal is not turned on, thereby reducing the power consumption of the shift register unit. This solves the problem in the prior art where all the drive circuits of the shift register units are active when the screen only displays a part of the area, resulting in high power consumption.

[0112] 2) The gate drive circuit control method of this application first generates a drive signal set, which includes multiple level signals, including a first scan signal and a second scan signal. Then, the first scan signal is applied to the latch structure to control the voltage of the first node. By controlling the voltage of the first node, the first switching module is turned on or off, thereby controlling the gate control signal output by the shift register. Finally, the second scan signal is applied to the second switching module to control the connection or disconnection of the current stage shift register with other stages by controlling the on or off state of the second switching module. This method controls the signals input to the shift register unit by controlling the first and second scan signals input in each frame, thereby enabling triggering of the shift register unit from any stage, opening any stage shift register, and closing any stage shift register. When the screen displays a normal image area, the shift register unit is active, and the shift register is turned on and off sequentially. When the screen displays a black image area, the shift register unit is not active, and the gate control signal is not turned on, thereby reducing the power consumption of the shift register unit. This solves the problem in the prior art where all the drive circuits of the shift register units are active when the screen only displays a part of the area, resulting in high power consumption.

[0113] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A gate driving circuit, characterized in that, The system includes multiple cascaded shift registers that sequentially output gate control signals via gate control lines. Each shift register includes a bidirectional selector, a latch, and a shift register unit connected in sequence. The latch includes an electrically connected latching structure, a first switching module, and a second switching module. The control terminal of the latch structure is connected to the first scan line. The first scan signal output by the first scan line is used to control the voltage of the first node. The first node is the node where the latch structure is connected to the first switch module. The voltage of the first node is used to control the gate control signal output by the shift register by controlling the conduction or disconnection of the first switch module. The shift register unit is electrically connected to the first switch module. The control terminal of the second switch module is connected to the second scan line. The second scan signal output by the second scan line is used to control the connection or disconnection of the shift register of the current stage with the shift register of other stages by controlling the conduction or disconnection of the second switch module. The bidirectional selector is electrically connected to the second switch module.

2. The gate driving circuit according to claim 1, characterized in that, The latching structure includes: The first inverter is electrically connected to the first terminal of the second switching module. The first switching unit has a first terminal electrically connected to the input terminal of the first inverter, a second terminal electrically connected to the output terminal of the first inverter, and a third terminal connected to the first scan line. A latch substructure, wherein the first end of the latch substructure is electrically connected to the fourth end of the first switching unit and the first node, and the second end of the latch substructure is electrically connected to the fifth end of the first switching unit.

3. The gate driving circuit according to claim 2, characterized in that, The first switching unit includes: The third switch module has a control terminal connected to the first scan line, a first terminal electrically connected to the first terminal of the second switch module, and a second terminal electrically connected to the first terminal of the latch substructure. The fourth switch module has its control terminal connected to the first scan line, its first terminal electrically connected to the output terminal of the first inverter, and its second terminal electrically connected to the second terminal of the latch substructure.

4. The gate driving circuit according to claim 3, characterized in that, Both the third and fourth switching modules are N-type switching transistors.

5. The gate driving circuit according to claim 3, characterized in that, The latch substructure includes: The second inverter has its input terminal electrically connected to the second terminal of the first node and the second terminal of the third switch module, and its output terminal electrically connected to the first terminal of the fourth switch module. The third inverter has its input terminal electrically connected to the first terminal of the fourth switch module, and its output terminal electrically connected to both the first node and the second terminal of the third switch module.

6. The gate driving circuit according to claim 5, characterized in that, The first inverter, the second inverter, and the third inverter are each composed of an N-type transistor and a P-type transistor, wherein the gate of the N-type transistor is electrically connected to the gate of the P-type transistor, and the first terminal of the N-type transistor is electrically connected to the second terminal of the P-type transistor.

7. The gate driving circuit according to claim 6, characterized in that, The first terminal of the P-type transistor is electrically connected to the first power supply line, and the second terminal of the N-type transistor is electrically connected to the second power supply line.

8. The gate driving circuit according to claim 1, characterized in that, The first switch module includes: A first switching device, wherein the control terminal of the first switching device is electrically connected to the output terminal of the latch structure, the first terminal of the first switching device is electrically connected to the first initial scan signal line, and the second terminal of the first switching device is electrically connected to the input terminal of the shift register unit.

9. The gate driving circuit according to claim 8, characterized in that, The first switching device is an N-type switching transistor.

10. The gate driving circuit according to claim 1, characterized in that, The second switch module includes: The second switching device has its control terminal connected to the second scan line, its first terminal electrically connected to the output terminal of the bidirectional selector, and its second terminal electrically connected to the input terminal of the latch structure.

11. The gate driving circuit according to claim 10, characterized in that, The second switching device is an N-type switching transistor.

12. A control method for a gate driving circuit, characterized in that, The method is used to control the gate drive circuit according to any one of claims 1 to 11, the method comprising: A drive signal set is generated, the drive signal set including multiple level signals, the multiple level signals including: a first scan signal and a second scan signal; The first scan signal is applied to the latch structure to control the voltage of the first node, and by controlling the voltage of the first node, the first switch module is turned on or off, thereby controlling the gate control signal output by the shift register. The second scan signal is applied to the second switch module to control the connection or disconnection of the shift register of the current stage with the shift register of other stages by controlling the conduction or disconnection of the second switch module.

13. The control method according to claim 12, characterized in that, The method further includes: When there is no signal output from the (n-1)th stage shift register and the nth stage shift register outputs a valid gate control signal, when the first frame scans to the (n-1)th stage shift register, the first scan signal is adjusted to a high level signal and applied to the latch structure to latch the voltage of the first node of the nth stage shift register to a high level, where n≥2; And / or, When the m-th stage shift register outputs a valid gate control signal and the (m+1)-th stage shift register has no signal output, the second scan signal is adjusted to a low level and applied to the second switch module to control the second switch module to disconnect, thereby controlling the m-th stage shift register to disconnect from the (m+1)-th stage shift register, where m≥2; Where m+1 < n-1, or m > n.

14. The control method according to claim 13, characterized in that, The plurality of said level signals also include a first initial scan signal, which is a signal output from a first initial scan signal line. The first initial scan signal line is electrically connected to a first terminal of the first switching module. When there is no signal output from the (n-1)th stage shift register and the nth stage shift register outputs a valid gate control signal, when the first frame scans to the (n-1)th stage shift register, the first scan signal is adjusted to a high level signal, and the first scan signal is applied to the latch structure to latch the voltage of the first node of the nth stage shift register to a high level, including: When there is no signal output from the (n-1)th stage shift register and the nth stage shift register outputs a valid gate control signal, when the first frame is scanned to the (n-1)th stage shift register, both the first scan signal and the first initial scan signal are adjusted to a high level signal to pull the potential of the first node to a high level. After the potential of the first node is pulled high, the first scan signal is adjusted to a low level signal to latch the voltage of the first node of the nth stage shift register to a high level. After the voltage of the first node is latched to a high level, the (n-1)th stage shift register outputs a high-level signal and adjusts the first initial scan signal to a low-level signal.

15. The control method according to claim 13, characterized in that, The plurality of said level signals also include a first initial scan signal, which is a signal output from a first initial scan signal line. The first initial scan signal line is electrically connected to a first terminal of the first switching module. After latching the voltage of the first node of the nth stage shift register to a high level, the method further includes: When the second frame scan reaches the (n-1)th stage shift register, the first initial scan signal is adjusted to a high level and applied to the first switching module, so that the first initial scan signal is transmitted through the first switching module to the input terminal of the shift register unit in the nth stage shift register. When the second frame scan reaches the nth level shift register, the second scan signal is adjusted to a high level and applied to the second switch module to control the second switch module to turn on.

16. The control method according to claim 15, characterized in that, After latching the voltage of the first node of the nth stage shift register to a high level, the method further includes: When the second frame scan reaches the (n-1)th stage shift register, the second scan signal is adjusted to a low level and applied to the second switch module to control the second switch module to disconnect, thereby controlling the nth stage shift register to disconnect from the (n-1)th stage shift register; and / or, When the second frame is scanned to the nth level shift register, the first initial scan signal is adjusted to a low level and applied to the first switching module.

17. The control method according to claim 13, characterized in that, The plurality of said level signals further include a second initial scan signal, which is a signal output from a second initial scan signal line. The second initial scan signal line is electrically connected to the signal input terminal of the first-stage shift register. The second initial scan signal is used to drive the first-stage shift register. The method further includes: During the second frame scan, the second initial scan signal is always a low-level signal.

18. A display panel, characterized in that, include: The gate drive circuit according to any one of claims 1 to 11; A first scan signal generator is configured to generate a first scan signal; The second scan signal generator is configured to generate a second scan signal.

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