Scan driving circuit, array substrate and display panel

Abstract

The application provides a scanning driving circuit, an array substrate and a display panel. The scanning driving circuit comprises n cascaded first shift register units and second shift register units; an output end of an i-th first shift register unit is connected to a first scan line signal line of a corresponding pixel row, a third scan line signal line of the pixel row is connected to an output end of an i+2-th first shift register, wherein i=1…n, and n is the number of the first shift register units; a third scan line signal line of a pixel row corresponding to an n-1-th first shift register unit is connected to an output end of a first second shift register unit; a third scan line signal line of a pixel row corresponding to an n-th first shift register unit is connected to an output end of a second second shift register unit, and output ends of the second shift register units are respectively connected to compensation modules, so as to improve the problem of display brightness unevenness caused by inconsistent row load of the last two rows.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a scanning driving circuit, an array substrate, and a display panel. Background Technology

[0002] With the development of display technology, people have increasingly higher requirements for the display quality of display panels. Currently, existing display panels suffer from uneven brightness, resulting in an uneven visual effect and thus reducing display quality. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a scanning driving circuit, an array substrate, and a display panel.

[0004] To achieve the above objectives, this application provides a scanning drive circuit, which includes:

[0005] n cascaded first shift register units and 2 cascaded second shift register units;

[0006] The output of the first shift register unit of the i-th stage is connected to the first scan line signal line of the corresponding pixel row, and the third scan line signal line of the pixel row is connected to the output of the first shift register of the (i+2)-th stage, where i = 1…n, and n is the number of first shift register units (the number of first shift register units is the same as the number of pixel rows, so n is also called the number of pixel rows).

[0007] The third scan line signal line of the pixel row corresponding to the first shift register unit of the (n-1)th stage is connected to the output terminal of the second shift register unit of the first stage; the third scan line signal line of the pixel row corresponding to the first shift register unit of the nth stage is connected to the output terminal of the second shift register unit of the second stage. The output terminals of the first and second shift register units are respectively connected to the compensation module. This scan drive circuit is used in the integrated gate drive circuit (Scan N cascade circuit), which can improve the brightness difference caused by the inconsistent row load between the last row of pixels and the adjacent rows (i.e., the last two rows of pixels) when the last row of pixels cannot be compensated.

[0008] In one embodiment, the number of the first shift register units matches the number of the pixel rows, the output of the first-stage first shift register unit is connected to the first scan line signal line of the corresponding pixel row, and the third scan line signal line of the pixel row is connected to the output of the third-stage first shift register.

[0009] Preferably, the first shift register unit in each stage matches the corresponding pixel row.

[0010] In one embodiment, the compensation module includes a first compensation module and a second compensation module, wherein the output of the first-stage second shift register unit is connected to the first compensation module, and the output of the second-stage second shift register unit is connected to the second compensation module.

[0011] Preferably, the first compensation module and the second compensation module have the same structure.

[0012] In one embodiment, the compensation module includes a virtual capacitor located in the non-display area;

[0013] Preferably, the capacitance value of the virtual capacitor is equal to or the total capacitance value of the pixels in the first or last row of the pixel row is within a threshold range; preferably, the threshold is between 3% and 15% (e.g., 3%, 5%, 10% or 15%).

[0014] Preferably, the number of virtual capacitors is one or more, and the combined capacitance value is equal to or the difference between the total capacitance value of the pixels in the first or last row of the pixel row and the total capacitance value of the virtual capacitors (the capacitance value of the virtual capacitors and the total capacitance value of the pixels in the first or last row) is within a threshold range; preferably, the threshold value is between 3% and 15% of the capacitance value of the virtual capacitors (e.g., 3%, 5%, 7%, 9%, 10%, 13%, or 15%).

[0015] In one embodiment, the compensation module includes virtual pixels or rows of virtual pixels located in a non-display area;

[0016] Preferably, the virtual pixel includes a first virtual pixel and a second virtual pixel, the output of the first-stage second shift register unit is connected to the first virtual pixel, and the output of the second-stage second shift register unit is connected to the second virtual pixel, or...

[0017] The virtual pixel row includes a first virtual pixel row and a second virtual pixel row. The output of the first-stage second shift register unit is connected to the first virtual pixel row, and the output of the second-stage second shift register unit is connected to the second virtual pixel row.

[0018] Preferably, the first virtual pixel row and the second virtual pixel row have the same structure;

[0019] Preferably, the first virtual pixel row and the second virtual pixel row have the same structure as the pixel row located in the display area.

[0020] In one embodiment, the first shift register unit is cascaded with the second shift register unit;

[0021] The first scan line signal line is electrically connected to the gate of the initialization transistor (fourth transistor) of the driving circuit of the matching pixel row.

[0022] The third scan line signal line is electrically connected to the gate of the threshold compensation transistor (third transistor) of the driving circuit of the matching pixel row.

[0023] In one embodiment, the initialization transistor and the threshold compensation transistor are indium gallium zinc oxide thin-film transistors (IGZO).

[0024] Based on the same inventive concept, this application proposes an array substrate that includes the aforementioned driving circuit.

[0025] Based on the same inventive concept, this application proposes a display panel that includes the array substrate described above.

[0026] It includes a display area and a non-display area that at least partially surrounds the display area, with the compensation module configured in the non-display area.

[0027] Compared with the prior art, the scanning drive circuit provided in this application includes a cascaded first shift register unit and a second shift register unit. The second shift register unit is electrically connected to the compensation module located in the non-display area (border area), and the scan signal connection lines of the gates of the third and fourth transistors of the last two rows of pixels used for the driving circuit are connected to the compensation module in the non-display area (border area), thereby avoiding the problem of uneven display brightness caused by inconsistent row load of the last two rows of pixels. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a functional block diagram of a display panel according to an embodiment of this application;

[0030] Figure 2 This is a schematic diagram of a pixel scanning driving circuit according to an embodiment of this application;

[0031] Figure 3 This is a schematic diagram of a pixel scanning driving circuit according to another embodiment of this application;

[0032] Figure 4 for Figure 3 A schematic diagram of the driving timing of the embodiment;

[0033] Figure 5 This is a schematic diagram of a display panel according to an embodiment of this application;

[0034] Figure 6 This is a schematic diagram of a scan driving circuit according to an embodiment of this application;

[0035] Figure 7 This is a schematic diagram of a scan driving circuit according to another embodiment of this application. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0037] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0038] With the development of display technology, integrated gate-driven OLED display panels have been widely used in smaller wearable products (such as smartwatches). The applicant's further research on the architecture of the integrated gate-driven circuit of this type of display panel revealed that in the current design of the Scan N cascade circuit architecture for GIP (gate in panel) (the Scan N cascade circuit is used to control capacitor initialization), if the signal is directly terminated on the opposite side of the driver chip (IC), i.e., at the end of the signal, the load of the last two rows of pixels will be different from that of the previous rows of pixels, causing brightness differences due to the different loads of the pixels in different rows.

[0039] To address this issue, the applicant proposes a scanning drive circuit, an array substrate, and a display panel. This display panel can improve the problem of brightness differences caused by varying row loads.

[0040] like Figure 1 The diagram shown is a functional module schematic of a display panel according to an embodiment of this application.

[0041] The display panel includes a display unit 100, a scan driver 200, a transmit driver 300, and a data driver 400.

[0042] The display unit 100 includes multiple light-emitting units, each of which includes multiple pixels (such as red / green / blue pixels). Typically, the pixels are arranged in an array.

[0043] The scan driver 200 is configured to sequentially supply scan signals to pixels via scan lines based on a scan start signal. For example, the scan driver 200 may receive a scan start signal, at least one clock signal, etc., from a timing controller (not shown). The scan driver 200 can be configured in a non-display area (border area) of the display panel (such as one side or opposite sides of the border area). This scan driver is also called a scan drive circuit.

[0044] The data driver 400 is configured to receive a data control signal DCS and an image data signal RGB from a timing controller (not shown). Based on the data control signal DCS and the image data signal RGB, the data driver 400 supplies data signals (data voltages) to the pixel driving circuitry via data lines.

[0045] The timing controller can control the driving of the scan driver 200, transmit driver 300, and data driver 400 based on timing signals supplied from an external source. The data control signals (DCS) used to control the data driver 400 may include source start signals, source output enable signals, source sampling clock signals, etc.

[0046] In one embodiment, the display panel further includes a power supply that generates a power supply voltage ELVSS and an initialization voltage based on a power control signal received from a timing controller, and provides the generated voltage to the display unit 100.

[0047] Figure 2 for Figure 1 A schematic diagram of the driving circuit for the pixels of the light-emitting unit.

[0048] The pixel driving circuit includes: a driving module, a data writing module, a threshold compensation module, an initialization module, and a light-emitting module.

[0049] This data writing module is used to write data voltage (also known as data signal) to the control terminal of the drive module.

[0050] The driving module generates a driving current based on the voltage at the control terminal to drive the light-emitting module to emit light.

[0051] The control terminal of the initialization module is electrically connected to the first scan line, the first terminal is electrically connected to the first initialization signal line, and the second terminal is electrically connected to the control terminal of the drive module. The first terminal of the drive module is electrically connected to the second terminal of the data writing module. The first terminal of the data writing module is electrically connected to the data signal line to receive the data voltage (DATA signal). The control terminal of the data writing module is electrically connected to the second scan line to receive the data writing signal. The second terminal of the drive module is electrically connected to the first terminal of the threshold compensation module and the first terminal of the light-emitting module. The control terminal of the threshold compensation module is electrically connected to the second scan line, and the second terminal of the light-emitting module is electrically grounded / ELVSS.

[0052] The control terminal of the threshold compensation module is electrically connected to the second scan line, the first terminal of the threshold compensation module is electrically connected to the second terminal of the drive module, and the second terminal of the threshold compensation module is electrically connected to the control terminal of the drive module.

[0053] In this embodiment, a first initialization voltage VREFN1 is provided through a first initialization signal line, and a second initialization voltage VREFN2 is provided through a second initialization signal line.

[0054] Next, combine Figure 3 And refer to Figure 2 The pixel driving circuit provided in the embodiments of this disclosure will be described in detail below.

[0055] The drive module includes a first transistor T1 (also called a drive transistor);

[0056] The data writing module includes a second transistor T2;

[0057] The threshold compensation module includes a capacitor C;

[0058] The first initialization module includes a third transistor T3 and a fourth transistor T4;

[0059] The second initialization module includes a seventh transistor T7 and an eighth transistor T8.

[0060] The storage capacitor module includes a storage capacitor Cst.

[0061] The gate of the first transistor T1 is electrically connected to the first terminal of the storage capacitor Cst and the second terminal of the third transistor T3. The first terminal of the third transistor T3 is electrically connected to the second terminal of the fourth transistor T4, the first terminal of the first transistor T1, the second terminal of the sixth transistor T6, and the first terminal of the capacitor C. The first terminal of the fourth transistor T4 is electrically connected to the first initialization signal line VERFN1.

[0062] The gate of the third transistor T3 is electrically connected to the third scan line S3.

[0063] The gate of the fourth transistor T4 is electrically connected to the first scan line S1.

[0064] The first electrode of the first transistor T1 is electrically connected to the second electrode of the sixth transistor T6 and the second electrode of the eighth transistor T8. The first electrode of the eighth transistor T8 is electrically connected to the initialization signal line VERFNP1. The gate of the eighth transistor T8 and the gate of the seventh transistor T7 are electrically connected to the fourth scan line S4, respectively. The first electrode of the seventh transistor T7 is electrically connected to the second initialization signal line VERFN2 (used for the anode initialization of the OLED). The second electrode of the seventh transistor T7 is electrically connected to the anode of the OLED. The cathode of the OLED is electrically grounded / ELVSS.

[0065] The second terminal of the first transistor T1 is electrically connected to the second terminal of the fifth transistor T5 and the second terminal of the second transistor T2. The first terminal of the fifth transistor T5 is electrically connected to the second terminal of the storage capacitor Cst and the ELVDD terminal.

[0066] The first terminal of the second transistor T2 is electrically connected to the data voltage line (received data voltage DATA), and the gate of the second transistor T2 is electrically connected to the second scan line S2 and the second terminal of the capacitor C.

[0067] The gate of the sixth transistor T6 is electrically connected to the gate of the fifth transistor T5 and the emitter control terminal to receive the emitter control signal EM. In this embodiment, the driving circuit uses an 8T1C circuit; in other embodiments, a 7T1C circuit or a 7T2C circuit can be used. In this embodiment, the third transistor T3 and the fourth transistor T4 can be indium gallium zinc oxide (IGZO) thin-film transistors, and other transistors can be low-temperature polycrystalline silicon (LTPS) thin-film transistors.

[0068] Next, combine Figure 4 This describes the driving timing (i.e., driving process) of the pixel's driving circuit. The pixel driving circuit operation includes an initialization phase, a data writing phase, and a light emission phase.

[0069] In stage t1 (also known as the initialization stage), the first scan line S1 is at a high level, the third scan line S3 is at a high level, the fourth transistor T4 and the third transistor T3 are turned on, and the gate of the first transistor T1 is initialized to the Vref potential, which facilitates the subsequent data voltage Vdata to be charged into the storage capacitor Cst.

[0070] In stage t2 (data writing stage), the third scan line S3 is high, the third transistor T3 is turned on / conducted, the second scan line S2 is low, the second transistor T2 is turned on / conducted, the gate of the first transistor T1 is at a low potential of Vref, the first transistor T1 is turned on, and the potential of the gate of the first transistor T1 continuously rises. When the voltage between the gate and source of the first transistor T1, Vgs, rises to 2Vth, the first transistor T1 is turned off. At this time, the voltage of the first transistor T1 is Vdata-Vth. At the same time (in stage t2, the anode of the OLED is initialized), the fourth scan line S4 is low, the seventh transistor T7 and the eighth transistor T8 are turned on respectively, and the anode of the OLED is initialized to Vref. This design can clear the residual charge of the previous frame, which is beneficial to improving the contrast of the displayed image.

[0071] In stage t3 (OLED light-emitting stage), the EM signal of the emitter driver 300 is low, and the fifth transistor T5 and the sixth transistor T6 are turned on / off respectively. At this time, the current flowing through the organic light-emitting diode OLED is related to the turn-on threshold voltage V of the first transistor T1. th Irrelevant, i.e., V th The compensation will be provided until the next scan.

[0072] This application provides a display panel, such as... Figure 5 As shown, the display panel 100 includes a display area 110 and a non-display area 120 surrounding the display area. The display area 110 contains a plurality of light-emitting units 111, arranged in an array. The non-display area includes a border area, which is equipped with a compensation module configured to be close to the first / last row of light-emitting units in the adjacent display area. Preferably, the border area includes an upper border area 121, where the compensation module is located. Preferably, the non-display area also includes a binding area, through which a control module is bound, and a preset pattern is displayed on the display area based on the control of the control module.

[0073] In one embodiment, the border area (such as the top border) is provided with dummy pixels or rows of dummy pixels (including multiple dummy pixels). These dummy pixels are electrically isolated from the pixels in the light-emitting units of the display area (i.e., the dummy pixels are not connected to the pixels in the light-emitting units of the display area). The dummy pixels may include dummy red / green / blue pixels. The configuration of the dummy pixels may be the same as the pixels in the first row of light-emitting units, except that the dummy pixels do not emit light. The configuration of the dummy pixel rows may be consistent with the pixel row structure of the display area; during operation, the dummy pixels do not emit light (e.g., the dummy pixels are not provided with organic light-emitting diodes (OLEDs)).

[0074] In one embodiment, a dummy capacitor is provided in the border area. Preferably, the capacitance value of the dummy capacitor is the same as or differs from the total capacitance value of the pixels in the first or last row of pixels within a preset threshold range (threshold between 3% and 15%, such as thresholds selected from 3%, 5%, 10%, 11%, 12%, 13%, 14%, or 15%). The number of dummy capacitors can be one or more, and the combined capacitance value is the same as or differs from the total capacitance value of the pixels in the first row of pixels within a preset threshold range (threshold between 3% and 15%, such as thresholds selected from 3%, 5%, 10%, 11%, 12%, 13%, 14%, or 15%).

[0075] like Figure 6 The diagram shows a topology of a scan driving circuit according to an embodiment of this application, with four first shift register units (matching and connecting four rows of pixels) as an example for description.

[0076] The scan driver includes four cascaded first shift register units 210 and two second shift register units 220. One of the two second shift register units 220 is cascaded with the first shift register unit 210, referred to as the first-stage second shift register unit (also called compensation stage 1), and the other is referred to as the second-stage second shift register unit (also called compensation stage 2). Each stage of the first shift register unit 210 corresponds to a pixel row located in the display area (the number of pixel rows is the same as the number of first shift register units 210). The two second shift register units 220 and their corresponding virtual pixel rows (see...) Figure 6 a) is located in the border area. In the first shift register unit 210, NVGH provides a high-level signal, NVGL provides a low-level signal, and RST provides a reset signal.

[0077] The output of the first shift register unit 210 is connected to the first scan line signal line S1 of the first level / first row of pixels (the first scan line signal line S1 is electrically connected to the gate of the fourth transistor of the driving circuit of the corresponding pixel row to transmit a signal thereto).

[0078] The output of the first shift register unit 210 of the second stage is connected to the first scan line signal line S1 of the second stage / second row of pixels (the first scan line signal line S1 is electrically connected to the gate of the fourth transistor of the driving circuit of the corresponding pixel row to transmit a signal thereto).

[0079] The output of the first shift register unit 210 of the third stage is connected to the first scan line signal line S1 of the third stage / third row of pixels (the first scan line signal line S1 is electrically connected to the gate of the fourth transistor of the pixel driving circuit in the row to transmit a signal to it).

[0080] The output of the first shift register unit 210 of the fourth stage is connected to the first scan line signal line S1 of the fourth stage / fourth row of pixels (the first scan line signal line S1 is electrically connected to the gate of the fourth transistor of the driving circuit of the corresponding pixel row to transmit a signal thereto).

[0081] Furthermore, the output of the first shift register unit 210 of the third stage is connected to the third scan line S3 of the corresponding row of the first shift register unit 210 of the first stage (this third scan line S3 is electrically connected to the gate of the third transistor of the pixel driving circuit in the row), that is, the transmission signal line S3 of the first pixel row is cascaded to the output of the first shift register unit 210 of the third stage. The third transistor is also called the threshold compensation transistor. The fourth transistor is also called the initialization transistor.

[0082] The output of the first shift register unit 210 of the fourth stage is connected to the third scan line S3 of the second stage / second row of pixels (the third scan line S3 is electrically connected to the gate of the third transistor of the driving circuit of the pixel row), that is, the third scan line S3 of the second row of pixels is cascaded to the output of the first shift register unit 210 of the fourth stage.

[0083] The third scan line S3 of the pixel row corresponding to the first shift register unit 210 of the third stage is connected to the output of the second shift register unit of the first stage (also known as the compensation stage 1), and the output of the second shift register unit of the first stage is connected to the first virtual pixel row.

[0084] The third scan line S3 of the corresponding pixel row in the fourth-stage first shift register unit 210 is connected to the output of the second-stage second shift register unit (also known as compensation stage 2). The output of the first-stage second shift register unit is connected to the first virtual pixel row, and the output of the second-stage second shift register unit is connected to the second virtual pixel row. This design avoids brightness differences caused by inconsistent row loads between the last pixel row and adjacent rows (i.e., the last two pixel rows) when compensation is unavailable. In this embodiment, the combination of two first shift register units 210 constitutes a GIP driving unit (e.g., the combination of the first-stage first shift register unit and the second-stage first shift register unit constitutes one GIP driving unit, and the combination of the third-stage first shift register unit and the fourth-stage first shift register unit constitutes one GIP driving unit).

[0085] As Figure 6 Variations of the implementation method, such as Figure 7 The diagram shows a topology of a scan drive circuit according to an embodiment of this application.

[0086] The scan driver includes n cascaded first shift register units 210 and two second shift register units 220 (i.e., n cascaded first shift register units are matched and connected to n rows of pixels, where n is a natural number, such as n selected from 128, 256, 512, 720, 1024, 1080, 2160, 4320, etc., depending on the resolution of the display panel).

[0087] The number of the first shift register units corresponds to the pixel rows (e.g., the display area includes i pixel rows, i = 1...n, where n is the number of the first shift register units and the number of pixel rows). Each pixel row is matched with a first shift register unit 210, that is, the i-th level first shift register unit 210 is matched with the i-th pixel row.

[0088] The output of the first shift register unit of the i-th stage is connected to the first scan line signal line S1 corresponding to the pixel row of this stage (i.e., the i-th row), and the third scan line signal line S3 corresponding to the pixel row of the i-th row is connected to the output of the first shift register of the (i+2)-th stage. The first scan line signal line is used to provide the first scan line signal, and the third scan line signal line is used to provide the third scan line signal. The first scan line signal line S1 is electrically connected to the gate of the fourth transistor T4 of the driving circuit of the matched pixel row (see reference). Figure 3 The third scan line signal line S3 is electrically connected to the gate of the third transistor T3 of the matching pixel row drive circuit (reference). Figure 3 The third transistor T3 and the fourth transistor T4 are IGZO type transistors.

[0089] The third scan line signal line of the pixel row corresponding to the (n-1)th stage first shift register unit 210 is connected to the output of the first stage second shift register unit (compensation stage 1). The third scan line signal line of the pixel row corresponding to the nth stage first shift register unit 210 is connected to the output of the second stage second shift register unit (compensation stage 2). The output of the first stage second shift register unit is connected to the first virtual pixel row, and the output of the second stage second shift register unit is connected to the second virtual pixel row. The first virtual pixel row and the second virtual pixel row are collectively referred to as virtual pixel rows. These virtual pixel rows provide compensation signals (i.e., act as compensation modules).

[0090] The second shift register unit 220 is cascaded with the first shift register unit 210, and the second shift register unit 220 is electrically connected to the virtual pixels of the border area. One of the two second shift register units 220 cascaded with the first shift register unit 210 is called the first-stage second shift register unit (also called compensation stage 1), and the other is called the second-stage second shift register unit (also called compensation stage 2). The two second shift register units 220 and their corresponding virtual pixel rows (see...) Figure 7a) Located in the border area. This design connects the cascaded wires to the virtual pixels located in the border area (i.e., for providing load compensation), avoiding brightness differences caused by inconsistent loads between the last row of pixels and adjacent pixel rows (i.e., the last two pixel rows) when the last row of pixels cannot be compensated by the normal compensation module. Simulation verification shows that the current difference between adjacent pixel rows under this method is approximately 1.85%, with almost no brightness difference.

[0091] As Figure 6 In a variation of the implementation, the second shift register unit 220 is electrically connected to the virtual capacitor in the border area (the capacitance of the virtual capacitor is equal to or approximately equal to the total capacitance of the pixel row in the light-emitting unit of the adjacent i-row) to avoid brightness differences caused by different loads. Simulation verification shows that the capacitance difference between adjacent rows in the implementation proposed in this application is 0.75pf, with almost no brightness difference.

[0092] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.

[0093] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0094] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A scanning drive circuit, characterized in that, include: n cascaded first shift register units and 2 cascaded second shift register units, wherein the second shift register units are located at the end of the signal in the border area; The output of the first shift register unit of the i-th stage is connected to the first scan line signal line of the corresponding pixel row, and the third scan line signal line of the pixel row is connected to the output of the first shift register of the (i+2)-th stage, where i=1…n, and n is the number of first shift register units; The third scan line signal line of the pixel row corresponding to the first shift register unit of the (n-1)th stage is connected to the output terminal of the second shift register unit of the first stage; The third scan line signal line corresponding to the pixel row of the first shift register unit in the nth stage is connected to the output terminal of the second shift register unit in the second stage. The output terminals of the first-stage second shift register unit and the second-stage second shift register unit are respectively connected to the compensation module. The compensation module includes a virtual capacitor. The capacitance value of the virtual capacitor is the same as or differs from the capacitance value of the total capacitance of the pixels in the first or last row of the pixel row within a threshold range. The threshold ranges from 3% to 15% of the capacitance value of the virtual capacitor.

2. The scanning drive circuit as described in claim 1, characterized in that, The number of the first shift register units matches the number of the pixel rows. The output of the first-stage first shift register unit is connected to the first scan line signal line of the corresponding pixel row, and the third scan line signal line of the pixel row is connected to the output of the third-stage first shift register.

3. The scanning drive circuit as described in claim 2, characterized in that, The first shift register unit in each stage matches the corresponding pixel row.

4. The scanning drive circuit as described in claim 2 or 3, characterized in that, The compensation module includes a first compensation module and a second compensation module. The output of the first-stage second shift register unit is connected to the first compensation module, and the output of the second-stage second shift register unit is connected to the second compensation module.

5. The scanning drive circuit as described in claim 4, characterized in that, The first compensation module and the second compensation module have the same structure.

6. The scanning drive circuit as described in claim 1, characterized in that, The number of virtual capacitors is one or more, and the difference between the capacitance value of the virtual capacitor combination and the total capacitance value of the pixels in the first or last row of the pixel row is within a threshold range.

7. The scanning drive circuit as described in claim 1, characterized in that, The compensation module includes virtual pixels or virtual pixel rows, which are located in the non-display area.

8. The scanning drive circuit as described in claim 7, characterized in that, The virtual pixel includes a first virtual pixel and a second virtual pixel. The output of the first-stage second shift register unit is connected to the first virtual pixel, and the output of the second-stage second shift register unit is connected to the second virtual pixel, or... The virtual pixel row includes a first virtual pixel row and a second virtual pixel row. The output of the first-stage second shift register unit is connected to the first virtual pixel row, and the output of the second-stage second shift register unit is connected to the second virtual pixel row.

9. The scanning drive circuit as described in claim 8, characterized in that, The first virtual pixel row and the second virtual pixel row have the same structure.

10. The scanning drive circuit as described in claim 8, characterized in that, The first virtual pixel row and the second virtual pixel row have the same structure as the pixel row located in the display area.

11. The scanning drive circuit as described in claim 1, characterized in that, The first shift register unit is cascaded with the second shift register unit; The first scan line signal line is electrically connected to the gate of the initialization transistor of the driving circuit of the matching pixel row. The third scan line signal line is electrically connected to the gate of the threshold compensation transistor of the driving circuit of the matching pixel row.

12. The scanning drive circuit as described in claim 11, characterized in that, The initialization transistor and the threshold compensation transistor are indium gallium zinc oxide thin film transistors.

13. An array substrate, characterized in that, Includes the scan drive circuit as described in any one of claims 1 to 12.

14. A display panel, characterized in that, Includes the array substrate as described in claim 13.

15. The display panel as claimed in claim 14, characterized in that, It includes a display area and a non-display area that at least partially surrounds the display area, with the compensation module configured in the non-display area.

Images