Display device and driving method of display panel

Abstract

The application provides a display device and a driving method of a display panel. The display device comprises the display panel, the display panel comprises M scanning lines, N data lines and M rows of pixel units, and the M scanning lines are used for performing line-by-line scanning on the M rows of pixel units according to a preset timing. The scanning end moment of a previous scanning line and the scanning start moment of a subsequent scanning line in any two adjacent scanning lines are both separated by a scanning gap. The display device further comprises Q switching modules. Each switching module comprises a first connection end and a second connection end. The first connection end is used for receiving an actual target gray scale voltage, and the second connection end is electrically connected to a corresponding data line. Each switching module is turned on during a scanning period of any scanning line to output the received actual target gray scale voltage to the corresponding data line, and is turned off during at least part of each scanning gap. The display device can avoid horizontal bright and dark line problems.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display device and a driving method for a display panel. Background Technology

[0002] The basic principle of LCD (Liquid Crystal Display) panels is to control the rotation angle of the liquid crystal by controlling the intensity of the electric field applied to it, thereby changing the luminous flux passing through the liquid crystal to achieve different grayscale levels. Combined with RGB color resist ratios, various colors can be displayed. The electric field applied to the liquid crystal is provided by storage capacitors and liquid crystal capacitors, which transmit the actual target grayscale voltage through data lines. However, due to the increasing refresh rates and resolutions of current panels, the charging time for the capacitors (storage capacitors and liquid crystal capacitors) is becoming shorter. Furthermore, the parasitic capacitance of the data lines within the panel can lead to insufficient charging of the storage and liquid crystal capacitors, causing horizontal bright and dark lines, especially during large grayscale transitions.

[0003] The basic principle of OLED (Organic Light-Emitting Diode) panel displays is to charge a storage capacitor. The voltage across the capacitor determines the current flowing through each individual OLED, thus determining its brightness. OLEDs using RGB colors work together to display various colors. Similarly, high-resolution and high-refresh-rate OLED panels, like LCD panels, also face the problem of insufficient charging due to parasitic capacitance, resulting in horizontal bright and dark lines. Summary of the Invention

[0004] In view of this, the main objective of this application is to propose a driving method for a display device and a display panel, which aims to solve the problem of horizontal bright and dark lines caused by insufficient charging due to parasitic capacitance in existing display panels.

[0005] To achieve the above objectives, a first aspect of this application provides a display device, comprising a display panel, the display panel including M scan lines, N data lines, and M rows of pixel units. The M scan lines extend along the row direction and are arranged along the column direction, the N data lines extend along the column direction and are arranged along the row direction, and the M rows of pixel units are arranged in an array and located at the intersection of the M scan lines and the N data lines. The M scan lines are used to scan the M rows of pixel units row by row according to a preset timing sequence; wherein M and N are both positive integers, and the scanning end time of the previous scan line and the scanning end time of the next scan line in any two adjacent scan lines are... Each scan start time is separated by a scan gap; the display device further includes Q switch modules, where Q is a positive integer and Q is less than or equal to N; each switch module corresponds to a data line, and each switch module includes a first connection terminal and a second connection terminal, the first connection terminal being used to receive the actual target grayscale voltage, and the second connection terminal being electrically connected to the corresponding data line; each switch module is turned on during the scanning period of any scan line to output the received actual target grayscale voltage to the corresponding data line, and is turned off at least for a portion of the time in each scan gap to stop outputting the actual target grayscale voltage to the corresponding data line.

[0006] The display device provided in this application, by setting a switch module electrically connected to the input end of the data line, controls the switch module to be turned on during the scanning period of any scan line, so as to output the corresponding target gray level voltage to the data line through the turned-on switch module, and controls the switch module to be turned off during at least part of the time period of each scan interval, thereby stopping the output voltage to the data line. In this way, the switch module cuts off the data line during at least part of the time period from the completion of charging of the previous row of pixel units to the charging of the current row of pixel units, which can eliminate the influence of the actual target gray level voltage of the previous row of pixel units on the current row of pixel units, thereby ensuring that the current row of pixel units can be charged to the corresponding actual target gray level voltage, and avoiding the problem of horizontal bright and dark lines on the display panel.

[0007] In some embodiments, Q equals N, and the Q switch modules correspond one-to-one with the N data lines.

[0008] In some embodiments, the display device further includes a timing control module, which outputs a switch control signal to control each of the switch modules to be turned on during the scanning period of any scan line and to be turned off during at least a portion of the scanning interval.

[0009] In some embodiments, the display device further includes a column driving module located on one side of the display panel in the column direction; the N switch modules are all disposed in the display panel and connected between the column driving module and the corresponding data line; the column driving module is electrically connected to the first connection terminal of each of the switch modules and is used to output the corresponding actual target grayscale voltage to the first connection terminal of each of the switch modules.

[0010] In some embodiments, each of the switch modules further includes a control terminal; the display device further includes a level conversion module, which is electrically connected to the timing control module and the control terminal of each of the switch modules, and is used to receive the switch control signal output by the timing control module, perform level conversion on the switch control signal, and output the level-converted switch control signal to the control terminal of each of the switch modules, so as to control each of the switch modules to be turned on during the scanning period of any scan line, and to be turned off during at least a portion of the time period of each scan interval.

[0011] In some embodiments, the display device further includes a column driving module located on one side of the display panel in the column direction; the N switch modules are disposed in the column driving module, and the column driving module further includes N output stage circuits corresponding one-to-one with the N switch modules, each output stage circuit being electrically connected to a first connection terminal of the corresponding switch module and used to output a corresponding actual target grayscale voltage to the first connection terminal of the corresponding switch module; each switch module further includes a control terminal for receiving the switch control signal, and each switch module is turned on during the scanning period of any scan line in response to the switch control signal, and is turned off during at least a portion of the time period in each scan interval.

[0012] In some embodiments, the timing control module is further configured to receive an image signal, determine the initial target grayscale voltage of each pixel unit based on the image signal, and determine the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column based on the magnitude relationship between the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit located in the (i-1)-th row and j-th column; wherein, 2≤i≤M, 1≤j≤N.

[0013] In some embodiments, the timing control module is specifically configured to increase the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column to obtain the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column when the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column is higher than the initial target grayscale voltage of the pixel unit located in the (i-1)-th row and j-th column; and to decrease the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column to obtain the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column when the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column is lower than the initial target grayscale voltage of the pixel unit located in the (i-1)-th row and j-th column.

[0014] A second aspect of this application also provides a driving method for a display panel, the display panel including M scan lines, N data lines, and M rows of pixel units. The M scan lines extend along the row direction and are arranged along the column direction, the N data lines extend along the column direction and are arranged along the row direction, and the M rows of pixel units are arranged in an array and located at the intersection of the M scan lines and the N data lines. The M scan lines are used to scan the M rows of pixel units line by line according to a preset timing sequence. The driving method includes: receiving an image signal and determining the initial position of each pixel unit based on the image signal. The target grayscale voltage; and, based on the magnitude relationship between the initial target grayscale voltage of the pixel unit located in the (i-1)th row and the jth column and the initial target grayscale voltage of the pixel unit located in the (i-2)th row and the jth column, and the magnitude relationship between the initial target grayscale voltage of the pixel unit located in the ith row and the jth column and the initial target grayscale voltage of the pixel unit located in the (i-1)th row and the jth column, the actual target grayscale voltage of the pixel unit located in the ith row and the jth column is determined; wherein, the actual target grayscale voltage of each pixel unit is used to drive the display of that pixel unit, 3≤i≤M, 1≤j≤N.

[0015] In some embodiments, determining the actual target grayscale voltage of a pixel unit located in the i-th row and j-th column based on the magnitude relationship between the initial target grayscale voltage of the pixel unit located in the (i-1)th row and j-th column and the initial target grayscale voltage of the pixel unit located in the (i-2)th row and j-th column, and the magnitude relationship between the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit located in the (i-1)th row and j-th column, includes: reducing the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column when the first difference obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-1th row and j-th column from the initial target grayscale voltage of the pixel unit located in the i-2th row and j-th column is greater than a first preset threshold, and when the second difference obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column from the initial target grayscale voltage of the pixel unit located in the i-1th row and j-th column is less than or equal to zero and greater than a second preset threshold. The initial target grayscale voltage of the pixel unit located in the i-th row and j-th column is used to obtain the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column; wherein, the first preset threshold is greater than zero, and the second preset threshold is less than zero; and, when the first difference obtained by subtracting the initial target grayscale voltage of the pixel unit located in the (i-1)-th row and j-th column from the initial target grayscale voltage of the pixel unit located in the (i-2)-th row and j-th column is less than the third preset threshold, and the second difference obtained by subtracting the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column from the initial target grayscale voltage of the pixel unit located in the (i-1)-th row and j-th column is greater than or equal to zero and less than the fourth preset threshold, the initial target grayscale voltage of the pixel unit located in the i-th row and j-th column is increased to obtain the actual target grayscale voltage of the pixel unit located in the i-th row and j-th column; wherein, the third preset threshold is less than zero, and the fourth preset threshold is greater than zero.

[0016] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the structure of a pixel unit in an LCD display panel provided in an embodiment of this application;

[0018] Figure 2 This is a schematic diagram of the structure of a pixel unit in an OLED display panel provided in an embodiment of this application;

[0019] Figure 3 This is a timing diagram of a first type of driving signal for a display panel provided in an embodiment of this application;

[0020] Figure 4 This is a second type of driving signal timing diagram for a display panel provided in an embodiment of this application;

[0021] Figure 5 This is a schematic diagram of the structure of the display device provided in the embodiments of this application;

[0022] Figure 6 This is a third driving signal timing diagram for a display panel provided in an embodiment of this application;

[0023] Figure 7 This is a schematic diagram of the column-driven module provided in an embodiment of this application;

[0024] Figure 8 A flowchart illustrating the driving method for a display panel provided in an embodiment of this application;

[0025] Figure 9 This is a timing diagram of the fourth driving signal for a display panel provided in an embodiment of this application.

[0026] The annotations in the attached figures are explained as follows:

[0027] Display device 1

[0028] Display panel 100

[0029] Column drive module 21

[0030] Timing control module 22

[0031] Level conversion module 23

[0032] Data cable 102

[0033] Scan line 101

[0034] Pixel units P1, P2, P

[0035] Transistors T11, T12, T13

[0036] Pixel Electrode 11

[0037] First common electrode 12

[0038] Second common electrode 13

[0039] Liquid crystal capacitor Clc

[0040] Storage capacitor Cst

[0041] Switch module 10

[0042] Switch control signals TTL, TTL1

[0043] Output stage circuit 211

[0044] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0045] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0046] Furthermore, the terms "first," "second," etc., used in this specification are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] It should be noted that, where there is no conflict, the features in the embodiments of this application can be combined with each other.

[0048] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a pixel unit in an LCD display panel in the related art. In an LCD display panel, a pixel unit P1 typically includes a pixel electrode 11, a first common electrode 12, a second common electrode 13, and a transistor T11.

[0049] The first common electrode 12 is used to receive the first common voltage Vcom1 (also known as the color filter substrate-side common voltage V). CF_COM The second common electrode 13 is used to receive the second common voltage Vcom2 (also known as the array substrate-side common voltage V). A_COM The transistor T11 includes a control terminal, a first connection terminal, and a second connection terminal. The control terminal of the transistor T11 is used to be electrically connected to a corresponding scan line 101 to receive a corresponding scan signal. The first connection terminal of the transistor T11 is used to be electrically connected to a corresponding data line 102 to receive a corresponding data voltage Vdata (also known as grayscale voltage). The first common electrode 12 and the pixel electrode 11 are arranged at a distance from each other to form a liquid crystal capacitor Clc. The second common electrode 13 and the pixel electrode 11 are arranged at a distance from each other to form a storage capacitor Cst.

[0050] During operation, the transistor T1 turns on when the received scan signal is the on-state voltage, thereby writing the data voltage Vdata provided by the data line 102 into the pixel electrode 11, so that there is a voltage difference between the pixel electrode 11 and the first common electrode 12 and an electric field is generated, thereby driving the liquid crystal molecules between the pixel electrode 11 and the first common electrode 12 to deflect, so that the pixel unit P1 displays the gray level corresponding to the data voltage Vdata.

[0051] However, as the refresh rate and resolution of panels are getting higher and higher, the charging time for the storage capacitor Cst and the liquid crystal capacitor Clc is getting shorter and shorter. In addition, the data line 102 has parasitic capacitance in its traces within the panel. Therefore, when the grayscale switching is large, the storage capacitor and liquid crystal capacitor are easily undercharged, which can cause horizontal bright and dark lines.

[0052] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a pixel unit in an OLED display panel in related technologies. In an OLED display panel, the pixel unit P2 typically includes transistor T12, transistor T13, storage capacitor Cst, and light-emitting device OLED.

[0053] In this configuration, the cathode of the OLED is electrically connected to the reference voltage terminal VSS to receive the reference voltage VSS; the anode of the OLED is electrically connected to the source of the transistor T13; the drain of the transistor T13 receives the driving voltage VDD; the gate of the transistor T13 is electrically connected to the source of the transistor T12; the drain of the transistor T12 is electrically connected to a corresponding data line 102 to receive the corresponding data voltage Vdata; and the gate of the transistor T12 is electrically connected to a corresponding scan line 101 to receive the corresponding scan signal. The first terminal of the storage capacitor Cst is electrically connected to the gate of the transistor T13, and the second terminal of the storage capacitor Cst is electrically connected to the drain of the transistor T13. For example, when transistor T12 receives the scan signal, it turns on. The data voltage Vdata on the data line 102 charges the storage capacitor Cst through transistor T11, thereby adjusting the voltage at the first terminal of the storage capacitor Cst to the data voltage Vdata. Transistor T13 drives the light-emitting device OLED to emit light based on the data voltage Vdata received at its gate. At this time, the gate-source voltage Vgs of transistor T13 is Vg - Vs = Vdata - Voled, where Voled is the anode of the light-emitting device OLED and the conduction voltage between the anode and cathode of the light-emitting device OLED2 when it emits light. The driving current Ids flowing through transistor T13 has the following relationship with the gate-source voltage Vgs of transistor T13:

[0054] Ids = (K / 2)(Vgs - Vth) 2 = (K / 2)(Vdata-Voled-Vth) 2

[0055] Where K = Cox × μ × W / L, Cox is the gate capacitance per unit area; μ is the channel electron mobility; W / L is the width-to-length ratio of the channel of the transistor T13; and Vth is the threshold voltage of the transistor T13.

[0056] Similarly, for OLED display panels, as the refresh rate and resolution of the panels are getting higher and higher, the charging time for the storage capacitor Cst is getting shorter and shorter. In addition, the data line 102 has parasitic capacitance in its routing within the panel. Therefore, when the grayscale switching is large, the storage capacitor Cst is easily undercharged, which can cause horizontal bright and dark lines.

[0057] Please see Figure 3 , Figure 3 This is a timing diagram of a first type of driving signal for a display panel provided in an embodiment of this application. To address the problem of horizontal bright and dark lines appearing easily in existing display panels, a Line Over Drive (LOD) algorithm has been proposed. This algorithm involves a Source Driver IC comparing the initial target grayscale voltage of the previous row with that of the current row, correcting the initial target grayscale voltage of the current row (increasing / decreasing the initial target grayscale voltage), obtaining the corrected target grayscale voltage, and outputting the corrected target grayscale voltage to drive the display panel for display.

[0058] Specifically, such as Figure 3 As shown, taking the grayscale voltage on the j-th column data line as an example, assuming the initial target grayscale voltages of the pixel units in the j-th column, from i-2 to i+1, are Dj_i-2, Dj_i-1, Dj_i, and Dj_i+1, respectively, the parasitic capacitance on the j-th column data line causes a grayscale voltage delay. Therefore, when the difference in grayscale voltage between rows is large, if the initial target grayscale voltages Dj_i-2 to Dj_i+1 are sequentially output to the j-th column data line, the grayscale voltage on the j-th column data line may not reach the corresponding initial target grayscale voltage at the end of the scan line scan. This results in pixel units in different rows not being bright enough or dark enough. When several rows display similar grayscale values ​​consecutively, the later rows can reach the initial target grayscale voltage, thus forming a problem of displaying bright and dark lines.

[0059] The Line OD algorithm compares Dj_i-2 and Dj_i-1, finding that Dj_i-1 is greater than Dj_i-2 and the difference between them is large. This increases Dj_i-1 to obtain the corrected target grayscale voltage Dj_i-1' for the pixel unit located in the j-th column and i-1-th row. This ensures that the storage capacitor in the pixel unit located in the j-th column and i-1-th row can be charged to Dj_i-1 at the end of the i-1-th row scan. Conversely, the Line OD algorithm compares Dj_i-1 and Dj_i, finding that Dj_i is less than Dj_i-1 and the difference between them is large. This decreases Dj_i to obtain the corrected target grayscale voltage Dj_i' for the pixel unit located in the j-th column and i-th row. This ensures that the storage capacitor in the pixel unit located in the j-th column and i-th row can be charged to Dj_i at the end of the i-th row scan. The OD algorithm compares Dj_i and Dj_i+1 and finds that Dj_i+1 is greater than Dj_i and the difference between the two is large. This improves Dj_i+1 to obtain the corrected target grayscale voltage Dj_i+1' of the pixel unit located in the j-th column and i-th row. This ensures that the storage capacitor in the pixel unit located in the j-th column and i-th row can be charged to Dj_i+1 when the scan line in the i+1-th row ends.

[0060] However, the line OD algorithm has a problem: such as Figure 4 As shown, assuming the initial target grayscale voltages of the pixel units located in column j and rows i-2 to i+1 are Dj_i-2, Dj_i-1, Dj_i, and Dj_i+1 respectively, where Dj_i-1 = Dj_i = Dj_i+1 > Dj_i-2, the line OD algorithm compares Dj_i-2 and Dj_i-1 to find that Dj_i-1 is greater than Dj_i-2 and the difference between them is large. This leads to an increase in Dj_i-1, resulting in the corrected target grayscale voltage Dj_i-1' for the pixel unit located in column j and row i-1. This ensures that the storage capacitor in the pixel unit located in column j and row i-1 can be charged to Dj_i-1 when the scan line in row i-1 ends. After the scan line in row i-1 ends but before the scan line in row i is turned on, the voltage output by the Source Driver IC to the data line in column j remains Dj_i-1'. Thus, when the charging of the (i-1)th row ends, the voltage on the data line of the jth column will continue to rise to a level greater than Dj_i-1. However, since Dj_i-1 = Dj_i = Dj_i+1, the line OD algorithm will not correct Dj_i and Dj_i+1. Consequently, when the scan line of the i-th row begins scanning, due to the parasitic capacitance of the data line, the Dj_i-1 output by the Source Driver IC is insufficient to pull back the voltage stored on the data line. Figure 4As shown, when the scan of the i-th row ends, the voltage on the j-th column data line cannot return to the initial target grayscale voltage Dj_i, and thus the storage capacitor in the pixel unit of the j-th column and the (i-1)-th row will be charged to a level higher than its initial target grayscale voltage Dj_i, so the pixel unit of the i-th row will appear as a bright line.

[0061] To address the problem of insufficient charging caused by parasitic capacitance in existing display panels, resulting in horizontal bright and dark lines, this application provides a display device 1. Please refer to [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0062] like Figure 5 As shown, the display device 1 includes a display panel 100, which includes M scan lines 101, N data lines 102, and M rows of pixel units P. The M scan lines 101 extend along the row direction and are arranged along the column direction, the N data lines 102 extend along the column direction and are arranged along the row direction, and the M rows of pixel units P are arranged in an array and located at the intersection of the M scan lines 101 and the N data lines 102.

[0063] The M scan lines 101 are used to scan the M rows of pixel units P line by line according to a preset timing sequence. Here, M and N are both positive integers, and there is a scan gap between the end time of the scan of the previous scan line 101 and the start time of the scan of the next scan line 101 in any two adjacent scan lines 101.

[0064] The display device 1 further includes Q switch modules 10, where Q is a positive integer and Q is less than or equal to N. Each switch module 10 corresponds to a data line 102, and each switch module 10 includes a first connection terminal and a second connection terminal. The first connection terminal is used to receive the actual target grayscale voltage, and the second connection terminal is electrically connected to the corresponding data line 102. Each switch module 10 is turned on during the scanning period of any scan line 101 to output the received actual target grayscale voltage to the corresponding data line 102, and is turned off at least for a portion of the time during each scanning interval to stop outputting the actual target grayscale voltage to the corresponding data line 102.

[0065] The display device 1 provided in this application, by setting a switch module 10 electrically connected to the input terminal of the data line 102, controls the switch module 10 to be turned on during the scanning period of any scan line 101, so as to output the corresponding target gray level voltage to the data line 102 through the turned-on switch module 10, and controls the switch module 10 to be turned off during at least part of the time period of each scanning interval, thereby stopping the output voltage to the data line 102. In this way, the switch module 10 cuts off the data line 102 during at least part of the time period from the completion of charging of the previous row pixel unit P to the charging of the current row pixel unit P, which can eliminate the influence of the actual target gray level voltage of the previous row pixel unit P on the current row pixel unit P, thereby ensuring that the current row pixel unit P can be charged to the corresponding actual target gray level voltage, and avoiding the problem of horizontal bright and dark lines appearing on the display panel 100.

[0066] For example, the switching module 10 includes, but is not limited to, switching transistors such as thin film transistors (TFTs), triodes, and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

[0067] In some embodiments, Q equals N, and the Q switch modules 10 correspond one-to-one with the N data lines 102.

[0068] It should be noted that when the switch module 10 is provided for each column of data lines 102, it can be ensured that each pixel unit P in each column of pixel units P is not affected by the actual target grayscale voltage of the previous pixel unit P during charging, resulting in a better display effect for the display device 1. Of course, in other embodiments, to save costs, the switch module 10 can be provided only for some data lines 102.

[0069] In some embodiments, the timing control module 22 is further configured to receive an image signal, determine the initial target grayscale voltage of each pixel unit P based on the image signal, and determine the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column based on the magnitude relationship between the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the (i-1)-th row and j-th column. Wherein, 2≤i≤M, 1≤j≤N. The actual target grayscale voltage of the pixel unit P in the first row can be the same as the initial target grayscale voltage.

[0070] Further, the timing control module 22 is specifically used to increase the initial target gray level voltage of the pixel unit P located in the i-th row and j-th column to obtain the actual target gray level voltage of the pixel unit P located in the i-th row and j-th column when the initial target gray level voltage of the pixel unit P located in the i-1-th row and j-th column is higher than the initial target gray level voltage of the pixel unit P located in the i-th row and j-th column; and to decrease the initial target gray level voltage of the pixel unit P located in the i-th row and j-th column to obtain the actual target gray level voltage of the pixel unit P located in the i-th row and j-th column when the initial target gray level voltage of the pixel unit P located in the i-th row and j-th column is lower than the initial target gray level voltage of the pixel unit P located in the i-1-th row and j-th column.

[0071] For example, please refer to Figure 6 , Figure 6 This is a third driving signal timing diagram for a display panel provided in an embodiment of this application. Taking the j-th column data line 102 as an example, assuming that the initial target grayscale voltages of the pixel units P located in the j-th column and in rows i-2 to i+1 are Dj_i-2, Dj_i-1, Dj_i, and Dj_i+1 respectively, where Dj_i-1 = Dj_i = Dj_i+1 > Dj_i-2, the timing control module 22 compares Dj_i-2 and Dj_i-1 to find that Dj_i-1 is greater than Dj_i-2, thereby increasing Dj_i-1 to obtain the corrected target grayscale voltage Dj_i-1' of the pixel unit P located in the j-th column and in row i-1. This ensures that when the scan line 101 in row i-1 is turned off, the storage capacitor in the pixel unit P located in the j-th column and in row i-1 can be charged to Dj_i-1. Since Dj_i-1 = Dj_i = Dj_i+1, the timing control module 22 will not adjust Dj_i and Dj_i+1, thereby directly determining Dj_i as the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column, and directly determining Dj_i+1 as the initial target grayscale voltage of the pixel unit P located in the (i+1)-th row and j-th column.

[0072] In some embodiments, the timing control module 22 is specifically configured to: determine a grayscale voltage adjustment value based on the difference between the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the (i-1)-th row and j-th column, and a first preset correspondence, when the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column is higher than that of the pixel unit P located in the (i-1)-th row and j-th column, and a first preset correspondence; and add the grayscale voltage adjustment value to the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column to obtain the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column. Wherein, the grayscale voltage adjustment value > 0, and the first preset correspondence includes a one-to-one correspondence between multiple difference ranges and multiple grayscale voltage adjustment values.

[0073] The timing control module 22 is further configured to, when the initial target grayscale voltage of pixel unit P located in row i and column j is lower than the initial target grayscale voltage of pixel unit P located in row (i-1) and column j, determine a grayscale voltage adjustment value based on the difference between the initial target grayscale voltage of pixel unit P located in row i and column j and the initial target grayscale voltage of pixel unit P located in row (i-1) and column j, and the first preset correspondence, and subtract the grayscale voltage adjustment value from the initial target grayscale voltage of pixel unit P located in row i and column j to obtain the actual target grayscale voltage of pixel unit P located in row i and column j. In other embodiments, the actual target grayscale voltage of each pixel unit P can also be determined in other ways, which are not limited here.

[0074] In some embodiments, the display device 1 further includes a timing control module 22, which is used to output a switch control signal TTL to control each of the switch modules 10 to be turned on during the scanning period of any scan line 101, and to be turned off during at least a portion of the time period of each scan interval.

[0075] For example, the turn-off voltage of the switch control signal TTL is 0V and the turn-on voltage is 3.3V. That is, when the voltage of the switch control signal TTL is 0V, all Q switch modules 10 are turned off in response to the switch control signal TTL, and when the voltage of the switch control signal TTL is 3.3V, all Q switch modules 10 are turned on in response to the switch control signal TTL.

[0076] In some embodiments, the display device 1 further includes a column driving module 21, which is located on one side of the display panel 100 in the column direction. The column driving module 21 is electrically connected to a first connection terminal of each of the switch modules 10 and is used to output a corresponding actual target grayscale voltage to the first connection terminal of each of the switch modules 10. The column driving module 21 may include at least one Source Driver IC.

[0077] In some embodiments, the N switch modules 10 are all disposed in the display panel 100 and connected between the column drive module 21 and the corresponding data line 102.

[0078] In some embodiments, each of the switch modules 10 is turned off at the end of the scan of the (i-1)th row scan line 101 and turned on at the beginning of the output of the actual target grayscale voltage of the i-th row pixel unit P by the column drive module 21. Wherein, 2≤i≤M.

[0079] like Figure 6 As shown, at this time, since the switch module 10 is turned off at the end of the scan of the (i-1)th row scan line 101, the jth column data line 102 stops receiving Dj_i-1', and its voltage no longer continues to rise but remains at Dj_i-1. Furthermore, since Dj_i-1 = Dj_i = Dj_i+1, the timing control module 22 does not correct Dj_i and Dj_i+1. Therefore, when the column driving module 21 starts to output the actual target grayscale voltage Dj_i of the i-th row pixel unit P, the switch module 10 is turned on, and the j-th column data line 102 receives Dj_i from the column driving module 21 through the turned-on switch module. Thus, during the scan of the i-th row scan line 101, the actual voltage clock of the j-th column data line 102 remains at Dj_i. As a result, the pixel unit P located in the j-th column and i-th row can be charged to Dj_i and the target grayscale can be displayed.

[0080] In other embodiments, each of the switch modules 10 may be turned off at the end of the scan of the (i-1)th row of scan lines 101 and turned on at the start of the scan of the i-th row of scan lines 101. To ensure that the pixel unit P can be fully charged, each of the switch modules 10 may also be turned off after a preset time after the end of the scan of the (i-1)th row of scan lines 101, which is not limited here.

[0081] In some embodiments, the switching module 10 may be a thin-film transistor (TFT), thus enabling it to be manufactured in the same process as other TFTs in the display panel 100. Since the on-state voltage of a TFT is typically above 20V and the off-state voltage is typically below 0V, in this embodiment, the TTL switching control signal output by the timing control module 22 needs to undergo level conversion to control the normal on / off state of the switching module 10.

[0082] Specifically, the display device 1 further includes a level conversion module 23, which is electrically connected to the timing control module 22 and the control terminal of each of the switch modules 10. The level conversion module 23 is used to receive the switch control signal TTL output by the timing control module 22, perform level conversion on the switch control signal TTL, and output the level-converted switch control signal TTL1 to the control terminal of each of the switch modules 10, so as to control each of the switch modules 10 to be turned on during the scanning period of any scan line 101, and to be turned off during at least a part of the time period of each scan interval.

[0083] Please see Figure 7 , Figure 7 This is a schematic diagram of the column driving module provided in an embodiment of this application. In some embodiments, the N switch modules 10 may also be disposed in the column driving module 21. The column driving module 21 further includes N output stage circuits 211 corresponding one-to-one with the N switch modules 10. Each output stage circuit is electrically connected to the first connection terminal of the corresponding switch module 10 and is used to output the corresponding actual target grayscale voltage to the first connection terminal of the corresponding switch module 10. Each switch module 10 also includes a control terminal for receiving the switch control signal TTL. Each switch module 10 is turned on during the scanning period of any scan line 101 in response to the switch control signal TTL, and is turned off during at least a portion of the time period in each scan interval.

[0084] In this embodiment, the switching module 10 can be a MOSFET. Since the driving voltage of the MOSFET is low, the switching control signal TTL output by the timing control module 22 can directly drive the switching module 10 without level conversion, making the circuit structure simpler.

[0085] The output stage circuit 211 includes a push-pull circuit, specifically comprising a high-side transistor Th and a low-side transistor Tl. The high-side transistor Th is a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor), and the low-side transistor Tl is an N-channel MOSFET. The gates of the high-side transistor Th and the low-side transistor Tl are connected together to form the input terminal of the output stage circuit 211, receiving the corresponding actual target grayscale voltage. The drain of the high-side transistor Th receives a high level provided by the voltage source VA. The sources of the high-side transistor Th and the low-side transistor Tl are connected together to form the output terminal of the output stage circuit 211, outputting the corresponding actual target grayscale voltage to the first connection terminal of the corresponding switching module 10. The drain of the low-side transistor Tl is grounded.

[0086] Please see Figure 8 , Figure 8 This is a flowchart illustrating a driving method for a display panel provided in an embodiment of this application. This application also provides a driving method for a display panel 100, the display panel 100 including M scan lines 101, N data lines 102, and M rows of pixel units P. The M scan lines 101 extend along the row direction and are arranged along the column direction, the N data lines 102 extend along the column direction and are arranged along the row direction, and the M rows of pixel units P are arranged in an array and located at the intersection of the M scan lines 101 and the N data lines 102.

[0087] The driving method includes:

[0088] Step S1: Receive the image signal and determine the initial target grayscale voltage of each pixel unit P based on the image signal; and,

[0089] Step S2: Based on the relationship between the initial target grayscale voltage of pixel unit P located in row (i-1) and column j and the initial target grayscale voltage of pixel unit P located in row (i-2) and column j, and the relationship between the initial target grayscale voltage of pixel unit P located in row i and column j and the initial target grayscale voltage of pixel unit P located in row i and column j, determine the actual target grayscale voltage of pixel unit P located in row i and column j; wherein, the actual target grayscale voltage of each pixel unit P is used to drive the display of pixel unit P, 3≤i≤M, 1≤j≤N.

[0090] The display panel driving method provided in this application combines the change trend of the initial target grayscale voltage of the previous two rows of pixel units P to the initial target grayscale voltage of the previous row of pixel units P and the change trend of the initial target grayscale voltage of the previous row of pixel units P to the initial target grayscale voltage of the current row of pixel units P to correct the initial target grayscale voltage of the current row of pixel units P. This can eliminate the influence of the actual target grayscale voltage of the previous row of pixel units P on the current row of pixel units P, thereby ensuring that the current row of pixel units P can be charged to the corresponding actual target grayscale voltage and avoiding the problem of horizontal bright and dark lines appearing on the display panel 100.

[0091] In some embodiments, determining the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column based on the magnitude relationship between the initial target grayscale voltage of the pixel unit P located in the (i-1)th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the (i-2)th row and j-th column, and the magnitude relationship between the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column and the initial target grayscale voltage of the pixel unit P located in the (i-1)th row and j-th column, includes:

[0092] When the first difference between the initial target grayscale voltage of pixel unit P located in row (i-1) and column j and the initial target grayscale voltage of pixel unit P located in row (i-2) and column j is greater than a first preset threshold, and the second difference between the initial target grayscale voltage of pixel unit P located in row i and column j and the initial target grayscale voltage of pixel unit P located in row i-1 and column j is less than or equal to zero and greater than a second preset threshold, the initial target grayscale voltage of pixel unit P located in row i and column j is reduced to obtain the actual target grayscale voltage of pixel unit P located in row i and column j; wherein, the first preset threshold is greater than zero, and the second preset threshold is less than zero; and,

[0093] When the first difference between the initial target grayscale voltage of pixel unit P located in row (i-1) and column j and the initial target grayscale voltage of pixel unit P located in row (i-2) and column j is less than a third preset threshold, and the second difference between the initial target grayscale voltage of pixel unit P located in row i and column j and the initial target grayscale voltage of pixel unit P located in row i-1 and column j is greater than or equal to zero and less than a fourth preset threshold, the initial target grayscale voltage of pixel unit P located in row i and column j is increased to obtain the actual target grayscale voltage of pixel unit P located in row i and column j; wherein the third preset threshold is less than zero and the fourth preset threshold is greater than zero.

[0094] For example, please refer to Figure 9 , Figure 9This is a fourth driving signal timing diagram for a display panel provided in an embodiment of this application. Taking the data line 102 in the j-th column as an example, assuming that the initial target grayscale voltages of the pixel unit P located in the j-th column and in the (i-2)th to (i+1)th rows are Dj_i-2, Dj_i-1, Dj_i, and Dj_i+1 respectively, where Dj_i-1 = Dj_i = Dj_i+1 > Dj_i-2, the timing control module 22 compares Dj_i-2 and Dj_i-1 to find that Dj_i-1 is greater than Dj_i-2, thereby increasing Dj_i-1 to obtain the corrected target grayscale voltage Dj_i-1' of the pixel unit P located in the j-th column and in the (i-1)th row. This ensures that when the scan line 101 in the (i-1)th row is turned off, the storage capacitor in the pixel unit P located in the j-th column and in the (i-1)th row can be charged to Dj_i-1. The timing control module 22 compares Dj_i-2 and Dj_i-1 and finds that the first difference obtained by subtracting Dj_i-2 from Dj_i-1 is greater than the first preset threshold. It also compares Dj_i-1 and Dj_i and finds that the second difference obtained by subtracting Dj_i from Dj_i-1 is less than or equal to zero and greater than the second preset threshold. Therefore, it reduces Dj_i to obtain Dj_i'. In this way, the output Dj_i' charges the pixel unit P located in the j-th column and i-th row, which can pull down the voltage of the j-th column data line 102 to Dj_i, thereby ensuring that the pixel is charged to Dj_i.

[0095] In some embodiments, reducing the initial target grayscale voltage of pixel unit P located in the i-th row and j-th column to obtain the actual target grayscale voltage of pixel unit P located in the i-th row and j-th column includes:

[0096] The grayscale voltage adjustment value is determined based on the first difference, the second difference, and the second preset correspondence. The actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column is obtained by subtracting the grayscale voltage adjustment value from the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column. Wherein, the grayscale voltage adjustment value > 0, and the second preset correspondence includes a correspondence between multiple first difference ranges, multiple second difference ranges, and multiple grayscale voltage adjustment values.

[0097] The method of increasing the initial target grayscale voltage of pixel unit P located in row i and column j to obtain the actual target grayscale voltage of pixel unit P located in row i and column j includes:

[0098] The grayscale voltage adjustment value is determined based on the first difference, the second difference, and the second preset correspondence, and the actual target grayscale voltage of the pixel unit P located in the i-th row and j-th column is obtained by adding the grayscale voltage adjustment value to the initial target grayscale voltage of the pixel unit P located in the i-th row and j-th column.

[0099] Based on the same inventive concept, this application also provides a computer-readable storage medium storing a computer program, which is executed by a processor to implement the steps in the display panel driving method described in any of the above embodiments.

[0100] The computer storage medium in this application embodiment can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0101] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of sending, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0102] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to wireless, wire, optical fiber, RF, etc., or any suitable combination thereof.

[0103] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0104] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A display device comprising a display panel, the display panel comprising M scan lines, N data lines and M rows of pixel units, the M scan lines extending along a row direction and arranged along a column direction, the N data lines extending along a column direction and arranged along a row direction, the M rows of pixel units arranged in an array and located at intersections of the M scan lines and the N data lines, the M scan lines being configured to scan the M rows of pixel units row by row according to a preset timing; wherein, M, N are both positive integers, and the scanning end time of a previous scanning line and the scanning start time of a next scanning line in any two adjacent scanning lines are separated by a scanning gap, characterized in that, The display device further comprises Q switch modules, wherein Q is a positive integer and Q is less than or equal to N; each of the switch modules corresponds to a data line; each of the switch modules comprises a first connection end and a second connection end; the first connection end is used for receiving an actual target gray scale voltage; the second connection end is electrically connected to the corresponding data line; each of the switch modules is turned on during the scanning period of any scanning line to output the received actual target gray scale voltage to the corresponding data line, and is turned off during at least part of the scanning gap to stop outputting the actual target gray scale voltage to the corresponding data line. The display device further comprises a timing control module, which is used for outputting a switch control signal to control each of the switch modules to be turned on during the scanning period of any scanning line and to be turned off during at least part of the scanning gap.

2. The display device of claim 1, wherein, Q is equal to N, and the Q switch modules correspond one-to-one to the N data lines.

3. The display device of claim 2, wherein, The display device further comprises a column driving module located on one side of the display panel in the column direction; N switch modules are arranged in the display panel and connected between the column driving module and the corresponding data lines; the column driving module is electrically connected to the first connection end of each of the switch modules and is used for outputting a corresponding actual target gray scale voltage to the first connection end of each of the switch modules.

4. The display device of claim 3, wherein, Each of the switch modules further comprises a control end; the display device further comprises a level conversion module electrically connected to the timing control module and the control end of each of the switch modules, and used for receiving the switch control signal output by the timing control module, performing level conversion on the switch control signal, and outputting the level-converted switch control signal to the control end of each of the switch modules to control each of the switch modules to be turned on during the scanning period of any scanning line and to be turned off during at least part of the scanning gap.

5. The display device of claim 2, wherein, The display device further comprises a column driving module located on one side of the display panel in the column direction; N switch modules are arranged in the column driving module; the column driving module further comprises N output stage circuits corresponding one-to-one to the N switch modules; each of the output stage circuits is electrically connected to the first connection end of the corresponding switch module and is used for outputting a corresponding actual target gray scale voltage to the first connection end of the corresponding switch module; each of the switch modules further comprises a control end for receiving the switch control signal; each of the switch modules is turned on during the scanning period of any scanning line and is turned off during at least part of the scanning gap in response to the switch control signal.

6. The display device of claim 2, wherein, The timing control module is also configured to receive an image signal, determine an initial target gray scale voltage of each pixel unit according to the image signal, and determine an actual target gray scale voltage of a pixel unit located at the i-th row and the j-th column according to a size relationship between the initial target gray scale voltage of the pixel unit located at the i-th row and the j-th column and the initial target gray scale voltage of a pixel unit located at the (i-1)-th row and the j-th column, where 2≤i≤M and 1≤j≤N.

7. The display device of claim 6, wherein, The timing control module is specifically configured to, when the initial target gray scale voltage of the pixel unit located at the i-th row and the j-th column is higher than the initial target gray scale voltage of the pixel unit located at the (i-1)-th row and the j-th column, increase the initial target gray scale voltage of the pixel unit located at the i-th row and the j-th column to obtain the actual target gray scale voltage of the pixel unit located at the i-th row and the j-th column, and when the initial target gray scale voltage of the pixel unit located at the i-th row and the j-th column is lower than the initial target gray scale voltage of the pixel unit located at the (i-1)-th row and the j-th column, decrease the initial target gray scale voltage of the pixel unit located at the i-th row and the j-th column to obtain the actual target gray scale voltage of the pixel unit located at the i-th row and the j-th column.

8. A driving method of a display panel, the display panel comprising M scan lines, N data lines and M rows of pixel units, the M scan lines extending along a row direction and arranged along a column direction, the N data lines extending along the column direction and arranged along the row direction, the M rows of pixel units arranged in an array and located at intersection positions of the M scan lines and the N data lines, the M scan lines being configured to perform line-by-line scanning on the M rows of pixel units according to a preset timing sequence, characterized in that, The driving method comprises: receiving an image signal, and determining an initial target gray scale voltage of each pixel unit according to the image signal; and determining an actual target gray scale voltage of a pixel unit located at the i-th row and the j-th column according to a size relationship between the initial target gray scale voltage of the pixel unit located at the (i-1)-th row and the j-th column and the initial target gray scale voltage of a pixel unit located at the (i-2)-th row and the j-th column, and a size relationship between the initial target gray scale voltage of the pixel unit located at the i-th row and the j-th column and the initial target gray scale voltage of the pixel unit located at the (i-1)-th row and the j-th column, where 3≤i≤M and 1≤j≤N; The determining of the actual target gray scale voltage of the pixel unit located at the i-th row and the j-th column according to the size relationship between the initial target gray scale voltage of the pixel unit located at the (i-1)-th row and the j-th column and the initial target gray scale voltage of the pixel unit located at the (i-2)-th row and the j-th column, and the size relationship between the initial target gray scale voltage of the pixel unit located at the i-th row and the j-th column and the initial target gray scale voltage of the pixel unit located at the (i-1)-th row and the j-th column comprises: when a first difference value obtained by subtracting the initial target gray scale voltage of the pixel unit located at the (i-2)-th row and the j-th column from the initial target gray scale voltage of the pixel unit located at the (i-1)-th row and the j-th column is greater than a first preset threshold value, and a second difference value obtained by subtracting the initial target gray scale voltage of the pixel unit located at the (i-1)-th row and the j-th column from the initial target gray scale voltage of the pixel unit located at the i-th row and the j-th column is less than or equal to zero and greater than a second preset threshold value, decreasing the initial target gray scale voltage of the pixel unit located at the i-th row and the j-th column to obtain the actual target gray scale voltage of the pixel unit located at the i-th row and the j-th column, where the first preset threshold value is greater than zero and the second preset threshold value is less than zero; and When a first difference value obtained by subtracting the initial target gray scale voltage of the pixel unit located at the i-2th row and the jth column from the initial target gray scale voltage of the pixel unit located at the i-1th row and the jth column is less than a third preset threshold value, and a second difference value obtained by subtracting the initial target gray scale voltage of the pixel unit located at the i-1th row and the jth column from the initial target gray scale voltage of the pixel unit located at the i th row and the jth column is greater than or equal to zero and less than a fourth preset threshold value, the initial target gray scale voltage of the pixel unit located at the i th row and the jth column is increased to obtain the actual target gray scale voltage of the pixel unit located at the i th row and the jth column; wherein the third preset threshold value is less than zero, and the fourth preset threshold value is greater than zero.

Images