Short-circuit protection circuit adaptive to bus voltage and high-voltage integrated circuit thereof

Abstract

The invention relates to the technical field of power electronics, in particular to a short-circuit protection circuit adaptive to bus voltage and a high-voltage integrated circuit thereof, the short-circuit protection circuit comprises a detection time adaptation unit, a detection time reference unit and a trigger unit; the detection time reference unit is used for generating reference voltage; the detection time adaptation unit is used for receiving the short-circuit signal and the reference voltage and delaying to generate a trigger signal, and delay time is inversely proportional to the difference value of the voltage of the short-circuit signal and the reference voltage; the trigger unit is used for generating a short-circuit protection signal when receiving the trigger signal; the high-voltage integrated circuit comprises a fault logic control unit, at least one fault detection unit and a short-circuit protection circuit, and the fault logic control unit is used for turning off the high-voltage integrated circuit when receiving a feedback protection signal of any unit; therefore, the detection time can be automatically adjusted according to different bus voltages, and short-circuit protection can be quickly realized for a bus voltage sensitive device or circuit on the premise of keeping the anti-false-triggering capability.

Description

Technical Field

[0001] The invention relates to the technical field of power electronics, in particular to a short-circuit protection circuit adapted to bus voltage and a high-voltage integrated circuit thereof. Background Art

[0002] High voltage integrated circuit, or HVIC, integrates PMOS tubes, NMOS tubes, triodes, diodes, voltage regulator tubes, resistors, and capacitors to form Schmitt, low voltage level, high voltage level, pulse generation circuit, delay circuit, filter circuit, overcurrent and overheat protection circuit, undervoltage protection circuit, bootstrap circuit and other circuits. It is an integrated circuit product that converts MCU signals into driving IGBT or MOS signals. There is no short-circuit detection and protection circuit for switching devices such as IGBT and SiC-MOSFET inside.

[0003] Existing high-voltage integrated circuits perform short-circuit detection on switching devices such as IGBTs and SiC-MOSFETs in power modules through peripheral circuits, and feed back the detection results together with other short-circuit signals and other fault detection signals in the peripheral circuits to the high-voltage integrated circuits for overall short-circuit fault detection and protection. That is, after comprehensively judging all fault conditions, the high-voltage integrated circuit executes protection actions (usually short-circuit protection is executed as long as a fault signal is detected).

[0004] However, since multiple short-circuit signals are sampled by peripheral circuits and then transmitted to the high-voltage integrated circuit inside the power module for processing, the short-circuit detection time is basically fixed, and the ability to prevent false triggering of narrow pulse widths is fixed, which can only be applied to limited short-circuit situations and has low adaptability; especially when a short-circuit fault occurs in the SiC-MOSFET switching device, due to the characteristics of the SiC-MOSFET, the higher the bus voltage of the SiC-MOSFET, the shorter the short-circuit tolerance time, so the fixed detection time is not suitable for such devices or circuits that are sensitive to the bus voltage. A short-circuit protection circuit is needed that can automatically adjust the detection time according to different bus voltages, so as to detect short-circuit faults faster and provide protection, while maintaining the ability to prevent narrow pulses of different pulse widths from falsely triggering short-circuit protection under different bus voltages. Summary of the invention

[0005] In view of the above-mentioned defects, the purpose of the present invention is to propose a short-circuit protection circuit and a high-voltage integrated circuit adapted to the bus voltage, which can automatically adjust the detection time according to different bus voltages and quickly realize short-circuit protection for bus voltage sensitive devices or circuits while maintaining the ability to prevent false triggering.

[0006] To achieve this object, the present invention adopts the following technical solutions:

[0007] A short-circuit protection circuit adapted to bus voltage, comprising a detection time adaptation unit, a detection time reference unit and a trigger unit; the input end of the detection time adaptation unit is used as the input end of the short-circuit protection circuit, and the output end of the trigger unit is used as the output end of the short-circuit protection circuit;

[0008] The reference end of the detection time adaptation unit is electrically connected to the output end of the detection time reference unit, the output end of the detection time adaptation unit is electrically connected to the input end of the trigger unit, the VCC ends of the detection time adaptation unit, the detection time reference unit and the trigger unit are all connected to the power supply VCC, and the VSS ends of the detection time adaptation unit, the detection time reference unit and the trigger unit are all connected to the power supply VSS;

[0009] The detection time reference unit is used to generate a reference voltage;

[0010] The detection time adaptation unit is used to receive the short-circuit signal and the reference voltage, and generate a trigger signal with a delay, wherein the delay time is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage;

[0011] The trigger unit is used to generate a short circuit protection signal when receiving the trigger signal.

[0012] Further, the short-circuit signal is a step signal, and the detection time adaptation unit is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, and the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage;

[0013] When the ramp signal ramps down or ramps up to a threshold of the trigger unit, the trigger unit generates the short-circuit protection signal.

[0014] Further, the detection time adaptation unit includes a current mirror circuit and an integration circuit; the input end of the integration circuit is used as the input end of the detection time adaptation unit, the output end of the integration circuit is used as the output end of the detection time adaptation unit, the reference end of the integration circuit is used as the reference end of the detection time adaptation unit, the VCC ends of the current mirror circuit and the integration circuit are both used as the VCC end of the detection time adaptation unit, and the VSS ends of the current mirror circuit and the integration circuit are both used as the VSS end of the detection time adaptation unit;

[0015] The output end of the current mirror circuit is electrically connected to the control end of the integration circuit;

[0016] The current mirror circuit is used to keep the constant current source of the integration circuit turned on;

[0017] The integration circuit is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, wherein the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage.

[0018] Further, the integration circuit includes a resistor R1, a capacitor C1, a MOS tube M3, a MOS tube M4, a MOS tube M5, a MOS tube M6 and a MOS tube M7; one end of the resistor R1 is used as an input end of the integration circuit, the drain of the MOS tube M5 is used as an output end of the integration circuit, the gate of the MOS tube M5 is used as a reference end of the integration circuit, the gate of the MOS tube M3 is used as a control end of the integration circuit, the source of the MOS tube M6 and the MOS tube M7 are used as the VCC end of the integration circuit, and the source of the MOS tube M3 is used as the VSS end of the integration circuit;

[0019] The other end of the resistor R1 and one end of the capacitor C1 are electrically connected to the gate of the MOS tube M4, the drain of the MOS tube M4, the drain of the MOS tube M6, and the gate of the MOS tube M6 are electrically connected to the gate of the MOS tube M7, the drain of the MOS tube M7 and the other end of the capacitor C1 are electrically connected to the drain of the MOS tube M5, and the source of the MOS tube M5 and the drain of the MOS tube M3 are electrically connected to the source of the MOS tube M4.

[0020] Furthermore, the MOS tube M4 and the MOS tube M5 are completely the same MOS tube, and the MOS tube M6 and the MOS tube M7 are completely the same MOS tube.

[0021] Further, the current mirror circuit includes a MOS tube M1 and a MOS tube M2; the gate of the MOS tube M1 is used as the output end of the current mirror circuit, the source of the MOS tube M1 and the gate of the MOS tube M2 are used as the VSS end of the current mirror circuit, and the source of the MOS tube M2 is used as the VCC end of the current mirror circuit;

[0022] The drain of the MOS tube M1 and the gate of the MOS tube M1 are electrically connected to the drain of the MOS tube M2.

[0023] Further, the detection time reference unit includes a resistor R2 and a resistor R3; one end of the resistor R2 is used as an output end of the detection time reference unit, the other end of the resistor R2 is used as a VCC end of the detection time reference unit, and one end of the resistor R3 is used as a VSS end of the detection time reference unit;

[0024] The other end of the resistor R2 is electrically connected to the other end of the resistor R3.

[0025] Further, the trigger unit includes a MOS tube M8 and a MOS tube M9; the gate of the MOS tube M8 is used as the input end of the trigger unit, the drain of the MOS tube M8 is used as the output end of the trigger unit, the source of the MOS tube M8 is used as the VSS end of the trigger unit, and the source of the MOS tube M9 is used as the VCC end of the trigger unit;

[0026] The gate of the MOS tube M9 is electrically connected to the gate of the MOS tube M8, and the drain of the MOS tube M9 is electrically connected to the drain of the MOS tube M8.

[0027] A high-voltage integrated circuit, comprising at least one of the above-mentioned short-circuit protection circuits adapted to bus voltage; further comprising a fault logic control unit and at least one fault detection unit; the input end of the short-circuit protection circuit and the input end of the fault detection unit are both used as feedback ports of the high-voltage integrated circuit, and the output end of the short-circuit protection circuit and the output end of the fault detection unit are respectively electrically connected to the input end of the fault logic control unit;

[0028] The fault logic control unit is used to shut down the high-voltage integrated circuit when any one of the short-circuit protection circuit and the fault detection unit feeds back a protection signal.

[0029] The technical solution provided by the present invention may include the following beneficial effects: taking an intelligent power module as an example, when the peripheral circuit of a high-voltage integrated circuit (HVIC) detects that a short-circuit fault occurs in a SiC-MOSFET in the intelligent power module, a short-circuit signal will be fed back to the high-voltage integrated circuit, and the high-voltage integrated circuit can use a detection time adaptation unit to receive the short-circuit signal, and at the same time start a delay, and only after the delay ends will a trigger signal be generated for the trigger unit to generate a short-circuit protection signal, so that the high-voltage integrated circuit implements a short-circuit protection action, thereby avoiding a temporary short-circuit fault (such as a narrow pulse disturbance with different pulse widths) from falsely triggering the short-circuit protection; and because the voltage of the short-circuit signal represents the voltage caused by the bus connected to the SiC-MOSFET The short-circuit voltage is the short-circuit signal, so the larger the voltage of the short-circuit signal (that is, the larger the connected bus voltage), the shorter the tolerance time of the SiC-MOSFET, and the shorter the false triggering detection time (that is, the delay time). Therefore, the detection time reference unit is used to generate a reference voltage as a reference to judge the size of the connected bus voltage, so that the delay time is set inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage, so as to automatically adjust the short-circuit detection time (that is, the delay time) according to different bus voltages, so as to detect short-circuit faults faster and provide protection, while maintaining the ability to prevent narrow pulses of different pulse widths from falsely triggering short-circuit protection under different bus voltages, which is particularly suitable for devices or circuits that are sensitive to bus voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The present invention is a schematic circuit diagram of a short-circuit protection circuit adapted to bus voltage according to one embodiment of the present invention.

[0031] Figure 2 Yes Figure 1 A waveform comparison diagram of a short-circuit protection circuit adapted to bus voltage is shown.

[0032] Figure 3 It is a partial schematic diagram of a high-voltage integrated circuit according to one embodiment of the present invention.

[0033] Among them: detection time adaptation unit 1, detection time reference unit 2, trigger unit 3, current mirror circuit 11, integration circuit 12, resistor R1, capacitor C1, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M1, MOS tube M2, resistor R2, resistor R3, MOS tube M8, MOS tube M9, short circuit protection circuit 4, fault logic control unit 5, fault detection unit 6. DETAILED DESCRIPTION

[0034] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0035] In the description of the embodiments of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0036] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0037] Combine the following Figures 1 to 3 , describing a short-circuit protection circuit adapted to bus voltage and a high-voltage integrated circuit thereof according to an embodiment of the present invention.

[0038] Example 1

[0039] A short-circuit protection circuit adapted to bus voltage, comprising a detection time adaptation unit 1, a detection time reference unit 2 and a trigger unit 3; the input end of the detection time adaptation unit 1 is used as the input end of the short-circuit protection circuit, and the output end of the trigger unit 3 is used as the output end of the short-circuit protection circuit;

[0040] The reference end of the detection time adaptation unit 1 is electrically connected to the output end of the detection time reference unit 2, the output end of the detection time adaptation unit 1 is electrically connected to the input end of the trigger unit 3, the VCC ends of the detection time adaptation unit 1, the detection time reference unit 2 and the trigger unit 3 are all connected to the power supply VCC, and the VSS ends of the detection time adaptation unit 1, the detection time reference unit 2 and the trigger unit 3 are all connected to the power supply VSS;

[0041] The detection time reference unit 2 is used to generate a reference voltage;

[0042] The detection time adaptation unit 1 is used to receive the short-circuit signal and the reference voltage, and generate a trigger signal with a delay, wherein the delay time is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage;

[0043] The trigger unit 3 is used to generate a short-circuit protection signal when receiving a trigger signal.

[0044] The present invention proposes a short-circuit protection circuit adapted to bus voltage and a preferred embodiment of a high-voltage integrated circuit thereof, as Figure 1 As shown, taking the intelligent power module as an example, when the peripheral circuit of the high-voltage integrated circuit (HVIC) detects that the SiC-MOSFET in the intelligent power module has a short-circuit fault, it will feed back a short-circuit signal to the high-voltage integrated circuit, and the high-voltage integrated circuit can use the detection time adaptation unit 1 to receive the short-circuit signal, and start delaying at the same time. After the delay, a trigger signal is generated for the trigger unit 3 to generate a short-circuit protection signal, so that the high-voltage integrated circuit implements short-circuit protection action, thereby avoiding temporary short-circuit faults (such as narrow pulse disturbances with different pulse widths) from falsely triggering short-circuit protection; and because the voltage of the short-circuit signal represents the short-circuit voltage caused by the bus connected to the SiC-MOSFET, The greater the voltage of the short-circuit signal (that is, the greater the connected bus voltage), the shorter the tolerance time of the SiC-MOSFET, and the shorter the false triggering detection time (that is, the delay time). Therefore, the detection time reference unit 2 is used to generate a reference voltage as a reference to judge the size of the connected bus voltage, so that the delay time is set inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage, thereby automatically adjusting the short-circuit detection time (that is, the delay time) according to different bus voltages, so that short-circuit faults can be detected more quickly and protection can be provided, while maintaining the ability to prevent narrow pulses of different pulse widths from falsely triggering short-circuit protection under different bus voltages. This is particularly suitable for devices or circuits that are sensitive to bus voltages.

[0045] Further, the short-circuit signal is a step signal, and the detection time adaptation unit 1 is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, and the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage;

[0046] When the ramp signal ramps down or ramps up to the threshold of the trigger unit 3 , the trigger unit 3 generates a short-circuit protection signal.

[0047] In this embodiment, the short-circuit signal is usually a step signal. For example, it is a low level in a normal state, and when a short-circuit fault occurs, it will step to a high level. In order to enable the detection time adaptation unit 1 to generate a trigger signal with a delay, the delay time is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage. The detection time adaptation unit 1 preferably converts the step signal into a ramp signal, and makes the slope of the ramp signal inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage, thereby obtaining the following: Figure 2 The waveform diagram shown in the figure (only a waveform diagram of one embodiment), Vin in the figure is the voltage of the short-circuit signal, Va in the figure is Figure 1 The voltage at point a in the figure (shows a ramp-down change, i.e., a ramp-changing signal), Vout in the figure represents the output signal change of the trigger unit 3, Vth8 in the figure is the threshold of the trigger unit 3 (equivalent to the trigger signal), when the ramp-changing signal ramps down to the threshold of the trigger unit 3, the trigger unit 3 generates a short-circuit protection signal (for example, Vout is a high level), and then Figure 2 It can be seen that the function to be realized by the detection time adaptation unit 1 is realized.

[0048] Further, the detection time adaptation unit 1 includes a current mirror circuit 11 and an integration circuit 12; the input end of the integration circuit 12 is used as the input end of the detection time adaptation unit 1, the output end of the integration circuit 12 is used as the output end of the detection time adaptation unit 1, the reference end of the integration circuit 12 is used as the reference end of the detection time adaptation unit 1, the VCC ends of the current mirror circuit 11 and the integration circuit 12 are both used as the VCC ends of the detection time adaptation unit 1, and the VSS ends of the current mirror circuit 11 and the integration circuit 12 are both used as the VSS ends of the detection time adaptation unit 1;

[0049] The output end of the current mirror circuit 11 is electrically connected to the control end of the integration circuit 12;

[0050] The current mirror circuit 11 is used to keep the constant current source of the integration circuit 12 turned on;

[0051] The integration circuit 12 is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, wherein the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage.

[0052] In this embodiment, the detection time adaptation unit 1 receives the short-circuit signal from the integration circuit 12, and integrates it to form a linear ramp signal according to the characteristics of the integration circuit; at the same time, the current mirror circuit 11 is used to keep the constant current source of the integration circuit 12 turned on, which can improve the stability of the integration circuit 12 and make the ramp signal more linear, because the current mirror circuit 11 can accurately replicate the current and is not affected by the process and temperature.

[0053] Further, the integration circuit 12 includes a resistor R1, a capacitor C1, a MOS tube M3, a MOS tube M4, a MOS tube M5, a MOS tube M6 and a MOS tube M7; one end of the resistor R1 is used as an input end of the integration circuit 12, the drain of the MOS tube M5 is used as an output end of the integration circuit 12, the gate of the MOS tube M5 is used as a reference end of the integration circuit 12, the gate of the MOS tube M3 is used as a control end of the integration circuit 12, the sources of the MOS tubes M6 and M7 are used as VCC ends of the integration circuit 12, and the source of the MOS tube M3 is used as VSS ends of the integration circuit 12;

[0054] The other end of the resistor R1 and one end of the capacitor C1 are electrically connected to the gate of the MOS tube M4, the drain of the MOS tube M4, the drain of the MOS tube M6, and the gate of the MOS tube M6 are electrically connected to the gate of the MOS tube M7, the drain of the MOS tube M7 and the other end of the capacitor C1 are electrically connected to the drain of the MOS tube M5, and the source of the MOS tube M5 and the drain of the MOS tube M3 are electrically connected to the source of the MOS tube M4.

[0055] In this embodiment, the resistor R1 and the capacitor C1 form a charge-discharge circuit, the MOS tube M3 (equivalent to a constant current source), the MOS tube M4, the MOS tube M5, the MOS tube M6 and the MOS tube M7 form an amplifier, and the above-mentioned charge-discharge circuit and the amplifier form an integration circuit 12. Taking the ramp signal as a ramp-down signal as an example, the step signal transmitted by Vin is converted into a ramp-down signal:

[0056] According to the formula of the integration circuit, we know

[0057] Where Va is Figure 1 The voltage at point a, R1 is the resistance of resistor R1, C1 is the capacitance of capacitor C1, Vin is the voltage of the short-circuit signal, and Vb is the reference voltage;

[0058] like Figure 1As shown in FIG. 1 , when the input terminal IN is at a low level, the MOS tube M4 is not turned on, the MOS tubes M3, M5, M6 and M7 are all turned on, and the voltage at point a is at a high level; when the voltage at the input terminal IN jumps to a high level, the MOS tubes M3, M4, M5, M6 and M7 are all turned on, and the voltage at point a becomes a low level. Due to the existence of the charge and discharge circuit of the resistor R1 and the capacitor C1, the voltage at point a will not suddenly change to a low level, but will drop to a low level, as shown in FIG. Figure 2 As shown in the Va-t waveform diagram.

[0059] The trigger unit 3 is equivalent to an inverter, which is used to invert the output voltage at point a and shape it into a square wave (such as Figure 2 When the voltage at point a is high, the output voltage at the OUT terminal is low; when the voltage at point a drops below the threshold Vth8 of the trigger unit 3, the OUT terminal outputs a high level (i.e., a short-circuit protection signal).

[0060] Therefore, when the input terminal IN is low level, the OUT terminal outputs low level, and when the input terminal IN jumps to high level, the OUT terminal also jumps to output high level. The delay time is t2-t1 (such as Figure 2 shown).

[0061] According to formula (1), short circuit detection time T = t2-t1 = R1*C1*Vth8 / (Vin-Vb)……(2);

[0062] It can be seen from formula (2) that the larger the input voltage Vin, the larger the Vin-Vb difference, the larger the gate voltage difference between the MOS tube M4 and the MOS tube M5, the smaller the short-circuit detection time T, and the smaller the ability to prevent narrow pulse false triggering; the smaller the input voltage Vin, the smaller the Vin-Vb difference, the smaller the gate voltage difference between the M4 tube and the M5 tube, and the larger the short-circuit detection time T (i.e., delay time); therefore, the circuit can automatically adjust the short-circuit detection time according to different bus voltages, and can detect short-circuit faults faster and perform protection, while maintaining the ability to prevent narrow pulses of different pulse widths from falsely triggering short-circuit protection under different bus voltages. More importantly, it can be seen from formula (2) that the integration circuit 12 composed of resistor R1, capacitor C1, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6 and MOS tube M7 has better linearity.

[0063] Furthermore, the MOS tube M4 and the MOS tube M5 are completely the same MOS tube, and the MOS tube M6 and the MOS tube M7 are completely the same MOS tube.

[0064] In this embodiment, in order to reduce the noise of the integration circuit 12 and improve the stability and linearity, the integration circuit 12 is set as symmetrically as possible to reduce the influence of the input signal noise. The MOS tube M4 and the MOS tube M5 use exactly the same MOS tube, so that the width-to-length ratio parameters of the MOS tube M4 and the MOS tube M5 are consistent; the MOS tube M6 and the MOS tube M7 use exactly the same MOS tube, so that the width-to-length ratio parameters of the MOS tube M6 and the MOS tube M7 are consistent.

[0065] Furthermore, the current mirror circuit 11 includes a MOS transistor M1 and a MOS transistor M2; the gate of the MOS transistor M1 is used as the output end of the current mirror circuit 11, the source of the MOS transistor M1 and the gate of the MOS transistor M2 are used as the VSS end of the current mirror circuit 11, and the source of the MOS transistor M2 is used as the VCC end of the current mirror circuit 11;

[0066] The drain of the MOS tube M1 and the gate of the MOS tube M1 are electrically connected to the drain of the MOS tube M2.

[0067] In this embodiment, the current mirror circuit 11 composed of MOS tubes has significant advantages in accuracy, stability, power consumption, input impedance and voltage range, making it more stable when the MOS tube M3 equivalent to the constant current source in the control integration circuit 12 remains turned on.

[0068] Further, the detection time reference unit 2 includes a resistor R2 and a resistor R3; one end of the resistor R2 is used as the output end of the detection time reference unit 2, the other end of the resistor R2 is used as the VCC end of the detection time reference unit 2, and one end of the resistor R3 is used as the VSS end of the detection time reference unit 2;

[0069] The other end of the resistor R2 is electrically connected to the other end of the resistor R3.

[0070] In this embodiment, the detection time reference unit 2 uses a resistor R2 and a resistor R3 to form a voltage divider circuit to provide a reference voltage Vb for the detection time adaptation unit 1, while keeping the MOS tube M5 turned on.

[0071] Further, the trigger unit 3 includes a MOS tube M8 and a MOS tube M9; the gate of the MOS tube M8 is used as the input end of the trigger unit 3, the drain of the MOS tube M8 is used as the output end of the trigger unit 3, the source of the MOS tube M8 is used as the VSS end of the trigger unit 3, and the source of the MOS tube M9 is used as the VCC end of the trigger unit 3;

[0072] The gate of the MOS tube M9 is electrically connected to the gate of the MOS tube M8, and the drain of the MOS tube M9 is electrically connected to the drain of the MOS tube M8.

[0073] In this embodiment, the trigger unit 3 is composed of a MOS tube M8 and a MOS tube M9 forming an inverter, so as to achieve the requirement of inverting the output voltage at point a and shaping it into a square wave; specifically, when the voltage at point a is at a high level, the MOS tube M8 is turned on, the MOS tube M9 is turned off, and the output voltage at the OUT terminal is at a low level; when the voltage at point a drops below the threshold voltage Vth8 of the MOS tube M8, the MOS tube M8 is turned off, the MOS tube M9 is turned on, and the OUT terminal outputs a high level.

[0074] Example 2

[0075] A high-voltage integrated circuit, comprising at least one of the above-mentioned short-circuit protection circuits 4 adapted to bus voltage; further comprising a fault logic control unit 5 and at least one fault detection unit 6; the input end of the short-circuit protection circuit 4 and the input end of the fault detection unit 6 are both used as feedback ports of the high-voltage integrated circuit, and the output end of the short-circuit protection circuit 4 and the output end of the fault detection unit 6 are electrically connected to the input end of the fault logic control unit 5 respectively;

[0076] The fault logic control unit 5 is used to shut down the high-voltage integrated circuit when any one of the short-circuit protection circuit 4 and the fault detection unit 6 feeds back a protection signal.

[0077] The present invention also proposes a preferred embodiment of a high voltage integrated circuit, such as Figure 3 As shown, the above-mentioned short-circuit protection circuit 4 adapted to the bus voltage can be integrated into a high-voltage integrated circuit. Devices or circuits insensitive to the bus voltage use the input connection detection of the fault detection unit 6, and devices or circuits sensitive to the bus voltage use the input connection detection of the short-circuit protection circuit 4. Then, the fault logic control unit 5 is used to comprehensively judge all fault conditions of the short-circuit protection circuit 4 and the fault detection unit 6. As long as there is a trigger feedback protection signal, the protection action is executed to shut down the high-voltage integrated circuit; thereby, the high-voltage integrated circuit has two protection detection modes: fixed detection time and automatic adjustment of detection time according to different bus voltages, so as to adapt to the application environment of more power modules.

[0078] A short-circuit protection circuit adapted to bus voltage according to an embodiment of the present invention and other structures and operations of its high-voltage integrated circuit are well known to those skilled in the art and will not be described in detail here.

[0079] In the description of this specification, the description with reference to the terms "embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0080] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A short-circuit protection circuit adapted to bus voltage, characterized in that: It includes a detection time adaptation unit, a detection time reference unit and a trigger unit; the input end of the detection time adaptation unit is used as the input end of the short-circuit protection circuit, and the output end of the trigger unit is used as the output end of the short-circuit protection circuit; The reference end of the detection time adaptation unit is electrically connected to the output end of the detection time reference unit, the output end of the detection time adaptation unit is electrically connected to the input end of the trigger unit, the VCC ends of the detection time adaptation unit, the detection time reference unit and the trigger unit are all connected to the power supply VCC, and the VSS ends of the detection time adaptation unit, the detection time reference unit and the trigger unit are all connected to the power supply VSS; The detection time reference unit is used to generate a reference voltage; The detection time adaptation unit is used to receive the short-circuit signal and the reference voltage, and generate a trigger signal with a delay, wherein the delay time is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage; The trigger unit is used to generate a short circuit protection signal when receiving the trigger signal.

2. A short-circuit protection circuit adapted to bus voltage according to claim 1, characterized in that: The short-circuit signal is a step signal, and the detection time adaptation unit is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, wherein the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage; When the ramp signal ramps down or ramps up to a threshold of the trigger unit, the trigger unit generates the short-circuit protection signal.

3. A short-circuit protection circuit adapted to bus voltage according to claim 1, characterized in that: The detection time adaptation unit comprises a current mirror circuit and an integration circuit; the input end of the integration circuit is used as the input end of the detection time adaptation unit, the output end of the integration circuit is used as the output end of the detection time adaptation unit, the reference end of the integration circuit is used as the reference end of the detection time adaptation unit, the VCC end of the current mirror circuit and the integration circuit are both used as the VCC end of the detection time adaptation unit, and the VSS end of the current mirror circuit and the integration circuit are both used as the VSS end of the detection time adaptation unit; The output end of the current mirror circuit is electrically connected to the control end of the integration circuit; The current mirror circuit is used to keep the constant current source of the integration circuit turned on; The integration circuit is used to receive the short-circuit signal and the reference voltage, and convert the step signal into a ramp signal, wherein the slope of the ramp signal is inversely proportional to the difference between the voltage of the short-circuit signal and the reference voltage.

4. A short-circuit protection circuit adapted to bus voltage according to claim 3, characterized in that: The integration circuit comprises a resistor R1, a capacitor C1, a MOS tube M3, a MOS tube M4, a MOS tube M5, a MOS tube M6 and a MOS tube M7; one end of the resistor R1 is used as an input end of the integration circuit, the drain of the MOS tube M5 is used as an output end of the integration circuit, the gate of the MOS tube M5 is used as a reference end of the integration circuit, the gate of the MOS tube M3 is used as a control end of the integration circuit, the sources of the MOS tube M6 and the MOS tube M7 are used as VCC ends of the integration circuit, and the source of the MOS tube M3 is used as VSS ends of the integration circuit; The other end of the resistor R1 and one end of the capacitor C1 are electrically connected to the gate of the MOS tube M4, the drain of the MOS tube M4, the drain of the MOS tube M6, and the gate of the MOS tube M6 are electrically connected to the gate of the MOS tube M7, the drain of the MOS tube M7 and the other end of the capacitor C1 are electrically connected to the drain of the MOS tube M5, and the source of the MOS tube M5 and the drain of the MOS tube M3 are electrically connected to the source of the MOS tube M4.

5. A short-circuit protection circuit adapted to bus voltage according to claim 4, characterized in that: The MOS tube M4 and the MOS tube M5 are identical MOS tubes, and the MOS tube M6 and the MOS tube M7 are identical MOS tubes.

6. A short-circuit protection circuit adapted to bus voltage according to claim 3, characterized in that: The current mirror circuit comprises a MOS tube M1 and a MOS tube M2; the gate of the MOS tube M1 is used as the output end of the current mirror circuit, the source of the MOS tube M1 and the gate of the MOS tube M2 are used as the VSS end of the current mirror circuit, and the source of the MOS tube M2 is used as the VCC end of the current mirror circuit; The drain of the MOS tube M1 and the gate of the MOS tube M1 are electrically connected to the drain of the MOS tube M2.

7. A short-circuit protection circuit adapted to bus voltage according to claim 1, characterized in that: The detection time reference unit includes a resistor R2 and a resistor R3; one end of the resistor R2 is used as the output end of the detection time reference unit, the other end of the resistor R2 is used as the VCC end of the detection time reference unit, and one end of the resistor R3 is used as the VSS end of the detection time reference unit; The other end of the resistor R2 is electrically connected to the other end of the resistor R3.

8. A short-circuit protection circuit adapted to bus voltage according to claim 1, characterized in that: The trigger unit includes a MOS tube M8 and a MOS tube M9; the gate of the MOS tube M8 is used as the input end of the trigger unit, the drain of the MOS tube M8 is used as the output end of the trigger unit, the source of the MOS tube M8 is used as the VSS end of the trigger unit, and the source of the MOS tube M9 is used as the VCC end of the trigger unit; The gate of the MOS tube M9 is electrically connected to the gate of the MOS tube M8, and the drain of the MOS tube M9 is electrically connected to the drain of the MOS tube M8.

9. A high voltage integrated circuit, characterized in that: The invention comprises at least one short-circuit protection circuit for adapting bus voltage according to any one of claims 1 to 8; further comprising a fault logic control unit and at least one fault detection unit; the input end of the short-circuit protection circuit and the input end of the fault detection unit are both used as feedback ports of the high-voltage integrated circuit, and the output end of the short-circuit protection circuit and the output end of the fault detection unit are electrically connected to the input end of the fault logic control unit respectively; The fault logic control unit is used to shut down the high-voltage integrated circuit when any one of the short-circuit protection circuit and the fault detection unit feeds back a protection signal.

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