A switching power supply driver chip and a switching power supply

Abstract

The invention relates to the technical field of switch power drive, and discloses a switch power drive chip and a switch power. The drive chip comprises a high-voltage power supply unit, a start-up unit, a voltage-controlled current source, a reference unit, an SR latch, a drive unit, a first delay unit, an XOR gate XOR, a D flip-flop, a clamp unit, a ramp generator, a comparator CMP1, a comparator CMP2, a comparator CMP3, a switch SW2, a switch SW3 and a resistor R10. The switch power comprises the drive chip. In actual use, the switch power effectively avoids the output of the load disappearing due to non-operation under the condition of a small overload or fluctuation, avoids causing the load to work abnormally or even damage the load, and must wait until the load is overloaded again to stop working. In addition, when the switch power is overloaded and working under rated load, the peak current of the switch power is consistent, avoiding the problem of reduced system reliability caused by increasing the peak current when a traditional forward pulse is used for overload.

Description

Technical Field

[0001] The present invention relates to the technical field of switching power supply driving, and in particular to a switching power supply driving chip and a switching power supply. Background Art

[0002] The structure of the existing switching power supply based on the current-mode PWM controller chip NCP1252 is as follows: Figure 1 As shown, the entire switching cycle of the PWM controller chip (hereinafter referred to as chip) is solidified, that is, the switching cycle is the same under different loads and input voltages. When controlling, the output voltage is controlled by adjusting the peak value of the primary current. The entire working process is as follows:

[0003] The input power AC passes through the rectifier bridge and is filtered by the capacitor Cbus to become a fluctuating DC voltage Vbus. The DC voltage Vbus charges the capacitor C4 in parallel with the VCC pin of the chip through the resistor Rbus. When the voltage of the VCC pin reaches the working voltage, the DRV pin of the chip starts to output a driving signal with a duty cycle waveform to the gate of the MOS tube Q1.

[0004] When the DRV pin of the chip outputs a high level, the MOS tube Q1 is turned on, and the DC voltage Vbus is loaded on the primary winding N1 of the transformer. The secondary winding N2 of the transformer outputs a voltage, and the voltage value is the input voltage of the primary winding N1 divided by the ratio of the number of primary turns to the number of secondary turns (hereinafter referred to as the turns ratio). The output voltage of the secondary winding N2 supplies power to the load through the filter inductor Lm. The current of the secondary winding N2 is limited by the inductor Lm and can only rise linearly from the starting value.

[0005] In addition, the current of the secondary winding will be reflected to the primary side, that is, the primary current will be composed of two parts: one part is the excitation current of the inductor formed by the primary coil N1, and the other part is the current reflected back to the primary by the secondary current, whose value is equal to the filter inductor current divided by the turns ratio. Due to the large inductance of the transformer, the excitation current will be designed to be largely smaller than the reflected current, accounting for only about 5%-10% of the reflected current. The entire primary current passes through the resistor Rcs, and the voltage drop Vcs of the resistor Rcs is collected by the CS pin of the chip, so that the chip can indirectly collect the primary current. When the DRV pin output is low, the MOS tube Q1 is turned off, and the entire transformer demagnetizes the capacitor Cbus through the demagnetization winding N3. The current of the filter inductor LM returns to the inductor through the load and the diode D2.

[0006] After the load voltage is detected, it is converted into a signal and transmitted to the chip through the optocoupler Opt and converted into a control value. When the peak voltage of the voltage drop Vcs reaches this control value, the chip turns off the MOS tube Q1. Therefore, the core idea of ​​the chip is to control the primary peak current. At the same time, the chip will start a fixed-cycle clock signal at the same time as the last high level of the DRV pin. When this clock signal completes a cycle time, a pulse is generated to turn on Q1 again.

[0007] Combined with the above content, Figure 1 The entire circuit works over and over again. According to the transformer principle, the primary current reflects the secondary current, and the secondary current is the load current, so adjusting the size of the primary current is equivalent to adjusting the size of the load current in disguise. When the load current required becomes larger, the circuit will lower the output voltage, and the feedback system will increase the control amount to increase the primary current to output more current to the load to stabilize the output voltage. Conversely, the control amount will be reduced to stabilize the output voltage. Obviously, under the same input voltage, the greater the current required by the load, the higher the peak current flowing through the primary, and the higher the control amount. The chip also determines whether the load current exceeds the design specifications by detecting whether the voltage of the resistor Rcs reaches the internal maximum value. Once the voltage of the voltage drop VCS reaches the rated value, it is considered that the circuit is overloaded and immediately enters protection. The relevant waveform signal is as follows Figure 2 As shown, Figure 2 Where Iout is the load current, ILm is the current of the filter inductor Lm at full load, and Vcs is the voltage drop of the resistor Rcs.

[0008] According to the working principle of the chip, if the user wants to perform a small overload operation for a short period of time or the circuit can still operate stably when the power fluctuates, a higher current must be allowed to flow through the primary winding of the control circuit to reach the protection value of the chip. The only way is to increase the maximum allowable current of the primary MOS tube Q1 and the primary inductor. The simple way is to reduce Figure 1 However, a larger peak current capability means increasing the area or volume of semiconductor devices and magnetic devices, thereby increasing costs. Summary of the invention

[0009] In view of the shortcomings of the background technology, the present invention provides a switching power supply driver chip and a switching power supply. The technical problem to be solved is that when the existing switching power supply needs to be overloaded, the resistance value of the resistor Rcs can only be reduced to increase the maximum current of the primary coil of the transformer, which will increase the device cost and area.

[0010] To solve the above technical problems, in a first aspect, the present invention provides the following technical solutions: a switching power supply driver chip, comprising a high voltage power supply unit, a startup unit, a voltage-controlled current source, a reference unit, an SR latch, a driver unit, a first delay unit, an XOR gate XOR, a D flip-flop, a clamp unit, a ramp generator, a comparator CMP1, a comparator CMP2, a comparator CMP3, a switch SW2, a switch SW3 and a resistor R10;

[0011] The high-voltage power supply unit outputs a working voltage based on an input external voltage, and the working voltage output terminal of the high-voltage power supply unit is electrically connected to the first output terminal of the startup unit, the reference unit and the voltage-controlled current source respectively; the second output terminal and the negative input terminal of the voltage-controlled current source are both grounded; the startup unit outputs a first startup signal VON and a second startup signal VOFF based on the working voltage; the reference unit includes a reference enable terminal for inputting a first startup signal VON, and outputs a reference voltage REF1, a reference voltage REF2 and a reference voltage REF3 when the first startup signal VON is at a high level;

[0012] The positive input terminal of the comparator CMP1 is used to input the sampling voltage and is electrically connected to the input terminal of the switch SW2. The negative input terminal of the comparator CMP1 is electrically connected to the output terminal of the clamping unit. The input terminal of the clamping unit is electrically connected to one end of the resistor R10, and the other end of the resistor R10 inputs the reference voltage REF2. The clamping unit outputs the voltage of its own input terminal when the voltage of its own input terminal is less than the clamping voltage, and outputs the clamping voltage when the voltage of its own input terminal is greater than or equal to the clamping voltage.

[0013] The control end of the switch SW2 is electrically connected to the output end of the XOR gate XOR, the two input ends of the XOR gate XOR are electrically connected to the output end of the first delay unit and the input end of the first delay unit respectively, the output end of the switch SW2 is electrically connected to the positive input end of the comparator CMP3, the negative input end of the comparator CMP3 is used to input the reference voltage REF3, the output end of the comparator CMP3 is electrically connected to the clock end of the D flip-flop, the reset end of the D flip-flop is used to input the second start signal VOFF, the Q output end of the D flip-flop outputs the control signal F1, and is electrically connected to the positive input end of the voltage-controlled current source, and the QN output end of the D flip-flop outputs the control signal F2;

[0014] The output end of the comparator CMP1 is electrically connected to the R input end of the SR latch, and the S input end of the SR latch is electrically connected to the output end of the comparator CMP2; the QP output end of the SR latch is electrically connected to the input end of the first delay unit and the input end of the driving unit respectively, and the driving unit includes a driving enable end for inputting the first start signal VON, and outputs a driving signal based on the signal of the QP output end of the SR latch when the first start signal VON is at a high level; the QN output end of the SR latch is electrically connected to the input end of the ramp generator, and the ramp generator includes a ramp enable end for inputting the control signal F2, and inputs a ramp compensation signal to the positive input end of the comparator CMP2 based on the signal of the QN output end of the SR latch when the control signal F2 is at a high level, and the negative input end of the comparator CMP2 is used to input the reference voltage REF1.

[0015] In a certain embodiment of the first aspect, the startup unit outputs a low-level first startup signal VON and a high-level second startup signal VOFF when the operating voltage is less than the startup threshold, and outputs a high-level first startup signal VON and a low-level second startup signal VOFF when the operating voltage is greater than the startup threshold.

[0016] In a certain implementation of the first aspect, when the first start signal VON is at a high level, the level state of the drive signal output by the drive unit is the same as the signal level state of the QP output terminal of the SR latch.

[0017] In a certain implementation of the first aspect, the ramp generator outputs a slope compensation signal when the control signal F2 is at a high level and the signal at the QN output terminal of the SR latch is at a high level.

[0018] In a certain embodiment of the first aspect, the present invention also includes a switch SW1 and a second delay unit, the QP output end of the SR latch is electrically connected to the input end of the first delay unit through the second delay unit, the input end of the first delay unit is electrically connected to the control end of the switch SW1, the output end of the switch SW1 is electrically connected to the positive input end of the comparator CMP1, and the input end of the switch SW1 is used to input the sampling voltage.

[0019] In a certain embodiment of the first aspect, the present invention further includes a chip body, wherein the high-voltage power supply unit, the startup unit, the voltage-controlled current source, the reference unit, the SR latch, the drive unit, the first delay unit, the XOR gate XOR, the D flip-flop, the clamp unit, the ramp generator, the comparator CMP1, the comparator CMP2, the comparator CMP3, the switch SW2, the switch SW3, the resistor R10, the switch SW1 and the second delay unit are all arranged on the chip body;

[0020] The chip body is also provided with an HV pin, a VCC pin, a CS pin, a COMP pin, a GND pin and a GATE pin; the HV pin is electrically connected to the high-voltage power supply unit for inputting an external voltage; the VCC pin is electrically connected to the working voltage output end of the high-voltage power supply unit; the CS pin is used to input a sampling voltage; the COMP pin is electrically connected to the input end of the clamp unit, and the GND pin is used to ground the ground terminal in the circuit; the GATE pin is electrically connected to the output end of the drive unit.

[0021] In a certain embodiment of the first aspect, the GATE pin and CS pin are distributed from top to bottom on the right side of the chip body; the HV pin, VCC pin, COMP pin, and GND pin are distributed from top to bottom on the left side of the chip body.

[0022] In a second aspect, the present invention further provides a switching power supply, comprising the above-mentioned switching power supply driver chip, and also comprising an EMI filter for filtering the AC power supply, wherein the output end of the EMI filter is electrically connected to the input end of the rectifier bridge, and the DC voltage output end of the rectifier bridge is electrically connected to the positive electrode of the capacitor Cbus, one end of the resistor Rbus, the cathode of the diode D3 and one end of the primary winding N1 of the transformer T1, respectively, the negative electrode of the capacitor Cbus is grounded, the other end of the resistor Rbus is electrically connected to the HV pin, the anode of the diode D3 is electrically connected to one end of the demagnetization winding N3 of the transformer T1, the other end of the demagnetization winding N3 of the transformer T1 is grounded, the other end of the primary winding N1 is electrically connected to the drain of the MOS tube N1, the gate of the MOS tube Q1 is electrically connected to the GATE pin, the source of the MOS tube Q1 is electrically connected to the CS pin, and is grounded through the resistor Rcs;

[0023] The VCC pin of the driver chip is electrically connected to the cathode of the diode D4 and is grounded through the capacitor C1. The anode of the diode D4 is grounded through the power supply winding N4 of the transformer T1. The COMP pin of the driver chip is grounded through the capacitor C2. The GND pin of the driver chip is grounded.

[0024] One end of the secondary winding N2 of the transformer T1 is electrically connected to the anode of the diode D1, the cathode of the diode D1 is electrically connected to the cathode of the diode D2 and one end of the filter inductor Lm respectively, the other end of the filter inductor Lm is grounded through the output capacitor Co and the output resistor Ro respectively, and the other end of the secondary winding N2 and the anode of the diode D2 are both grounded;

[0025] The device further includes a feedback current generating unit, which is electrically connected to the other end of the filter inductor Lm and the COMP pin respectively, and forms a feedback current flowing out of the COMP pin based on the voltage at the other end of the filter inductor Lm.

[0026] In a certain embodiment of the second aspect, the feedback current generating unit includes a resistor R1, one end of the resistor R1 is electrically connected to one end of a resistor R3 and the other end of a filter inductor Lm, respectively, the other end of the resistor R3 is electrically connected to the primary side input end of the photoelectric coupler OPT, the other end of the resistor R1 is electrically connected to one end of a resistor R2, one end of a capacitor C3 and the input end of a feedback amplifier chip of model TL431, the other end of the resistor R2 and the anode of the feedback amplifier chip are both grounded, the other end of the capacitor C3 is electrically connected to the output end of the primary side of the photoelectric coupler OPT and the cathode of the feedback amplifier chip, the secondary side input end of the photoelectric coupler OPT is electrically connected to the COMP pin, and the secondary side output end of the photoelectric coupler OPT is grounded.

[0027] In a certain implementation of the second aspect, the MOS transistor Q1 is an NMOS transistor.

[0028] Compared with the prior art, the present invention has the following beneficial effects: From the working process of the switching power supply in the second embodiment, it can be known that as long as the switching power supply is working at rated load, V CS_PK Designed in V CLAMP , once the load resistance Ro continues to decrease, as long as the reduction amplitude makes V CS_0 If the reference voltage REF3 is not exceeded, the switching power supply will continue to work, but the switching power supply is in an open-loop state, that is, V COMP It is already at the maximum value of effective control. The secondary output of transformer T1 is manifested as a decrease in output voltage, but the switching power supply will not stop working, effectively preventing the output of the switching power supply from disappearing due to non-operation when the load is slightly overloaded or fluctuating, avoiding abnormal operation of the load or even damage to the load, and the load must be overloaded again before it stops working;

[0029] Also refer to the attached Figure 5 When the switching power supply is working under overload and rated load, the peak current of the switching power supply is consistent, which avoids the problem of reduced system reliability caused by increasing the peak current when the traditional forward converter is overloaded. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The circuit diagram of the existing switching power supply;

[0031] Figure 2 for Figure 1 Relevant signal waveform diagram when the circuit is in use;

[0032] Figure 3 This is a schematic diagram of the structure of the switching power supply driver chip in the first embodiment;

[0033] Figure 4 is a circuit diagram of the switching power supply in Embodiment 2;

[0034] Figure 5 for Figure 4 Relevant signal waveform diagram when the circuit is in use. DETAILED DESCRIPTION

[0035] The following is an explanation of the implementation methods of the switching power supply driver chip and the switching power supply disclosed in the present invention through specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention from the contents disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and the details in this specification can also be modified and changed in various ways based on different viewpoints and applications without departing from the concept of the present invention. In addition, the drawings of the present invention are only simple schematic illustrations and are not depicted according to actual dimensions. It is stated in advance. The following embodiments will further explain the relevant technical contents of the present invention in detail, but the disclosed contents are not intended to limit the scope of protection of the present invention.

[0036] It should be understood that, although the terms first, second, third, etc. may be used herein to describe various components or features, these components or features should not be limited by these terms. These terms are mainly used to distinguish one component from another component, or one feature from another feature. In addition, the terms or used herein may include any one or more combinations of the associated listed items depending on the actual situation.

[0037] like Figure 3 As shown, a switching power supply driver chip provided in this embodiment includes a high-voltage power supply unit 1, a startup unit 3, a voltage-controlled current source 2, a reference unit 4, an SR latch 5, a driving unit 6, a first delay unit 8, a second delay unit 7, an XOR gate XOR, a D flip-flop 9, a clamping unit 10, a ramp generator 11, a comparator CMP1, a comparator CMP2, a comparator CMP3, a switch SW1, a switch SW2, a switch SW3 and a resistor R10.

[0038] In this embodiment, the connection relationship and functions of each unit of the driver chip are as follows:

[0039] The high-voltage power supply unit 1 outputs a working voltage based on an input external voltage, and a working voltage output terminal of the high-voltage power supply unit 1 is electrically connected to the start-up unit 3, the reference unit 4 and the first output terminal of the voltage-controlled current source 2 respectively;

[0040] The second output terminal and the negative input terminal of the voltage-controlled current source 2 are both grounded;

[0041] The start-up unit 3 outputs a first start-up signal VON and a second start-up signal VOFF based on the working voltage;

[0042] The reference unit includes a reference enable terminal for inputting a first start signal VON, and outputs a reference voltage REF1, a reference voltage REF2 and a reference voltage REF3 when the first start signal VON is at a high level;

[0043] The positive input terminal of the comparator CMP1 is electrically connected to the output terminal of the switch SW1, and is electrically connected to the input terminal of the switch SW2; the input terminal of the switch SW1 is used to input the sampling voltage, the negative input terminal of the comparator CMP1 is electrically connected to the output terminal of the clamping unit 10, the input terminal of the clamping unit 10 is electrically connected to one end of the resistor R10, and the other end of the resistor R10 inputs the reference voltage REF2; the clamping unit 10 outputs the voltage of its own input terminal when the voltage of its own input terminal is less than the clamping voltage, and outputs the clamping voltage when the voltage of its own input terminal is greater than or equal to the clamping voltage;

[0044] The control end of the switch SW2 is electrically connected to the output end of the XOR gate XOR, the two input ends of the XOR gate XOR are electrically connected to the output end of the first delay unit 8 and the input end of the first delay unit 8 respectively, the output end of the switch SW2 is electrically connected to the positive input end of the comparator CMP3, the negative input end of the comparator CMP3 is used to input the reference voltage REF3, the output end of the comparator CMP3 is electrically connected to the clock end of the D flip-flop 9, the reset end of the D flip-flop 9 is used to input the second start signal VOFF, the Q output end of the D flip-flop 9 outputs the control signal F1, and is electrically connected to the positive input end of the voltage-controlled current source 2, and the QN output end of the D flip-flop 9 outputs the control signal F2;

[0045] The output end of the comparator CMP1 is electrically connected to the R input end of the SR latch 5, and the S input end of the SR latch 5 is electrically connected to the output end of the comparator CMP2; the QP output end of the SR latch 5 is electrically connected to the input end of the second delay unit 7 and the input end of the driving unit 6 respectively, and the input end of the second delay unit 7 is electrically connected to the input end of the first delay unit 8 and the control end of the switch SW1 respectively, and the driving unit 6 includes a driving enable end for inputting the first start signal VON, and outputs a driving signal based on the signal of the QP output end of the SR latch 5 when the first start signal VON is at a high level; the QN output end of the SR latch 5 is electrically connected to the input end of the ramp generator 11, and the ramp generator 11 includes a ramp enable end for inputting the control signal F2, and inputs the ramp compensation signal to the positive input end of the comparator CMP2 based on the signal of the QN output end of the SR latch 5 when the control signal F2 is at a high level, and the negative input end of the comparator CMP2 is used to input the reference voltage REF1.

[0046] Specifically, in this embodiment, the start-up unit 3 outputs a low-level first start-up signal VON and a high-level second start-up signal VOFF when the operating voltage is less than the start-up threshold, and outputs a high-level first start-up signal VON and a low-level second start-up signal VOFF when the operating voltage is greater than the start-up threshold.

[0047] In actual use, the first start-up signal VON and the second start-up signal VOFF outputted by the start-up unit 3 can be used to control whether other units in the driving chip are working.

[0048] Specifically, in this embodiment, when the first start signal VON is at a high level, the level state of the drive signal output by the drive unit 6 is the same as the signal level state of the QP output terminal of the SR latch, that is, when the signal at the QP output terminal of the SR latch 5 is at a high level, the drive unit 6 outputs a high-level drive signal, and when the signal at the QP output terminal of the SR latch 5 is at a low level, the drive unit 6 outputs high-low level drive signals.

[0049] Specifically, in this embodiment, the ramp generator 11 outputs the slope compensation signal when the control signal F2 is at a high level and the signal at the QN output terminal of the SR latch is at a high level.

[0050] Specifically, in this embodiment, the switches SW1, SW2 and SW3 can all be NMOS switches, wherein the drain of the NMOS tube is the input end of the switch, the gate of the NMOS tube is the control end of the switch, and the source of the NMOS tube is the output end of the switch.

[0051] In this embodiment, the present invention further includes a chip body 100, a high-voltage power supply unit 1, a startup unit 3, a voltage-controlled current source 2, a reference unit 4, an SR latch 5, a driving unit 6, a first delay unit 8, an XOR gate XOR, a D flip-flop 9, a clamping unit 10, a ramp generator 11, a comparator CMP1, a comparator CMP2, a comparator CMP3, a switch SW2, a switch SW3, a resistor R10, a switch SW1 and a second delay unit 7 are all arranged on the chip body 100;

[0052] In addition, the chip body 100 is also provided with an HV pin, a VCC pin, a CS pin, a COMP pin, a GND pin and a GATE pin; the HV pin is electrically connected to the high-voltage power supply unit 1 for inputting an external voltage; the VCC pin is electrically connected to the working voltage output terminal of the high-voltage power supply unit 1; the CS pin is used to input a sampling voltage; the COMP pin is electrically connected to the input terminal of the clamp unit 10, and the GND pin is used to ground the ground terminal in the circuit; and the GATE pin is electrically connected to the output terminal of the driving unit 6.

[0053] It should be noted that Figure 3The pin distribution on the chip body 100 is only for the convenience of connecting with the unit on the chip body 100, and is not the actual distribution position. The actual distribution position of the pins can be referred to Figure 4 , as follows:

[0054] The GATE pin and the CS pin are arranged on the right side of the chip body 100 from top to bottom; the HV pin, the VCC pin, the COMP pin, and the GND pin are arranged on the left side of the chip body 100 from top to bottom.

[0055] In addition, the operation of the driving chip in this embodiment and the beneficial effects of the related units are described with reference to the switching power supply part in the second embodiment, and no redundant description is given here.

[0056] Embodiment 2

[0057] The second embodiment provides a switching power supply, including the switching power supply driver chip in the first embodiment, and also includes an EMI filter 12 for filtering the alternating current power supply AC, the output end of the EMI filter 12 is electrically connected to the input end of the rectifier bridge BD, the DC voltage output end of the rectifier bridge BD is electrically connected to the positive electrode of the capacitor Cbus, one end of the resistor Rbus, the cathode of the diode D3 and one end of the primary winding N1 of the transformer T1, the negative electrode of the capacitor Cbus is grounded, the other end of the resistor Rbus is electrically connected to the HV pin, the anode of the diode D3 is electrically connected to one end of the demagnetization winding N3 of the transformer T1, the other end of the demagnetization winding N3 of the transformer T1 is grounded, the other end of the primary winding N1 is electrically connected to the drain of the MOS tube N1, the gate of the MOS tube Q1 is electrically connected to the GATE pin, the source of the MOS tube Q1 is electrically connected to the CS pin, and is grounded through the resistor Rcs;

[0058] The VCC pin of the driver chip is electrically connected to the cathode of the diode D4 and is grounded through the capacitor C1. The anode of the diode D4 is grounded through the power supply winding N4 of the transformer T1. The COMP pin of the driver chip is grounded through the capacitor C2. The GND pin of the driver chip is grounded.

[0059] One end of the secondary winding N2 of the transformer T1 is electrically connected to the anode of the diode D1, the cathode of the diode D1 is electrically connected to the cathode of the diode D2 and one end of the filter inductor Lm respectively, the other end of the filter inductor Lm is grounded through the output capacitor Co and the output resistor Ro respectively, and the other end of the secondary winding N2 and the anode of the diode D2 are both grounded;

[0060] The circuit also includes a feedback current generating unit 13 , which is electrically connected to the other end of the filter inductor Lm and the COMP pin, and forms a feedback current flowing out of the COMP pin based on the voltage at the other end of the filter inductor Lm.

[0061] Specifically, in this embodiment, the feedback current generating unit 13 includes a resistor R1, one end of the resistor R1 is electrically connected to one end of the resistor R3 and the other end of the filter inductor Lm respectively, the other end of the resistor R3 is electrically connected to the primary side input end of the photoelectric coupler OPT, the other end of the resistor R1 is electrically connected to one end of the resistor R2, one end of the capacitor C3 and the input end of the feedback amplifier chip U2 of model TL431, the other end of the resistor R2 and the anode of the feedback amplifier chip U2 are both grounded, the other end of the capacitor C3 is electrically connected to the output end of the primary side of the photoelectric coupler OPT and the cathode of the feedback amplifier chip U2 respectively, the secondary side input end of the photoelectric coupler OPT is electrically connected to the COMP pin, and the secondary side output end of the photoelectric coupler OPT is grounded.

[0062] In addition, in this embodiment, the MOS transistor Q1 is an NMOS transistor.

[0063] In this embodiment, the working process of the switching power supply of the present invention is as follows:

[0064] The AC power source AC passes through the rectifier bridge BD and is converted into a fluctuating bus voltage Vbus by the capacitor Cbus. The bus voltage Vbus charges the capacitor C1 through the resistor Rbus and the HV pin in turn. The function of the capacitor C1 is to power the entire chip.

[0065] When the voltage of capacitor C1 rises, it supplies power to reference unit 4. Meanwhile, the voltage of capacitor C1 is detected by start-up unit 3. When the voltage of capacitor C1 does not reach the start-up threshold, the first start-up signal VON and the second start-up signal VOFF output by start-up unit 3 are respectively in low level state and high level state, and the control signal F1 output by the output terminal Q of D flip-flop is in low level state.

[0066] When the voltage of capacitor C1 reaches the start threshold, the first start signal VON and the second start signal VOFF output by the start unit 3 are respectively in high level state and low level state. After the reference unit 4 is enabled, the three output terminals output reference voltage REF1, reference voltage REF2 and reference voltage REF3 respectively. At the same time, the drive unit 6 is also enabled, and the QP output terminal of the SR latch 5 outputs a high level to the drive unit 6, and the drive unit 6 starts to output a high level, so that the Gate pin of the chip outputs a high level signal to drive the MOS tube Q1 to turn on. After the MOS tube Q1 is turned on, the bus voltage Vbus is loaded on the primary winding N1 of the transformer T1, and the primary winding N1 begins to flow current. The current flowing through the primary winding N1 is transmitted to the CS pin through the sampling voltage generated by the resistor RCS. According to the transformer principle, the voltage of the primary winding N1 divided by the ratio of the number of turns of the primary and secondary coils ( Figure 4The ratio of N1 to N2 (referred to as turns ratio) is equal to the secondary voltage. The secondary voltage charges the load through the filter inductor Lm. The charging current divided by the turns ratio is equal to the primary current (compared to the reflected current, the excitation current is ignored).

[0067] In addition, because the MOS tube Q1 in the switching power supply will bring noise and burrs at the node every time it is turned off and on, the sampling of the CS pin must be separated by a switch, that is, the switch SW1 inside the chip, and the controlled end of the switch SW1 is electrically connected to the output end of the second delay unit 7. When the QP output end of the SR latch 5 starts to output a high-level signal, the switch SW1 will be turned on after the delay of the second delay unit 7; thereafter, the sampled voltage will be transmitted to the positive input end of the comparator CMP1.

[0068] When the peak voltage of the sampling voltage reaches the voltage of the negative input terminal of the comparator CMP1, the comparator CMP1 outputs a high-level signal and makes the SR latch 5 output inversion, that is, the QP output terminal outputs a low-level signal, and the QN output terminal outputs a high-level signal, and the driving unit 6 outputs a low-level signal to turn off the MOS tube Q1. At the same time, the high-level signal output from the QN output terminal starts the slope compensator 11 to output the slope compensation voltage. When the peak value of the slope compensation voltage output by the slope compensator 11 reaches the reference voltage REF2, the output of the comparator CMP2 is high, making the SR latch 5 output inversion, that is, the QP output terminal outputs a high-level signal, and the QN output terminal outputs a low-level signal. The low-level signal output from the QN output terminal stops the output of the slope compensator 11, and the high-level signal output from the QP output terminal makes the driving unit 6 output a high level to turn on the MOS tube Q1, and the switching power supply works repeatedly.

[0069] For the switching power supply, its output voltage, i.e., the voltage at the other end of the filter inductor Lm, is divided by resistors R1 and R2 and input to the feedback amplifier chip U2. The feedback amplifier chip U2, the optocoupler opt and the resistor R3 form a feedback current, which is amplified by the optocoupler opt and forms a current at the primary side and flows out of the COMP pin. The COMP pin will generate a voltage VCOMP related to the load energy. When the load increases, i.e., the equivalent resistance of the load decreases, the output voltage decreases, and the feedback current generating unit 12 increases the voltage VCOMP value. The peak voltage of the sampling voltage increases, which increases the output voltage. Otherwise, the voltage VCOMP is reduced, thereby reducing the output voltage. The function of the capacitor C2 is to prevent the VCOMP voltage from generating a large peak noise voltage when the MOS tube Q1 is turned on and off.

[0070] Each time the signal output from the QP output terminal of the SR latch 5 is converted to a high level, it is delayed by the second delay unit 7 and then sends out a CS_LEB signal, thereby turning on the switch SW1, and the sampling voltage is transmitted to the positive input terminal of the comparator CMP1 to avoid the spike noise signal generated by the opening of the MOS tube Q1. At the same time, the CS_LEB signal is delayed by the second delay unit 8 and then transmitted to the two input terminals of the XOR gate XOR with the CS_LEB signal itself. According to the input characteristics of the XOR gate XOR, the XOR gate XOR outputs a high level before the CS_LEB signal arrives after the delay signal of the first delay unit 8, so the switch SW2 is turned on and the sampling voltage is transmitted to the positive input terminal of the comparator CMP3; after the CS_LEB signal arrives at the XOR gate XOR after the delay signal of the first delay unit 8, the switch SW2 is turned off, and the sampling voltage stops being input to the positive input terminal of the comparator CMP3. Therefore, each time the MOS tube Q1 is turned on, after the delay of the first delay unit 8, the sampled voltage will be sampled by the comparator CMP3 for a period of time, and this period of time is the delay time of the first delay unit 8. As long as the delay time of the first delay unit 8 is appropriate, the primary starting current of the MOS tube Q1 after each turn-on is indirectly sampled.

[0071] According to the energy conversion of the forward topology of the switching power supply in the CCM state, the following formula is obtained:

[0072]

[0073] V OUT It is the specified output voltage, the value that can be adjusted in a designed system.

[0074] T OFF It is the turn-off time of MOS tube Q1, which can remain unchanged in the designed system.

[0075] N PS It is the ratio of the primary winding N1 to the secondary winding N2 of the transformer T1, and is a value that can remain unchanged in a designed system.

[0076] Lm is the inductance of the secondary filter inductor, which can remain unchanged in a designed system.

[0077] R O is the equivalent resistance of the output

[0078] R CS It is the resistance from the source of MOS tube Q1 to the GND pin, which can remain unchanged in the designed system.

[0079] V CS_0 The voltage on the resistor RCS after the MOS tube Q1 is turned on and delayed by the first delay unit is transmitted to the positive input terminal of the comparator CMP3.

[0080] V CS_PK The voltage when the MOS tube Q1 is turned on is equal to the voltage VCOMP.

[0081] When the load resistance Ro is the rated value, the best state is V CS_PK Equal to V CLAMP Voltage, V CLAMP is the clamping threshold of the clamping unit, thereby ensuring that the peak current of the system is the maximum value when the rated load is applied, and the peak value of the system can also be limited.

[0082] Set the load resistor Ro to a rated value of V CS_PK Set to V CLAMP Value, if V OUT unchanged, according to the formula 1V CS_0 That's confirmed.

[0083] Once the load becomes heavier or fluctuates to a heavier value, the load resistance Ro decreases because V CS_PK has been clamped to its maximum value, V CS_0 According to formula 1, there should be no sudden change. Then according to formula 2V OUT will inevitably decrease. Once V OUT decreases, which will inevitably lead to V CS_0 Increase.

[0084] So as long as the rated V CS_PK Set to V CLAMP Once the system is overloaded, the positive input of comparator CMP3 will be passed to a higher V CS_0 The smaller the load resistance Ro is, the V CS_0 The higher the value, the lower the VCS_0 will be. The system will still operate stably if VCS_0 does not reach the reference voltage REF3. CS_0 When the reference voltage REF3 is reached, the comparator CMP3 outputs a high-level signal. After the high-level signal is received by the D flip-flop, the control signal F1 output from the Q output terminal is high, and the control signal F2 output from the QN output terminal turns to a low level. The enable terminal of the ramp generator 11 is low, the output ramp voltage stops, the comparator CMP2 does not invert, and the SR latch 5 is not triggered. The QP output terminal of the SR latch 5 no longer outputs a high level, the drive unit 6 no longer outputs a high level to the Gate pin, and the MOS tube Q1 is no longer turned on.

[0085] At the same time, the high-level control signal F1 will also start the voltage-controlled current source 2, and the controlled current will pull the voltage of the VCC pin down until the voltage of the VCC pin is less than the start threshold of the start unit 3, and then the first start signal VON and the second start signal VOFF are reversed, which are low-level and high-level states respectively. The low-level first start signal VON makes the reference unit 4 and the drive unit 6 not work, and the high-level second start signal VOFF is transmitted to the reset end of the D flip-flop 9. The control signal F1 output by the D flip-flop 9 changes from high level to low level, and the voltage-controlled current source 2 no longer pulls down the voltage of the VCC pin. The voltage of the VCC pin rises again due to the charging of the high-voltage power supply unit 1 until the first start signal VON and the second start signal VOFF are reversed again, and then the system starts working again. The period from sending the control signal F1 to the system restarting is called restart. If the overload state is not eliminated, the system's V CS_0 After the voltage is equal to the reference voltage REF3, the comparator CMP3 sends out a control signal F1 and starts to restart, and the cycle repeats until the overload state is eliminated. After the system restarts, V CS_0 The device will maintain stable operation if the reference voltage REF3 is no longer touched.

[0086] From the working process of the above switching power supply, we can know that as long as the switching power supply is working at rated load, V CS_PK Designed in V CLAMP , once the load resistance Ro continues to decrease, as long as the reduction amplitude makes V CS_0 If the reference voltage REF3 is not exceeded, the switching power supply will continue to work, but the switching power supply is in an open-loop state, that is, V COMP It is already at the maximum value of effective control. The secondary output of transformer T1 is manifested as a decrease in output voltage, but the switching power supply will not stop working, effectively preventing the output of the switching power supply from disappearing due to non-operation when the load is slightly overloaded or fluctuating, avoiding abnormal operation of the load or even damage to the load, and the load must be overloaded again before it stops working;

[0087] The relevant signals during the operation of the switching power supply in this embodiment are as follows Figure 5 As shown, from Figure 5 It can be seen that the peak current of the switching power supply is consistent when the switching power supply is overloaded and rated load, avoiding the problem of reduced system reliability caused by increasing the peak current when the traditional forward pulse is overloaded.

[0088] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A switching power supply driver chip, characterized in that: It includes a high-voltage power supply unit, a startup unit, a voltage-controlled current source, a reference unit, an SR latch, a driving unit, a first delay unit, an XOR gate XOR, a D flip-flop, a clamping unit, a ramp generator, a comparator CMP1, a comparator CMP2, a comparator CMP3, a switch SW2, a switch SW3 and a resistor R10; The high-voltage power supply unit outputs a working voltage based on an input external voltage, and the working voltage output terminal of the high-voltage power supply unit is electrically connected to the first output terminal of the startup unit, the reference unit and the voltage-controlled current source respectively; the second output terminal and the negative input terminal of the voltage-controlled current source are both grounded; the startup unit outputs a first startup signal VON and a second startup signal VOFF based on the working voltage; the reference unit includes a reference enable terminal for inputting a first startup signal VON, and outputs a reference voltage REF1, a reference voltage REF2 and a reference voltage REF3 when the first startup signal VON is at a high level; The positive input terminal of the comparator CMP1 is used to input the sampling voltage and is electrically connected to the input terminal of the switch SW2. The negative input terminal of the comparator CMP1 is electrically connected to the output terminal of the clamping unit. The input terminal of the clamping unit is electrically connected to one end of the resistor R10, and the other end of the resistor R10 inputs the reference voltage REF2. The clamping unit outputs the voltage of its own input terminal when the voltage of its own input terminal is less than the clamping voltage, and outputs the clamping voltage when the voltage of its own input terminal is greater than or equal to the clamping voltage. The control end of the switch SW2 is electrically connected to the output end of the XOR gate XOR, the two input ends of the XOR gate XOR are electrically connected to the output end of the first delay unit and the input end of the first delay unit respectively, the output end of the switch SW2 is electrically connected to the positive input end of the comparator CMP3, the negative input end of the comparator CMP3 is used to input the reference voltage REF3, the output end of the comparator CMP3 is electrically connected to the clock end of the D flip-flop, the reset end of the D flip-flop is used to input the second start signal VOFF, the Q output end of the D flip-flop outputs the control signal F1, and is electrically connected to the positive input end of the voltage-controlled current source, and the QN output end of the D flip-flop outputs the control signal F2; The output end of the comparator CMP1 is electrically connected to the R input end of the SR latch, and the S input end of the SR latch is electrically connected to the output end of the comparator CMP2; the QP output end of the SR latch is electrically connected to the input end of the first delay unit and the input end of the driving unit respectively, and the driving unit includes a driving enable end for inputting the first start signal VON, and outputs a driving signal based on the signal of the QP output end of the SR latch when the first start signal VON is at a high level; the QN output end of the SR latch is electrically connected to the input end of the ramp generator, and the ramp generator includes a ramp enable end for inputting the control signal F2, and inputs a ramp compensation signal to the positive input end of the comparator CMP2 based on the signal of the QN output end of the SR latch when the control signal F2 is at a high level, and the negative input end of the comparator CMP2 is used to input the reference voltage REF1.

2. A switching power supply driver chip according to claim 1, characterized in that: The startup unit outputs a low-level first startup signal VON and a high-level second startup signal VOFF when the operating voltage is less than the startup threshold, and outputs a high-level first startup signal VON and a low-level second startup signal VOFF when the operating voltage is greater than the startup threshold.

3. A switching power supply driver chip according to claim 1, characterized in that: When the first start signal VON is at a high level, the level state of the drive signal output by the drive unit is the same as the signal level state of the QP output terminal of the SR latch.

4. A switching power supply driver chip according to claim 1, characterized in that: The ramp generator outputs a slope compensation signal when the control signal F2 is at a high level and the signal at the QN output terminal of the SR latch is at a high level.

5. A switching power supply driver chip according to any one of claims 1 to 4, characterized in that: It also includes a switch SW1 and a second delay unit, the QP output end of the SR latch is electrically connected to the input end of the first delay unit through the second delay unit, the input end of the first delay unit is electrically connected to the control end of the switch SW1, the output end of the switch SW1 is electrically connected to the positive input end of the comparator CMP1, and the input end of the switch SW1 is used to input a sampling voltage.

6. A switching power supply driver chip according to claim 5, characterized in that: It also includes a chip body, wherein the high-voltage power supply unit, the startup unit, the voltage-controlled current source, the reference unit, the SR latch, the drive unit, the first delay unit, the XOR gate XOR, the D flip-flop, the clamp unit, the ramp generator, the comparator CMP1, the comparator CMP2, the comparator CMP3, the switch SW2, the switch SW3, the resistor R10, the switch SW1 and the second delay unit are all arranged on the chip body; The chip body is also provided with an HV pin, a VCC pin, a CS pin, a COMP pin, a GND pin and a GATE pin; the HV pin is electrically connected to the high-voltage power supply unit for inputting an external voltage; the VCC pin is electrically connected to the working voltage output end of the high-voltage power supply unit; the CS pin is used to input a sampling voltage; the COMP pin is electrically connected to the input end of the clamp unit, and the GND pin is used to ground the ground terminal in the circuit; the GATE pin is electrically connected to the output end of the drive unit.

7. A switching power supply driver chip according to claim 6, characterized in that: The GATE pin and the CS pin are arranged from top to bottom on the right side of the chip body; the HV pin, the VCC pin, the COMP pin, and the GND pin are arranged from top to bottom on the left side of the chip body.

8. A switching power supply, characterized in that: The invention comprises the switching power supply driver chip as claimed in claim 7, and further comprises an EMI filter for filtering the AC power supply, wherein the output end of the EMI filter is electrically connected to the input end of the rectifier bridge, the DC voltage output end of the rectifier bridge is electrically connected to the positive electrode of the capacitor Cbus, one end of the resistor Rbus, the cathode of the diode D3 and one end of the primary winding N1 of the transformer T1, respectively, the negative electrode of the capacitor Cbus is grounded, the other end of the resistor Rbus is electrically connected to the HV pin, the anode of the diode D3 is electrically connected to one end of the demagnetization winding N3 of the transformer T1, the other end of the demagnetization winding N3 of the transformer T1 is grounded, the other end of the primary winding N1 is electrically connected to the drain of the MOS tube N1, the gate of the MOS tube Q1 is electrically connected to the GATE pin, the source of the MOS tube Q1 is electrically connected to the CS pin, and is grounded through the resistor Rcs; The VCC pin of the driver chip is electrically connected to the cathode of the diode D4 and is grounded through the capacitor C1. The anode of the diode D4 is grounded through the power supply winding N4 of the transformer T1. The COMP pin of the driver chip is grounded through the capacitor C2. The GND pin of the driver chip is grounded. One end of the secondary winding N2 of the transformer T1 is electrically connected to the anode of the diode D1, the cathode of the diode D1 is electrically connected to the cathode of the diode D2 and one end of the filter inductor Lm respectively, the other end of the filter inductor Lm is grounded through the output capacitor Co and the output resistor Ro respectively, and the other end of the secondary winding N2 and the anode of the diode D2 are both grounded; The device further includes a feedback current generating unit, which is electrically connected to the other end of the filter inductor Lm and the COMP pin respectively, and forms a feedback current flowing out of the COMP pin based on the voltage at the other end of the filter inductor Lm.

9. A switching power supply according to claim 8, characterized in that: The feedback current generating unit includes a resistor R1, one end of the resistor R1 is electrically connected to one end of a resistor R3 and the other end of a filter inductor Lm respectively, the other end of the resistor R3 is electrically connected to the primary side input end of the photoelectric coupler OPT, the other end of the resistor R1 is electrically connected to one end of a resistor R2, one end of a capacitor C3 and the input end of a feedback amplifier chip of model TL431 respectively, the other end of the resistor R2 and the anode of the feedback amplifier chip are both grounded, the other end of the capacitor C3 is electrically connected to the output end of the primary side of the photoelectric coupler OPT and the cathode of the feedback amplifier chip respectively, the secondary side input end of the photoelectric coupler OPT is electrically connected to the COMP pin, and the secondary side output end of the photoelectric coupler OPT is grounded.

10. A switching power supply according to claim 8, characterized in that: The MOS tube Q1 is an NMOS tube.

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