Inverter circuit, inverter control method and storage medium

Abstract

The present application provides an inverter circuit, an inverter control method and a storage medium, which can improve the efficiency of inverter conversion. The inverter circuit includes: a processor, an inverter input module, a transformer module; and an inverter output module; the inverter input module includes a DC power supply and four MOS tubes; the inverter output module includes four MOS tubes connected in sequence; the transformer module includes a transformer and a first inductor; the processor is connected to the third ends of the above eight MOS tubes, and is used to control the conduction or shutdown of each MOS tube to convert the DC voltage output by the DC power supply into an AC voltage.

Description

Technical Field

[0001] The present application relates to the technical field of photovoltaic grid-connected inverters, and in particular to an inverter circuit, an inverter control method and a storage medium. Background Art

[0002] In a photovoltaic system, after the solar panels convert solar energy into direct current, an inverter is needed to convert direct current (DC) into alternating current (AC). Inverters play a vital role in modern power systems and electronic devices, and are widely used in home, industrial, commercial and renewable energy fields. Although existing inverters can convert direct current (DC) into alternating current (AC), the conversion efficiency of the inverter still needs to be improved. Summary of the invention

[0003] One advantage of the present application is that it provides an inverter circuit, an inverter control method and a storage medium, which can improve the efficiency of inverter conversion.

[0004] Another advantage of the present application is to provide an inverter circuit, an inverter control method and a storage medium, wherein in order to achieve the above advantages, no expensive materials or complex structures are required in the present application. Therefore, the solution provided by the present application can successfully and effectively solve the above problems, and not only provides a simple inverter circuit, inverter control method and storage medium, but also increases the practicality and reliability of the inverter circuit, inverter control method and storage medium.

[0005] Based on this, in order to achieve at least one of the above advantages or other advantages and purposes of the present application, the present application provides an inverter circuit, the inverter circuit comprising:

[0006] Processor, inverter input module, transformer module; and inverter output module;

[0007] The inverter input module includes a DC power supply, a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, one end of the DC power supply is connected to the first end of the first MOS tube, and the other end of the DC power supply is connected to the second end of the second MOS tube, the second end of the first MOS tube is connected to the first end of the second MOS tube, the first end of the third MOS tube is connected to the first end of the first MOS tube, the second end of the fourth MOS tube is connected to the second end of the second MOS tube, and the second end of the third MOS tube is connected to the first end of the fourth MOS tube;

[0008] The inverter output module includes a first capacitor, a second capacitor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor, wherein the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are connected in sequence, the second end of the first capacitor is connected to the first end of the second capacitor, and the first end of the first capacitor is connected to the first end of the fifth MOS transistor, and the second end of the second capacitor is connected to the second end of the eighth MOS transistor;

[0009] The voltage transformation module includes a transformer and a first inductor, one end of the first inductor is connected to the output positive terminal of the transformer, the input positive terminal of the transformer is connected to the second end of the first MOS transistor, the input negative terminal of the transformer is connected to the second end of the third MOS transistor, the output negative terminal of the transformer is connected to the second end of the first capacitor, and the other end of the first inductor is connected to the second end of the sixth MOS transistor;

[0010] The processor is connected to the third end of the first MOS tube, the third end of the second MOS tube, the third end of the third MOS tube, and the third end of the fourth MOS tube, and the processor is connected to the third end of the fifth MOS tube, the third end of the sixth MOS tube, the third end of the seventh MOS tube, and the third end of the eighth MOS tube, and is used to control the conduction state of each MOS tube so that the change of the working state of each MOS tube of the inverter circuit occurs at the moment when the AC voltage is zero.

[0011] With such configuration, the processor can convert the DC voltage output by the DC power supply into an AC voltage by means of the bridge composed of the MOS transistors in the inverter input module and the bridge composed of the MOS transistors in the inverter control module.

[0012] According to one embodiment of the present application, the inverter circuit also includes a sampling module, a first input end of the sampling module is connected to the two ends of the DC power supply, and a second input end of the sampling module is connected to the two ends of the first inductor, an output end of the sampling module is connected to the processor, and the processor is connected to the third end of the fifth MOS tube, the third end of the sixth MOS tube, the third end of the seventh MOS tube, and the third end of the eighth MOS tube, and the sampling module is used to sample the DC voltage Upv output by the DC power supply and the inductor voltage Uac between the two ends of the first inductor.

[0013] With such configuration, the DC voltage Upv output by the DC power supply and the inductor voltage Uac between the two ends of the first inductor can be sampled by means of the sampling module, and the collected data can be transmitted to the processor so that the processor can control the circuit according to the collected data.

[0014] According to an embodiment of the present application, the capacitance values ​​of the first capacitor and the second capacitor are equal.

[0015] In this way, the voltage value across the first capacitor and the voltage value across the second capacitor can be made the same, so that the voltage value (second voltage Ucd) between the other end of the first inductor and the second end of the first capacitor is constant and does not change with the different conduction states of the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube.

[0016] According to another aspect of the present application, the present application further provides an inverter control method for controlling the above-mentioned inverter circuit, the inverter control method comprising the following steps:

[0017] S1, sampling to obtain a DC voltage Upv output by the DC power supply and an inductor voltage Uac between two ends of the first inductor, and obtaining a first voltage Uab and a second voltage Ucd according to the DC voltage Upv and the inductor voltage Uac;

[0018] S2, determining a current voltage angle θ according to the first voltage Uab, and determining a voltage ratio k according to the first voltage Uab and the second voltage Ucd, where k=the first voltage Uab / the second voltage Ucd;

[0019] S3, calculating the target power instantaneous value Pnow according to the preset target power Pall and the current voltage angle θ;

[0020] S4, calculating a first maximum power Pmax1 according to a preset cut-off frequency fs;

[0021] S5. Compare the target power transient value Pnow with the first maximum power Pmax1. If the target power transient value Pnow is greater than the first maximum power Pmax1, determine the target frequency fs1 according to the target power transient value Pnow. If the target power transient value Pnow is less than or equal to the first maximum power Pmax1, the value of the target frequency fs1 is equal to the cutoff frequency fs.

[0022] S6, obtaining a second maximum power Pmax2 according to the target frequency fs1, and determining a per-unit power value P according to the target power instantaneous value Pnow and the second maximum power Pmax2, wherein the per-unit power value P=target power instantaneous value Pnow / second maximum power Pmax2;

[0023] S7, determining a first lag time and a second lag time according to the power per unit value P, the voltage ratio k and the target frequency fs1;

[0024] S8. Control the conduction state of each MOS tube in the inverter circuit according to the first lag time and the second lag time, so that the change of the working state of each MOS tube in the inverter circuit occurs at the moment when the AC voltage is zero.

[0025] With such a configuration, the conduction state of each MOS tube in the inverter circuit can be controlled according to the sampled DC voltage Upv, the inductor voltage Uac, the preset target power Pall and the preset cut-off frequency fs, so that the change of the working state of each MOS tube in the inverter circuit occurs at the moment when the AC voltage is zero, thereby significantly reducing the switch loss and electromagnetic interference (EMI). In this way, not only the efficiency of each MOS tube in the inverter circuit is improved, the service life of each MOS tube is extended, but also the heat dissipation demand is reduced, thereby improving the overall efficiency of the power system and reducing the overall cost of the power system.

[0026] According to an embodiment of the present application, the calculation process of S3 is specifically as follows: target power transient value Pnow=target power Pall×sinθ×sinθ.

[0027] With such a configuration, the target power transient value Pnow can be calculated according to the preset target power Pall and the current voltage angle θ, which lays a foundation for subsequent processing of the target power transient value Pnow.

[0028] According to an embodiment of the present application, the calculation process of S4 is specifically as follows: first maximum power Pmax1=first voltage Uab×second voltage Ucd / (8×cut-off frequency fs×Lr), where Lr is the inductance value of the first inductor in the inverter circuit.

[0029] With such configuration, the first maximum power Pmax1 can be calculated according to the preset cut-off frequency fs, so as to compare the target power transient value Pnow with the first maximum power Pmax1 later.

[0030] According to an embodiment of the present application, the first lag time in S7 is the time that the fourth MOS transistor in the inverter circuit lags behind the first MOS transistor in the inverter circuit.

[0031] According to one embodiment of the present application, when the first voltage Uab is positive, the second lag time in S7 is the time that the fifth MOS tube in the inverter circuit lags behind the first MOS tube in the inverter circuit; when the first voltage Uab is negative, the second lag time in S7 is the time that the eighth MOS tube in the inverter circuit lags behind the first MOS tube in the inverter circuit.

[0032] According to one embodiment of the present application, S7 specifically includes:

[0033] A first phase difference D1 and a second phase difference D2 are calculated according to a ratio k of the power per unit value P and the voltage;

[0034] A first lag time and a second lag time are calculated according to the first phase difference D1, the second phase difference D2 and the target frequency fs1.

[0035] According to another aspect of the present application, the present application further provides a storage medium, which includes a stored program, wherein when the program is running, the device where the storage medium is located is controlled to execute the above-mentioned inverter power control method.

[0036] With such a configuration, the program stored in the storage medium can automatically perform complex tasks, reduce human intervention, thereby improving overall efficiency and ensuring the reliability and trustworthiness of operations. In addition, the program is repeatable and extensible, so that the same program can be repeatedly executed in different environments and at different times, and is easy to expand to meet new needs, thereby enhancing the adaptability and flexibility of the program. In addition, running the program can greatly optimize resource utilization and reduce manpower and error costs by automatically processing large amounts of data and tasks. Finally, the program is also traceable and secure, and can ensure the auditability and security of operations by recording and tracking each step of program execution, thereby reducing the risks brought by human operations.

[0037] Beneficial effect: The sampling module samples the DC voltage Upv output by the DC power supply and the inductor voltage Uac between the two ends of the first inductor, and transmits the collected data to the processor, and the processor obtains the first voltage Uab and the second voltage Ucd according to the DC voltage Upv and the inductor voltage Uac, and then determines the current voltage angle θ according to the first voltage Uab, and determines the voltage ratio k according to the first voltage Uab and the second voltage Ucd, and then calculates the target power transient value Pnow according to the preset target power Pall and the current voltage angle θ, and calculates the first maximum power Pmax1 according to the preset cut-off frequency fs, and compares the two. If the target power transient value Pnow is greater than the first maximum power Pmax1, the target frequency fs1 is determined according to the target power transient value Pnow; if the target power transient value If Pnow is less than or equal to the first maximum power Pmax1, the value of the target frequency fs1 is equal to the cut-off frequency fs, and then the second maximum power Pmax2 is obtained according to the determined target frequency fs1, and the power per unit value P is determined according to the target power transient value Pnow and the second maximum power Pmax2, and according to the power per unit value P and the ratio k of the voltage determined above, a first lag time of the fourth MOS tube in the inverter circuit lagging behind the first MOS tube in the inverter circuit and a second lag time of the fifth MOS tube or the eighth MOS tube in the inverter circuit lagging behind the first MOS tube in the inverter circuit are determined, and finally, the conduction state of each MOS tube in the inverter circuit is controlled according to the first lag time and the second lag time, so that the change of the working state of each MOS tube in the inverter circuit occurs at the moment when the AC voltage is zero, thereby significantly reducing the loss and electromagnetic interference (EMI) of the switch. For the inverter circuit, this can not only improve the efficiency of each MOS tube in the inverter circuit and extend the service life of each MOS tube, but also reduce the heat dissipation demand of the inverter circuit, thereby improving the overall efficiency of the power system and reducing the overall cost of the power system. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 A circuit diagram of an inverter circuit provided for one embodiment of the present application;

[0040] Figure 2A flowchart of an inverter control method provided for other embodiments of the present application.

[0041] Figure numerals: 10, inverter circuit; 11, inverter input module; 12, transformer module; 13, inverter output module. DETAILED DESCRIPTION

[0042] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. In the following description, many specific details are set forth to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar improvements without violating the connotation of the present application, so the present application is not limited by the specific embodiments disclosed below.

[0043] Considering that the existing inverter can convert direct current (DC) into alternating current (AC), the conversion efficiency of the inverter still has room for improvement. In order to solve this problem, the present application provides an inverter circuit 10, an inverter control method and a storage medium, which can improve the efficiency of inverter conversion.

[0044] For details, please refer to the attached Figure 1 An embodiment of the present application provides an inverter circuit 10, which may include: a processor, an inverter input module 11, a voltage transformation module 12; and an inverter output module 13.

[0045] More specifically, if Figure 1 As shown, the inverter input module 11 includes a DC power supply, a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, one end of the DC power supply is connected to the first end of the first MOS tube, and the other end of the DC power supply is connected to the second end of the second MOS tube, the second end of the first MOS tube is connected to the first end of the second MOS tube, the first end of the third MOS tube is connected to the first end of the first MOS tube, the second end of the fourth MOS tube is connected to the second end of the second MOS tube, and the second end of the third MOS tube is connected to the first end of the fourth MOS tube;

[0046] The inverter output module 13 includes a first capacitor, a second capacitor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor, wherein the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are connected in sequence, the second end of the first capacitor is connected to the first end of the second capacitor, and the first end of the first capacitor is connected to the first end of the fifth MOS transistor, and the second end of the second capacitor is connected to the second end of the eighth MOS transistor;

[0047] The transformer module 12 includes a transformer and a first inductor, one end of the first inductor is connected to the output positive terminal of the transformer, the input positive terminal of the transformer is connected to the second end of the first MOS transistor, the input negative terminal of the transformer is connected to the second end of the third MOS transistor, the output negative terminal of the transformer is connected to the second end of the first capacitor, and the other end of the first inductor is connected to the second end of the sixth MOS transistor;

[0048] The processor is connected to the third end of the first MOS tube, the third end of the second MOS tube, the third end of the third MOS tube, and the third end of the fourth MOS tube, and the processor is connected to the third end of the fifth MOS tube, the third end of the sixth MOS tube, the third end of the seventh MOS tube, and the third end of the eighth MOS tube, and is used to control the conduction state of each MOS tube so that the change of the working state of each MOS tube of the inverter circuit 10 occurs at the moment when the AC voltage is zero.

[0049] It should be noted that the processor can convert the DC voltage output by the DC power supply into an AC voltage with the help of the bridge composed of the MOS tubes in the inverter input module 11 and the bridge composed of the MOS tubes in the inverter control module.

[0050] It is worth noting that the inverter circuit 10 also includes a sampling module, the first input end of the sampling module is connected to the two ends of the DC power supply, and the second input end of the sampling module is connected to the two ends of the first inductor, the output end of the sampling module is connected to the processor, and the processor is connected to the third end of the fifth MOS tube, the third end of the sixth MOS tube, the third end of the seventh MOS tube, and the third end of the eighth MOS tube, and the sampling module is used to sample the DC voltage Upv output by the DC power supply and the inductor voltage Uac between the two ends of the first inductor. In this way, the DC voltage Upv output by the DC power supply and the inductor voltage Uac between the two ends of the first inductor can be sampled with the help of the sampling module, and the collected data can be transmitted to the processor, so that the processor controls the circuit according to the collected data.

[0051] It is worth noting that Figure 1 As shown in the figure, the capacitance values ​​of the first capacitor and the second capacitor are equal, so that the voltage value across the first capacitor and the voltage value across the second capacitor can be made the same, so that the voltage value (second voltage Ucd) between the other end of the first inductor and the second end of the first capacitor is constant and will not change with the different conduction states of the fifth MOS tube, the sixth MOS tube, the seventh MOS tube and the eighth MOS tube.

[0052] In another embodiment of the present application, Figure 2 As shown, an inverter control method is provided for controlling the above-mentioned inverter circuit 10, and the inverter control method comprises the following steps:

[0053] S1, sampling to obtain a DC voltage Upv output by the DC power supply and an inductor voltage Uac between two ends of the first inductor, and obtaining a first voltage Uab and a second voltage Ucd according to the DC voltage Upv and the inductor voltage Uac;

[0054] It is worth noting that, in S1, the first voltage Uab=DC voltage Upv×number of turns of transformer coil N, and the second voltage Ucd=inductor voltage Uac / 2.

[0055] S2, determining a current voltage angle θ according to the first voltage Uab, and determining a voltage ratio k according to the first voltage Uab and the second voltage Ucd, where k=the first voltage Uab / the second voltage Ucd;

[0056] It is worth noting that, in S2, the current voltage angle θ is determined according to the first voltage Uab as follows:

[0057] Decomposing the AC voltage Uac into two mutually perpendicular first voltage vectors Uα and second voltage vectors Uβ by using a SOGI algorithm;

[0058] The first voltage vector Uα and the second voltage vector Uβ are converted into an active voltage component Ud and a reactive voltage component Uq, and Uq is PI modulated with 0 as the target value to obtain the current voltage angle θ.

[0059] In particular, the SOGI (Second-Order Generalized Integrator) algorithm is often used in filter structures in power electronics and signal processing, especially in environments such as power grid synchronization, harmonic analysis and active filtering, and converts the input quantity of the SOGI algorithm into two mutually perpendicular vectors, namely, a sine component and a cosine component.

[0060] In particular, a phase-locked loop (PLL) is a feedback control system that is mainly used to synchronize frequency and phase and is widely used in communications, signal processing, audio and video equipment, etc. The basic goal of a PLL is to lock the frequency and phase of the output signal to the frequency and phase of the input signal.

[0061] In particular, PI (proportional integral) modulation is a common control strategy that is widely used in various control systems, such as motor control, temperature control, voltage regulation, etc. PI modulation combines the two control functions of proportional (P) and integral (I), which can effectively reduce the steady-state error and improve the response speed of the system. Specifically, proportional control (P): adjust according to the current deviation (the difference between the target value and the actual value) to provide a control amount proportional to the deviation, and integral control (I): accumulate past deviations to eliminate steady-state errors, and adjust the output by integrating historical deviations to ensure that the system is stable near the set point. It is worth noting, however, that the first lag time in S7 is the time that the fourth MOS tube in the inverter circuit 10 lags behind the first MOS tube in the inverter circuit 10, and when the first voltage Uab is positive, the second lag time in S7 is the time that the fifth MOS tube in the inverter circuit 10 lags behind the first MOS tube in the inverter circuit 10; when the first voltage Uab is negative, the second lag time in S7 is the time that the eighth MOS tube in the inverter circuit 10 lags behind the first MOS tube in the inverter circuit 10.

[0062] S3, calculating the target power instantaneous value Pnow according to the preset target power Pall and the current voltage angle θ;

[0063] It is worth noting that the calculation process of S3 is specifically as follows: target power instantaneous value Pnow=target power Pall×sinθ×sinθ.

[0064] S4, calculating a first maximum power Pmax1 according to a preset cut-off frequency fs;

[0065] It is worth noting that the calculation process of S4 is specifically as follows: first maximum power Pmax1 = first voltage Uab×second voltage Ucd / (8×cut-off frequency fs×Lr), where Lr is the inductance value of the first inductor in the inverter circuit 10 .

[0066] S5. Compare the target power transient value Pnow with the first maximum power Pmax1. If the target power transient value Pnow is greater than the first maximum power Pmax1, determine the target frequency fs1 according to the target power transient value Pnow. If the target power transient value Pnow is less than or equal to the first maximum power Pmax1, the value of the target frequency fs1 is equal to the cutoff frequency fs.

[0067] It is worth noting that in S5, when the target power transient value Pnow is greater than the first maximum power Pmax1, the target frequency fs1 is determined according to the target power transient value Pnow, specifically: target frequency fs1 = first voltage Uab×second voltage Ucd / (8×target power transient value Pnow×Lr), Lr is the inductance value of the first inductor in the inverter circuit 10.

[0068] S6, obtaining a second maximum power Pmax2 according to the target frequency fs1, and determining a per-unit power value P according to the target power instantaneous value Pnow and the second maximum power Pmax2, wherein the per-unit power value P=target power instantaneous value Pnow / second maximum power Pmax2;

[0069] It is worth noting that the second maximum power Pmax2 obtained in S6 according to the target frequency fs1 is specifically: second maximum power Pmax2=first voltage Uab×second voltage Ucd / (8×target frequency fs1×Lr), where Lr is the inductance value of the first inductor in the inverter circuit 10.

[0070] S7, determining a first lag time and a second lag time according to the power per unit value P, the voltage ratio k and the target frequency fs1;

[0071] It is worth noting that S7 specifically comprises: calculating the first phase difference D1 and the second phase difference D2 according to the ratio k of the power per unit value P and the voltage; calculating the first lag time and the second lag time according to the first phase difference D1, the second phase difference D2 and the target frequency fs1.

[0072] Table 1 Relationship between the voltage ratio k and the power per unit value P and the first phase difference D1 and the second phase difference D2

[0073]

[0074] It should be noted that, as shown in the table above, the calculation relationship between the value range of the voltage ratio k and the power per unit value P and the values ​​of the first phase difference D1 and the second phase difference D2 is obtained by solving the first phase difference D1 and the second phase difference D2 with il as the objective function and the power per unit value P and ZVS conduction as constraints by the Lagrange multiplier method. The specific il is.

[0075] The zero voltage switching (Zero Voltage Switching, ZVS) refers to ensuring that the voltage is zero at the moment of turning on the switch device, thereby avoiding the situation where voltage and current exist at the same time. The voltage drops to zero before the switch is turned on, thereby significantly reducing switching losses and electromagnetic interference (EMI). In this way, not only the efficiency of each MOS tube in the inverter circuit 10 is improved, the service life of each MOS tube is extended, but also the heat dissipation demand is reduced, thereby improving the overall efficiency of the power system and reducing the overall cost of the power system.

[0076] S8. Control the conduction state of each MOS tube in the inverter circuit 10 according to the first lag time and the second lag time, so that the change of the working state of each MOS tube in the inverter circuit 10 occurs at the moment when the AC voltage is zero.

[0077] It should be noted that as the transient value of the AC voltage changes, the processor controls the conduction state of each MOS tube in the inverter circuit 10 according to the first lag time and the second lag time, that is, when the transient value of the AC voltage is zero, the processor controls each MOS tube in the inverter circuit 10 to change the working state (on or off).

[0078] It is worth noting that the first MOS tube and the second MOS tube are complementarily turned on, the third MOS tube and the fourth MOS tube are complementarily turned on, and when the AC voltage is positive, the fifth MOS tube and the seventh MOS tube are complementarily turned on, and the sixth MOS tube and the eighth MOS tube are always turned on; when the AC voltage is negative, the sixth MOS tube and the eighth MOS tube are complementarily turned on, and the fifth MOS tube and the seventh MOS tube are always turned on.

[0079] In particular, complementary conduction refers to the use of two complementary semiconductor devices (such as N-channel and P-channel MOSFETs, or N-channel and P-channel IGBTs) in electronic circuits to achieve signal switching control or power modulation by alternating on and off, and after one of the semiconductor devices switches from the on state to the off state, the other semiconductor device will delay for a certain period of time before switching from the off state to the on state. This time is called dead time, which is generally in the us level (microsecond level). The dead time of MOS tubes is generally 0.2us-0.3us, and the dead time of IGBT (insulated gate bipolar transistor) is generally 1.2us-2us), which is determined according to the performance of the actual semiconductor device. This structure is often used in applications such as power amplifiers, switching power supplies, and motor drives to improve efficiency and reduce power consumption, while reducing electromagnetic interference. The two complementary devices complement each other in design, one is turned on and the other is turned off, thereby achieving efficient signal processing and power control.

[0080] It should be noted that the processor can calculate the first lag time and the second lag time according to the DC voltage Upv, the inductor voltage Uac, the preset target power Pall and the preset cut-off frequency fs sampled by the sampling module, so as to control the conduction state of each MOS tube in the inverter circuit 10 according to the first lag time and the second lag time, so that the change of the working state of each MOS tube in the inverter circuit 10 occurs at the moment when the AC voltage is zero, thereby significantly reducing the loss and electromagnetic interference (EMI) of the switch. In this way, not only the efficiency of each MOS tube in the inverter circuit 10 is improved, the service life of each MOS tube is extended, but also the heat dissipation demand is reduced, thereby improving the overall efficiency of the power system and reducing the overall cost of the power system.

[0081] In other embodiments of the present application, a computer program is provided, and running the computer program can execute the above-mentioned inverter control method.

[0082] Other embodiments of the present application further provide a storage device, wherein the storage medium includes a stored program, wherein when the program is executed, the device where the storage medium is located is controlled to execute the above-mentioned inverter control method.

[0083] It is worth noting that the program stored in the storage medium can automatically perform complex tasks, reduce human intervention, thereby improving overall efficiency and ensuring the reliability and trustworthiness of operations. In addition, the program is repeatable and extensible, so that the same program can be repeatedly executed in different environments and times, and is easy to expand to meet new needs, enhancing the adaptability and flexibility of the program. In addition, running the program can greatly optimize resource utilization and reduce manpower and error costs by automating the processing of large amounts of data and tasks. Finally, the program is also traceable and secure, and can ensure the auditability and security of operations by recording and tracking every step of the program execution, reducing the risks brought by human operations.

[0084] In other embodiments of the present application, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the above-mentioned inverter control method when executing the computer program.

[0085] It is worth noting that the computer program is flexible and adaptable, so that the execution steps can be adjusted according to different inputs and conditions, so as to adapt to the ever-changing needs and technical environment, and maintain the advancement and practicality of the computer program. In addition, the architecture of the computer device allows the realization of multiple functions, so that the program in the memory can contain multiple functional modules, and the computer program can be executed by the processor to meet different application needs, thereby improving the function of the computer program and enhancing the integration of the computer device.

[0086] It should be noted that when a component is referred to as being "fixed to" or "disposed on" another component, it may be directly on the other component or there may also be a central component. When a component is considered to be "connected to" another component, it may be directly connected to the other component or there may be a central component at the same time. The terms "vertical", "horizontal", "upper", "lower", "left", "right" and similar expressions used in the specification of this application are for illustrative purposes only and do not represent the only implementation method.

[0087] In addition, the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "multiple" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, device, product or equipment that includes a series of steps or units is not limited to the listed steps or units, but optionally also includes steps or units that are not listed, or optionally also includes other steps or units inherent to these processes, methods, products or equipment.

[0088] In the present application, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may mean that the first feature is directly in contact with the second feature, or the first feature and the second feature are indirectly in contact through an intermediate medium. Moreover, a first feature being “above”, “above” or “above” a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being “below”, “below” or “below” a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0089] Unless otherwise defined, all technical and scientific terms used in the specification of this application have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in the specification of this application includes any and all combinations of one or more related listed items.

[0090] The technical features of the above embodiments can be combined without changing the basic principles of the present application. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0091] The above embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the scope of patent protection of the present application shall be subject to the attached claims.

Claims

1. An inverter circuit, characterized in that: The inverter circuit comprises: Processor, inverter input module, transformer module; and inverter output module; The inverter input module includes a DC power supply, a first MOS tube, a second MOS tube, a third MOS tube and a fourth MOS tube, one end of the DC power supply is connected to the first end of the first MOS tube, and the other end of the DC power supply is connected to the second end of the second MOS tube, the second end of the first MOS tube is connected to the first end of the second MOS tube, the first end of the third MOS tube is connected to the first end of the first MOS tube, the second end of the fourth MOS tube is connected to the second end of the second MOS tube, and the second end of the third MOS tube is connected to the first end of the fourth MOS tube; The inverter output module includes a first capacitor, a second capacitor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor, wherein the fifth MOS transistor, the sixth MOS transistor, the seventh MOS transistor and the eighth MOS transistor are connected in sequence, the second end of the first capacitor is connected to the first end of the second capacitor, and the first end of the first capacitor is connected to the first end of the fifth MOS transistor, and the second end of the second capacitor is connected to the second end of the eighth MOS transistor; The voltage transformation module includes a transformer and a first inductor, one end of the first inductor is connected to the output positive terminal of the transformer, the input positive terminal of the transformer is connected to the second end of the first MOS transistor, the input negative terminal of the transformer is connected to the second end of the third MOS transistor, the output negative terminal of the transformer is connected to the second end of the first capacitor, and the other end of the first inductor is connected to the second end of the sixth MOS transistor; The processor is connected to the third end of the first MOS tube, the third end of the second MOS tube, the third end of the third MOS tube, and the third end of the fourth MOS tube, and the processor is connected to the third end of the fifth MOS tube, the third end of the sixth MOS tube, the third end of the seventh MOS tube, and the third end of the eighth MOS tube, and is used to control the conduction state of each MOS tube so that the change of the working state of each MOS tube of the inverter circuit occurs at the moment when the AC voltage is zero.

2. The inverter circuit according to claim 1, characterized in that: The inverter circuit also includes a sampling module, a first input end of the sampling module is connected to the two ends of the DC power supply, and a second input end of the sampling module is connected to the two ends of the first inductor, an output end of the sampling module is connected to the processor, and the sampling module is used to sample the DC voltage Upv output by the DC power supply and the inductor voltage Uac between the two ends of the first inductor.

3. The inverter circuit according to claim 1, characterized in that: The capacitance values ​​of the first capacitor and the second capacitor are equal.

4. An inverter control method for controlling the inverter circuit according to any one of claims 1 to 3, characterized in that: The inverter control method comprises the following steps: S1, sampling to obtain a DC voltage Upv output by the DC power supply and an inductor voltage Uac between two ends of the first inductor, and obtaining a first voltage Uab and a second voltage Ucd according to the DC voltage Upv and the inductor voltage Uac; S2, determining a current voltage angle θ according to the first voltage Uab, and determining a voltage ratio k according to the first voltage Uab and the second voltage Ucd, where k=the first voltage Uab / the second voltage Ucd; S3, calculating the target power instantaneous value Pnow according to the preset target power Pall and the current voltage angle θ; S4, calculating a first maximum power Pmax1 according to a preset cut-off frequency fs; S5. Compare the target power transient value Pnow with the first maximum power Pmax1. If the target power transient value Pnow is greater than the first maximum power Pmax1, determine the target frequency fs1 according to the target power transient value Pnow. If the target power transient value Pnow is less than or equal to the first maximum power Pmax1, the value of the target frequency fs1 is equal to the cutoff frequency fs. S6, obtaining a second maximum power Pmax2 according to the target frequency fs1, and determining a per-unit power value P according to the target power instantaneous value Pnow and the second maximum power Pmax2, wherein the per-unit power value P=target power instantaneous value Pnow / second maximum power Pmax2; S7, determining a first lag time and a second lag time according to the power per unit value P, the voltage ratio k and the target frequency fs1; S8. Control the conduction state of each MOS tube in the inverter circuit according to the first lag time and the second lag time, so that the change of the working state of each MOS tube in the inverter circuit occurs at the moment when the AC voltage is zero.

5. The inverter control method according to claim 4, characterized in that: The calculation process of S3 is specifically as follows: target power instantaneous value Pnow=target power Pall×sinθ×sinθ.

6. The inverter control method according to claim 4, characterized in that: The calculation process of S4 is specifically as follows: first maximum power Pmax1 = first voltage Uab×second voltage Ucd / (8×cut-off frequency fs×Lr), where Lr is the inductance value of the first inductor in the inverter circuit.

7. The inverter control method according to claim 4, characterized in that: The first lag time in S7 is the time that the fourth MOS transistor in the inverter circuit lags behind the first MOS transistor in the inverter circuit.

8. The inverter control method according to claim 4, characterized in that: When the first voltage Uab is positive, the second lag time in S7 is the time that the fifth MOS tube in the inverter circuit lags behind the first MOS tube in the inverter circuit; when the first voltage Uab is negative, the second lag time in S7 is the time that the eighth MOS tube in the inverter circuit lags behind the first MOS tube in the inverter circuit.

9. The inverter control method according to claim 4, characterized in that: The S7 is specifically: A first phase difference D1 and a second phase difference D2 are calculated according to a ratio k of the power per unit value P and the voltage; A first lag time and a second lag time are calculated according to the first phase difference D1, the second phase difference D2 and the target frequency fs1.

10. A storage medium, characterized in that: The storage medium includes a stored program, wherein when the program is executed, the device where the storage medium is located is controlled to execute the inverter control method according to any one of claims 4 to 9.

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