A bistable weak PUF circuit capable of autonomously screening stable bits

Abstract

The present invention discloses a bistable weak PUF circuit capable of autonomously screening stable bits. The circuit comprises a decoder, a timing circuit, and a PUF core circuit. The PUF core circuit implements stable bit screening by accessing two screening levels. When the two screening levels accessed by the PUF core circuit are equal, the PUF core circuit generates a W-bit original PUF response within one clock cycle under the control of an m-bit wordline level signal outputted thereto by the decoder. The m-bit wordline level signal accessed by the PUF core circuit is kept unchanged, so that one of the two screening levels accessed by the PUF core circuit remains unchanged at the original value, while the other is reduced by a certain amplitude. After exchanging the screening levels, two W-bit screened PUF responses are obtained. After performing an XOR operation on the two levels, if the i-th bit is 1, it is considered that the response value of the bit in the original PUF response under the excitation signal is an unstable response. The circuit has the advantages of high stability, low hardware overhead, and low detection cost.

Description

Technical Field

[0001] The present invention relates to a weak PUF circuit, and in particular to a bistable weak PUF circuit capable of autonomously screening stable bits. Background Art

[0002] Physically Unclonable Functions (PUFs) provide a novel method for generating chip fingerprints, enabling the generation of random, unique, and tamper-resistant signature keys. They are ideally suited for the Internet of Things (IoT) industry. PUFs capture random process variations during chip manufacturing, converting them into physical variations such as voltage, current, and delay. An arbiter compares these variations and generates an output response. PUFs can be broadly categorized into weak and strong PUF circuits based on their ability to generate stimulus-response pairs. In weak PUF circuits, each PUF unit in the PUF array typically generates only one bit of PUF response. Because the hardware entropy source is not reused, all generated PUF responses are independent. In strong PUF circuits, the PUF units in the array are interconnected, allowing a single PUF unit to generate multiple bits of PUF responses. Because the hardware entropy source is reused, correlations are unavoidable between the generated PUF responses. Therefore, compared to strong PUF circuits, weak PUF circuits offer improved resistance to model-based attacks and machine learning attacks, and are primarily used for key generation in information systems. However, since a PUF unit in a weak PUF circuit has only one corresponding PUF response, and the PUF response is easily affected by changes in environmental conditions such as temperature, power supply voltage and noise, it may flip and become unstable, resulting in poor stability of the weak PUF circuit.

[0003] To address the stability issues of weak PUF circuits, some researchers have proposed some detection methods to detect unstable bits of the PUF response, thereby improving the stability of weak PUF circuits. For example, the paper "An SRAM-Based PUF With a Capacitive Digital Preselection for a 1E-9Key Error Probability[J], IEEE Transactions on Circuits and Systems I: Regular Papers, 2020, vol. 67, no. 12, pp. 4855-4868" proposes a capacitance tilt stabilization technique for detecting the stability of the PUF response based on metastable weak PUF circuits. This capacitance tilt stabilization technique avoids the flipping of the PUF response by adding a capacitor with adjustable capacitance value to the cross-coupled inverter of the PUF unit in the weak PUF circuit, thereby improving the stability of the PUF response. However, the capacitor area added by this capacitor tilt stabilization technology in the weak PUF circuit is much larger than the original weak PUF circuit area, and an additional switch must be set up for each capacitor to control whether the capacitor is connected to the weak PUF circuit. This significantly increases the hardware overhead of the weak PUF circuit and makes the detection cost very high.

[0004] The paper "High-Density and Low-Power PUF Designs in 5nm Achieving 23× and 39× BER Reduction After Unstable Bit Detection and Masking [C]," 2024 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2024, pp. 302-304, proposes a technique for detecting potentially unstable bits (i.e., unstable PUF responses) in weak PUF circuits using a high-resolution digital-to-analog converter (DAC) injected with current offset, thereby filtering out unstable PUF responses. However, this technique requires the addition of an additional high-resolution digital-to-analog converter to the weak PUF circuit, which consumes a large area, resulting in a feature size of up to 3920F in the weak PUF circuit. 2 , the hardware overhead is large and the detection cost is high.

[0005] The paper "A6T-SRAM-Based Physically-Unclonable-Function With Low BER Through Automated Maximum Mismatch Detection[J], IEEE Transactions on Circuits and Systems II: Express Briefs, 2024, vol. 71, no. 7, pp. 3493-3497." proposes a 6T-SRAM PUF. This PUF uses maximum mismatch detection technology to detect unstable responses by identifying and selecting the configuration with the highest mismatch between adjacent PUF cells under four different configurations. However, additional storage space is required to store the different configuration information corresponding to each PUF cell, which also increases hardware resource overhead and detection costs. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a bistable weak PUF circuit that can autonomously screen stable bits while having high stability, low hardware overhead, and low detection cost.

[0007] The technical solution adopted by the present invention to solve the above technical problems is: a bistable weak PUF circuit that can autonomously screen stable bits, including a decoder, a timing circuit and a PUF core circuit; the decoder is used to access the n-bit excitation signal C1-C n , and the n-bit excitation signal C1-C n Perform decoding operation to obtain the m-bit word line level signal WL1-WL m Output to the PUF core circuit, n is an integer greater than or equal to 1, m = 2 n; The timing circuit is used to access the clock signal CLK and the enable signal CEN, perform an AND operation on the clock signal CLK and the enable signal CEN to obtain a clock signal AEN for controlling the working timing of the decoder and output it to the decoder, and delay the clock signal AEN and invert it and perform an NAND operation on the clock signal AEN to obtain a clock signal PRE for controlling the working timing of the PUF core circuit and output it to the PUF core circuit; the PUF core circuit is used to generate a W-bit PUF response in each clock cycle of the clock signal PRE under the control of the m-bit word line level signal outputted thereto by the decoder, where W is an integer greater than or equal to 1; the PUF core circuit has an autonomous stable bit screening function, and the PUF core circuit realizes stable bit screening by accessing two screening levels. When the two screening levels accessed by the PUF core circuit are equal, the PUF core circuit outputs a W-bit PUF response to the decoder. Under the control of the m-bit wordline level signal, a W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the original PUF response for the clock cycle. Then, the m-bit wordline level signal connected to the PUF core circuit is kept unchanged. First, one of the two screening levels connected to the PUF core circuit is kept unchanged, while the other is reduced by a certain amplitude. The W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the first screening PUF response. Then, the two screening levels are swapped, and the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the second screening PUF response. An exclusive OR operation is performed on the first and second screening PUF responses to obtain a W-bit stability flag value. If the value of a bit in the W-bit stability flag value is 1, it is considered that the response value of that bit in the original PUF response under the current stimulus signal is an unstable response.

[0008] Compared with the prior art, the advantage of the present invention is that it performs unstable response detection by connecting two screening levels to the PUF core circuit. When the PUF core circuit generates a W-bit PUF response of a certain clock cycle, the m-bit word line level signal connected to it is kept unchanged. First, two equal screening levels are connected to generate the original PUF response, and then two unequal screening levels are connected to generate two screened PUF responses. Since the unstable response value in the original PUF response will be flipped when the two screening levels are unequal, if there is an unstable response in the original PUF response, the unstable response will be flipped, so that the two screened PUF responses will be The corresponding bit in the W-bit stability flag value obtained after the XOR operation will be 1. At this time, if the value of a bit in the W-bit stability flag value is 1, it is considered that the response value of that bit in the original PUF response under the current excitation signal is an unstable response. If there is no unstable response in the original PUF response, no flip will occur at this time, and all bits of the W-bit stability flag value will be completely 0. Therefore, the present invention can filter out unstable responses and has high stability. In addition, by simply connecting two screening levels and making the two screening levels equal or unequal, unstable screening can be achieved. No additional devices are required, hardware overhead is small, and detection cost is low.

[0009] Furthermore, the decoder has n excitation signal input terminals, 1 clock signal input terminal and m output terminals; the timing circuit has 2 input terminals and 2 output terminals, the 2 input terminals are respectively referred to as the first input terminal and the second input terminal, and the 2 output terminals are respectively referred to as the first output terminal and the second output terminal. The PUF core circuit has a power supply terminal, a ground terminal, m word line level signal input terminals, 1 clock signal input terminal, 2 screening level input terminals and W output terminals. The n excitation signal input terminals of the decoder are used to access the n-bit excitation signals C1-C n The m output terminals of the decoder are used to output m-bit word line level signals. The m output terminals of the decoder are connected one-to-one with the m word line level signal input terminals of the PUF core circuit. The first input terminal of the timing circuit is connected to the enable signal CEN, and the second input terminal is connected to the clock signal CLK. The first output terminal of the timing circuit is connected to the clock signal input terminal of the decoder. The first output terminal of the timing circuit outputs the clock signal AEN. The second output terminal of the timing circuit is connected to the clock signal input terminal of the PUF core circuit. The second output terminal of the timing circuit outputs the clock signal PRE. The power supply terminal of the PUF core circuit is used to connect to the working power supply VDD. The ground terminal of the PUF core circuit is used to connect to the ground voltage VSS. The W output terminals of the PUF core circuit are used to output the W-bit PUF response Z1-Z WThe two screening level input terminals of the PUF core circuit are respectively connected to the screening level V L and V R .

[0010] Furthermore, the timing circuit includes a D flip-flop, 21 inverters, a two-input AND gate and a first two-input NAND gate, the D flip-flop having an input terminal, a clock terminal and an output terminal, the two-input AND gate having a first input terminal, a second input terminal and an output terminal, the first two-input NAND gate having a first input terminal, a second input terminal and an output terminal, the input terminal of the D flip-flop is connected to the first input terminal of the timing circuit, the clock terminal of the D flip-flop and the second input terminal of the two-input AND gate, and its connection terminal is the second input terminal of the timing circuit The output end of the D flip-flop is connected to the first input end of the two-input AND gate, the output end of the two-input AND gate, the input end of the first inverter and the second input end of the first two-input NAND gate are connected, and the connection end is the first output end of the timing circuit, the output end of the kth inverter is connected to the input end of the k+1th inverter, k=1, 2,…, 20, the output end of the 21st inverter is connected to the first input end of the first two-input NAND gate, and the output end of the first two-input NAND gate is the second output end of the timing circuit.

[0011] Furthermore, the PUF core circuit includes W PUF unit arrays and W latches, each PUF unit array has a power supply terminal, a ground terminal, a clock signal input terminal, m word line level signal input terminals, two screening level input terminals and two output terminals, the two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, each latch has two input terminals and one output terminal, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the power supply terminals of the W PUF unit arrays are connected, and their connection terminals are the power supply terminals of the PUF core circuit, the ground terminals of the W PUF unit arrays are connected, and their connection terminals are the ground terminals of the PUF core circuit, the first screening level input terminals of the W PUF unit arrays are connected, And its connection end is the first screening level input end of the PUF core circuit, the second screening level input end of the W PUF unit arrays is connected, and its connection end is the second screening level input end of the PUF core circuit, the clock signal input end of the W PUF unit arrays is connected, and its connection end is the clock signal input end of the PUF core circuit, the i-th word line level signal input end of the W PUF unit arrays is connected, and its connection end is the i-th word line level signal input end of the PUF core circuit, i=1, 2, ..., m, the first output end of the b-th PUF unit array is connected to the first input end of the b-th latch, the second output end of the b-th PUF unit array is connected to the second input end of the b-th latch, b=1, 2, ..., W, and the output ends of the W latches are the W output ends of the PUF core circuit;Each of the PUF unit arrays includes a decision unit and m PUF units, each PUF unit has a word line level signal input terminal, two screening level input terminals and four output terminals, the four output terminals are respectively referred to as the first output terminal, the second output terminal, the third output terminal and the fourth output terminal, the two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the decision unit has a power supply terminal, a ground terminal, a clock signal input terminal, two input terminals and two output terminals, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, the word line level signal input terminals of the m PUF units are the m word line level signal input terminals of the PUF unit array, the first screening level input terminals of the m PUF units are connected, and their connection terminals are the first screening level input terminals of the PUF unit array. The first input terminal of the decision unit is connected to the third output terminals of the m PUF units, the second input terminal of the decision unit is connected to the fourth output terminals of the m PUF units, the first output terminal of the decision unit is connected to the first output terminals of the m PUF units, and the second output terminal of the decision unit is connected to the second output terminal of the PUF unit array.

[0012] Furthermore, the judgment unit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube, and a sixth MOS tube. The first MOS tube, the second MOS tube, the third MOS tube, and the fourth MOS tube are all PMOS tubes, the fifth MOS tube and the sixth MOS tube are both NMOS tubes, the source of the first MOS tube, the source of the second MOS tube, the source of the third MOS tube, and the source of the fourth MOS tube are connected, and the connection end thereof is the power supply end of the judgment unit, the source of the fifth MOS tube is connected to the source of the sixth MOS tube, and the connection end thereof is the ground end of the judgment unit, and the The gate of the third MOS transistor is connected to the gate of the fourth MOS transistor, and the connection end thereof is the clock signal input end of the judgment unit; the drain of the first MOS transistor, the drain of the third MOS transistor, the gate of the second MOS transistor, and the gate of the sixth MOS transistor are connected, and the connection end thereof is the first output end of the judgment unit; the drain of the second MOS transistor, the drain of the fourth MOS transistor, the gate of the first MOS transistor, and the gate of the fifth MOS transistor are connected, and the connection end thereof is the second output end of the judgment unit; the drain of the fifth MOS transistor is the first input end of the judgment unit, and the drain of the sixth MOS transistor is the second input end of the judgment unit.

[0013] Furthermore, each PUF unit includes a seventh MOS transistor, an eighth NMOS transistor, a ninth MOS transistor, and a tenth MOS transistor. The seventh MOS transistor, the eighth NMOS transistor, the ninth MOS transistor, and the tenth MOS transistor are all NMOS transistors. The drain of the seventh MOS transistor is the first output end of the PUF unit, the drain of the eighth MOS transistor is the second output end of the PUF unit, the drain of the ninth MOS transistor is the third output end of the PUF unit, and the drain of the tenth MOS transistor is the fourth output end of the PUF unit. The source of the seventh MOS transistor is connected to the source of the ninth MOS transistor, the source of the eighth MOS transistor is connected to the source of the tenth MOS transistor, and the gate of the seventh MOS transistor is connected to the gate of the eighth MOS transistor, and the connection end thereof is the word line level signal input end of the PUF unit. The gate of the ninth MOS transistor is the first screening level input end of the PUF unit, and the gate of the tenth MOS transistor is the second screening level input end of the PUF unit.

[0014] Furthermore, each of the latches includes two NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two NAND gates are respectively referred to as a first NAND gate and a second NAND gate. The first input terminal of the first NAND gate is the first input terminal of the latch, the first input terminal of the second NAND gate is the second input terminal of the latch, the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and their connection terminals are the output terminals of the latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is the overall structure diagram of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention;

[0016] Figure 2 A circuit diagram of a sequential circuit of a bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0017] Figure 3 A circuit diagram of a PUF core circuit of a bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0018] Figure 4 A circuit diagram of a PUF unit array of a bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0019] Figure 5 This is a circuit diagram of a decision unit of a bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0020] Figure 6 A circuit diagram of a PUF unit of a bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0021] Figure 7 A circuit diagram of a latch of a bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0022] Figure 8 The layout of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention;

[0023] Figure 9 A grayscale image of the PUF response of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0024] Figure 10 This is an average grayscale image of the PUF response of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0025] Figure 11The figure is a simulation diagram of the normalized inter-chip Hamming distance and intra-chip Hamming distance of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention;

[0026] Figure 12 A diagram showing the ratio of unstable bits in the PUF response of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0027] Figure 13 This is a diagram showing the ratio of unstable bits in the PUF response after 5mV composite screening of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0028] Figure 14 This is a diagram showing the ratio of unstable bits in the PUF response after 10mV composite screening of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0029] Figure 15 This is a graph showing the ratio of unstable bits in the PUF response after 15mV composite screening of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0030] Figure 16 This is a diagram showing the ratio of unstable bits in the PUF response after 20mV composite screening of the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention;

[0031] Figure 17 This is a diagram showing the ratio of unstable bits in the PUF response after composite screening at different screening levels is performed on the bistable weak PUF circuit capable of autonomously screening stable bits according to the present invention. DETAILED DESCRIPTION

[0032] The present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0033] Example 1: Figure 1 As shown, a bistable weak PUF circuit that can autonomously screen stable bits includes a decoder, a timing circuit, and a PUF core circuit; the decoder is used to access the n-bit excitation signal C1-C n , and the n-bit excitation signal C1-C n Perform decoding operation to obtain the m-bit word line level signal WL1-WL m Output to the PUF core circuit, n is an integer greater than or equal to 1, m = 2 n; The timing circuit is used to access the clock signal CLK and the enable signal CEN, perform AND operation on the clock signal CLK and the enable signal CEN, obtain a clock signal AEN for controlling the working timing of the decoder and output it to the decoder, and delay and invert the clock signal AEN and perform NAND operation on the clock signal AEN to obtain a clock signal PRE for controlling the working timing of the PUF core circuit and output it to the PUF core circuit; the PUF core circuit is used to generate a W-bit PUF response in each clock cycle of the clock signal PRE under the control of the m-bit word line level signal output by the decoder, where W is an integer greater than or equal to 1; the PUF core circuit has an autonomous stable bit screening function, and the PUF core circuit realizes stable bit screening by accessing two screening levels. When the two screening levels accessed by the PUF core circuit are equal, the PUF core circuit is controlled by the m-bit word line level signal output by the decoder, in the clock A W-bit PUF response generated within one clock cycle of the signal PRE is used as the original PUF response for that clock cycle. The m-bit wordline level signal connected to the PUF core circuit is maintained unchanged. One of the two screening levels connected to the PUF core circuit is maintained unchanged, while the other is reduced by a certain amplitude. The W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the first screened PUF response. The two screening levels are then swapped, and the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the second screened PUF response. An exclusive-OR operation is performed on the first and second screened PUF responses to obtain a W-bit stability flag value. If the value of a bit in the W-bit stability flag value is 1, the response value of that bit in the original PUF response under the current stimulus signal is considered to be an unstable response. In this embodiment, the decoder has n excitation signal input terminals, 1 clock signal input terminal and m output terminals; the timing circuit has 2 input terminals and 2 output terminals, its 2 input terminals are respectively referred to as its first input terminal and second input terminal, and its 2 output terminals are respectively referred to as its first output terminal and second output terminal. The PUF core circuit has a power supply terminal, a ground terminal, m word line level signal input terminals, 1 clock signal input terminal, 2 screening level input terminals and W output terminals. The n excitation signal input terminals of the decoder are used to access the n-bit excitation signals C1-C nThe m output terminals of the decoder are used to output m-bit word line level signals. The m output terminals of the decoder are connected one-to-one with the m word line level signal input terminals of the PUF core circuit. The first input terminal of the timing circuit is connected to the enable signal CEN, and the second input terminal is connected to the clock signal CLK. The first output terminal of the timing circuit is connected to the clock signal input terminal of the decoder. The first output terminal of the timing circuit outputs the clock signal AEN. The second output terminal of the timing circuit is connected to the clock signal input terminal of the PUF core circuit. The second output terminal of the timing circuit outputs the clock signal PRE. The power supply terminal of the PUF core circuit is used to connect to the working power supply VDD. The ground terminal of the PUF core circuit is used to connect to the ground voltage VSS. The W output terminals of the PUF core circuit are used to output the W-bit PUF response Z1-Z W , the two screening level input terminals of the PUF core circuit are connected to the screening level V L and V R .

[0034] In this embodiment, unstable response detection is performed by connecting two screening levels to the PUF core circuit. When the PUF core circuit generates a W-bit PUF response in a certain clock cycle, the m-bit word line level signal connected to it remains unchanged. First, two equal screening levels are connected to generate the original PUF response, and then two unequal screening levels are connected to generate two screened PUF responses. Since the unstable response value in the original PUF response will flip when the two screening levels are unequal, if there is an unstable response in the original PUF response, the unstable response will flip, so that the two screened PUF responses are XORed. The corresponding bit value in the W-bit stability mark value obtained after the operation will be 1. At this time, if the value of a certain bit in the W-bit stability mark value is 1, it is considered that the response value of this bit in the original PUF response under the current excitation signal is an unstable response. If there is no unstable response in the original PUF response, no flip will occur at this time, and all bits of the W-bit stability mark value will be completely 0. Thus, the unstable response can be screened out, with high stability, and unstable screening can be achieved by only connecting two screening levels and making the two screening levels equal or unequal. No additional devices are required, the hardware overhead is small, and the detection cost is low. Example 2: This embodiment is basically the same as Example 1, except that: in this embodiment, if Figure 2As shown, the sequential circuit includes a D flip-flop LA1, 21 inverters INV1-INV21, a two-input AND gate AND1, and a first two-input NAND gate NAND1. The D flip-flop LA1 has an input terminal, a clock terminal, and an output terminal. The two-input AND gate AND1 has a first input terminal, a second input terminal, and an output terminal. The first two-input NAND gate NAND1 has a first input terminal, a second input terminal, and an output terminal. The input terminal of the D flip-flop LA1 is connected to the first input terminal of the sequential circuit, the clock terminal of the D flip-flop LA1 is connected to the second input terminal of the two-input AND gate AND1, and its connection terminal is the second input terminal of the sequential circuit. The output end of the D flip-flop LA1 is connected to the first input end of the two-input AND gate AND1, the output end of the two-input AND gate AND1, the input end of the first inverter and the second input end of the first two-input NAND gate NAND1 are connected, and the connection end thereof is the first output end of the sequential circuit, the output end of the kth inverter is connected to the input end of the k+1th inverter, k=1, 2, ..., 20, the output end of the 21st inverter INV1-INV21 is connected to the first input end of the first two-input NAND gate NAND1, and the output end of the first two-input NAND gate NAND1 is the second output end of the sequential circuit.

[0035] In this embodiment, when the sequential circuit is operating, the enable signal CEN is input to the D flip-flop LA1. Under the control of the clock signal CLK, the D flip-flop LA1 outputs the enable signal CEN through its output terminal during each cycle of the clock signal CLK. At this time, the enable signal CEN and the clock signal CLK are ANDed together through the first and second input AND gates AND1 to obtain the clock signal AEN. At the same time, the clock signal AEN and the signal obtained by inverting it through 21 inverters INV1-INV21 are NANDed together through the first and second input NAND gates NAND1 to obtain the clock signal PRE. This implements the overall sequential control of the bistable weak PUF circuit that can autonomously screen stable bits.

[0036] Example 3: This example is basically the same as Example 1, except that: in this example, Figure 3 and Figure 4As shown, the PUF core circuit includes W PUF unit arrays and W latches, each PUF unit array has a power supply terminal, a ground terminal, a clock signal input terminal, m word line level signal input terminals, two screening level input terminals and two output terminals, the two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, each latch has two input terminals and one output terminal, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the power supply terminals of the W PUF unit arrays are connected, and the connection terminal is the power supply terminal of the PUF core circuit, the ground terminals of the W PUF unit arrays are connected, and the connection terminal is the ground terminal of the PUF core circuit, the first screening level input terminals of the W PUF unit arrays are connected The first output terminal of the bth PUF cell array is connected to the first input terminal of the bth latch, the second output terminal of the bth PUF cell array is connected to the second input terminal of the bth latch, b=1, 2, ..., W, and the output terminals of the W latches are the W output terminals of the PUF core circuit;Each PUF unit array includes a decision unit and m PUF units, each PUF unit has a word line level signal input terminal, two screening level input terminals and four output terminals, the four output terminals are respectively referred to as the first output terminal, the second output terminal, the third output terminal and the fourth output terminal, the two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the decision unit has a power supply terminal, a ground terminal, a clock signal input terminal, two input terminals and two output terminals, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, the word line level signal input terminals of the m PUF units are the m word line level signal input terminals of the PUF unit array, the first screening level input terminals of the m PUF units are connected, and their connection The first terminal of the decision unit is connected to the first screening level input terminal of the PUF unit array, the second screening level input terminals of the m PUF units are connected, and the connection terminal thereof is the second screening level input terminal of the PUF unit array, the power supply terminal of the decision unit is the power supply terminal of the PUF unit array, the ground terminal of the decision unit is the ground terminal of the PUF unit array, the clock signal input terminal of the decision unit is the clock signal input terminal of the PUF unit array, the first input terminal of the decision unit is connected to the third output terminals of the m PUF units, the second input terminal of the decision unit is connected to the fourth output terminals of the m PUF units, the first output terminal of the decision unit is connected to the first output terminals of the m PUF units, and the connection terminal thereof is the first output terminal of the PUF unit array, and the second output terminal of the decision unit is connected to the second output terminals of the m PUF units, and the connection terminal thereof is the second output terminal of the PUF unit array.

[0037] In this embodiment, when the PUF core circuit is in operation, the decoder outputs the m-bit word line level signals WL1-WL m Only one of them is high level, and the remaining m-1 bits are all low level. In each clock cycle of the clock signal PRE, only the m-bit word line level signals WL1-WL1 are connected in each PUF unit array. mA PUF unit with a high level in the PUF array is selected and is in working state, while other PUF units are not selected and are in standby state and do not participate in work. When a PUF unit in the PUF unit array is selected, the clock signal PRE is at a low level, and the decision unit in the PUF unit array enters the charging stage. The decision unit in the PUF unit array charges the selected PUF unit, so that the first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the PUF unit are all pre-charged to equal to the high level VDD. Then PRE becomes a high level, and the decision unit in the PUF unit array enters the judgment stage. During the decision evaluation phase, due to inevitable random process variations, the PUF unit has a difference in discharge rate between its first and second output terminals. This also causes a difference in discharge rate between the first and second output terminals of the decision unit. The decision unit further pulls down the signal of the output with the faster discharge rate to VSS, while raising the signal of the output with the slower discharge rate to near VDD. A latch connected to the PUF unit judges the signals output by the first and second output terminals of the PUF unit to obtain a corresponding PUF response.

[0038] Example 4: This example is basically the same as Example 1, except that: in this example, Figure 5 As shown, the judgment unit includes a first MOS tube M1, a second MOS tube M2, a third MOS tube M3, a fourth MOS tube M4, a fifth MOS tube M5 and a sixth MOS tube M6. The first MOS tube M1, the second MOS tube M2, the third MOS tube M3 and the fourth MOS tube M4 are all PMOS tubes, the fifth MOS tube M5 and the sixth MOS tube M6 are all NMOS tubes, the source of the first MOS tube M1, the source of the second MOS tube M2, the source of the third MOS tube M3 and the source of the fourth MOS tube M4 are connected, and the connection end thereof is the power supply end of the judgment unit, the source of the fifth MOS tube M5 and the source of the sixth MOS tube M6 are connected, and the connection end thereof is the power supply end of the judgment unit. The ground terminal of the element, the gate of the third MOS transistor M3 and the gate of the fourth MOS transistor M4 are connected, and the connection end thereof is the clock signal input terminal of the judgment unit, the drain of the first MOS transistor M1, the drain of the third MOS transistor M3, the gate of the second MOS transistor M2 and the gate of the sixth MOS transistor M6 are connected, and the connection end thereof is the first output terminal of the judgment unit, the drain of the second MOS transistor M2, the drain of the fourth MOS transistor M4, the gate of the first MOS transistor M1 and the gate of the fifth MOS transistor M5 are connected, and the connection end thereof is the second output terminal of the judgment unit, the drain of the fifth MOS transistor M5 is the first input terminal of the judgment unit, and the drain of the sixth MOS transistor M6 is the second input terminal of the judgment unit.

[0039] In this embodiment, when the decision unit is working, when the clock signal PRE is at a low level, the third MOS transistor M3 and the fourth MOS transistor M4 of the decision unit are both turned on, and the decision unit enters a pre-charging stage. The voltage values ​​of the first output terminal and the second output terminal gradually increase to VDD, so that the first MOS transistor M1 and the second MOS transistor M2 are both turned off, and the fifth MOS transistor M5 and the sixth MOS transistor M6 are both turned on. When the clock signal PRE is at a high level, the third MOS transistor M3 and the fourth MOS transistor M4 of the decision unit are both turned off, and the decision unit enters a decision evaluation stage. Due to inevitable random process deviations, the discharge rates of the first output terminal and the second output terminal of the PUF unit differ. At this time, the discharge rates of the first output terminal and the second output terminal of the decision unit also differ. The one with a faster discharge rate of the first output terminal and the second output terminal of the decision unit will be pulled down to VSS, and the one with a slower discharge rate will be pulled up to close to VD D. Specifically, there are the following two situations: if the first output terminal of the decision unit discharges faster, the second MOS transistor M2 will be the first to show a turning-on trend, and the sixth MOS transistor M6 will be the first to show a turning-off trend, thereby charging the second output terminal of the decision unit. The voltage value of the second output terminal of the decision unit will stop decreasing and gradually increase to approach VDD, thereby further turning off the first MOS transistor M1 and turning on the fifth MOS transistor M5, so that the voltage value of the first output terminal of the decision unit is further reduced to VSS; if the second output terminal of the decision unit discharges faster, the first MOS transistor M1 will be the first to show a turning-on trend, and the fifth MOS transistor M5 will be the first to show a turning-off trend, thereby charging the first output terminal of the decision unit. The voltage value of the first output terminal of the decision unit will stop decreasing and gradually increase to approach VDD, thereby further turning off the second MOS transistor M2 and turning on the sixth MOS transistor M6, so that the voltage value of the second output terminal of the decision unit is further reduced to VSS.

[0040] Example 5: This example is basically the same as Example 1, except that: in this example, Figure 6As shown, each PUF unit includes a seventh MOS transistor M7, an eighth NMOS transistor, a ninth MOS transistor M9, and a tenth MOS transistor M10. The seventh MOS transistor M7, the eighth NMOS transistor, the ninth MOS transistor M9, and the tenth MOS transistor M10 are all NMOS transistors. The drain of the seventh MOS transistor M7 is the first output end of the PUF unit, the drain of the eighth MOS transistor M8 is the second output end of the PUF unit, the drain of the ninth MOS transistor M9 is the third output end of the PUF unit, and the drain of the tenth MOS transistor M10 is the fourth output end of the PUF unit. The source of the seventh MOS transistor M7 is connected to the source of the ninth MOS transistor M9, the source of the eighth MOS transistor M8 is connected to the source of the tenth MOS transistor M10, and the gate of the seventh MOS transistor M7 is connected to the gate of the eighth MOS transistor M8, and the connection end thereof is the word line level signal input end of the PUF unit. The gate of the ninth MOS transistor M9 is the first screening level input end of the PUF unit, and the gate of the tenth MOS transistor M10 is the second screening level input end of the PUF unit.

[0041] In this embodiment, the PUF unit adopts a twin structure, consisting of only four minimum-sized NMOS transistors. By comparing the subthreshold leakage currents of a group of symmetrical MOS transistors of the same size, the final output response is obtained through quantization, further reducing the hardware overhead of the PUF unit.

[0042] In this embodiment, the PUF unit determines whether it is selected based on the word line level signal connected to its word line level signal input terminal. When the word line level signal connected to its word line level signal input terminal is at a low level, the PUF unit is not selected and does not participate in the operation. When the word line level signal connected to its word line level signal input terminal is at a high level, the PUF unit is selected to participate in the operation. When the PUF unit is selected, the PUF unit first enters the charging stage, the seventh MOS tube M7 and the eighth NMOS tube are both turned on, the first output terminal, the second output terminal, the third output terminal and the fourth output terminal of the PUF unit are first precharged to the high level VDD, and then the PUF unit enters the evaluation stage, the seventh MOS tube M7 and the eighth NMOS tube are both turned on, and generally the screening level V L Equal to the V connected to its second screening level input R , are equal to 325mV, the first output end of the PUF unit is discharged through the seventh MOS tube M7 and the ninth NMOS tube M9, and the second output end of the PUF unit is discharged through the eighth MOS tube M8 and the tenth NMOS tube M10. If screening is required, maintain the screening level V L and V R Keep one of them unchanged and change the other one so that the screening level V L Not equal to V RAt this time, the gate voltages of the ninth NMOS transistor M9 and the tenth NMOS transistor M10 are different, resulting in different conduction levels of the ninth NMOS transistor M9 and the tenth NMOS transistor M10. As a result, the charge leakage rate of the first output terminal and the second output terminal of the decision unit connected to the PUF unit will be affected not only by the random process variation of the seventh MOS transistor M7 and the eighth MOS transistor M8, but also by the artificially added variation of the ninth NMOS transistor M9 and the tenth NMOS transistor M10. The original response (affected only by the random process variation of the seventh MOS transistor M7 and the eighth MOS transistor M8) is compared with the response now affected by the artificially added variation to screen out stable and unstable bits.

[0043] Example 6: This example is basically the same as Example 1, except that: in this example, Figure 7 As shown, each latch includes two NAND gates, each NAND gate has a first input terminal, a second input terminal and an output terminal, and the two NAND gates are respectively referred to as the first NAND gate U1 and the second NAND gate U2. The first input terminal of the first NAND gate U1 is the first input terminal of the latch, the first input terminal of the second NAND gate U2 is the second input terminal of the latch, the second input terminal of the first NAND gate U1 is connected to the output terminal of the second NAND gate U2, and the second input terminal of the second NAND gate U2 is connected to the output terminal of the first NAND gate U1, and the connection terminal thereof is the output terminal of the latch.

[0044] In this embodiment, when the first input terminal of the latch is connected to a high level and the second input terminal is connected to a low level, the output terminal of the first NAND gate U1 outputs a high level, and the output terminal of the second NAND gate U2 is a low level. At this time, the output terminal of the latch outputs a high level. When the second input terminal of the latch is connected to a high level and its first input terminal is connected to a low level, the output terminal of the first NAND gate U1 is reset to a low level, and the output terminal of the second NAND gate U2 outputs a high level. At this time, the output terminal of the latch outputs a low level.

[0045] X mV composite screening refers to placing the bistable weak PUF circuit that can independently screen the stable bit at the golden working point, that is, the working environment temperature is 27℃ and the working power supply voltage VDD is 1.2V; and four extreme working points, that is, the working environment temperature is -40℃ and the working power supply voltage VDD is 1.0V, the temperature is -40℃ and the working power supply voltage VDD is 1.4V, the temperature is 125℃ and the working power supply voltage VDD is 1.0V, and the temperature is 125℃ and the working power supply voltage VDD is 1.4V. The same screening operation is performed under the above five working points respectively, and X represents the screening level V L or V R The amplitude is reduced compared to 325mV. Under a certain excitation signal, the first screening level V LSet to 325mV, the second screening level V R Set to 325mV, and after obtaining the original PUF response, perform screening. The specific screening operation is as follows: Step 1: Set the first screening level V in all PUF units in the PUF core circuit of the bistable weak PUF circuit that can autonomously screen the stable bit L Set to 325-X mV, the second screening level V R Set to 325mV. At this time, according to the input excitation signal, the decoder outputs an m-bit word line level signal, and the PUF core circuit of the bistable weak PUF circuit that can autonomously screen the stable bit outputs the first W-bit PUF response value. Step 2: Set the first screening level V in the PUF unit in the PUF core circuit of the bistable weak PUF circuit that can autonomously screen the stable bit to L Set to 325mV, the second screening level V L Set to 325-X mV. At this point, the same excitation signal as in the first step is applied. The PUF core circuit of the bistable weak PUF circuit, which can autonomously screen for stable bits, outputs a second W-bit PUF response value. Step 3: XOR the first W-bit PUF response value with the second W-bit PUF response value to obtain a W-bit stability flag value. If a bit in the W-bit stability flag value is 0, that bit of the original PUF response under that excitation signal is determined to be a stable PUF response. If a bit in the W-bit stability flag value is 1, that bit of the original PUF response under that excitation signal is determined to be a PUF response prone to transitions.

[0046] The bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is implemented using TSMC 65nm technology. The chip layout is as follows: Figure 8 As shown. This layout includes four bistable weak PUF circuits capable of autonomously screening stable bits of the present invention and one BIST test circuit. The BIST test circuit is mainly used to perform serial-to-parallel and parallel-to-serial conversion on the input and output data of the four bistable weak PUF circuits capable of autonomously screening stable bits of the present invention (shared by the four bistable weak PUF circuits capable of autonomously screening stable bits of the present invention). The PUF unit area is only 1.728μm 2 The characteristic size of a single PUF unit is only 204.5F 2 .

[0047] Randomness is an important property of PUF. The output responses of different PUF units are arranged according to their spatial position to form a grayscale matrix to intuitively observe the distribution of 0 and 1 of the output responses. Figure 9 The grayscale image of the output response of a randomly selected individual bistable weak PUF circuit that can autonomously select stable bits is given, where white pixels and black pixels are used to mark responses 1 and 0, respectively. Figure 9It can be seen that the probabilities of "1" and "0" in the response are 50.03% and 49.97% respectively, which are close to the ideal value of 50%. The average grayscale of the response bit of the 10 bistable weak PUF circuits that can autonomously screen the stable bit of the present invention is shown as follows: Figure 10 Analysis Figure 10 It can be seen that the grayscale value is concentrated around 0.5, and no obvious spatial artifacts are observed. Therefore, it can be seen that the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention has good randomness.

[0048] Reliability is an extremely important performance indicator of PUF, and is usually measured by the intra-chip Hamming distance. The intra-chip Hamming distance is the statistical characteristic of the response changes of the same PUF circuit under the same excitation signal in different environments. The normalized inter-chip Hamming distance and intra-chip Hamming distance of the bistable weak PUF circuit with autonomous stable bit selection of the present invention are shown in the figure. Figure 11 Analysis Figure 11 It can be seen that the average intra-chip Hamming distance of the bistable weak PUF that can autonomously select stable bits is 0.00379, and the reliability is 99.6%. Figure 11 It can be seen that the HD of the bistable weak PUF of the present invention that can autonomously screen stable positions inter with HD intra The ratio of is greater than 130, indicating that the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention has good recognition

[0049] To characterize the stability of the output response of the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention, the circuit was repeatedly read 100 times at different temperatures and voltages to obtain statistical results of the bit error rate and unstable bit ratio of the output response at different temperatures and voltages. The original unstable bit ratio of the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention in the range of -40°C to 125°C and 1.0V to 1.4V is shown in the figure below. Figure 12 Analysis Figure 12 It can be seen that when the voltage changes within the range of 1.0V to 1.4V and the temperature changes within the range of -40°C to 125°C, the maximum bit error rate (unstable bit ratio) of the output response of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is 10.62% (12.17%) @1.0V / 125°C. This shows that the output response of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention has good robustness.

[0050] The bistable weak PUF circuit capable of autonomously screening stable bits of the present invention was subjected to four X mV ​​composite screenings. In the three X mV ​​composite screenings, X mV ​​was 5 mV, 10 mV, 15 mV, and 20 mV, respectively. The unstable bit ratio of the PUF response after the 5 mV composite screening of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is shown in FIG. Figure 13 As shown; the unstable bit ratio diagram of the PUF response after 10mV composite screening of the bistable weak PUF circuit of the present invention that can independently screen the stable bit is shown as follows Figure 14 As shown; the unstable bit ratio diagram of the PUF response after the screening level 15mV composite screening of the bistable weak PUF circuit of the present invention that can independently screen the stable bit is shown as follows Figure 15 As shown; the unstable bit ratio diagram of the PUF response after the screening level 20mV composite screening of the bistable weak PUF circuit of the present invention that can independently screen the stable bit is shown as follows Figure 16 shown.

[0051] analyze Figure 13 It can be seen that after the 5mV composite screening, the maximum unstable bit ratio of the PUF output response of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is reduced to 2.21%. Figure 14 It can be seen that after the 10mV composite screening, the maximum unstable bit ratio of the PUF output response of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is reduced to 0.22%. Figure 15 It can be seen that after the 15mV composite screening, the maximum unstable bit ratio of the PUF output response of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is reduced to 0.04%. Figure 16 It can be seen that after the 20mV composite screening, the maximum unstable bit ratio of the PUF output response of the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention is reduced to 0.01%. Therefore, it can be seen that the bistable weak PUF circuit capable of autonomously selecting stable bits of the present invention has high stability.

[0052] To evaluate the screening efficiency of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention, in addition to focusing on the proportion of unstable bits after screening, it is also necessary to pay attention to the proportion of originally stable bits mistakenly marked as unstable bits, that is, the false screening rate. The unstable bit ratio of the PUF response after composite screening at different screening levels of the bistable weak PUF circuit capable of autonomously screening stable bits of the present invention is shown in the figure below. Figure 17 As shown. Figure 17 As shown in the figure, the average false positive rate of the bistable weak PUF circuit capable of autonomously screening stable bits in the 20mV composite screening was 24.44%, and the maximum proportion of unstable bits was 0.01%. This shows that the screening efficiency of the bistable weak PUF circuit capable of autonomously screening stable bits is relatively high.

[0053] In summary, the bistable weak PUF circuit of the present invention, which can autonomously screen stable bits, can achieve unstable screening by simply connecting two screening levels and making the two screening levels equal or unequal. It does not require additional devices, has low hardware overhead, and has low detection costs. The MPW tape-out is carried out using TSMC 65nm CMOS process, and the total area of ​​the PUF core circuit is 4455μm 2 , the single-bit feature size is only 204.5F 2 The chip test results show that the bistable weak PUF circuit of the present invention, which can autonomously screen stable bits, has good randomness (50.03%), uniqueness (48.8%), and reliability (99.6%). When the temperature is between -40℃ and 125℃ and the voltage varies between 1.0V and 1.4V, the maximum unstable bit ratio can be reduced from 12.17% to nearly 0 (less than 1×10 -4 The bistable weak PUF circuit capable of autonomously screening stable bits of the present invention has outstanding performance in terms of hardware overhead and stability, and is very suitable for Internet of Things security protection.

Claims

1. A bistable weak PUF circuit capable of autonomously screening stable bits, characterized in that It includes a decoder, a timing circuit and a PUF core circuit; the decoder is used to access the n-bit excitation signal C1-C n , and the n-bit excitation signal C1-C n Perform decoding operation to obtain the m-bit word line level signal WL1-WL m Output to the PUF core circuit, n is an integer greater than or equal to 1, m = 2 n ; The timing circuit is used to access the clock signal CLK and the enable signal CEN, perform AND operation on the clock signal CLK and the enable signal CEN to obtain a clock signal AEN for controlling the working timing of the decoder and output it to the decoder, and delay the clock signal AEN and invert it and perform NAND operation on the clock signal AEN to obtain a clock signal PRE for controlling the working timing of the PUF core circuit and output it to the PUF core circuit; the PUF core circuit is used to generate a W-bit PUF response in each clock cycle of the clock signal PRE under the control of the m-bit word line level signal outputted thereto by the decoder, where W is an integer greater than or equal to 1; the PUF core circuit has an autonomous stable bit screening function, and the PUF core circuit realizes stable bit screening by accessing two screening levels. When the two screening levels accessed by the PUF core circuit are equal, the PUF core circuit outputs a W-bit PUF response to the decoder. Under the control of the m-bit wordline level signal at the clock signal PRE, a W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the original PUF response for the clock cycle. Then, the m-bit wordline level signal connected to the PUF core circuit is kept unchanged. First, one of the two screening levels connected to the PUF core circuit is kept unchanged, while the other is reduced by a certain amplitude. The W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the first screening PUF response. Then, the two screening levels are swapped, and the W-bit PUF response generated within one clock cycle of the clock signal PRE is used as the second screening PUF response. An exclusive-OR operation is performed on the first and second screening PUF responses to obtain a W-bit stability flag value. If the value of a bit in the W-bit stability flag value is 1, it is considered that the response value of the bit in the original PUF response under the current stimulus signal is an unstable response.

2. A bistable weak PUF circuit capable of autonomously screening stable bits according to claim 1, characterized in that The decoder has n excitation signal input terminals, 1 clock signal input terminal and m output terminals; the timing circuit has 2 input terminals and 2 output terminals, the 2 input terminals are respectively referred to as the first input terminal and the second input terminal, and the 2 output terminals are respectively referred to as the first output terminal and the second output terminal. The PUF core circuit has a power supply terminal, a ground terminal, m word line level signal input terminals, 1 clock signal input terminal, 2 screening level input terminals and W output terminals. The n excitation signal input terminals of the decoder are used to access the n-bit excitation signals C1-C n The m output terminals of the decoder are used to output m-bit word line level signals. The m output terminals of the decoder are connected one-to-one with the m word line level signal input terminals of the PUF core circuit. The first input terminal of the timing circuit is connected to the enable signal CEN, and the second input terminal is connected to the clock signal CLK. The first output terminal of the timing circuit is connected to the clock signal input terminal of the decoder. The first output terminal of the timing circuit outputs the clock signal AEN. The second output terminal of the timing circuit is connected to the clock signal input terminal of the PUF core circuit. The second output terminal of the timing circuit outputs the clock signal PRE. The power supply terminal of the PUF core circuit is used to connect to the working power supply VDD. The ground terminal of the PUF core circuit is used to connect to the ground voltage VSS. The W output terminals of the PUF core circuit are used to output the W-bit PUF response Z1-Z W The two screening level input terminals of the PUF core circuit are respectively connected to the screening level V L and V R .

3. A bistable weak PUF circuit capable of autonomously screening stable bits according to claim 2, characterized in that The timing circuit includes a D flip-flop, 21 inverters, a two-input AND gate and a first two-input NAND gate, wherein the D flip-flop has an input terminal, a clock terminal and an output terminal, the two-input AND gate has a first input terminal, a second input terminal and an output terminal, and the first two-input NAND gate has a first input terminal, a second input terminal and an output terminal, the input terminal of the D flip-flop is connected to the first input terminal of the timing circuit, the clock terminal of the D flip-flop and the second input terminal of the two-input AND gate, and its connection terminal is the second input terminal of the timing circuit, the The output end of the D flip-flop is connected to the first input end of the two-input AND gate, the output end of the two-input AND gate, the input end of the first inverter and the second input end of the first two-input NAND gate are connected, and the connection end is the first output end of the timing circuit, the output end of the kth inverter is connected to the input end of the k+1th inverter, k=1, 2,…, 20, the output end of the 21st inverter is connected to the first input end of the first two-input NAND gate, and the output end of the first two-input NAND gate is the second output end of the timing circuit.

4. A bistable weak PUF circuit capable of autonomously screening stable bits according to claim 2, characterized in that The PUF core circuit includes W PUF unit arrays and W latches. Each PUF unit array has a power supply terminal, a ground terminal, a clock signal input terminal, m word line level signal input terminals, two screening level input terminals, and two output terminals. The two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, and the two output terminals are respectively referred to as the first output terminal and the second output terminal. Each latch has two input terminals and one output terminal, and the two input terminals are respectively referred to as the first input terminal and the second input terminal. The power supply terminals of the W PUF unit arrays are connected, and their connection terminals are the power supply terminals of the PUF core circuit. The ground terminals of the W PUF unit arrays are connected, and their connection terminals are the ground terminals of the PUF core circuit. The first screening level input terminals of the W PUF unit arrays are connected, and the connection terminal thereof is the first screening level input terminal of the PUF core circuit. The second screening level input terminals of the W PUF unit arrays are connected, and the connection terminal thereof is the second screening level input terminal of the PUF core circuit. The clock signal input terminals of the W PUF unit arrays are connected, and the connection terminal thereof is the clock signal input terminal of the PUF core circuit. The i-th word line level signal input terminals of the W PUF unit arrays are connected, and the connection terminal thereof is the i-th word line level signal input terminal of the PUF core circuit, i=1, 2, ..., m, the first output terminal of the b-th PUF unit array is connected to the first input terminal of the b-th latch, the second output terminal of the b-th PUF unit array is connected to the second input terminal of the b-th latch, b=1, 2, ..., W, and the output terminals of the W latches are the W output terminals of the PUF core circuit.Each of the PUF unit arrays includes a decision unit and m PUF units, each PUF unit has a word line level signal input terminal, two screening level input terminals and four output terminals, the four output terminals are respectively referred to as the first output terminal, the second output terminal, the third output terminal and the fourth output terminal, the two screening level input terminals are respectively referred to as the first screening level input terminal and the second screening level input terminal, the decision unit has a power supply terminal, a ground terminal, a clock signal input terminal, two input terminals and two output terminals, the two input terminals are respectively referred to as the first input terminal and the second input terminal, the two output terminals are respectively referred to as the first output terminal and the second output terminal, the word line level signal input terminals of the m PUF units are the m word line level signal input terminals of the PUF unit array, the first screening level input terminals of the m PUF units are connected, and their connection terminals are the first screening level input terminals of the PUF unit array. The first input terminal of the decision unit is connected to the third output terminals of the m PUF units, the second input terminal of the decision unit is connected to the fourth output terminals of the m PUF units, the first output terminal of the decision unit is connected to the first output terminals of the m PUF units, and the second output terminal of the decision unit is connected to the second output terminal of the PUF unit array.

5. A bistable weak PUF circuit capable of autonomously screening stable bits according to claim 4, characterized in that The judgment unit includes a first MOS tube, a second MOS tube, a third MOS tube, a fourth MOS tube, a fifth MOS tube and a sixth MOS tube. The first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are all PMOS tubes, the fifth MOS tube and the sixth MOS tube are both NMOS tubes, the source of the first MOS tube, the source of the second MOS tube, the source of the third MOS tube and the source of the fourth MOS tube are connected, and the connection end thereof is the power supply end of the judgment unit, the source of the fifth MOS tube is connected to the source of the sixth MOS tube, and the connection end thereof is the ground end of the judgment unit, and the first MOS tube is connected to the source of the sixth MOS tube, and the connection end thereof is the ground end of the judgment unit. The gates of the third MOS transistor are connected to the gate of the fourth MOS transistor, and the connection ends thereof are the clock signal input ends of the judgment unit. The drain of the first MOS transistor, the drain of the third MOS transistor, the gate of the second MOS transistor, and the gate of the sixth MOS transistor are connected, and the connection ends thereof are the first output ends of the judgment unit. The drain of the second MOS transistor, the drain of the fourth MOS transistor, the gate of the first MOS transistor, and the gate of the fifth MOS transistor are connected, and the connection ends thereof are the second output ends of the judgment unit. The drain of the fifth MOS transistor is the first input end of the judgment unit, and the drain of the sixth MOS transistor is the second input end of the judgment unit.

6. A bistable weak PUF circuit capable of autonomously screening stable bits according to claim 4, characterized in that Each PUF unit includes a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, and a tenth MOS transistor. The seventh MOS transistor, the eighth MOS transistor, the ninth MOS transistor, and the tenth MOS transistor are all NMOS transistors. The drain of the seventh MOS transistor is the first output end of the PUF unit, the drain of the eighth MOS transistor is the second output end of the PUF unit, the drain of the ninth MOS transistor is the third output end of the PUF unit, and the drain of the tenth MOS transistor is the fourth output end of the PUF unit. The source of the seventh MOS transistor is connected to the source of the ninth MOS transistor, the source of the eighth MOS transistor is connected to the source of the tenth MOS transistor, and the gate of the seventh MOS transistor is connected to the gate of the eighth MOS transistor, and the connection end thereof serves as the word line level signal input end of the PUF unit. The gate of the ninth MOS transistor serves as the first screening level input end of the PUF unit, and the gate of the tenth MOS transistor serves as the second screening level input end of the PUF unit.

7. The bistable weak PUF circuit capable of autonomously screening stable bits according to claim 4, characterized in that Each of the latches includes two NAND gates, each of which has a first input terminal, a second input terminal and an output terminal. The two NAND gates are respectively referred to as a first NAND gate and a second NAND gate. The first input terminal of the first NAND gate is the first input terminal of the latch, the first input terminal of the second NAND gate is the second input terminal of the latch, the second input terminal of the first NAND gate is connected to the output terminal of the second NAND gate, the second input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, and the connection terminal thereof is the output terminal of the latch.

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