SpaceWire bus network time delay measurement method and device based on FPGA

Abstract

The invention relates to a SpaceWire bus network time delay measurement method and device based on an FPGA, an SPW-EOP interrupt module is added in an interface controller of a SpaceWire bus time delay network, a time delay measurement FPGA module is connected, a data sending end host CPU controls the interface controller to send variable-length data packets in a cycle according to a fixed period, and the variable-length data packets are connected with the SPW-EOP interrupt module. When the packet tail of each data packet leaves the host interface of the interface controller, the SPW-EOP interrupt module is triggered to generate an interrupt signal, and the interrupt signal is sent to the time delay measurement FPGA; the data packet is forwarded to a receiving end interface controller through a SpaceWire bus, an SPW-EOP interrupt module of the interface controller is triggered to generate an interrupt signal, and the interrupt signal is sent to a time delay measurement FPGA; and the time delay measurement FPGA collects the interrupt signal and calculates the transmission time delay. According to the invention, high-precision measurement of the data transmission delay of the SpaceWire link is realized on a physical layer, the measured data is accurate, the universality is high, the measurement method is efficient, and a reliable basis is provided for time planning of a spacecraft data transmission task.

Description

Technical Field

[0001] The invention relates to a SpaceWire bus network delay measurement method and device based on FPGA, belonging to the field of spacecraft communication bus. Background Art

[0002] The SpaceWire bus can provide highly reliable high-speed communication functions in extreme environments. As the SpaceWire bus is increasingly used in spacecraft with complex structures and high data transmission requirements, network parameters such as delay and transmission rate have gradually become the focus of attention. Since it supports communication rates of 2 to 300Mbps, the load rates and frequencies of different nodes in the network vary greatly, which can easily lead to overload or even blockage of some paths, resulting in significant delay problems and affecting the time planning of the entire network. At present, there are many engineering solutions for SpaceWire network time planning, but most of them are based on the worst-case delay calculated by theoretical models, which has a large error with the actual situation. Some test systems involving the SpaceWire bus are mainly tested through the application layer or network layer, but due to the poor real-time performance of these layers, the delay data obtained has a large error. And due to the direct influence of the processing delay of different types of host systems, it cannot intuitively reflect the hardware delay of the SpaceWire network and has poor versatility. Some methods of testing delay through data packet byte redundancy are affected by the cross-clock domain, with limited accuracy and directly reducing the data transmission efficiency of the SpaceWire bus. Summary of the invention

[0003] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art, to provide a SpaceWire bus network delay measurement method and device based on FPGA, to test the SpaceWire bus data transmission delay from the physical layer based on the SPW-EOP trigger interrupt mode, with extremely high measurement accuracy and without affecting the data transmission efficiency of the SpaceWire bus; to separate the host system processing delay, which can be applied to the time analysis and planning of the SpaceWire network composed of different host systems, and the measurement results are highly universal; based on FPGA, to realize the automatic test of the transmission delay of a large number of data packets with different lengths, with high measurement efficiency.

[0004] The technical solution of the present invention is: in the first aspect, a method for measuring delay of a SpaceWire bus network based on FPGA is provided, wherein the SpaceWire bus network comprises: a first node host CPU, a first node high-speed SpaceWire interface controller, a high-speed SpaceWire router, a second node high-speed SpaceWire interface controller and a second node host CPU, and the above parts are connected in sequence; wherein the first node high-speed SpaceWire interface controller, the high-speed SpaceWire router and the second node high-speed SpaceWire interface controller are connected via a SpaceWire bus;

[0005] Measurement methods include:

[0006] Adding a SPW-EOP interrupt module to the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller;

[0007] Connect the delay measurement FPGA module in the SpaceWire bus network.

[0008] The host CPU of the first node controls the high-speed SpaceWire interface controller of the first node to send variable-length data packets in a fixed cycle. When the tail of each data packet leaves the host interface of the high-speed SpaceWire interface controller of the first node, the SPW-EOP interrupt module is triggered to generate a sending node SPW-EOP interrupt signal, which is sent to the delay measurement FPGA module.

[0009] The data packet is transmitted along the SpaceWire bus to the high-speed SpaceWire router, and then forwarded to the second node high-speed SpaceWire interface controller via the SpaceWire bus;

[0010] When the tail of each data packet enters the host interface of the high-speed SpaceWire interface controller of the second node, the SPW-EOP interrupt module of the high-speed SpaceWire interface controller of the second node is triggered to generate a receiving node SPW-EOP interrupt signal, which is sent to the delay measurement FPGA module;

[0011] The delay measurement FPGA module cyclically collects and synchronizes the sending node SPW-EOP interrupt signal and the receiving node SPW-EOP interrupt signal corresponding to each data packet, and records the value of the corresponding FPGA counter when the two SPW-EOP interrupt signals arrive. This value multiplied by the FPGA clock cycle is the arrival timestamp of the corresponding signal. The time difference between the two timestamps is calculated to obtain the transmission delay and store it in the BRAM of the delay measurement FPGA module.

[0012] Preferably, the delay measurement FPGA module includes: a delay measurement FPGA, and a measurement node host CPU connected to the delay measurement FPGA; two ends of the delay measurement FPGA are respectively connected to the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller, and the measurement node host CPU is also connected to the host computer PC;

[0013] The host CPU of the measurement node reads the data in the BRAM of the delay measurement FPGA and transmits it to the host PC, where the delay data is saved and analyzed.

[0014] Preferably, the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller are provided with a SPW-EOP interrupt module.

[0015] Preferably, the SPW-EOP interrupt module includes an SPW-EOP module and an interrupt controller, specifically:

[0016] When the tail of each data packet leaves the host interface of the high-speed SpaceWire interface controller of the first node, the SPW-EOP module interrupt control register is enabled to allow an interrupt request to be initiated;

[0017] The SPW-EOP interrupt module compares the characters in the data packet with the standard end-of-packet character specified by the SpaceWire protocol. <1> <xxxxxxx0>”:

[0018] If there is inconsistency, continue to judge;

[0019] If they are consistent, the SPW-EOP module sends an interrupt request to the interrupt controller and sets the corresponding position in the interrupt status register to 1; the interrupt controller generates an interrupt signal and outputs a high level to the delay measurement FPGA through the interrupt pin to complete the sending of the interrupt signal.

[0020] Preferably, the FPGA sampling frequency is not less than twice the highest SPW-EOP interrupt signal frequency.

[0021] Preferably, the high-speed SpaceWire can be cascaded in one or two stages in the SpaceWire bus network.

[0022] Preferably, the process loop of FPGA collecting and timing the SPW-EOP interrupt signal runs in parallel;

[0023] The worst time error of FPGA acquisition and synchronization signals does not exceed 8ns.

[0024] Preferably, the measurement node host CPU communicates with the host computer PC via a UART serial port communication protocol.

[0025] Preferably, the first node high-speed SpaceWire interface controller, the second node high-speed SpaceWire interface controller, the high-speed SpaceWire router, and the SpaceWire bus operate at a rate ranging from 2 to 300 MHz.

[0026] In a second aspect, a FPGA-based SpaceWire bus network delay measurement device is provided, comprising: an SPW-EOP interrupt module and a delay measurement FPGA module arranged in a first node high-speed SpaceWire interface controller and a second node high-speed SpaceWire interface controller of the SpaceWire bus network; wherein:

[0027] The delay measurement FPGA module includes: a delay measurement FPGA, and a measurement node host CPU connected to the delay measurement FPGA; two ends of the delay measurement FPGA are respectively connected to a first node high-speed SpaceWire interface controller and a second node high-speed SpaceWire interface controller, and the measurement node host CPU is simultaneously connected to a host computer PC;

[0028] The SPW-EOP interrupt module includes an SPW-EOP module and an interrupt controller. When the tail of each data packet leaves the host interface of the first node high-speed SpaceWire interface controller or the second node high-speed SpaceWire interface controller, the SPW-EOP interrupt module enables the SPW-EOP interrupt module interrupt control register to allow the initiation of an interrupt request. The SPW-EOP interrupt module compares the characters in the data packet with the standard tail characters specified by the SpaceWire protocol. <1> <xxxxxxx0>”: If they are inconsistent, continue to judge; if they are consistent, the SPW-EOP module sends an interrupt request to the interrupt controller and sets the corresponding position in the interrupt status register to 1; the interrupt controller generates an interrupt signal and outputs a high level to the delay measurement FPGA through the interrupt pin to complete the sending of the interrupt signal.

[0029] Compared with the prior art, the present invention has the following advantages:

[0030] (1) The present invention tests the SpaceWire bus data transmission delay from the physical layer by triggering an interruption via SPW-EOP, with extremely high measurement accuracy and without affecting the original data transmission efficiency of the SpaceWire network;

[0031] (2) The delay parameters measured by the present invention separate the processing delay of the host system and can be applied to the time analysis and planning of SpaceWire networks composed of different host systems;

[0032] (3) The automated testing device of the present invention can continuously measure the delay of data packets of different lengths in large quantities, greatly saving manual testing time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Schematic diagram of the SpaceWire bus delay measurement device of the present invention; wherein (a) is a schematic diagram of a 1-level router cascade network, (b) is a schematic diagram of a 2-level router cascade network,

[0034] Figure 2 It is the working flow chart of the SPW-EOP interrupt module of the present invention;

[0035] Figure 3 This is a working diagram of the FPGA delay measurement module of the present invention;

[0036] Figure 4 This is a diagram of the delay measurement results of the present invention. DETAILED DESCRIPTION

[0037] A SpaceWire bus network delay measurement method based on FPGA, specifically:

[0038] Connecting a delay measurement FPGA module in a SpaceWire bus network, wherein the SpaceWire bus network includes: a first node host CPU, a first node high-speed SpaceWire interface controller, a high-speed SpaceWire router, a second node high-speed SpaceWire interface controller, and a second node host CPU, and the above-mentioned mechanisms are connected in sequence; wherein the first node high-speed SpaceWire interface controller, the high-speed SpaceWire router, and the second node high-speed SpaceWire interface controller are connected through a SpaceWire bus;

[0039] The delay measurement FPGA module includes: a delay measurement FPGA, and a measurement node host CPU connected to the delay measurement FPGA; two ends of the delay measurement FPGA are respectively connected to a first node high-speed SpaceWire interface controller and a second node high-speed SpaceWire interface controller, and the measurement node host CPU is simultaneously connected to a host computer PC;

[0040] The first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller are provided with a SPW-EOP interrupt module.

[0041] The specific delay test method is as follows:

[0042] (1) The first node host CPU controls the first node high-speed SpaceWire interface controller (interface controller B1) to send variable-length data packets in a fixed periodic cycle. When the tail of each data packet leaves the host interface of the first node high-speed SpaceWire interface controller (interface controller B1), the SPW-EOP interrupt module is triggered to generate a sending node SPW-EOP interrupt signal, which is sent to the delay measurement FPGA.

[0043] (2) At the same time, the data packet is transmitted along the SpaceWire bus to the high-speed SpaceWire router, and then forwarded to the second node high-speed SpaceWire interface controller (receiving node interface controller B2) via the SpaceWire bus.

[0044] (3) When the tail of each data packet enters the host interface of the second-node high-speed SpaceWire interface controller (receiving node interface controller B2), the SPW-EOP interrupt module of the second-node high-speed SpaceWire interface controller (receiving node interface controller B2) is triggered to generate a receiving node SPW-EOP interrupt signal, which is sent to the delay measurement FPGA.

[0045] (4) The delay measurement FPGA loop collects the sending node SPW-EOP interrupt signal and the receiving node SPW-EOP interrupt signal corresponding to each data packet, records the timestamps of the two SPW-EOP interrupt signals, calculates the time difference between the two timestamps to obtain the transmission delay and stores it in the BRAM of the delay measurement FPGA (the specific FPGA workflow is as follows: Figure 3 shown).

[0046] (5) The data in the BRAM of the delay measurement FPGA is read through the measurement node host CPU and transmitted to the host PC, where the delay data is saved and analyzed.

[0047] In the SPW-EOP interrupt module in the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller: the SPW-EOP interrupt module includes an SPW-EOP module and an interrupt controller;

[0048] When the tail of each data packet leaves the first node high-speed SpaceWire interface controller (interface controller B1) or the host interface, the SPW-EOP interrupt module interrupt control register is enabled to allow the initiation of an interrupt request;

[0049] The SPW-EOP interrupt module compares the characters in the data packet with the standard end-of-packet characters specified by the SpaceWire protocol. <1> <xxxxxxx0>”:

[0050] If there is inconsistency, continue to judge;

[0051] If they are consistent, the SPW-EOP module sends an interrupt request to the interrupt controller and sets the corresponding position (SPW-EOP bit) in the interrupt status register to 1; the interrupt controller generates an interrupt signal and outputs a high level to the delay measurement FPGA through the interrupt pin to complete the sending of the interrupt signal.

[0052] The SPW-EOP interrupt module compares the data packet data characters sent by the first node host CPU with the standard packet end characters specified by the SpaceWire protocol. <1> <xxxxxxx0>", triggers a valid SPW-EOP interrupt signal at the same time as the data packet leaves the host interface.

[0053] The FPGA sampling frequency is not less than twice the SPW-EOP interrupt signal frequency.

[0054] The process loop of FPGA acquisition and timing SPW-EOP signal runs in parallel.

[0055] The worst time error of FPGA acquisition and synchronization signals does not exceed 8ns.

[0056] The BRAM space instantiated in the FPGA is mapped into the IO space of the host CPU.

[0057] The host CPU of the measurement node communicates with the host PC through the UART serial port communication protocol.

[0058] The nodes and routers in the network are connected via the SpaceWire bus.

[0059] Routers in the network can be cascaded into level 1 and level 2 respectively.

[0060] The first node high-speed SpaceWire interface controller, the second node high-speed SpaceWire interface controller, the router, and the link operating rate range are 2 to 300 MHz.

[0061] The measuring device includes a node host CPU, a high-speed SpaceWire interface controller, a high-speed SpaceWire router, an FPGA, and a host PC.

[0062] The present invention is further described below with reference to the accompanying drawings and embodiments. The SpaceWire bus network of Embodiment 1 is composed of a level 1 router, a sending node, and a receiving node, and the SpaceWire bus network of Embodiment 2 is composed of a level 2 serially connected router, a sending node, and a receiving node.

[0063] Embodiment 1:

[0064] Attached Figure 1 The device shown in (a) realizes high-precision SpaceWire bus delay measurement in a single-stage router network environment. The delay measurement device includes: a node host CPU, a high-speed SpaceWire interface controller, a high-speed SpaceWire router, a delay measurement FPGA, and a host PC. The node host CPU is connected to the high-speed SpaceWire interface controller through 13-bit address lines, 32-bit data lines and other control lines, the high-speed SpaceWire interface controller is connected to the high-speed SpaceWire router through a SpaceWire link, the delay measurement FPGA is connected to the measurement node host CPU through 13-bit address lines, 32-bit data lines and other control lines, and the measurement node host CPU is connected to the host computer through a serial bus.

[0065] In the example of the present invention, in the typical application circuit, router A selects XXX006 developed by a certain company, interface controllers B1 and B2 select XXX005 developed by a certain company, FPGA selects Xilinx Virtex-5XC5VLX155T, node host selects Sparc-V8 architecture CPU, FPGA delay measurement module selects 50MHz crystal oscillator, and SpaceWire node selects 25MHz crystal oscillator.

[0066] according to Figure 1 (a) Connect the SpaceWire bus network and set the SpaceWire link speed to 300MHz. Start the FPGA delay measurement module, start timing and wait for the collection of SPW-EOP interrupt signals. Whenever the interrupt signal of the sending / receiving node is collected, record the corresponding timestamp. The transmission delay is calculated as follows:

[0067] T delay =T receive -T send

[0068] Among them, T send Represents the timestamp corresponding to the sending node interrupt signal, T receive Represents the timestamp corresponding to the interrupt signal of the receiving node, T delay Represents the transmission delay. The FPGA will sequentially calculate the transmission delay corresponding to each data packet and store it in the BRAM.

[0069] Configure the CPU2 program to control the interface controller B2 to continuously wait for data from the SpaceWire bus. Configure the CPU1 program to control the interface controller B1 to cyclically send data packets with a length of 124 to 12400 bytes to the SpaceWire bus at a fixed period. The length of the data packet in the 0th cycle is 124 bytes, the length of the data packet in the 1st cycle is 248 bytes, ..., and the length of the data packet in the 99th cycle is 12400 bytes. Configure the CPU3 program to read the data in the BRAM and transmit it to the host computer, record and process the experimental data. The corresponding delay data of data packets of different lengths transmitted from the sending node to the receiving node is shown in Figure 4 And as shown in Table 1.

[0070] Table 1 Corresponding delay data of different lengths of data packets transmitted from the sending node to the receiving node

[0071] Packet size (bytes) Transmission delay (microseconds) 124 8.24 248 15.08 372 21.88 496 28.68 ··· ··· 12028 663.56 12152 670.4 12276 677.24 12400 684.04

[0072] As can be seen from the chart, there is a nearly linear relationship between the transmission delay and the data packet length; in the first cycle, that is, when the transmission data packet length is 124 bytes, the delay is 8.24 microseconds, and in the 100th cycle, that is, when the transmission data packet length is 12400 bytes, the delay is close to 684.04us.

[0073] Example 2

[0074] Attached Figure 1 The device shown in (b) realizes high-precision SpaceWire bus delay measurement in a two-level router cascade network environment. The delay measurement device includes: a node host CPU, a high-speed SpaceWire interface controller, a high-speed SpaceWire router, an FPGA, and a host PC.

[0075] In the example of the present invention, in the typical application circuit, routers A and B select XXX006 developed by a certain company, interface controllers B1 and B2 select XXX005 developed by a certain company, FPGA selects Xilinx Virtex-5XC5VLX155T, node host selects Sparc-V8 architecture CPU, FPGA delay measurement module selects 50MHz crystal oscillator, and SpaceWire node selects 25MHz crystal oscillator.

[0076] according to Figure 1 Connect the SpaceWire bus network and set the SpaceWire link speed to 300MHz. Start the FPGA delay measurement module, start timing and wait for the collection of SPW-EOP interrupt signals. Whenever the interrupt signal of the sending / receiving node is collected, record the corresponding timestamp. The transmission delay calculation method is as follows:

[0077] T delay =T receive -T send

[0078] Among them, T send Represents the timestamp corresponding to the sending node interrupt signal, T receive Represents the timestamp corresponding to the interrupt signal of the receiving node, T delay Represents the transmission delay. The FPGA will sequentially calculate the transmission delay corresponding to each data packet and store it in the BRAM.

[0079] Configure the CPU2 program to control the interface controller B2 to continuously wait for data from the SpaceWire bus. Configure the CPU1 program to control the interface controller B1 to send data packets with a length of 124 to 12400 bytes to the SpaceWire bus in a fixed cycle. The length of the data packet in the 0th cycle is 124 bytes, the length of the data packet in the 1st cycle is 248 bytes, ..., and the length of the data packet in the 99th cycle is 12400 bytes. Configure the CPU3 program to read the data in the BRAM and transmit it to the host computer to record and process the experimental data.

[0080] The contents not described in detail in the specification of the present invention belong to the prior art known to the professional and technical personnel in this field.

Claims

1. A SpaceWire bus network delay measurement method based on FPGA, the SpaceWire bus network includes: The first node host CPU, the first node high-speed SpaceWire interface controller, the high-speed SpaceWire router, the second node high-speed SpaceWire interface controller and the second node host CPU are connected in sequence; wherein the first node high-speed SpaceWire interface controller, the high-speed SpaceWire router and the second node high-speed SpaceWire interface controller are connected via a SpaceWire bus; characterized in that: the measuring method comprises: Adding a SPW-EOP interrupt module to the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller; Connect the delay measurement FPGA module in the SpaceWire bus network. The host CPU of the first node controls the high-speed SpaceWire interface controller of the first node to send variable-length data packets in a fixed cycle. When the tail of each data packet leaves the host interface of the high-speed SpaceWire interface controller of the first node, the SPW-EOP interrupt module is triggered to generate a sending node SPW-EOP interrupt signal, which is sent to the delay measurement FPGA module. The data packet is transmitted along the SpaceWire bus to the high-speed SpaceWire router, and then forwarded to the second node high-speed SpaceWire interface controller via the SpaceWire bus; When the tail of each data packet enters the host interface of the high-speed SpaceWire interface controller of the second node, the SPW-EOP interrupt module of the high-speed SpaceWire interface controller of the second node is triggered to generate a receiving node SPW-EOP interrupt signal, which is sent to the delay measurement FPGA module; The delay measurement FPGA module cyclically collects and synchronizes the sending node SPW-EOP interrupt signal and the receiving node SPW-EOP interrupt signal corresponding to each data packet, and records the value of the corresponding FPGA counter when the two SPW-EOP interrupt signals arrive. This value multiplied by the FPGA clock cycle is the arrival timestamp of the corresponding signal. The time difference between the two timestamps is calculated to obtain the transmission delay and store it in the BRAM of the delay measurement FPGA module.

2. The method for measuring delay of a SpaceWire bus network based on FPGA according to claim 1, characterized in that: The delay measurement FPGA module includes: a delay measurement FPGA, and a measurement node host CPU connected to the delay measurement FPGA; two ends of the delay measurement FPGA are respectively connected to a first node high-speed SpaceWire interface controller and a second node high-speed SpaceWire interface controller, and the measurement node host CPU is also connected to a host computer PC; The host CPU of the measurement node reads the data in the BRAM of the delay measurement FPGA and transmits it to the host PC, where the delay data is saved and analyzed.

3. The method for measuring delay of a SpaceWire bus network based on FPGA according to claim 1, characterized in that: The first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller are provided with a SPW-EOP interrupt module.

4. The method for measuring delay of a SpaceWire bus network based on FPGA according to claim 3, characterized in that: The SPW-EOP interrupt module includes the SPW-EOP module and the interrupt controller. Specifically: When the tail of each data packet leaves the host interface of the high-speed SpaceWire interface controller of the first node, the SPW-EOP module interrupt control register is enabled to allow an interrupt request to be initiated; The SPW-EOP interrupt module compares the characters in the data packet with the standard end-of-packet characters specified by the SpaceWire protocol. <1> <xxxxxxx0> ”：< / xxxxxxx0> If there is inconsistency, continue to judge; If they are consistent, the SPW-EOP module sends an interrupt request to the interrupt controller and sets the corresponding position in the interrupt status register to 1; the interrupt controller generates an interrupt signal and outputs a high level to the delay measurement FPGA through the interrupt pin to complete the sending of the interrupt signal.

5. The method for measuring delay of a SpaceWire bus network based on FPGA according to claim 1, characterized in that: The FPGA sampling frequency is not less than twice the highest SPW-EOP interrupt signal frequency.

6. The method for measuring delay of a SpaceWire bus network based on FPGA according to claim 1, characterized in that: High-speed SpaceWire can be cascaded in one or two stages in a SpaceWire bus network.

7. The method for measuring delay of a SpaceWire bus network based on FPGA according to claim 1, characterized in that: The process loop of FPGA collecting and timing SPW-EOP interrupt signals runs in parallel; The worst time error of FPGA acquisition and synchronization signals does not exceed 8ns.

8. The method for measuring delay of a SpaceWire bus network based on FPGA according to claim 1, characterized in that: The host CPU of the measurement node communicates with the host PC through the UART serial port communication protocol.

9. The method for measuring delay of a SpaceWire bus network based on FPGA according to claim 1, characterized in that: The first node high-speed SpaceWire interface controller, the second node high-speed SpaceWire interface controller, the high-speed SpaceWire router, and the SpaceWire bus operate at a rate ranging from 2 to 300 MHz.

10. A SpaceWire bus network delay measurement device based on FPGA, characterized in that include: The SPW-EOP interrupt module and the delay measurement FPGA module are arranged in the first node high-speed SpaceWire interface controller and the second node high-speed SpaceWire interface controller of the SpaceWire bus network; wherein: The delay measurement FPGA module includes: a delay measurement FPGA, and a measurement node host CPU connected to the delay measurement FPGA; two ends of the delay measurement FPGA are respectively connected to a first node high-speed SpaceWire interface controller and a second node high-speed SpaceWire interface controller, and the measurement node host CPU is simultaneously connected to a host computer PC; The SPW-EOP interrupt module includes an SPW-EOP module and an interrupt controller. When the tail of each data packet leaves the host interface of the first node high-speed SpaceWire interface controller or the second node high-speed SpaceWire interface controller, the SPW-EOP interrupt module enables the SPW-EOP interrupt module interrupt control register to allow the initiation of an interrupt request. The SPW-EOP interrupt module compares the characters in the data packet with the standard tail characters specified by the SpaceWire protocol. <1> <xxxxxxx0> ”: If they are inconsistent, continue to judge; if they are consistent, the SPW-EOP module sends an interrupt request to the interrupt controller and sets the corresponding position in the interrupt status register to 1; the interrupt controller generates an interrupt signal and outputs a high level to the delay measurement FPGA through the interrupt pin to complete the sending of the interrupt signal.< / xxxxxxx0>

Images