Semiconductor structure and manufacturing method thereof

Abstract

The present disclosure relates to a semiconductor structure and a method for manufacturing the same. A second hole disposed away from a substrate and enclosed by a memory cell increases the contact area between a second conductive structure and a second electrode layer, thereby increasing the drive current of the memory cell driven by the second conductive structure. Thus, when the first functional layer is a gating layer and the second functional layer is a resistive switching layer, increasing the contact area between the second conductive structure and the second electrode layer is beneficial for improving the read and write capabilities and read and write speeds of the memory cell. When the first functional layer is a resistive switching layer and the second functional layer is a gating layer, increasing the contact area between the second conductive structure and the second electrode layer is beneficial for improving the gating capability and gating speed of the memory cell.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Since the advent of Moore's Law, the industry has proposed various semiconductor device designs and process optimizations to meet people's demand for current products.

[0003] However, with the continuous development of fields such as artificial intelligence and autonomous driving, higher requirements are placed on memory, such as requiring memory to have higher integration density and better reliability. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof to address the problem in the prior art of requiring a memory to have higher integration density and better reliability.

[0005] In a first aspect, the present disclosure provides a semiconductor structure comprising:

[0006] substrate;

[0007] A first conductive structure is provided on the substrate;

[0008] a memory cell disposed on a side of the first conductive structure away from the substrate, the memory cell comprising a first electrode layer, a first functional layer, a second functional layer, and a second electrode layer stacked in sequence in a direction away from the substrate; the memory cell forming a second hole above the first conductive structure, the opening direction of the second hole facing away from the substrate; one of the first functional layer and the second functional layer being a gating layer, and the other being a resistive switching layer;

[0009] The second conductive structure is arranged on a side of the memory cell away from the substrate, and the second conductive structure is in contact with the second electrode layer on the sidewall and bottom wall of the second hole.

[0010] Optionally, it also includes:

[0011] an isolation layer, provided on a side of the first conductive structure away from the substrate, the isolation layer being penetrated by a first hole;

[0012] The storage unit is arranged corresponding to the first hole, and the second hole is surrounded above the first hole; wherein, the first electrode layer covers the first conductive structure of the bottom wall of the first hole, the side wall of the first hole and a portion of the top surface of the isolation layer around the first hole, and the first functional layer, the second functional layer and the second electrode layer sequentially cover the first electrode layer.

[0013] Optionally, the storage unit further includes an intermediate layer, wherein the intermediate layer is provided between the first functional layer and the second functional layer;

[0014] The material of the intermediate layer includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0015] Optionally, the material of the gate layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride;

[0016] The material of the resistive layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0017] Optionally, the memory cell further comprises a barrier layer, wherein the barrier layer is arranged between the gate layer and the first electrode layer, or the barrier layer is arranged between the gate layer and the second electrode layer;

[0018] The electron affinity of the barrier layer is less than the electron affinity of the gating layer; the material of the barrier layer includes at least one of zinc oxide, nickel oxide, titanium oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, barium titanate, indium oxide, vanadium oxide, strontium titanate, aluminum titanate, manganese oxide, and gallium nitride.

[0019] Optionally, the memory cell further comprises a buffer layer, wherein the buffer layer is disposed between the gate layer and the barrier layer;

[0020] The electron affinity of the buffer layer is between that of the gating layer and the barrier layer; the material of the buffer layer includes at least one of titanium oxide, nickel oxide, zinc oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, indium oxide, vanadium oxide, niobium oxide, manganese oxide, neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide, gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide or magnesium oxide.

[0021] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0022] providing a substrate, and forming a first conductive structure on the substrate;

[0023] forming an isolation layer on a side of the first conductive structure away from the substrate, and etching the isolation layer to form a first hole, wherein the first hole exposes a portion of the top surface of the first conductive structure;

[0024] A first electrode layer, a first functional layer, a second functional layer, and a second electrode layer are sequentially formed to form a memory cell, wherein the memory cell forms a second hole above the first conductive structure, and the opening direction of the second hole is away from the substrate; one of the first functional layer and the second functional layer is a gating layer, and the other is a resistive switching layer;

[0025] A second conductive structure is formed on a side of the memory cell away from the substrate, wherein the second conductive structure contacts the second electrode layer on the sidewall and bottom wall of the second hole.

[0026] Optionally, the material of the gate layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride;

[0027] The material of the resistive layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide;

[0028] After forming the first functional layer and the second functional layer, an annealing process is performed on the first functional layer and the second functional layer together.

[0029] Optionally, forming the storage unit further includes: forming an intermediate layer between the first functional layer and the second functional layer.

[0030] Optionally, forming the memory cell further comprises: forming a barrier layer between the gate layer and the first electrode layer, or forming a barrier layer between the gate layer and the second electrode layer; the electron affinity of the barrier layer is smaller than the electron affinity of the gate layer;

[0031] The memory cell is formed, further comprising: forming a buffer layer between the gate layer and the barrier layer; the electron affinity of the buffer layer is between that of the gate layer and the barrier layer.

[0032] The semiconductor structure and manufacturing method disclosed herein increase the contact area between the second conductive structure and the second electrode layer by enclosing the second hole disposed away from the substrate by the storage unit, thereby increasing the drive current of the storage unit driven by the second conductive structure. In this way, when the first functional layer is a gating layer and the second functional layer is a resistive switching layer, increasing the contact area between the second conductive structure and the second electrode layer is beneficial to improving the read and write capabilities and read and write speed of the storage unit. When the first functional layer is a resistive switching layer and the second functional layer is a gating layer, increasing the contact area between the second conductive structure and the second electrode layer is beneficial to improving the gating capability and gating speed of the storage unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the following briefly introduces the drawings required for use in the embodiments or the description of the traditional technology. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 is a schematic structural diagram of a semiconductor structure provided in one embodiment;

[0035] Figure 2 is a schematic structural diagram of a semiconductor structure provided in another embodiment;

[0036] Figure 3 is a schematic structural diagram of a semiconductor structure provided in yet another embodiment;

[0037] Figure 4 is a process flow chart of a method for manufacturing a semiconductor structure provided in one embodiment;

[0038] Figure 5 This is a structural schematic diagram of providing a substrate and forming a first conductive structure on the substrate according to an embodiment;

[0039] Figure 6 A schematic diagram of a structure after an isolation layer is formed on a side of the first conductive structure away from the substrate provided in one embodiment;

[0040] Figure 7 A schematic diagram of the structure after etching the isolation layer to form a first hole provided in one embodiment;

[0041] Figure 8 A schematic diagram of a structure after sequentially forming a first electrode layer, a first functional layer, a second functional layer, and a second electrode layer, provided in one embodiment;

[0042] Figure 9 A schematic diagram of a structure after a storage unit is formed according to an embodiment;

[0043] Figure 10 FIG. 1 is a schematic structural diagram after forming a second conductive structure provided in an embodiment.

[0044] Description of reference numerals:

[0045] 10. Substrate; 20. First conductive structure; 21. First conductive layer; 22. Second conductive layer; 23. Third conductive layer; 30. Storage cell; 31. First electrode layer; 32. First functional layer; 33. Second functional layer; 34. Second electrode layer; 35. Intermediate layer; 36. Barrier layer; 37. Buffer layer; 40. Second conductive structure; 41. Fourth conductive layer; 42. Fifth conductive layer; 51. First dielectric layer; 52. Second dielectric layer; 101. First hole; 102. Second hole; A1, storage area; A2, logic area. DETAILED DESCRIPTION

[0046] To facilitate understanding of the present disclosure, a more comprehensive description of the present disclosure will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present disclosure. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the art of the present disclosure. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0048] The 1S1R architecture consists of a selector (a threshold switching device) and a memristor (such as resistive random access memory (RRAM)). The selector has a threshold transition characteristic: when the applied voltage or current exceeds a certain threshold, the selector changes from a high-resistance state to a low-resistance state, allowing current to flow. In RRAM, when in the low-resistance state, leakage current may occur. However, in the 1S1R architecture, the threshold transition characteristic of the selector effectively suppresses leakage current in unselected cells, thereby improving the stability and reliability of the memory.

[0049] 1S1R architecture memories offer smaller feature sizes, low power consumption, and high reliability, helping to achieve high-density storage. However, as the critical dimensions of integrated circuits continue to shrink, the three-dimensional integration of 1S1R architecture memories remains challenging.

[0050] According to an exemplary embodiment, the present disclosure provides a semiconductor structure, referring to Figure 1 、 Figure 2 or Figure 3As shown, the semiconductor structure includes a substrate 10, a first conductive structure 20, a storage unit 30 and a second conductive structure 40; the first conductive structure 20 is provided on the substrate 10; the storage unit 30 is provided on the side of the first conductive structure 20 away from the substrate 10, and the storage unit 30 includes a first electrode layer 31, a first functional layer 32, a second functional layer 33 and a second electrode layer 34 stacked in sequence in a direction away from the substrate 10, and the storage unit 30 forms a second hole 102 above the first conductive structure 20, and the opening direction of the second hole 102 is away from the substrate 10; one of the first functional layer 32 and the second functional layer 33 is a selection layer, and the other is a resistive layer; the second conductive structure 40 is provided on the side of the storage unit 30 away from the substrate 10, and the second conductive structure 40 is in contact with the second electrode layer 34 on the side wall and bottom wall of the second hole 102.

[0051] The substrate 10 includes a memory area A1 and a logic area A2. Both memory area A1 and logic area A2 are formed with a first conductive structure 20. The first conductive structure 20 may be a wire or wiring structure embedded in a first dielectric layer 51. The first conductive structure 20 is used to transmit current within the semiconductor structure. The material of the first conductive structure 20 includes a metal (such as copper, aluminum, etc.) or a metal alloy, and the first conductive structure 20 has excellent electrical conductivity. The first conductive structure 20 may also include a barrier layer disposed between the metal material (such as copper, aluminum, etc.) and the first dielectric layer 51. The barrier layer supports the first conductive structure 20 and isolates the first conductive structure 20 from other film layers to prevent outward diffusion of the conductive material. The barrier layer may be made of titanium, tantalum, etc. In this embodiment, the first conductive structure 20 includes a first conductive layer 21, a second conductive layer 22, and a third conductive layer 23, which are sequentially connected in a direction perpendicular to the substrate 10. The first conductive layer 21, the second conductive layer 22, and the third conductive layer 23 may be wires or pads disposed in a direction extending outward from the substrate 10.

[0052] The memory cell 30 is located on a side of the first conductive structure 20 in the storage area A1 away from the substrate 10. The memory cell 30 is in contact with the top surface of the first conductive structure 20. In this embodiment, the memory cell 30 adopts a 1S1R memory architecture. The memory cell 30 includes a first electrode layer 31, a first functional layer 32, a second functional layer 33, and a second electrode layer 34, which are sequentially stacked on the first conductive structure 20. One of the first functional layer 32 and the second functional layer 33 is a selector layer, and the other is a resistive layer. The selector layer blocks current flow at low voltages and allows current flow at high voltages. This prevents current from flowing through other unselected memory cells 30 when a specific memory cell 30 is selected for read and write operations, thereby avoiding crosstalk. The resistance value of the resistive layer can be switched between a high resistance state and a low resistance state under current stimulation, thereby achieving data storage.

[0053] The first electrode layer 31 serves as the bottom electrode of the memory cell 30 and is connected to the first conductive structure 20 and the first functional layer 32. The second electrode layer 34 serves as the top electrode of the memory cell 30 and is connected to the second functional layer 33. The first electrode layer 31 is used to connect to an external circuit. The first electrode layer 31 and the second electrode layer 34 can be used to operate the memory cell 30, turn on the selection layer, and perform read and write operations on the resistive layer.

[0054] The storage unit 30 forms a second hole 102 above the first conductive structure 20, and the opening direction of the second hole 102 is away from the substrate 10. The second conductive structure 40 is located on the side of the storage unit 30 away from the substrate 10, and the second conductive structure 40 is in contact with the second electrode layer 34 on the sidewalls and bottom wall of the second hole 102. The second conductive structure 40 can be a wire or wiring structure embedded in the second dielectric layer 52, which is used to transmit current inside the semiconductor structure. In this embodiment, the second conductive structure 40 includes a fourth conductive layer 41 and a fifth conductive layer 42 connected in sequence along a direction perpendicular to the substrate 10. The fourth conductive layer 41 and the fifth conductive layer 42 can be wires or pads arranged along a direction from the substrate 10. The second conductive structure 40 is formed in both the storage area A1 and the logic area A2, and the logic area A2 is connected to the first conductive structure 20.

[0055] In the semiconductor structure of this embodiment, the memory cell 30 encloses a second hole 102 disposed away from the substrate 10, thereby increasing the contact area between the second conductive structure 40 and the second electrode layer 34, and can increase the driving current of the memory cell 30 driven by the second conductive structure 40; thus, when the first functional layer 32 is a gating layer and the second functional layer 33 is a resistive switching layer, increasing the contact area between the second conductive structure 40 and the second electrode layer 34 is beneficial to improving the read and write capabilities and the read and write speed of the memory cell 30; when the first functional layer 32 is a resistive switching layer and the second functional layer 33 is a gating layer, increasing the contact area between the second conductive structure 40 and the second electrode layer 34 is beneficial to improving the gating capability and the gating speed of the memory cell 30.

[0056] In some embodiments, reference Figure 1 、 Figure 2 or Figure 3 As shown, the storage unit 30 also includes an isolation layer 60, which is arranged on the side of the first conductive structure 20 away from the substrate 10, and the isolation layer 60 is penetrated by the first hole 101; the storage unit 30 is arranged corresponding to the first hole 101, and a second hole 102 is formed above the first hole 101; wherein the first electrode layer 31 covers the first conductive structure 20 of the bottom wall of the first hole 101, the side wall of the first hole 101 and the part of the top surface of the isolation layer 60 around the first hole 101, and the first functional layer 32, the second functional layer 33, and the second electrode layer 34 cover the first electrode layer 31 in sequence.

[0057] The isolation layer 60 is disposed on a side of the first conductive structure 20 away from the substrate 10 . The isolation layer 60 is used to isolate adjacent electrical devices to prevent current leakage or interference between the devices.

[0058] For example, the material of the isolation layer 60 may include at least one of silicon oxide, silicon nitride, or nitrogen-doped silicon oxide.

[0059] In some embodiments, the memory cells 30 are spaced apart in a direction perpendicular to the substrate 10 , and the memory cells 30 are connected via the second conductive structure 40 .

[0060] In some embodiments, reference Figure 2 or Figure 3 As shown, the memory cell 30 further includes an intermediate layer 35, which is disposed between the first functional layer 32 and the second functional layer 33. Thus, the memory cell 30 includes a first electrode layer 31, a first functional layer 32, an intermediate layer 35, a second functional layer 33, and a second electrode layer 34 stacked in sequence. The intermediate layer 35 prevents the performance of the memory cell 30 from deteriorating due to mutual diffusion of materials between the first electrode layer 31 and the first functional layer 32, thereby improving the reliability and performance stability of the memory cell 30.

[0061] Furthermore, the thermal conductivity of the intermediate layer 35 is lower than that of the resistive switching layer. This prevents heat from the gate layer from transferring to the resistive switching layer, shortening the time it takes for the gate layer to reach its turn-on temperature and reducing the turn-on voltage (Vth) of the memory cell 30. Furthermore, the intermediate layer 35 improves the thermal stability of the gate layer, slowing down the temperature drop of the gate layer and lowering the write and read voltages of the memory cell 30.

[0062] For example, the thermal conductivity of the gate layer is 0.3 W / m·K-1.5 W / m·K; the thermal conductivity of the resistive layer is 2.2 W / m·K-5 W / m·K; and the thermal conductivity of the intermediate layer 3540 is 0.2 W / m·K-2 W / m·K.

[0063] In one example, the thermal conductivity of the gating layer is 0.3 W / m·K, the thermal conductivity of the resistive layer is 2.2 W / m·K, and the thermal conductivity of the intermediate layer 3540 is 0.2 W / m·K; in another example, the thermal conductivity of the gating layer is 1.5 W / m·K, the thermal conductivity of the resistive layer is 5 W / m·K, and the thermal conductivity of the intermediate layer 3540 is 2 W / m·K; in yet another example, the thermal conductivity of the gating layer is 1 W / m·K, the thermal conductivity of the resistive layer is 4 W / m·K, and the thermal conductivity of the intermediate layer 3540 is 3 W / m·K.

[0064] Furthermore, the conductivity of the intermediate layer 35 is in the range of 10 -7 S / m-10 -2S / m. Example, 10 -7 S / m, 10 -6 S / m, 10 -5 S / m, 10 -4 S / m, 10 -3 S / m or 10 -2 Thus, the intermediate layer 35 has good electrical conductivity and certain heat insulation. Thus, the intermediate layer 35 disposed between the gate layer and the resistive switching layer does not affect the conduction between the gate layer and the resistive switching layer, and can also reduce the turn-on voltage of the self-memory unit 30.

[0065] In some embodiments, the material of the intermediate layer 35 includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0066] The intermediate layer 35 may be a single-layer structure or a multi-layer structure. For example, the intermediate layer 35 may include a single-layer amorphous carbon layer; or, for another example, the intermediate layer 35 may include a stacked amorphous carbon layer and an indium gallium zinc oxide layer.

[0067] In some embodiments, the material of the gate layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride.

[0068] The gating layer may be a single-layer structure or a multi-layer structure. For example, the intermediate layer 35 may include a single-layer niobium oxide layer; for another example, the intermediate layer 35 may include a stacked niobium oxide layer and an antimony telluride layer.

[0069] The material of the resistive layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0070] The resistive switching layer may be a single-layer structure or a multi-layer structure. For example, the resistive switching layer may include a single-layer tantalum oxide layer. For another example, the intermediate layer 35 may be a stacked tantalum oxide layer and a titanium oxide layer.

[0071] The semiconductor structure of this embodiment, by reasonably setting the materials of the selection layer and the resistive layer of the storage unit 30, matches the materials of the selection layer and the resistive layer, so that the storage unit 30 has a self-rectifying effect, which can effectively suppress the leakage current generated by the storage unit 30, is conducive to further reducing the size of the storage unit 30, can improve the integration density of the storage unit 30 in the semiconductor structure, and is conducive to expanding the application fields and application scenarios applicable to the storage unit 30.

[0072] The material of the first electrode layer 31 may include at least one of vanadium (V), niobium (Nb), ruthenium (Ru), tungsten (W), tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), aluminum (Al), titanium aluminum tungsten (TiAlW), yttrium (Ir), yttrium oxide (IrO2), indium tin oxide (ITO), titanium aluminum nitride (TiAlN), aluminum nitride (AlNx), titanium aluminum nitride (TiAlN) or (AlTiN), hafnium (Hf), iridium (Ir), manganese (Mn), zinc (Zn), platinum (Pt), palladium (Pd), and copper (Cu). The first electrode layer 31 may have a single-layer structure or a multi-layer structure.

[0073] The selection range of the material of the second electrode layer 34 is the same as that of the first electrode layer 31 , and will not be further described.

[0074] In some embodiments, reference Figure 3 As shown, the memory cell 30 further includes a barrier layer 36, which is disposed between the gate layer and the first electrode layer 31, or between the gate layer and the second electrode layer 34; the electron affinity of the barrier layer 36 is less than that of the gate layer; the material of the barrier layer 36 includes at least one of zinc oxide, nickel oxide, titanium oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, barium titanate, indium oxide, vanadium oxide, strontium titanate, aluminum titanate, manganese oxide, and gallium nitride.

[0075] In some examples, the first functional layer 32 is a gate layer, the second functional layer 33 is a resistive switching layer, and the memory cell 30 includes a first electrode layer 31, a barrier layer 36, a first functional layer 32, an intermediate layer 35, a second functional layer 33, and a second electrode layer 34 stacked in sequence. The barrier layer 36 is used to localize electrons and prevent them from leaking outward, thereby reducing leakage current of the memory cell 30.

[0076] In other examples, the first functional layer 32 is a resistive layer, the second functional layer 33 is a gate layer, and the memory cell 30 includes a first electrode layer 31, a resistive layer, an intermediate layer 35, a gate layer, a barrier layer 36, and a second electrode layer 34 stacked in sequence.

[0077] In some embodiments, the memory cell 30 further includes a buffer layer 37, which is disposed between the gate layer and the barrier layer 36; the electron affinity of the buffer layer 37 is between that of the gate layer and the barrier layer 36; the material of the buffer layer 37 includes at least one of titanium oxide, nickel oxide, zinc oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, indium oxide, vanadium oxide, niobium oxide, manganese oxide, neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide, gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide or magnesium oxide.

[0078] The buffer layer 37 is used to buffer the difference in electron affinity between the gate layer and the barrier layer 36, thereby preventing performance fluctuations in the memory cell 30 caused by a large difference in electron affinity between the gate layer and the barrier layer 36. At the same time, when the memory cell 30 is turned on, the gate layer transitions from a high-resistance state to a low-resistance state, and the voltage drop of the barrier layer 36 increases. By providing the buffer layer 37 between the gate layer and the barrier layer 36, the present application can reduce the voltage drop of the barrier layer 36, preventing the barrier layer 36 from being broken down by the high voltage drop. This further reduces the risk of leakage in the memory cell 30, improves the performance stability and reliability of the memory cell 30, and helps optimize the performance of the device and extend its service life.

[0079] In some embodiments, the first functional layer 32 is a gate layer, and the second functional layer 33 is a resistive switching layer. The difference between the work function of the first electrode layer 31 and the electron affinity of the gate layer is greater than 2 eV; and the difference between the work function of the second electrode layer 34 and the electron affinity of the barrier layer 36 is greater than 2 eV.

[0080] The electron affinity of the gate layer is 2eV to 4.5eV, the electron affinity of the barrier layer 36 is 1eV to 2eV, and the electron affinity of the buffer layer 37 is 1eV to 4.5eV.

[0081] In this way, one surface of the gate layer contacts the first electrode layer 31, forming a potential barrier between the gate layer and the first electrode layer 31; and a potential barrier is formed between the surface of the barrier layer 36 away from the buffer layer 37 and the second electrode layer 34. Electrons can be localized at the potential barrier between the gate layer and the first electrode layer 31, and electrons can be localized at the potential barrier between the barrier layer 36 and the second electrode layer 34, preventing electron leakage and thereby reducing leakage current of the memory cell 30.

[0082] In some embodiments, an intermediate layer 35 is provided between the first functional layer 32 and the second functional layer 33 of the memory cell 30 , and a buffer layer 37 and a barrier layer 36 are sequentially stacked between the gate layer and the connected electrode layer.

[0083] In the semiconductor structure of this embodiment, the memory cell 30 forms a second hole 102 on the first conductive structure 20, thereby increasing the contact area between the second conductive structure 40 and the second electrode layer 34 and improving the read and write capabilities and speed of the memory cell 30. By rationally setting the materials of the selection layer and the resistive layer, the memory cell 30 has a self-rectifying effect, suppresses leakage current, reduces size, and is conducive to improving the integration density of the memory cell 30. Through the design of the barrier layer 36 and the buffer layer 37, the leakage current of the memory cell 30 can be further reduced, thereby improving the performance stability and reliability of the semiconductor structure.

[0084] According to an exemplary embodiment, the present disclosure also provides a method for manufacturing a semiconductor structure, such as Figure 4As shown, the method for manufacturing a semiconductor structure includes the following steps:

[0085] Step S101: providing a substrate, and forming a first conductive structure on the substrate;

[0086] Step S102: forming an isolation layer on a side of the first conductive structure away from the substrate, etching the isolation layer to form a first hole, wherein the first hole exposes a portion of the top surface of the first conductive structure;

[0087] Step S103: forming a first electrode layer, a first functional layer, a second functional layer, and a second electrode layer in sequence to form a memory cell, wherein the memory cell forms a second hole above the first conductive structure, and the opening direction of the second hole faces away from the substrate; one of the first functional layer and the second functional layer is a gate layer, and the other is a resistive switching layer;

[0088] Step S104: forming a second conductive structure on a side of the memory cell away from the substrate, wherein the second conductive structure contacts the second electrode layer on the sidewalls and the bottom wall of the second hole.

[0089] In the method for manufacturing the semiconductor structure of this embodiment, before forming a memory cell, an isolation layer is first formed on the first conductive structure, the isolation layer is etched to form a first hole penetrating the isolation layer, and the memory cell is formed in the first hole so that the memory cell encloses a second hole disposed away from the substrate, and then a second conductive structure is formed to fill the second hole, thereby increasing the contact area between the second conductive structure and the second electrode layer, and can increase the drive current of the memory cell driven by the second conductive structure; in this way, when the first functional layer is a gating layer and the second functional layer is a resistive switching layer, increasing the contact area between the second conductive structure and the second electrode layer is beneficial to improving the read and write capabilities and the read and write speed of the memory cell; when the first functional layer is a resistive switching layer and the second functional layer is a gating layer, increasing the contact area between the second conductive structure and the second electrode layer is beneficial to improving the gating capability and the gating speed of the memory cell.

[0090] In step S101, refer to Figure 5 As shown, substrate 10 may be a semiconductor substrate. Semiconductor substrate materials include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc. Alternatively, in some cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP).

[0091] The substrate 10 includes a storage area A1 and a logic area A2, and both the storage area A1 and the logic area A2 are formed with a first conductive structure 20. The first conductive structure 20 is formed on the substrate 10, and the first conductive structure 20 can be a wire or wiring structure embedded in the first dielectric layer 51. The first conductive structure 20 can be manufactured in the following manner: a first dielectric layer 51 is deposited on the substrate 10, and the material of the first dielectric layer 51 can include at least one of silicon oxide, silicon carbide, silicon oxynitride or silicon nitride. For example, the first dielectric layer 51 can be deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).

[0092] Next, a photoresist layer is formed on the first dielectric layer 51 and subjected to an exposure and development process. The pattern of the first conductive structure 20 is defined in the photoresist layer. The first dielectric layer 51 is then etched based on the patterned photoresist layer to form a through-hole in the first dielectric layer 51, exposing a portion of the top surface of the substrate 10. Subsequently, a conductive material can be deposited using physical vapor deposition (PVD) or CVD to fill the through-hole. The conductive material on the top surface of the first dielectric layer 51 is then etched back to remove it, forming the first conductive structure 20 in the through-hole that is electrically connected to the substrate 10.

[0093] Illustratively, the material of the first conductive structure 20 includes metal (such as copper, aluminum, etc.) or a metal alloy.

[0094] For example, before forming the first conductive structure 20, a barrier layer can be deposited to cover the hole wall of the through hole. The barrier layer is disposed between the metal material such as copper and aluminum and the first dielectric layer 51. The barrier layer is used to support the first conductive structure 20 and isolate the first conductive structure 20 from other film layers to prevent the conductive material from diffusing outward. The barrier layer can be made of titanium, tantalum, etc.

[0095] In this embodiment, the first conductive structure 20 includes a first conductive layer 21, a second conductive layer 22 and a third conductive layer 23 connected in sequence along a direction perpendicular to the substrate 10, wherein the first conductive layer 21, the second conductive layer 22 and the third conductive layer 23 can be wires or pads arranged along a direction from the substrate 10.

[0096] In step S102, refer to Figure 6As shown, the isolation layer 60 can be formed by CVD, PECVD or ALD deposition. The isolation layer 60 covers the top surface of the first conductive layer. The material of the isolation layer 60 can include at least one of silicon oxide, silicon nitride or nitrogen-doped silicon oxide.

[0097] Then, refer to Figure 7 As shown, a photoresist layer is formed on the isolation layer 60, and the pattern of the first hole 101 is defined by exposing and developing the patterned photoresist layer. The isolation layer 60 is etched according to the patterned photoresist layer until the top surface of the first conductive structure 20 is exposed, forming the first hole 101 in the storage area A1.

[0098] For example, the isolation layer 60 may be etched by using a dry process, a wet process, or a combination of dry and wet processes to form the first hole 101 .

[0099] In step S103, refer to Figure 8 As shown, a stack of a first electrode layer 31, a first functional layer 32, a second functional layer 33, and a second electrode layer 34 can be sequentially deposited using PVD or CVD. The first electrode layer 31, the first functional layer 32, the second functional layer 33, and the second electrode layer 34 sequentially cover the hole walls of the first holes 101 and the top surface of the isolation layer 60. The total thickness of the stack is less than the depth of the first holes 101. The stack forms a second hole 102 above each first hole 101. The size of the second hole 102 is smaller than that of the first hole 101.

[0100] Then, a photoresist layer is formed on the top surface of the stack, and the pattern of the memory cell 30 is defined by the patterned photoresist layer. Figure 9 As shown, the stack is etched according to the patterned photoresist layer until the top surface of the isolation layer 60 is reached, and the retained stack is etched to form a storage unit 30. The storage unit 30 includes a first electrode layer 31, a first functional layer 32, a second functional layer 33 and a second electrode layer 34 sequentially stacked in the first hole 101.

[0101] For example, the stack of the first electrode layer 31 , the first functional layer 32 , the second functional layer 33 and the second electrode layer 34 may be etched using a dry process to form the memory cell 30 .

[0102] In some embodiments, reference Figure 9 As shown, after the storage unit 30 is formed, the top surface of the first dielectric layer 51 is used as the etching end point, and the isolation layer 60 is continuously etched according to the patterned photoresist layer to ensure that the adjacent storage units 30 are completely disconnected, avoiding the presence of residual conductive film layers between adjacent storage units 30, and reducing the risk of leakage of the storage units 30, short circuiting of adjacent storage units 30, and crosstalk.

[0103] For example, the isolation layer 60 may be etched using a wet process.

[0104] In step S104, refer to Figure 10 A second dielectric layer 52 may be deposited by ALD, CVD, or PECVD. The second dielectric layer 52 covers the second electrode layer 34 of the memory cell 30 and the top surface of the first dielectric layer 51 between adjacent memory cells 30. The material of the second dielectric layer 52 may include at least one of silicon oxide, silicon carbide, silicon oxynitride, or silicon nitride.

[0105] In this embodiment, the isolation layer 60 between adjacent storage cells 30 is removed by etching, thereby deepening the filling depth between adjacent storage cells 30, which is beneficial to optimizing the filling quality of the second dielectric layer 52, avoiding the formation of filling gaps at the corners of the storage cells 30, and ensuring that the second dielectric layer 52 has a good electrical isolation effect, thereby avoiding leakage of the storage cells 30.

[0106] Then, a photoresist layer is formed on the top surface of the second dielectric layer 52 , and the patterned photoresist layer defines the pattern of the second conductive structure 40 . The second dielectric layer 52 is etched according to the patterned photoresist layer to remove the second dielectric layer 52 in the second hole 102 and form a groove penetrating the second dielectric layer 52 .

[0107] Conductive material is deposited by PVD or CVD to fill the trench of the second dielectric layer 52 and fill the second hole 102, and then CMP is used to remove the conductive material on the top surface of the second dielectric layer 52 to form a second conductive structure 40 connected to the memory cell 30 in the trench.

[0108] For example, refer to Figure 10 The material of the second conductive structure 40 includes metal (such as copper, aluminum, etc.) or metal alloy.

[0109] For example, before forming the second conductive structure 40 , a barrier layer may be deposited to cover the trench to isolate the second conductive structure 40 from other film layers and prevent the conductive material from diffusing outward.

[0110] In this embodiment, referring to Figure 10 The second conductive structure 40 includes a fourth conductive layer 41 and a fifth conductive layer 42 connected in sequence along a direction perpendicular to the substrate 10. The fourth conductive layer 41 and the fifth conductive layer 42 may be wires or pads arranged along a direction extending from the substrate 10. The second conductive structure 40 is formed in both the storage area A1 and the logic area A2, and the logic area A2 is connected to the first conductive structure 20.

[0111] In some embodiments, the material of the gate layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride.

[0112] The gating layer may be a single-layer structure or a multi-layer structure. For example, the intermediate layer 35 may include a single-layer niobium oxide layer; for another example, the intermediate layer 35 may include a stacked niobium oxide layer and an antimony telluride layer.

[0113] The material of the resistive layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

[0114] The resistive switching layer may be a single-layer structure or a multi-layer structure. For example, the resistive switching layer may include a single-layer tantalum oxide layer. For another example, the intermediate layer 35 may be a stacked tantalum oxide layer and a titanium oxide layer.

[0115] After the first functional layer 32 and the second functional layer 33 are formed, an annealing process is performed on both the first functional layer 32 and the second functional layer 33 .

[0116] For the manufacturing process of the memory with 1S1R architecture, after the gate layer and the resistive switching layer are formed, annealing steps need to be performed on the gate layer and the resistive switching layer respectively. For the gate layer, annealing treatment can improve its switching characteristics, such as reducing the switching voltage and increasing the switching speed; for the resistive switching layer, annealing treatment can adjust its resistive switching characteristics, such as changing the resistive switching threshold and improving the resistive switching stability and durability.

[0117] In this embodiment, by rationally designing the materials of the selection layer and the resistive switching layer of the memory cell 30, the first functional layer 32 and the second functional layer 33 of the memory cell 30 can be annealed in the same step, saving one annealing process, thereby simplifying the production process, improving production efficiency and reducing costs.

[0118] In some embodiments, the material of the first electrode layer 31 may include at least one of vanadium, niobium, ruthenium, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, titanium tungsten, aluminum, titanium aluminum tungsten, yttrium, yttrium oxide, indium tin oxide, aluminum titanium nitride, aluminum nitride, aluminum titanium nitride, hafnium, iridium, manganese, zinc, platinum, palladium, and copper. The first electrode layer 31 may have a single-layer structure or a multi-layer structure.

[0119] The selection range of the material of the second electrode layer 34 is the same as that of the first electrode layer 31 , and will not be further described.

[0120] In some embodiments, reference Figure 8 、 Figure 9 , forming a storage unit 30 , further comprising: forming an intermediate layer 35 between the first functional layer 32 and the second functional layer 33 .

[0121] After forming the first functional layer 32 and before forming the second functional layer 33, an intermediate layer 35 may be deposited on a side of the first functional layer 32 away from the substrate 10 using a CVD or ALD process. The intermediate layer 35 is used to prevent the performance degradation of the memory cell 30 caused by the mutual diffusion of materials between the first electrode layer 31 and the first functional layer 32, thereby improving the reliability and performance stability of the memory cell 30.

[0122] In some embodiments, the thermal conductivity of the intermediate layer 35 is lower than that of the resistive switching layer. For example, the thermal conductivity of the gate layer is 0.3W / m·K to 1.5W / m·K; the thermal conductivity of the resistive switching layer is 2.2W / m·K to 5W / m·K; and the thermal conductivity of the intermediate layer 3540 is 0.2W / m·K to 2W / m·K. This prevents heat from the gate layer from transferring to the resistive switching layer, shortening the time it takes for the gate layer to reach the turn-on temperature and lowering the turn-on voltage (Vth) of the memory cell 30. Furthermore, the intermediate layer 35 improves the thermal stability of the gate layer, slowing the temperature drop of the gate layer and reducing the write and read voltages of the memory cell 30.

[0123] In one example, the thermal conductivity of the gate layer is 0.3 W / m·K, the thermal conductivity of the resistive layer is 2.2 W / m·K, and the thermal conductivity of the intermediate layer 3540 is 0.2 W / m·K. In another example, the thermal conductivity of the gate layer is 1.5 W / m·K, the thermal conductivity of the resistive layer is 5 W / m·K, and the thermal conductivity of the intermediate layer 3540 is 2 W / m·K. In yet another example, the thermal conductivity of the gate layer is 1 W / m·K, the thermal conductivity of the resistive layer is 4 W / m·K, and the thermal conductivity of the intermediate layer 3540 is 3 W / m·K.

[0124] Furthermore, the conductivity of the intermediate layer 35 is in the range of 10 -7 S / m-10 -2 S / m. Example, 10 -7 S / m, 10 -6 S / m, 10 -5 S / m, 10 -4 S / m, 10 -3 S / m or 10 -2 Thus, the intermediate layer 35 has good electrical conductivity and certain heat insulation. Thus, the intermediate layer 35 disposed between the gate layer and the resistive switching layer does not affect the conduction between the gate layer and the resistive switching layer, and can also reduce the turn-on voltage of the self-memory unit 30.

[0125] In some embodiments, the material of the intermediate layer 35 includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

[0126] The intermediate layer 35 may be a single-layer structure or a multi-layer structure. For example, the intermediate layer 35 may include a single-layer amorphous carbon layer; or, for another example, the intermediate layer 35 may include a stacked amorphous carbon layer and an indium gallium zinc oxide layer.

[0127] In some embodiments, reference Figure 8 、 Figure 9 , forming a memory cell 30, further comprising: forming a barrier layer 36 between the gate layer and the first electrode layer 31, or forming a barrier layer 36 between the gate layer and the second electrode layer 34; the electron affinity of the barrier layer 36 is lower than the electron affinity of the gate layer. The barrier layer 36 is used to localize electrons and prevent them from leaking outward, thereby reducing leakage current of the memory cell 30.

[0128] Illustratively, the material of the barrier layer 36 includes at least one of zinc oxide, nickel oxide, titanium oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, barium titanate, indium oxide, vanadium oxide, strontium titanate, aluminum titanate, manganese oxide, and gallium nitride.

[0129] In some embodiments, reference Figure 8 、 Figure 9 , forming a memory cell 30 , further comprising: forming a buffer layer 37 between the gate layer and the barrier layer 36 ; the electron affinity of the buffer layer 37 is between that of the gate layer and the barrier layer 36 .

[0130] Illustratively, the material of the buffer layer 37 includes at least one of titanium oxide, nickel oxide, zinc oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, indium oxide, vanadium oxide, niobium oxide, manganese oxide, neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide, gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide, or magnesium oxide.

[0131] The buffer layer 37 is used to buffer the difference in electron affinity between the gate layer and the barrier layer 36, thereby preventing performance fluctuations in the memory cell 30 caused by a large difference in electron affinity between the gate layer and the barrier layer 36. At the same time, when the memory cell 30 is turned on, the gate layer transitions from a high-resistance state to a low-resistance state, and the voltage drop of the barrier layer 36 increases. By providing the buffer layer 37 between the gate layer and the barrier layer 36, the present application can reduce the voltage drop of the barrier layer 36, preventing the barrier layer 36 from being broken down by the high voltage drop. This further reduces the risk of leakage in the memory cell 30, improves the performance stability and reliability of the memory cell 30, and helps optimize the performance of the device and extend its service life.

[0132] Taking the first functional layer 32 as a gate layer and the second functional layer 33 as a resistive switching layer as an example, the difference between the work function of the first electrode layer 31 and the electron affinity of the gate layer is greater than 2eV; the difference between the work function of the second electrode layer 34 and the electron affinity of the barrier layer 36 is greater than 2eV.

[0133] The electron affinity of the gate layer is 2eV to 4.5eV, the electron affinity of the barrier layer 36 is 1eV to 2eV, and the electron affinity of the buffer layer 37 is 1eV to 4.5eV.

[0134] In this way, one surface of the gate layer contacts the first electrode layer 31, forming a potential barrier between the gate layer and the first electrode layer 31; and a potential barrier is formed between the surface of the barrier layer 36 away from the buffer layer 37 and the second electrode layer 34. Electrons can be localized at the potential barrier between the gate layer and the first electrode layer 31, and electrons can be localized at the potential barrier between the barrier layer 36 and the second electrode layer 34, preventing electron leakage and thereby reducing leakage current of the memory cell 30.

[0135] In some embodiments, an intermediate layer 35 is formed between the first functional layer 32 and the second functional layer 33 of the memory cell 30 , and a buffer layer 37 and a barrier layer 36 are sequentially formed between the gate layer and the connected electrode layer.

[0136] The semiconductor structure and manufacturing method of the present application, by enclosing the second hole 102 set away from the substrate 10 by the storage unit 30, thereby increasing the contact area between the second conductive structure 40 and the second electrode layer 34, the driving current, read and write capabilities and gating capabilities of the storage unit 30 are significantly improved, and the integration density of the storage unit 30 of the 1S1R architecture can be improved. It has broad application prospects in the field of high-performance memory, especially in situations where high density, low power consumption and fast read and write capabilities are required, and can meet the continuous advancement of memory technology and the continued growth of demand.

[0137] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0138] The above-described embodiments merely represent several implementation methods of the present disclosure. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present disclosure, all of which fall within the scope of protection of the present disclosure. Therefore, the scope of protection of the patent disclosed herein shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: substrate; A first conductive structure is provided on the substrate; a memory cell disposed on a side of the first conductive structure away from the substrate, the memory cell comprising a first electrode layer, a first functional layer, a second functional layer, and a second electrode layer stacked in sequence in a direction away from the substrate; the memory cell forming a second hole above the first conductive structure, the opening direction of the second hole facing away from the substrate; one of the first functional layer and the second functional layer being a gating layer, and the other being a resistive switching layer; a second conductive structure, disposed on a side of the memory cell away from the substrate, the second conductive structure being in contact with the second electrode layer on the sidewalls and bottom wall of the second hole; The memory cell further includes a barrier layer, which is arranged between the gating layer and the first electrode layer, or between the gating layer and the second electrode layer; the electron affinity of the barrier layer is smaller than the electron affinity of the gating layer.

2. The semiconductor structure according to claim 1, wherein: Also includes: an isolation layer, provided on a side of the first conductive structure away from the substrate, the isolation layer being penetrated by a first hole; The storage unit is arranged corresponding to the first hole, and the second hole is surrounded above the first hole; wherein, the first electrode layer covers the first conductive structure of the bottom wall of the first hole, the side wall of the first hole and a portion of the top surface of the isolation layer around the first hole, and the first functional layer, the second functional layer and the second electrode layer sequentially cover the first electrode layer.

3. The semiconductor structure according to claim 1, wherein: The memory cell further includes an intermediate layer disposed between the first functional layer and the second functional layer; The material of the intermediate layer includes at least one of amorphous carbon, silicon carbide, tellurium carbide, tellurium carbon sulfide, molybdenum sulfide, tungsten sulfide, molybdenum telluride, indium gallium zinc oxide, indium aluminum zinc oxide, tin-doped indium oxide, manganese telluride, tungsten telluride, and zinc-doped indium oxide.

4. The semiconductor structure according to claim 1, wherein: The material of the gate layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride; The material of the resistive layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide.

5. The semiconductor structure according to claim 4, wherein: The material of the barrier layer includes at least one of zinc oxide, nickel oxide, titanium oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, barium titanate, indium oxide, vanadium oxide, strontium titanate, aluminum titanate, manganese oxide, and gallium nitride.

6. The semiconductor structure according to claim 5, wherein: The memory cell further includes a buffer layer, wherein the buffer layer is disposed between the gate layer and the barrier layer; The electron affinity of the buffer layer is between that of the gating layer and the barrier layer; the material of the buffer layer includes at least one of titanium oxide, nickel oxide, zinc oxide, chromium oxide, molybdenum oxide, tungsten oxide, bismuth oxide, antimony oxide, indium oxide, vanadium oxide, niobium oxide, manganese oxide, neodymium oxide, strontium oxide, germanium oxide, lanthanum oxide, hafnium oxide, gallium oxide, aluminum oxide, zirconium oxide, silicon oxide, ytterbium oxide or magnesium oxide.

7. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: providing a substrate, and forming a first conductive structure on the substrate; forming an isolation layer on a side of the first conductive structure away from the substrate, and etching the isolation layer to form a first hole, wherein the first hole exposes a portion of the top surface of the first conductive structure; A first electrode layer, a first functional layer, a second functional layer, and a second electrode layer are sequentially formed to form a memory cell, wherein the memory cell forms a second hole above the first conductive structure, and the opening direction of the second hole is away from the substrate; one of the first functional layer and the second functional layer is a gating layer, and the other is a resistive switching layer; forming a second conductive structure on a side of the memory cell away from the substrate, wherein the second conductive structure contacts the second electrode layer on the sidewall and bottom wall of the second hole; Forming a memory cell further includes: forming a barrier layer between the gate layer and the first electrode layer, or forming a barrier layer between the gate layer and the second electrode layer; The electron affinity of the barrier layer is lower than the electron affinity of the gate layer.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: The material of the gate layer includes at least one of niobium oxide, vanadium oxide, iron oxide, neodymium nickel oxide, samarium nickel oxide, lanthanum cobalt oxide, gadolinium cobalt oxide, germanium telluride, aluminum telluride, boron telluride, germanium selenide, germanium sulfide, and antimony telluride; The material of the resistive layer includes at least one of tantalum oxide, titanium oxide, hafnium oxide, zirconium oxide, silicon oxide, magnesium oxide, aluminum nitride, germanium antimony telluride, scandium antimony telluride, indium silver antimony telluride, germanium antimonide, germanium telluride, antimony telluride, copper sulfide, germanium sulfide, germanium selenide, zinc sulfide, aluminum borate, strontium titanate, zirconium titanate, barium titanate, hafnium zirconium oxide, and hafnium aluminum oxide; After forming the first functional layer and the second functional layer, an annealing process is performed on the first functional layer and the second functional layer together.

9. The method for manufacturing a semiconductor structure according to claim 7, wherein: The method further comprises forming an intermediate layer between the first functional layer and the second functional layer.

10. The method for manufacturing a semiconductor structure according to claim 7, wherein: The memory cell is formed, further comprising: forming a buffer layer between the gate layer and the barrier layer; the electron affinity of the buffer layer is between that of the gate layer and the barrier layer.

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