A chip-type surface mount diode assembly

Abstract

The present invention discloses a chip type surface adhesive diode assembly, each assembly at least comprising: a positive electrode as one of the assembly external electrodes; a negative electrode as another external electrode of the assembly; a back groove / point group and / or horizontal through channel capable of increasing the negative electrode area of the assembly, thinning effect and increasing adhesive effect; a metal layer conducive to the external connection of the assembly and increasing the characteristic transmission function of the assembly; and an insulating material capable of buffering impact and protecting the assembly. When the positive and negative electrodes of the assembly are constructed side by side, a group of grooves / points and / or horizontal through channels are made on the back surface, and then surface metallization and appropriate insulation protection are performed, the electrical properties of the assembly will be optimized, the insulation adhesive effect will be better, and the assembly can be directly used as a complete assembly.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technology field, and particularly relates to a chip type surface mount diode assembly. The technical key point of manufacturing the assembly is to effectively expand the back surface area of the assembly wafer in the process design, and to make the chip achieve the similar thinning and adhesion effect, so as to improve the electrical characteristics and the protection effect of the assembly, and to complete the manufacturing of the assembly in the chip. BACKGROUND

[0002] In the diode manufacturing packaging process, the wafer manufacturing is carried out in the chip factory, and then the wafer is transferred to the packaging factory to complete the packaging of the assembly. At present, in addition to a small number of axial production packaging, most of the surface mount packaging is adopted. The packaging method is to weld an additional metal lead plate on each surface of the wafer. The metal lead plate used is mainly composed of two pieces of upper and lower material. The positive and negative electrodes of the wafer are designed on the front and back surfaces respectively. This kind of wafer must be tested after subsequent packaging. The size of the packaged assembly is usually several times larger than that of the wafer.

[0003] Nowadays, in order to protect the earth and improve the environment, countries around the world are actively promoting ESG in various fields. Under the trend and requirement of energy saving and carbon reduction, the industry will focus on reducing the use of raw materials. The miniaturization of various assemblies will be an important direction for future research and development. How to effectively integrate the manufacturing and packaging of traditional diodes in the chip is a big challenge. The present application designs the above-mentioned target elements in the packaging of the surface mount diode assembly, so that the size of the assembly can be reduced while maintaining its stable characteristics and optimizing the electricity under the effective necessary protection. This is the key point of the present application. SUMMARY

[0004] As we all know, the wafer used to manufacture the diode assembly is designed with the positive and negative electrodes arranged on the front and back surfaces respectively. At least two kinds of upper and lower materials must be used to weld the wafer. In view of this problem, the present application mainly arranges the positive and negative electrodes of the wafer in parallel, so that the wafer can be packaged without the upper and lower materials after the necessary insulation protection, or only a single material type of lead plate / lead can be used to form a complete assembly. In addition, the back surface of the traditional wafer maintains its flatness. In the present application, appropriate grooves / point groups and or horizontal through channels are added to the back surface of each wafer to increase the area of the back surface, achieve the thinning effect, optimize the negative electrode characteristics, and strengthen the adhesion in the subsequent processing. In addition, the negative electrode is generally manufactured by related diffusion process. The present application also provides another method for manufacturing the negative electrode without diffusion process: the use of L-shaped through channel or semi-L-shaped through channel manufacturing.

[0005] The present invention is a chip type surface adhering diode assembly, each assembly at least comprising: K positive electrodes: K is the number of positive electrodes of the assembly, the mesa is the external positive electrode of the assembly, K≥1; M negative electrodes: M is the number of negative electrodes of the assembly, the mesa is the external negative electrode of the assembly, and each positive electrode is constructed in parallel, M≥0; a back groove / pit group and / or a transverse conducting channel: the production of the groove / pit and / or the transverse conducting channel can achieve the effect of thinning and increasing the surface area of the chip, and can enhance the firmness during subsequent insulation material coating; a metal layer: a metal layer is made on the positive and negative electrode surfaces of the assembly and the back of the assembly, which is beneficial for subsequent application of lead and gain of electrical properties; an insulation material protective layer: the back of the assembly, and / or the positive surface that may collide is covered with insulation material to protect the integrity of the assembly.

[0006] The positive electrodes of the above-mentioned assembly all contain the production of a protection ring or an insulating ring groove, and the negative electrodes are determined whether to produce a protection ring or an insulating ring groove according to their construction method.

[0007] The above-mentioned assembly is completed in the chip state, and after the assembly is completed, each component in the chip is cut along the designed cutting path to separate it into a single component for use.

[0008] The assembly after cutting can be covered with the required insulation layer according to the needs.

[0009] When K>M≥1, it means that the assembly contains K unidirectional functional components, and at least two unidirectional components share a common negative electrode, and the positive electrode and the common negative electrode are constructed in parallel.

[0010] When K=2, M=0, the assembly is a bidirectional electrical functional component.

[0011] When K≥1, M=0, after the metal layer on the surface of the assembly is completed, no insulation material coating process is performed, and the back surface is changed to the negative electrode of the assembly, so the assembly can be used as K unidirectional functional dies.

[0012] The negative electrode and the positive electrode are constructed in parallel on the assembly, in addition to the diffusion method, L-shaped conducting channels or semi-L-shaped conducting channels can also be used; as follows:

[0013] Production of L-shaped conducting channel: whether the assembly uses a die to complete the positive electrode after production, or uses a silicon wafer to complete the diffusion of the front and back surfaces, whether the negative electrode on the front surface is related to the diffusion or not, an L-shaped conducting channel can be produced from the back surface of the assembly, extending from the back surface of the positive electrode to the back surface of the negative electrode and reaching the predetermined negative electrode surface, and after surface metallization, a new negative electrode is made by filling conductive material at the original predetermined negative electrode position on the front surface, achieving the parallel construction of the positive and negative electrodes of the assembly, and achieving the goal of thinning and optimizing the electrical properties.

[0014] The production of half L-shaped conducting channel: whether the positive electrode is produced using epitaxial wafer after the production of the positive electrode or using silicon wafer after the diffusion of the positive and negative surfaces, the original negative electrode on the positive surface can be used to produce an upper conducting channel from the appropriate position on the original negative electrode surface to the lower surface, which is deeper than the thickness of the epitaxial layer of the epitaxial wafer or exceeds the depth of the PN junction of the silicon wafer. The two upper and lower non-actual conducting channels are collectively referred to as half L-shaped conducting channels, and the electrical properties of the components produced by this process are similar to those of L-shaped conducting channels.

[0015] When the negative electrode of the component or wafer is produced using L-shaped conducting channels or half L-shaped conducting channels, the outer protective ring or insulating ring trench of the negative electrode can be omitted.

[0016] If the above-mentioned recesses / point groups, transverse conducting channels, etc. on the back surface of the component are applied to the positive electrode of the component, the basic electrical properties of the component can also be adjusted.

[0017] In order to facilitate the subsequent testing and packaging needs of the user end, the positive and negative electrode surfaces of the above-mentioned component can be pre-coated with solder material or a single sheet of soldered connecting electrode plate / lead, and the insulation protection of the surrounding and / or each surface except the connecting electrode plate / lead of the component is strengthened. Because the packaging only soldered the connecting electrode plate / lead on the electrode surface of the positive surface of the component, the thinnest and shortest diode component with connecting electrode plate / lead in the same electrical specification can be produced.

[0018] The implementation of the present application can produce the following benefits:

[0019] 1. The packaging volume of the same functional component is reduced.

[0020] 2. The adhesion of the insulation protection layer can be improved.

[0021] 3. The electrical properties of the component can be improved.

[0022] 4. More diverse and smaller components can be produced.

[0023] 5. Reduce the use of related raw materials, in line with the energy-saving and carbon-reducing goals of ESG. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained from the structures shown in these drawings without creative labor for those skilled in the art.

[0025] Figure 1 is a configuration design schematic diagram of a single unidirectional component built on a chip;

[0026] Figure 2 is a schematic diagram of a configuration design of a two unidirectional components common negative electrode built on a chip;

[0027] Figure 3 is a schematic diagram of a configuration design of a six unidirectional components common negative electrode built on a chip;

[0028] Figure 4 is a schematic diagram of a configuration design of a single bidirectional component built on a chip;

[0029] Figure 5 is a schematic diagram of a cross section of a back surface of a Schottky component built by a epitaxial chip, with a groove / point group and covered by an insulating material;

[0030] Figure 6 is a schematic diagram of a cross section of a back surface of a Schottky component built by a epitaxial chip, with a groove / point group and covered by an insulating material on the front and back surfaces;

[0031] Figure 7 is a schematic diagram of a cross section of a back surface of a Schottky component built by a epitaxial chip, with a groove / point group, a lateral conducting channel and covered by an insulating material;

[0032] Figure 8 is a schematic diagram of a cross section of a back surface of a Schottky component built by a epitaxial chip, with a groove / point group and a conducting channel of a depth equivalent to the groove / point;

[0033] Figure 9 is a schematic diagram of a cross section of a new negative electrode built by a epitaxial chip, with a L-shaped conducting channel for a Schottky component;

[0034] Figure 10 is a schematic diagram of a cross section of a back surface of a bidirectional TVS component built by a epitaxial chip, with a groove / point group and covered by an insulating material;

[0035] Figure 11 is a schematic diagram of a cross section of a back surface of a bidirectional TVS component built by a epitaxial chip, with a groove / point group;

[0036] Figure 12 is a schematic diagram of a cross section of a bidirectional TVS component built by a epitaxial chip, without a groove / point group on the back surface;

[0037] Figure 13 is a schematic diagram of a cross section of a unidirectional diode component built by a silicon chip, with a groove / point group and a L-shaped conducting channel on the back surface;

[0038] Figure 14 is a schematic diagram of a cross section of a unidirectional diode component built by a silicon chip, with a groove / point group and a half L-shaped conducting channel on the back surface, and covered by an insulating material on the front and back surfaces except for the positive and negative electrodes;

[0039] Figure 15This is a cross-sectional diagram of an epitaxial chip used to create a unidirectional diode assembly by fabricating a back groove / dot group and an L-shaped conductive channel, with only the back side covered with an insulating material.

[0040] Figure 16 This is a cross-sectional schematic diagram showing the grooves / dots on the back of a bidirectional TVS module made of silicon chips and covered with insulating material.

[0041] Figure 17 This is a cross-sectional schematic diagram of a bidirectional TVS die fabricated on a silicon chip, showing grooves / dots on the back side without being covered with insulating material.

[0042] Figure 18 This is a cross-sectional schematic diagram of a silicon chip fabricated with a lateral conductive channel on the back side of a bidirectional TVS die, without being covered by an insulating material.

[0043] Figure 19 This is a cross-sectional diagram of a silicon chip manufacturing unidirectional TVS die system, which features grooves / dot groups on the back side and constructs a half-L-shaped conductive channel, with a conductive electrode plate / pin soldered to each of the positive and negative electrodes.

[0044] Figure 20 This is a cross-sectional diagram showing the construction of a groove / dot group and a half-L-shaped conductive channel on the back side and negative electrode surface during the fabrication of a unidirectional functional die for a silicon chip, and the fabrication of a transverse conductive channel on the positive electrode.

[0045] Figure 21 This is a cross-sectional schematic diagram showing the fabrication of a transverse conductive channel on both the two positive electrodes and the back side during the fabrication of a bidirectional functional die for a silicon chip.

[0046] Figure 22 This is a cross-sectional diagram showing a transverse conductive channel created on the positive electrode surface and a groove / dot group created on the back side during the fabrication of a unidirectional die for a silicon chip.

[0047] Explanation of icon numbers:

[0048] 10: Chip;

[0049] 10a: Epitaxial layer;

[0050] 10b: substrate;

[0051] 11: Positive electrode;

[0052] 11a: Positive electrode region;

[0053] 12: Negative electrode;

[0054] 12a: Negative electrode region;

[0055] 13: Protective ring;

[0056] 14: P+ diffusion layer;

[0057] 15: N+ diffusion layer;

[0058] 16: SKY barrier layer;

[0059] 16a: PN junction;

[0060] 17: Insulating ring trench;

[0061] 18: Groove / point group;

[0062] 19: L-shaped conducting channel;

[0063] 20: Upper conducting channel;

[0064] 21, 21a: Lateral conducting channel;

[0065] 22: Semi-L-shaped conducting channel;

[0066] 23: Conductive substance;

[0067] 24: Metal layer;

[0068] 25: Insulating substance;

[0069] 26: Oxide layer;

[0070] 27: Dicing lane;

[0071] 28: Common negative electrode;

[0072] 29: Solder material;

[0073] 30, 30a: Conducting electrode plate / lead;

[0074] 50: Crystal grain;

[0075] 60: Assembly.

[0076] The implementation, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0077] The chip-type surface-adhesion diode assembly of the present application has a wide range of practical applications, which cannot be listed in detail. The following examples are mainly partial example descriptions of the content of the assembly made by referring to the single-layer epitaxial chip and silicon chip according to the present application:

[0078] Example 1: Epitaxial chip for making Schottky chip-type surface-adhesion diode assembly:

[0079] As Figures 1-3As shown, the positive and negative electrodes are constructed on the same epitaxial layer 10a surface of the chip 10: the epitaxial layer 10a surface is divided into a plurality of parallel positive electrode regions 11a and negative electrode regions 12a, and the positive electrodes 11 and negative electrodes 12 of each component 60 are constructed within the positive electrode regions 11a and negative electrode regions 12a. The number of positive electrodes 11 and negative electrodes 12 of each component 60 can be designed according to the functional requirements of each component. Let K be the number of positive electrodes 11 of each component 60, and M be the number of negative electrodes 12 of each component 60, K≥M≥1. A cutting path 27 is provided around each component 60 as needed. Figure 1 An example of K=1, M=1 positive electrode 11 and negative electrode 12 configuration. Figure 2 An example of K=2, M=1 positive electrode 11 and common negative electrode 28 configuration. Figure 3 An example of K=6, M=1 positive electrode 11 and common negative electrode 28 configuration.

[0080] Figures 5-8 An example of K=1, M=1 configuration of the chip 10 after cutting the component 60 after the component 60 manufacturing process is complete. Wherein Figure 5 Figure 6 For the parallel design of positive electrodes 11 and negative electrodes 12 (including protection ring 13 or insulating ring trench 17, oxide layer 26, subsequent examples will not be repeated), a groove / pit group 18 is made on the back surface substrate 10b, and the positive electrode 11 and negative electrode 12 surfaces and the back surface are metallized to produce a metal layer 24, and then Figure 5 only the back surface of the component 60 is covered with insulating material 25 for protection; while in Figure 6 the positive electrode 11 and negative electrode 12 surfaces are covered with insulating material 25 for double-sided protection. Figure 7 In addition to making a groove / pit group 18 on the back surface, the groove / pit group 18 is connected by a horizontal passage 21, and conductive material 23 is filled in the horizontal passage 21. Figure 8 An example of constructing a horizontal passage 21 on the back surface, the depth of which is comparable to the groove / pit group 18, and which is not filled with conductive material.

[0081] Example 2: Schottky chip type surface mount diode component made of epitaxial chip plus L-shaped conduction channel

[0082] As shown in Figure 9 K=1, M=1, after the positive electrode 11 surface of each component 60 is completed with electrical manufacturing (the negative electrode 12 surface is omitted from the related diffusion operation of manufacturing the negative electrode 12), a groove / pit group 18 and an L-shaped conduction channel 19 are made from the back surface of the component 60 to the negative electrode 12 surface on the original front surface, and then conductive material 23 is filled in the groove / pit group 18 and the L-shaped conduction channel 19 on the back surface after surface metallization to produce a metal layer 24, and then the back surface is covered with insulating material 25.

[0083] Example 3: Fabricating bidirectional TVS chip type surface mount diode assembly with epitaxial wafer

[0084] Figure 4 The configuration of chip 10 surface assembly 60, where K=2, M=0. Figure 10 The configuration of chip 10 surface assembly 60, where K=2, M=0.

[0085] The configuration of chip 10 surface assembly 60, where K=2, M=0. Figure 11 The configuration of chip 10 surface assembly 60, where K=2, M=0. Figure 12 The configuration of chip 10 surface assembly 60, where K=2, M=0.

[0086] Example 4: Fabricating unidirectional function STD, FR, TVS, etc. assembly with silicon wafer

[0087] The configuration of chip 10 surface assembly 60, where K=2, M=0. Figure 13 The configuration of chip 10 surface assembly 60, where K=2, M=0. Figure 14 The configuration of chip 10 surface assembly 60, where K=2, M=0. Figure 15 The configuration of chip 10 surface assembly 60, where K=2, M=0.

[0088] Example 5: Fabricating bidirectional function TVS, etc. assembly with silicon wafer

[0089] As Figure 16 shown in the structure cross-section of the TVS component 60 with K=2, M=0, the component 60 is configured with two positive electrode 11 faces on the front surface, and a PN junction 16a is formed by electrically diffusing the front and back surfaces of the component 60 in both directions; an insulating ring groove 17 is formed on the outside of the two positive electrode 11 faces for protection, and a groove / pit group 18 is formed on the back surface of the component; after a metal layer 24 is formed on the two positive electrode 11 faces on the front surface and the back surface of the component 60, and an insulating material 25 is coated on the areas outside the two external electrode faces for insulation and protection, the production of the bidirectional TVS component 60 is completed.

[0090] If the previous insulation protection operation is omitted, each component 60 can be used as a bidirectional TVS die 50 after cutting, as Figure 17 shown in the die 50 with a groove / pit group 18 formed on the back surface; Figure 18 shown in the bidirectional die 50 with a horizontal through channel 21 formed on the back surface and filled with conductive material 23; Figure 17 , Figure 18 Both examples can also be used as double unidirectional dies 50.

[0091] Example six, welding a lead plate / lead on the external electrode face of each component:

[0092] As Figure 19 shown, K=1, M=1, after the diffusion operation is completed, the component 60 is configured with an insulating ring groove 17 around the positive electrode 11 and the negative electrode 12, and a groove / pit group 18 and a half L-shaped through channel 22 are formed, the positive electrode 11 and the negative electrode 12 of the component 60 are constructed on the front surface of the component 60, and a single sheet type welding lead plate / lead 30, 30a is added on the positive electrode 11 and the negative electrode 12 plate of the component 60, and the upper and lower surfaces of the component 60 except for the lead plates / leads 30, 30a are coated with an appropriate amount of insulating material 25 to strengthen the protection of the component 60.

[0093] Example seven, diagram examples of horizontal through channels, upper through channels, groove / pit groups, and / or horizontal through channels formed on the positive and negative electrode faces and the back surface of the component:

[0094] As Figures 20-22 shown, K and M are respectively: Figure 20 .K=1, M=1; Figure 21 .K=2, M=0; Figure 22K=1, M=0; this three-diagram example aims to show the partial application of the horizontal conducting channel 20 / 21a, the upper conducting channel 20 and the groove / point group 18 in the manufacture of the component 60 or the die 50; and in this three-diagram, only the position of the groove / point 18, the upper conducting channel 20 and the horizontal conducting channel 21 / 21a in the component 60 or the die 50 is symbolically indicated; the symbolic indication of other structural parts has been described in the above examples, and this example will not be indicated and described again.

[0095] The above description is only the preferred embodiment of the present application, and does not limit the patent scope of the present application, and any equivalent structural transformation made under the concept of the present application, using the content of the present application specification and drawings, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A chip-type surface-mount diode assembly, characterized in that, Each component at least contains: K positive electrodes: K is the number of positive electrodes of the component, whose mesa is the external positive electrode of the component, K≧1; M negative electrodes: M is the number of negative electrodes of the component, whose mesa is the external negative electrode of the component, and is constructed in parallel with the positive electrode, M≧0; a back groove / pit group and / or a horizontal through channel; a metal layer: located on the surface of the positive and negative electrodes and the back of the component; an insulating material protective layer: on the back of the component, or the front surface; Wherein, K>M≧1, indicates that the component contains K unidirectional functional components, and at least two unidirectional components share a common negative electrode, and the positive electrode and the common negative electrode are constructed in parallel; Wherein the original negative electrode of the component is made into a horizontal through channel from the back of the component, and a half upper through channel with a depth greater than the epitaxial layer thickness of the epitaxial chip or exceeding the PN junction depth of the silicon chip is made from the appropriate position of the original negative electrode on the front surface; and a horizontal through channel is made from the back of the component, combined with a half L-shaped through channel, to make a new negative electrode.

2. The chip surface mount diode assembly of claim 1, wherein, Wherein the original negative electrode of the component is made into a L-shaped through channel from the back of the component, extending from the back of the positive electrode to the back of the negative electrode, and then to the surface of the original negative electrode on the front surface to make a new negative electrode.

3. The chip surface mount diode assembly of claim 1 wherein, Wherein the groove / pit group and the horizontal through channel are applied to the positive electrode on the front surface of the component.

4. The chip surface mount diode assembly of claim 1 wherein, Wherein the positive and negative electrode surfaces of the component are pre-welded with welding materials or single sheet type welding electrode plates / leads, and the insulation protection of the surrounding and / or each surface except the electrode plates / leads is strengthened.

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