Display panel and display device

Abstract

The invention discloses a display panel and a display device. The pixel driving circuit in the display panel comprises a first driving transistor, and the first driving transistor comprises a first electrode and a second electrode; the first electrode comprises a first branch part extending along a first direction, the second electrode comprises a second branch part extending along a second direction, the first branch part comprises a first section and a second section which are arranged along the first direction, the vertical projection of the second section on the substrate is overlapped with the vertical projection of the second branch part on the substrate, and the first section and the second section are arranged along the first direction. The area of the second segment per unit length is smaller than the area of the first segment per unit length. According to the display panel and the display device provided by the embodiment of the invention, the overlapping area between the first branch part of the first electrode and the second branch part of the second electrode is reduced, so that the parasitic capacitance formed between the first electrode and the second electrode of the first driving transistor is reduced, and the driving capability of the pixel driving circuit is further improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] Light Emitting Diode (LED) display panels are widely used in various display devices due to their advantages such as high brightness, good luminous efficiency and low power consumption.

[0003] In a display panel, since the pixel driving circuit includes a large number of transistors and the circuit structure is relatively complex, under the requirements of high-resolution display, the transistors and the corresponding connected signal lines and other wiring need to be arranged in a limited space, resulting in dense distribution of transistors and wiring. This will increase the mutual interference between the various signal nodes, and thus affect the driving capability of the pixel driving circuit. Summary of the invention

[0004] The present invention provides a display panel and a display device to solve the problem of mutual interference between signals of various nodes in a pixel driving circuit and improve the driving capability of the pixel driving circuit.

[0005] According to one aspect of the present invention, there is provided a display panel, comprising a base substrate and a pixel driving circuit located on one side of the base substrate;

[0006] The pixel driving circuit includes a first driving transistor;

[0007] The first driving transistor includes a first electrode and a second electrode;

[0008] The first electrode includes a first subsection extending along a first direction;

[0009] The second electrode includes a second portion extending along a second direction;

[0010] The first direction and the second direction intersect;

[0011] The first sub-portion includes a first segment and a second segment arranged along the first direction, and a vertical projection of the second segment on the substrate overlaps with a vertical projection of the second sub-portion on the substrate;

[0012] Along the first direction, an area per unit length of the second segment is smaller than an area per unit length of the first segment.

[0013] According to another aspect of the present invention, a display device is provided, comprising the display panel according to the first aspect.

[0014] The display panel and the display device provided by the embodiments of the present invention include a first driving transistor in the pixel driving circuit, the first electrode of the first driving transistor includes a first section extending along a first direction, the second electrode of the first driving transistor includes a second section extending along a second direction, and the first direction and the second direction intersect, the first section includes a first segment and a second segment arranged along the first direction, and the vertical projection of the second segment on the substrate overlaps with the vertical projection of the second segment on the substrate, and along the first direction, the area of ​​the second segment per unit length is set to be smaller than the area of ​​the first segment per unit length, so that the first segment and the second segment are within the same length in the first direction. The area of ​​the overlapping portion is smaller than the area of ​​the non-overlapping portion between the first section and the second section, so as to reduce the area per unit length of the second section in the first direction, thereby reducing the overlapping area between the first section of the first electrode and the second section of the second electrode in a direction perpendicular to the plane of the substrate, thereby reducing the parasitic capacitance formed between the first electrode and the second electrode of the first driving transistor, and reducing unnecessary coupling power consumption; at the same time, it can also reduce the mutual interference of the voltage between the first electrode and the second electrode, thereby helping to achieve precise control of the working state of the first driving transistor, reducing the control difficulty of the pixel driving circuit, and thus helping to improve the driving capability of the pixel driving circuit.

[0015] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0018] Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the A-A' direction;

[0019] Figure 3 A schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0020] Figure 4 for Figure 3 A schematic diagram of a film layer structure of a pixel driving circuit shown;

[0021] Figure 5 for Figure 4 A schematic diagram of the enlarged structure at B;

[0022] Figure 6 for Figure 4 A schematic diagram of the enlarged structure at C;

[0023] Figure 7 for Figure 3 Another schematic diagram of a film layer structure of a pixel driving circuit shown;

[0024] Figure 8 for Figure 7 A schematic diagram of the enlarged structure at D;

[0025] Fig. 9 for Figure 7 A schematic diagram of the enlarged structure at E;

[0026] Fig.10 A schematic diagram of the structure of a first subdivision and a second subdivision provided in an embodiment of the present invention;

[0027] Fig.11 A schematic diagram of the structure of another first subdivision and a second subdivision provided in an embodiment of the present invention;

[0028] Fig.12 A schematic diagram of the structure of another first subdivision and a second subdivision provided in an embodiment of the present invention;

[0029] Fig.13 A schematic diagram of the structure of another first subdivision and a second subdivision provided in an embodiment of the present invention;

[0030] Fig.14 A schematic structural diagram of another pixel driving circuit provided by an embodiment of the present invention;

[0031] Fig.15 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention;

[0032] Fig.16 for Fig.15 A schematic structural diagram of a first metal layer in a display panel shown;

[0033] Fig.17 for Fig.15 A schematic structural diagram of a semiconductor layer in a display panel shown;

[0034] Fig.18 for Fig.15 A schematic structural diagram of a second metal layer in a display panel shown;

[0035] Fig.19 for Fig.15A schematic structural diagram of a third metal layer in a display panel shown;

[0036] Fig. 20 for Fig.15 A schematic structural diagram of a fourth metal layer in a display panel shown;

[0037] Fig.21 for Fig.15 A schematic diagram of a stacked structure of all film layers in a display panel shown, specifically a schematic diagram of a stacked structure from a first semiconductor layer to an anode layer;

[0038] Fig. 22 for Fig.21 A schematic diagram of the enlarged structure at F;

[0039] Fig.23 for Fig.21 Schematic diagram of the enlarged structure at G;

[0040] Fig.24 A schematic diagram of the structure of a third sub-section and a first connecting sub-section provided in an embodiment of the present invention;

[0041] Fig.25 for Fig.15 A schematic structural diagram of another first metal layer in the display panel shown;

[0042] Fig.26 for Fig.15 A schematic diagram of the structure of another semiconductor layer in the display panel shown;

[0043] Fig. 27 for Fig.15 A schematic structural diagram of another second metal layer in the display panel shown;

[0044] Fig.28 for Fig.15 A schematic diagram of the structure of another third metal layer in the display panel shown;

[0045] Fig.29 for Fig.15 A schematic diagram of the structure of another fourth metal layer in the display panel shown;

[0046] Fig.30 for Fig.15 Another schematic diagram of the stacked structure of all film layers in the display panel shown;

[0047] Fig.31 A schematic structural diagram of a gate and a second connection portion of a pulse width driving transistor provided in an embodiment of the present invention;

[0048] Fig.32 A schematic diagram of the structure of a display device provided by an embodiment of the present invention;

[0049] Fig.33 A schematic structural diagram of another display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0050] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0051] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0052] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention, Figure 2 for Figure 1 Schematic diagram of the cross-sectional structure along the A-A' direction, Figure 3 A schematic diagram of a pixel driving circuit provided by an embodiment of the present invention is shown in FIG. Figure 1-Figure 3 As shown, the display panel provided by the embodiment of the present invention includes a base substrate 10 and a pixel driving circuit 11 located on one side of the base substrate 10. The pixel driving circuit 11 includes a first driving transistor M3, and the first driving transistor M3 includes a first electrode M31 and a second electrode M32. The first electrode M31 includes a first section 21 extending along a first direction X, and the second electrode M32 includes a second section 22 extending along a second direction Y, and the first direction X and the second direction Y intersect. The first section 21 includes a first segment 211 and a second segment 212 arranged along the first direction X, and the vertical projection of the second segment 212 on the base substrate 10 overlaps with the vertical projection of the second segment 22 on the base substrate 10. Along the first direction X, the area of ​​the second segment 212 per unit length is smaller than the area of ​​the first segment 211 per unit length.

[0053] Specifically, Figure 1 and Figure 2 As shown, a plurality of pixel driving circuits 11 arranged in an array and a plurality of light emitting elements 12 arranged in an array are provided on one side of the base substrate 10. The plurality of pixel driving circuits 11 and the plurality of light emitting elements 12 are electrically connected to each other. The pixel driving circuit 11 is used to transmit the driving current to the light emitting element 12 under the action of the signal of the driving signal line (such as the scanning signal line, the data signal line, the power signal line, etc.) on the display panel, so as to drive the light emitting element 12 to emit light. Among them, the light emitting element 12 and the pixel driving circuit 11 electrically connected thereto together constitute the sub-pixel 100 of the display panel. The plurality of sub-pixels 100 are arranged according to a certain rule. By accurately controlling the brightness of different sub-pixels 100, the display of a complete image can be realized.

[0054] It should be noted that the arrangement of the multiple pixel driving circuits 11 and the multiple light emitting elements 12 can be set according to actual needs, and the embodiment of the present invention does not specifically limit this.

[0055] Continue to refer Figure 2 Optionally, the pixel driving circuit 11 may include at least one thin film transistor T, and the thin film transistor T may include an active layer 1 , a gate 2 , a source 3 and a drain 4 .

[0056] The gate 2 may include a bottom gate 201 and a top gate 202 to form a double-gate transistor, thereby reducing the leakage current in the thin film transistor T, and further reducing the influence of the leakage current on the potential of each node in the pixel driving circuit 11 .

[0057] Continue to refer Figure 2 Optionally, a bottom gate insulating layer 71 may be provided between the bottom gate 201 and the active layer 1, a gate insulating layer GI may be provided between the active layer 1 and the top gate 202, an interlayer dielectric layer IMD and an insulating intermediate layer ILD may be provided between the top gate 202 and the source 3, and a first passivation layer PV1, a first planarization layer PLN1, a first connection metal layer 72, a second planarization layer PLN2, a second connection metal layer 73 and a second passivation layer PV2 may be provided in sequence on the side of the source 3 away from the base substrate 10, but it is not limited thereto.

[0058] Furthermore, the light emitting element 12 may include a micro light emitting diode (such as Micro-LED, Mini-LED) to achieve higher brightness and a longer service life, which can meet the display requirements in outdoor or high-brightness environments, but is not limited to this.

[0059] In other embodiments, the light-emitting element 12 may also be an organic light-emitting diode (OLED) or other types of light-emitting devices, which is not specifically limited in the embodiment of the present invention.

[0060] Continue to refer Figure 3 Optionally, the thin film transistor T in the pixel driving circuit 11 includes a first driving transistor M3, which is used to transmit a specific voltage or a driving current to a specific node based on its gate voltage. For example, the first driving transistor M3 can generate a driving current according to its gate potential, and transmit the driving current to the light emitting element 12 to drive the light emitting element 12 to emit light, but is not limited thereto.

[0061] For example, Figure 3 As shown, the pixel driving circuit 11 includes a pulse width regulation module PWM and an amplitude regulation module PAM, the pulse width regulation module PWM includes a pulse width driving transistor PWM_M3, the amplitude regulation module PAM includes an amplitude driving transistor PAM_M3, the pulse width driving transistor PWM_M3 is electrically connected to the gate of the amplitude driving transistor PAM_M3, and the first driving transistor M3 includes at least one of the amplitude driving transistor PWM_M3 and the pulse width driving transistor PAM_M3.

[0062] The amplitude adjustment module PAM is used to provide a driving current to the light emitting element 12 and control the luminous efficiency of the light emitting element 12 by adjusting the amplitude of the driving current.

[0063] Optionally, the driving current may be a constant driving current, so as to drive the light emitting element 12 with a better driving current to ensure that the light emitting element 12 works in an optimal state, which is conducive to achieving higher luminous efficiency and better display effect.

[0064] The pulse width modulation module PWM is used to control the duration of the driving current provided by the amplitude adjustment module PAM to the light-emitting element 12, thereby controlling the light-emitting duration of the light-emitting element 12. It can be understood that by controlling the light-emitting duration of the light-emitting element 12 (i.e., adjusting the light-emitting duty cycle of the light-emitting element 12), the brightness of the light emitted by the light-emitting element 12 can be controlled.

[0065] Therefore, the pixel driving circuit 11 provided in this embodiment can adjust the grayscale or brightness displayed by the light-emitting element 12 through the combined action of the pulse width modulation module PWM and the amplitude modulation module PAM.

[0066] Furthermore, if Figure 3As shown, in the amplitude adjustment module PAM, the amplitude driving transistor PAM_M3 is connected in series between the second power line PAM_VDD and the light emitting element 12, the second power line PAM_VDD is used to provide a second power supply voltage, and the amplitude driving transistor PAM_M3 can generate a driving current based on the voltage of its gate and the second power supply voltage to drive the light emitting element 12 to emit light. The same voltage signal can be provided to the gate of the amplitude driving transistor PAM_M3 to generate a constant driving current.

[0067] It should be noted that, for the pixel driving circuit 11 connected to the light emitting elements 12 of different colors, different voltage signals may be provided to the gate of the amplitude driving transistor PAM_M3 thereof, which is not specifically limited in the embodiment of the present invention.

[0068] Continue to refer Figure 3 Optionally, in the pulse width modulation module PWM, the pulse width driving transistor PWM_M3 is connected in series between the first power line PWM_VDD and the gate of the amplitude driving transistor PAM_M3, and is used to transmit the first power supply voltage provided by the first power line PWM_VDD to the gate of the amplitude driving transistor PAM_M3, so as to control the amplitude driving transistor PAM_M3 to be cut off, so that the pulse width modulation module PWM can control the conduction time of the amplitude driving transistor PAM_M3, that is, the pulse width modulation module PWM can control the duration of the driving current, so that the light-emitting element 12 presents the brightness of the corresponding gray scale.

[0069] Among them, in the case where the first power supply voltage controls the amplitude driving transistor PAM_M3 to be cut off, if the amplitude driving transistor PAM_M3 is a P-type transistor, the first power supply voltage can be a high level, otherwise, if the amplitude driving transistor PAM_M3 is an N-type transistor, the first power supply voltage can be a low level, and the embodiment of the present invention does not specifically limit this.

[0070] It can be understood that the amplitude driving transistor PAM_M3 and the pulse width driving transistor PWM_M3 play an important role in the pixel driving circuit 11, wherein the performance of the amplitude driving transistor PAM_M3 will directly affect the size of the driving current, thereby affecting the luminous efficiency of the light-emitting element 12; the performance of the pulse width driving transistor PWM_M3 will directly affect the luminous time of the light-emitting element 12, thereby affecting the grayscale control of the light-emitting element 12.

[0071] It should be noted that Figure 3 An exemplary circuit structure of 13T2C (i.e., including 13 transistors and 2 capacitors) is shown, but it is not limited thereto. In other embodiments, the pixel driving circuit 11 may also adopt other circuit structures, such as 17T3C, 7T1C or 8T1C circuit structures, etc., which is not specifically limited in the embodiments of the present invention.

[0072] Furthermore, the inventors have discovered through research that since the pixel driving circuit 11 includes a large number of transistors and the circuit structure is relatively complex, under the requirements of high-resolution display, the transistors and corresponding connected signal lines and other wiring need to be arranged in a limited space, resulting in dense distribution of transistors and wiring, which will increase mutual interference between various signal nodes, and thus affect the driving capability of the pixel driving circuit 11.

[0073] For example, Figure 4 for Figure 3 A schematic diagram of a film structure of a pixel driving circuit shown in FIG. Figure 5 for Figure 4 A schematic diagram of the enlarged structure at B. Figure 6 for Figure 4 The enlarged structural diagram at C is as follows: Figure 4-Figure 6 As shown, the gate PWM_M30 of the pulse width driving transistor PWM_M3 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3 (for example, the source of the pulse width driving transistor PWM_M3) are insulated and cross-arranged, and a first overlapping area O1 exists between the gate PWM_M30 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3, and the gate PWM_M30 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3 are both located on the substrate, and along the direction perpendicular to the plane where the substrate is located, the gate PWM_M30 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3 are close to each other, so that in the first overlapping area O1, a large parasitic capacitance is formed between the gate PWM_M30 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3. In this way, when a voltage is applied to the gate PWM_M30 to turn on the pulse width driving transistor PWM_M3, part of the energy will be consumed in the parasitic capacitance, causing unnecessary coupling power consumption, resulting in a decrease in the actual voltage of the gate PWM_M30, so that the gate PWM_M30 voltage of the pulse width driving transistor PWM_M3 cannot reach the expected turn-on voltage. At the same time, the voltage of the gate PWM_M30 will also be disturbed by the change in the voltage of the first pole PWM_M31, resulting in an unpredictable deviation between the gate PWM_M30 voltage and the expected turn-on voltage, so that the actual voltage of the gate PWM_M30 cannot be accurately controlled, which increases the control difficulty of the pixel driving circuit 11. The above problems will eventually affect the driving ability of the pixel driving circuit 11.

[0074] It should be noted that Figure 4 and Figure 5In the figure, only the overlap between the gate PWM_M30 and the first electrode PWM_M31 of the pulse width driving transistor PWM_M3 is used as an example for explanation. When the connection relationship of the pulse width driving transistor PWM_M3 changes, it is also possible that there is an overlap between the gate PWM_M30 and the drain of the pulse width driving transistor PWM_M3. The embodiment of the present invention does not specifically limit this.

[0075] Similarly, if Figure 4 and Figure 6 As shown, the gate PAM_M30 of the amplitude driving transistor PAM_M3 and the first electrode PAM_M31 of the amplitude driving transistor PAM_M3 (for example, the source of the amplitude driving transistor PAM_M3) are insulated and cross-arranged, and a second overlapping area O2 exists between the gate PAM_M30 and the first electrode PAM_M31 of the amplitude driving transistor PAM_M3, and the gate PAM_M30 and the first electrode PAM_M31 of the amplitude driving transistor PAM_M3 are both located on the substrate, and along the direction perpendicular to the plane where the substrate is located, the distance between the gate PAM_M30 and the first electrode PAM_M31 of the amplitude driving transistor PAM_M3 is relatively close, so that in the second overlapping area O2, a large parasitic capacitance is formed between the gate PAM_M30 and the first electrode PAM_M31 of the amplitude driving transistor PAM_M3. In this way, when a voltage is applied to the gate PAM_M30 to turn on the amplitude driving transistor PAM_M3, part of the energy will be consumed in the parasitic capacitance, resulting in unnecessary coupling power consumption, causing the actual voltage of the gate PAM_M30 to decrease, so that the gate PAM_M30 voltage of the amplitude driving transistor PAM_M3 cannot reach the expected turn-on voltage, thereby causing insufficient driving current, resulting in lower display brightness than expected. At the same time, the voltage of the gate PAM_M30 will also be disturbed by the voltage change of the first pole PAM_M31, resulting in an unpredictable deviation between the gate PAM_M30 voltage and the expected turn-on voltage, so that the actual voltage of the gate PAM_M30 cannot be accurately controlled, increasing the control difficulty of the pixel driving circuit 11. The above problems will eventually affect the driving capability of the pixel driving circuit 11.

[0076] It should be noted that Figure 4 and Figure 6 In the figure, only the overlap between the gate PAM_M30 and the first electrode PAM_M31 of the amplitude driving transistor PAM_M3 is used as an example for explanation. When the connection relationship of the amplitude driving transistor PAM_M3 changes, it is also possible that the gate PAM_M30 and the drain of the amplitude driving transistor PAM_M3 overlap, which is not specifically limited in the embodiment of the present invention.

[0077] Based on the above technical issues, Figure 7 for Figure 3 Another schematic diagram of the film structure of the pixel driving circuit shown in FIG. Figure 8 for Figure 7 Schematic diagram of the enlarged structure at D, Fig. 9 for Figure 7 The enlarged structural diagram at E is as follows: Figure 7-Figure 9 As shown, in this embodiment, at least one of the amplitude driving transistor PAM_M3 and the pulse width driving transistor PWM_M3 is used as the first driving transistor M3, that is, the first driving transistor M3 can be the amplitude driving transistor PAM_M3, or the first driving transistor M3 is the pulse width driving transistor PWM_M3, or the first driving transistor M3 includes the amplitude driving transistor PAM_M3 and the pulse width driving transistor PWM_M3, and the embodiment of the present invention does not specifically limit this.

[0078] like Figure 7-Figure 9 As shown, the first driving transistor M3 is taken as an amplitude driving transistor PAM_M3 as an example for explanation, the electrode of the first driving transistor M3 includes a first electrode M31 and a second electrode M32, and the first subdivision 21 in the first electrode M31 and the second subdivision 22 in the second electrode M32 are cross-arranged, illustratively, as Figure 8 As shown, the first section 21 extends along the first direction X, and the second section 22 extends along the second direction Y. At this time, an overlapping area is formed between the first section 21 and the second section 22.

[0079] Further, Fig.10 A schematic diagram of the structure of a first subdivision and a second subdivision provided in an embodiment of the present invention, such as Figure 7-10 As shown, the first section 21 is divided into a first section 211 and a second section 212 arranged along the first direction X, wherein, along the direction perpendicular to the plane where the substrate is located, the first section 211 does not overlap with the second section 22, and the second section 212 overlaps with the second section 22. In other words, along the direction perpendicular to the plane where the substrate is located, the portion where the first section 21 does not overlap with the second section 22 is the first section 211, and the portion where the first section 21 overlaps with the second section 22 is the second section 212.

[0080] Among them, in the first direction X, the area of ​​the second segment 212 per unit length is smaller than the area of ​​the first segment 211 per unit length. Then, within the same length in the first direction X, the area of ​​the overlapping portion of the first section 21 and the second section 22 is smaller than the area of ​​the non-overlapping portion of the first section 21 and the second section 22, thereby reducing the area of ​​the second segment 212 per unit length in the first direction X. Then, in the direction perpendicular to the plane where the substrate is located, the overlapping area between the first section 21 of the first electrode M31 and the second section 22 of the second electrode M32 is reduced. The smaller the overlapping area, the smaller the parasitic capacitance formed between the first electrode M31 and the second electrode M32, thereby reducing the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3, and reducing unnecessary coupling power consumption. At the same time, the mutual interference of the voltage between the first electrode M31 and the second electrode M32 can also be reduced, thereby facilitating the precise control of the working state of the first driving transistor M3, reducing the control difficulty of the pixel driving circuit 11, and thereby facilitating improving the driving capability of the pixel driving circuit 11.

[0081] It should be noted that Figure 7-10 Taking the first direction X being perpendicular to the second direction Y as an example, in practical applications, the angle between the first direction X and the second direction Y can be set according to actual needs, and it is only necessary to ensure that the first direction X and the second direction Y intersect, and the embodiment of the present invention does not specifically limit this.

[0082] also, Figure 7-Figure 9 Only the first driving transistor M3 is taken as an example of the amplitude driving transistor PAM_M3 for explanation. It can be understood that the first driving transistor M3 is not limited to the amplitude driving transistor PAM_M3 in the above-mentioned pixel driving circuit 11. For example, as mentioned above, the first driving transistor M3 can also be a pulse width driving transistor PWM_M3. When the pixel driving circuit 11 adopts other circuit structures, the first driving transistor M3 can also be a driving transistor in the corresponding circuit structure, which is not specifically limited in the embodiment of the present invention.

[0083] In summary, the display panel provided by the embodiment of the present invention includes a first driving transistor in the pixel driving circuit, the first electrode of the first driving transistor includes a first section extending along the first direction, the second electrode of the first driving transistor includes a second section extending along the second direction, and the first direction and the second direction intersect, the first section includes a first segment and a second segment arranged along the first direction, and the vertical projection of the second segment on the substrate overlaps with the vertical projection of the second segment on the substrate, and along the first direction, the area of ​​the second segment per unit length is set to be smaller than the area of ​​the first segment per unit length, so that the first segment and the second segment are within the same length in the first direction. The area of ​​the overlapping portion is smaller than the area of ​​the non-overlapping portion between the first section and the second section, so as to reduce the area per unit length of the second section in the first direction, thereby reducing the overlapping area between the first section of the first electrode and the second section of the second electrode in a direction perpendicular to the plane of the substrate, thereby reducing the parasitic capacitance formed between the first electrode and the second electrode of the first driving transistor, and reducing unnecessary coupling power consumption; at the same time, it can also reduce the mutual interference of the voltage between the first electrode and the second electrode, thereby helping to achieve precise control of the working state of the first driving transistor, reducing the control difficulty of the pixel driving circuit, and thus helping to improve the driving capability of the pixel driving circuit.

[0084] Continue to refer Figure 7-10 Optionally, the first electrode M31 is a gate electrode, and the second electrode M32 is a source electrode or a drain electrode.

[0085] Specifically, Figure 7-10 As shown, the first electrode M31 is the gate of the first driving transistor M3, and the second electrode M32 is the source or drain of the first driving transistor M3. In this embodiment, the gate of the first driving transistor M3 includes a first section 21, and the extension direction of the first section 21 is the first direction X. The source or drain of the first driving transistor M3 includes a second section 22, and the extension direction of the second section 22 is the second direction Y. The first section 21 in the gate of the first driving transistor M3 is divided into a first section 211 and a second section 212 arranged along the first direction X, and along the direction perpendicular to the plane where the substrate is located, the first section 211 does not overlap with the second section 22, and the second section 212 overlaps with the second section 22.

[0086] In the present embodiment, the area per unit length of the second segment 212 in the gate of the first driving transistor M3 in the first direction X can be reduced to reduce the parasitic capacitance formed between the gate of the first driving transistor M3 and its source or drain, thereby reducing unnecessary coupling power consumption; at the same time, the mutual interference of the voltage between the gate of the first driving transistor M3 and its source or drain can also be reduced, thereby facilitating precise control of the working state of the first driving transistor M3, reducing the control difficulty of the pixel driving circuit 11, and further improving the driving capability of the pixel driving circuit 11.

[0087] At the same time, in this embodiment, the structure of the source and drain of the first driving transistor M3 may not be changed, thereby ensuring that the source and drain of the first driving transistor M3 have sufficient setting area, ensuring that the source and drain of the first driving transistor M3 have a smaller resistance, then when the first driving transistor M3 is working, the first driving transistor M3 can output a larger current, which is beneficial to improving the output capacity of the first driving transistor M3.

[0088] It should be noted that, in other embodiments, the first electrode M31 may be set as a source or a drain, and the second electrode M32 may be set as a gate. In this way, a second segment 212 overlapping with the gate may be set in the source or the drain of the first driving transistor M3, and by reducing the area per unit length of the second segment 212 in the first direction X, the parasitic capacitance formed between the gate of the first driving transistor M3 and its source or drain may be reduced, thereby improving the driving capability of the pixel driving circuit 11. The embodiment of the present invention does not specifically limit this.

[0089] Fig.11 Another structural diagram of the first subdivision and the second subdivision provided in an embodiment of the present invention is as follows: Fig.11 As shown, optionally, the second section 212 includes a first connecting portion 2121 connected to the first section 211 , the length of the first connecting portion 2121 along the second direction Y is d1 , and the length of the first section 211 along the second direction Y is D, wherein d1<D.

[0090] Specifically, Fig.11 As shown, along the first direction X, the first connecting portion 2121 of the second segment 22 connects the adjacent first segments 211 to ensure the conductivity of the first sub-portion 21 .

[0091] The length d1 of the first connecting portion 2121 along the second direction Y is smaller than the length D of the first segment 211 along the second direction Y, so as to reduce the length of the second segment 212 in the second direction Y, thereby forming a gap overlapping with the second segment 22 on the first segment 21 in a direction perpendicular to the plane where the substrate is located. With such a configuration, along the first direction X, the area of ​​the second segment 212 per unit length is smaller than the area of ​​the first segment 211 per unit length, thereby reducing the overlapping area between the first segment 21 of the first electrode M31 and the second segment 22 of the second electrode M32, thereby reducing the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0092] The embodiment of the present invention does not specifically limit the shape and position of the first connecting portion 2121 .

[0093] For example, Fig.11 As shown, along the second direction Y, the first connecting portion 2121 can be disposed on one side of the first sub-portion 21 , thereby forming a gap overlapping with the second sub-portion 22 on the other side of the first sub-portion 21 .

[0094] Fig.12 A schematic diagram of the structure of another first subdivision and a second subdivision provided in an embodiment of the present invention is shown in FIG. Fig.12 As shown, optionally, along the second direction Y, the first connecting portion 2121 may also be disposed in the middle of the first sub-portion 21 , so that a gap overlapping with the second sub-portion 22 is formed on both sides of the first sub-portion 21 .

[0095] exist Fig.11 and Fig.12 In the illustrated embodiment, only one first connection portion 2121 is used to connect the adjacent first segment 211. Under the condition of ensuring the normal operation of the first driving transistor M3, the overlapping area between the first section 21 of the first electrode M31 and the second section 22 of the second electrode M32 can be reduced to a large extent, thereby reducing the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0096] It should be noted that the specific value of the length d1 of the first connecting portion 2121 in the second direction Y can be set according to actual needs. It can be understood that the smaller the length d1 of the first connecting portion 2121 along the second direction Y, the smaller the area of ​​the second segment 212 per unit length along the first direction X, the smaller the overlapping area between the first section 21 of the first electrode M31 and the second section 22 of the second electrode M32, and the smaller the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0097] Optionally, d1≥2.5μm, which helps to reduce the process difficulty while ensuring that the overlapping area between the first section 21 of the first electrode M31 and the second section 22 of the second electrode M32 is small, thereby avoiding the problem of short circuit of the first connecting portion 2121 due to process errors and ensuring the conductive performance between the second section 212 and the first section 211.

[0098] Optionally, d1≤5μm, which is beneficial to significantly reduce the length of the second segment 212 in the second direction Y, reduce the overlapping area between the first section 21 of the first electrode M31 and the second section 22 of the second electrode M32, and reduce the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0099] Continue to refer Fig.11 Optionally, the second section 212 further includes a second connecting portion 2122 connected to the first section 211 , and the length of the second connecting portion 2122 along the second direction Y is d2 , wherein d1 + d2 <D.

[0100] Specifically, Fig.11 As shown, along the first direction X, the second section 212 is further provided with a second connecting portion 2122 to connect the adjacent first section 211, so that the reliability of the second section 212 can be improved while ensuring that the length of the second section 212 in the second direction Y is reduced and the overlapping area between the first section 21 and the second section 22 is reduced, thereby avoiding the problem of disconnection of the first section 21 in the second section 212.

[0101] Among them, the second connecting portion 2122 can be arranged with the first connecting portion 2121 along the second direction Y, and the sum of the length d1 of the first connecting portion 2121 along the second direction Y and the length d2 of the second connecting portion 2122 along the second direction Y is less than the length D of the first segment 211 along the second direction Y, thereby ensuring that the area of ​​the second segment 212 per unit length in the first direction X is less than the area of ​​the first segment 211 per unit length, reducing the overlapping area between the first division 21 of the first electrode M31 and the second division 22 of the second electrode M32, and reducing the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0102] It should be noted that the embodiment of the present invention does not specifically limit the shape and position of the first connection portion 2121 and the second connection portion 2122. The specific values ​​of the lengths of the first connection portion 2121 and the second connection portion 2122 along the second direction Y can also be set according to actual needs. It can be understood that the smaller the sum of the lengths of the first connection portion 2121 and the second connection portion 2122 along the second direction Y is, the smaller the area of ​​the second segment 212 per unit length along the first direction X is, the smaller the overlapping area between the first section 21 of the first electrode M31 and the second section 22 of the second electrode M32 is, and the smaller the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3 is.

[0103] Optionally, d2≥2.5μm, which is beneficial to reducing the process difficulty while ensuring that the overlapping area between the first section 21 of the first electrode M31 and the second section 22 of the second electrode M32 is small, thereby avoiding the problem of short circuit of the second connecting portion 2122 due to process errors and ensuring the conductive performance between the second section 212 and the first section 211.

[0104] Optionally, d2≤5μm, which is beneficial to significantly reduce the length of the second segment 212 in the second direction Y, reduce the overlapping area between the first section 21 of the first electrode M31 and the second section 22 of the second electrode M32, and reduce the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0105] Continue to refer Fig.11 Optionally, the first connection portion 2121 and the second connection portion 2122 are arranged along the second direction Y, and a first hollow portion 213 is provided between the first connection portion 2121 and the second connection portion 2122, and a vertical projection of the first hollow portion 213 on the base substrate overlaps with a vertical projection of the second portion 22 on the base substrate.

[0106] Specifically, Fig.11 As shown, along the second direction Y, there is a gap between the second connection portion 2122 and the first connection portion 2121, so that in a direction perpendicular to the plane of the substrate, a first hollow portion 213 overlapping with the second section 22 is formed between the first connection portion 2121 and the second connection portion 2122. With this arrangement, the area of ​​the second section 212 per unit length is smaller than the area of ​​the first section 211 per unit length in the first direction X, thereby reducing the overlapping area between the first section 21 of the first electrode M31 and the second section 22 of the second electrode M32, and reducing the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0107] Continue to refer Fig.11Optionally, the first section 211 includes a third hollow portion 220 connected to the first hollow portion 213, so that in the first direction X, the distance between the first section 211 and the second section 22 can be increased in a partial area, thereby reducing the parasitic capacitance between the first section 211 and the second section 22, thereby achieving the effect of reducing the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0108] Wherein, along the first direction X, the third hollow portion 220 may be located on at least one side of the second sub-portion 22. For example, Fig.11 As shown, along the first direction X, the third hollow portion 220 is located at opposite sides of the second section 22 to further reduce the parasitic capacitance between the first section 211 and the second section 22, thereby facilitating the reduction of the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3, but is not limited thereto.

[0109] In other embodiments, along the first direction X, the third hollow portion 220 may also be located only on one side of the second sub-portion 22 , which is not specifically limited in the embodiment of the present invention.

[0110] Furthermore, the length of the third hollow portion 220 in the first direction X can be greater than 0 and less than or equal to 3 μm. In this way, while ensuring that the parasitic capacitance between the first section 211 and the second section 22 is reduced, the third hollow portion 220 can be prevented from having a significant impact on the conductive properties of the first section 211, which is beneficial to ensuring the working performance of the first driving transistor M3.

[0111] Fig.13 A schematic diagram of the structure of another first subdivision and a second subdivision provided in an embodiment of the present invention is shown in FIG. Fig.13 As shown, optionally, the length of the second segment 212 along the second direction Y is equal to the length of the first segment 211 along the second direction Y, and the second segment 212 includes at least one second hollow portion 214, and the vertical projection of the second hollow portion 214 on the substrate overlaps with the vertical projection of the second section 22 on the substrate.

[0112] Specifically, Fig.13 As shown, along the second direction Y, the length of the second segment 212 can be equal to the length of the first segment 211. In the direction perpendicular to the plane of the substrate, a second hollow portion 214 overlapping the second portion 22 is provided on the second segment 212 to reduce the overlapping area between the first portion 21 of the first electrode M31 and the second portion 22 of the second electrode M32, thereby reducing the parasitic capacitance formed between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0113] The shape and number of the second hollow portions 214 can be set according to actual needs, and are not specifically limited in the embodiment of the present invention.

[0114] Optionally, the length of the second hollow portion 214 in the first direction X and the length of the second hollow portion 214 in the second direction Y can both be greater than or equal to 2.5 μm. This can ensure that the overlapping area between the first section 21 of the first electrode M31 and the second section 22 of the second electrode M32 is significantly reduced, while also helping to reduce the difficulty of the process, thereby avoiding the situation in which the second section 212 is unable to form an effective opening at the position of the second hollow portion 214 due to process errors.

[0115] Continue to refer Fig.13 Optionally, the length of the second hollow portion 214 in the first direction X is less than or equal to the length of the second section 22 in the first direction X. In this way, while ensuring that the parasitic capacitance between the second section 212 and the second section 22 is reduced, the space occupied by the second hollow portion 214 is reduced, which is beneficial to reducing the negative impact of the third hollow portion 220 on the conductive performance of the second section 212.

[0116] Fig.14 A schematic diagram of the structure of another pixel driving circuit provided by an embodiment of the present invention, Fig.15 A schematic diagram of a film layer structure of a display panel provided in an embodiment of the present invention, Fig.16 for Fig.15 A schematic diagram of the structure of a first metal layer in a display panel shown in FIG. Fig.17 for Fig.15 A schematic diagram of the structure of a semiconductor layer in a display panel shown in FIG. Fig.18 for Fig.15 A schematic diagram of the structure of a second metal layer in a display panel shown in FIG. Fig.19 for Fig.15 A schematic diagram of the structure of a third metal layer in a display panel shown in FIG. Fig. 20 for Fig.15 A schematic diagram of the structure of a fourth metal layer in a display panel shown in FIG. Fig.21 for Fig.15 The schematic diagram of the stacked structure of all film layers in a display panel shown is specifically a schematic diagram of the stacked structure from the first metal layer to the fourth metal layer. Fig. 22 for Fig.21 Schematic diagram of the enlarged structure at F, Fig.23 for Fig.21 Schematic diagram of the enlarged structure at G.

[0117] Specifically, Fig.14 An exemplary circuit structure of 17T3C (i.e., including 17 transistors and 3 capacitors) is shown. Figure 15-Figure 23The film structure shown can correspond to Fig.14 The pixel driving circuit 11 shown in FIG. Fig.15 As shown, taking the transistors in the pixel driving circuit 11 as an example, all of which are low temperature polysilicon (LTPS) transistors, a first metal layer M0, a semiconductor layer POLY, a second metal layer GAT, a third metal layer MC and a fourth metal layer SD1 are stacked on one side of the base substrate 10, and an insulating layer 40 can be set between any two adjacent conductive film layers to avoid short circuits between the two adjacent conductive film layers, but it is not limited to this.

[0118] like Fig.21 and Fig.23 As shown, optionally, the pixel driving circuit 11 further includes a first capacitor C1, and the first capacitor C1 includes a first electrode plate c11. The first electrode M31 further includes a third subdivision 23 extending along the second direction Y, the first subdivision 21 and the third subdivision 23 are connected, and the second subdivision 22 and the third subdivision 23 are arranged along the first direction X. The first electrode plate c11 includes a first connecting subdivision 31 connected to the third subdivision 23, and the third subdivision 23 and the first connecting subdivision 31 are arranged along the second direction Y. Along the first direction X, the spacing L1 between the third subdivision 23 and the second subdivision 22 is greater than the spacing L2 between the first connecting subdivision 31 and the second subdivision 22.

[0119] Specifically, Figure 3 and Fig.14 As shown, the amplitude adjustment module PAM may include an amplitude storage capacitor PAM_C1, which is connected in series between the second power line PAM_VDD and the amplitude driving transistor PAM_M3, and the second power line PAM_VDD is used to provide a second power supply voltage. The amplitude storage capacitor PAM_C1 can be used to receive the amplitude data signal written to the gate of the amplitude driving transistor PAM_M3 and maintain the potential of the gate of the amplitude driving transistor PAM_M3, so that the amplitude driving transistor PAM_M3 can continuously provide a constant driving current.

[0120] Continue to refer Figure 3 and Fig.14The pulse width modulation module PWM may include a pulse width storage capacitor PWM_C1, which is connected in series between a sweep signal line SWEEP and a gate of a pulse width driving transistor PWM_M3. The sweep signal line SWEEP is used to provide a sweep signal, which may be in the form of a triangular wave. For example, the sweep signal may decrease linearly from a high level to a low level, or the sweep signal may increase linearly from a low level to a high level. The pulse width storage capacitor PWM_C1 is used to receive a pulse width data signal written to the gate of the pulse width driving transistor PWM_M3 and to maintain the potential of the gate of the pulse width driving transistor PWM_M3.

[0121] In this embodiment, at least one of the amplitude storage capacitor PAM_C1 and the pulse width storage capacitor PWM_C1 can be used as the first capacitor C1, that is, the first capacitor C1 can be the amplitude storage capacitor PAM_C1, or the first capacitor C1 is the pulse width storage capacitor PWM_C1, or the first capacitor C1 includes the amplitude storage capacitor PAM_C1 and the pulse width storage capacitor PWM_C1, and the embodiment of the present invention does not specifically limit this.

[0122] Wherein, the first plate c11 of the first capacitor C1 is electrically connected to the first electrode M31 of the first driving transistor M3. Exemplarily, when the first driving transistor M3 is an amplitude driving transistor PAM_M3, the first capacitor C1 may be an amplitude storage capacitor PAM_C1, in which case the first plate c11 of the first capacitor C1 is connected to the gate of the amplitude driving transistor PAM_M3 (i.e., the first electrode M31 of the first driving transistor M3); when the first driving transistor M3 is a pulse width driving transistor PWM_M3, the first capacitor C1 may be a pulse width storage capacitor PWM_C1, in which case the first plate c11 of the first capacitor C1 is connected to the gate of the pulse width driving transistor PWM_M3 (i.e., the first electrode M31 of the first driving transistor M3).

[0123] Furthermore, if Fig.21 and Fig.23As shown, taking the first driving transistor M3 as the amplitude driving transistor PAM_M3 and the first capacitor C1 as the amplitude storage capacitor PAM_C1 as an example for explanation, the first electrode plate c11 of the first capacitor C1 includes a main body section 32, wherein the main body section 32 and the first driving transistor M3 are arranged along the second direction Y, then a first connecting section 31 connected to the main body section 32 is arranged on the first electrode plate c11, and a third section 23 connected to the first section 21 is arranged on the first electrode M31, the extension direction of the third section 23 is the second direction Y, and the third section 23 and the first connecting section 31 are arranged along the second direction Y, so that an electrical connection can be formed between the third section 23 and the first connecting section 31, thereby realizing an electrical connection between the first electrode plate c11 of the first capacitor C1 and the first electrode M31 of the first driving transistor M3.

[0124] like Fig.21 and Fig.23 As shown, the second section 22 and the third section 23 are arranged along the first direction X to avoid the second section 22 and the third section 23 from overlapping in a direction perpendicular to the plane of the substrate, thereby facilitating the reduction of the overlapping area between the first electrode M31 and the second electrode M32 of the first driving transistor M3, and reducing the parasitic capacitance formed between the first electrode M31 and the second electrode M32.

[0125] Furthermore, if Fig.21 and Fig.23 As shown, along the first direction X, the spacing L1 between the third section 23 and the second section 22 is set to be greater than the spacing L2 between the first connecting section 31 and the second section 22, so as to increase the spacing between the third section 23 of the first electrode M31 and the second section 22 of the second electrode M32 in the first direction X, thereby reducing the parasitic capacitance between the first electrode M31 and the second electrode M32 of the first driving transistor M3 and reducing unnecessary coupling power consumption; at the same time, the mutual interference of the voltage between the first electrode M31 and the second electrode M32 of the first driving transistor M3 can also be reduced, thereby facilitating the precise control of the working state of the first driving transistor M3, reducing the control difficulty of the pixel driving circuit 11, and further facilitating the improvement of the driving capability of the pixel driving circuit 11.

[0126] The spacing L1 between the third section 23 and the second section 22 may be set to be greater than or equal to 1 μm, so as to ensure that the parasitic capacitance between the first electrode M31 and the second electrode M32 of the first driving transistor M3 is small. Further, the spacing L1 between the third section 23 and the second section 22 may be set to be greater than or equal to 2.5 μm, so as to ensure that the parasitic capacitance between the first electrode M31 and the second electrode M32 is still maintained at a low level under the condition of process error, which is not specifically limited in the embodiment of the present invention.

[0127] It should be noted that Fig.21 and Fig.23 Only the first capacitor C1 is taken as an example of the amplitude storage capacitor PAM_C1. It can be understood that the first capacitor C1 is not limited to the amplitude storage capacitor PAM_C1 in the above-mentioned pixel driving circuit 11. For example, as mentioned above, the first capacitor C1 can also be a pulse width storage capacitor PWM_C1. When the pixel driving circuit 11 adopts other circuit structures, the first capacitor C1 can also be a storage capacitor in the corresponding circuit structure, which is not specifically limited in the embodiment of the present invention.

[0128] Continue to refer Fig.21 and Fig.23 Optionally, a length L3 of the third section 23 in the first direction X is smaller than a length L4 of the first connecting section 31 in the first direction X.

[0129] Specifically, Fig.21 and Fig.23 As shown, in the first direction X, the length L3 of the third section 23 is set to be smaller than the length L4 of the first connecting section 31, so as to shorten the length L3 of the third section 23 in the first direction X. In this way, the distance between the third section 23 and the second section 22 can be increased. While achieving a smaller parasitic capacitance between the first electrode M31 and the second electrode M32 of the first driving transistor M3, it is also helpful to increase the distance between the third section 23 and other signal lines or nodes in the first direction X, thereby reducing the signal interference between the first electrode M31 of the first driving transistor M3 and other signal lines or nodes, achieving precise control of the working state of the first driving transistor, reducing the control difficulty of the pixel driving circuit, and thus facilitating improving the driving capability of the pixel driving circuit.

[0130] Optionally, a length L3 of the third section 23 in the first direction X is greater than or equal to 1.2 μm, so as to ensure electrical conductivity between the first section 21 and the first connecting section 31 .

[0131] Furthermore, the length L3 of the third section 23 in the first direction X may be set to be greater than or equal to 2.5 μm, which is helpful to reduce the process difficulty and avoid the problem of the third section 23 being broken due to process error.

[0132] Continue to refer Fig.21 and Fig.23Optionally, the boundary of the third subdivision 23 close to the second subdivision 22 is the first boundary S1, and the boundary of the third subdivision 23 away from the second subdivision 22 is the second boundary S2. The boundary of the first connecting subdivision 31 close to the second subdivision 22 is the third boundary S3, and the boundary of the first connecting subdivision 31 away from the second subdivision 22 is the fourth boundary S4. Along the first direction X, the first boundary S1 is located on the side of the third boundary S3 away from the second subdivision 22, and the second boundary S2 is located on the side of the fourth boundary S4 close to the second subdivision 22.

[0133] Specifically, Fig.21 and Fig.23 As shown, along the first direction X, the first boundary S1 on the left side of the third division 23 is located on the side of the third boundary S3 on the left side of the first connection division 31 away from the second division 22, so that the distance L1 between the first boundary S1 of the third division 23 and the second division 22 is greater than the distance L2 between the third boundary S3 of the first connection division 31 and the second division 22, thereby increasing the distance between the third division 23 of the first electrode M31 and the second division 22 of the second electrode M32 in the first direction X, thereby reducing the parasitic capacitance between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0134] Furthermore, along the first direction X, the second boundary S2 on the right side of the third division 23 is located on the side of the fourth boundary S4 on the right side of the first connecting division 31 close to the second division 22, which can further reduce the length L3 of the third division 23 in the first direction X. In this way, the spacing between the third division 23 and other signal lines or nodes in the first direction X can be increased, thereby reducing the signal interference between the first electrode M31 of the first driving transistor M3 and other signal lines or nodes, achieving precise control of the working state of the first driving transistor, reducing the control difficulty of the pixel driving circuit, and thus facilitating improving the driving capability of the pixel driving circuit.

[0135] Among them, along the first direction X, the distance between the first boundary S1 and the third boundary S3 can be greater than or equal to 0.1 μm, ensuring that under the condition of process errors, the spacing L1 between the first boundary S1 of the third division 23 and the second division 22 can be greater than the spacing L2 between the third boundary S3 of the first connecting division 31 and the second division 22, thereby increasing the spacing between the third division 23 of the first electrode M31 and the second division 22 of the second electrode M32 in the first direction X, thereby reducing the parasitic capacitance between the first electrode M31 and the second electrode M32 of the first driving transistor M3.

[0136] Furthermore, along the first direction X, the distance between the first boundary S1 and the third boundary S3 may be less than or equal to 5 μm, so as to avoid the problem of disconnection caused by the length L3 of the third section 23 in the first direction X being too short.

[0137] Fig.24 A schematic diagram of the structure of a third sub-section and a first connecting sub-section provided in an embodiment of the present invention, such as Fig.21 , Fig.23 and Fig.24 As shown, optionally, the boundary of the third subdivision 23 close to the second subdivision 22 is the first boundary S1, and the first boundary S1 extends along the second direction Y. The boundary of the first connecting subdivision 31 close to the second subdivision 22 is the third boundary S3, and the third boundary S3 extends along the second direction Y. The first connecting subdivision 31 also includes a first chamfered boundary S01, and the first chamfered boundary S01 connects the third boundary S3 and the first boundary S1 respectively. The angle θ1 between the first chamfered boundary S01 and the third boundary S3 is an obtuse angle, and the angle θ2 between the first chamfered boundary S01 and the first boundary S1 is an obtuse angle.

[0138] Specifically, Fig.21 , Fig.23 and Fig.24 As shown, the first boundary S1 on the left side of the third division 23 and the third boundary S3 on the left side of the first connecting division 31 are connected by a first chamfered boundary S01, wherein an angle θ1 between the first chamfered boundary S01 and the third boundary S3 is greater than 90°, and an angle θ2 between the first chamfered boundary S01 and the first boundary S1 is greater than 90°, so that the first boundary S1 and the third boundary S3 are connected by chamfering, so that the edge of the first connecting division 31 between the first boundary S1 and the third boundary S3 can be smoother, avoiding the electric field from being concentrated at this position, thereby preventing the generation of tip static electricity, reducing the risk of electrostatic discharge, and improving the reliability and stability of the pixel driving circuit 11.

[0139] The first chamfered edge S01 may be a straight line, which is simple in design and easy to implement. In other embodiments, the first chamfered edge S01 may also be a curve, thereby providing a smoother transition between the first edge S1 and the third edge S3, reducing electric field concentration, and further preventing tip static electricity, which is not specifically limited in the embodiments of the present invention.

[0140] It should be noted that, in this embodiment, the length of the first chamfered boundary S01 in the first direction X can be set to be less than or equal to half the length of the first connecting section 31 in the first direction X, so as to ensure that the third section 23 has sufficient length in the first direction X and ensure the electrical connection performance between the third section 23 and the first connecting section 31.

[0141] Continue to refer Fig.21 , Fig.23 and Fig.24Optionally, the second boundary S2 extends along the second direction Y, and the fourth boundary S4 extends along the second direction Y. The first connecting section 31 further includes a second chamfered boundary S02, which connects the fourth boundary S4 and the second boundary S2 respectively. An angle θ3 between the second chamfered boundary S02 and the fourth boundary S4 is an obtuse angle, and an angle θ4 between the second chamfered boundary S02 and the second boundary S2 is an obtuse angle.

[0142] Specifically, Fig.21 , Fig.23 and Fig.24 As shown, the second boundary S2 on the right side of the third division 23 and the fourth boundary S4 on the right side of the first connection division 31 are connected via a second chamfered boundary S02, wherein an angle θ3 between the second chamfered boundary S02 and the fourth boundary S4 is greater than 90°, and an angle θ4 between the second chamfered boundary S02 and the second boundary S2 is greater than 90°, so that the second boundary S2 and the fourth boundary S4 are connected via the chamfer, thereby making the edge of the first connection division 31 between the second boundary S2 and the fourth boundary S4 smoother, avoiding the electric field from being concentrated at this position, thereby preventing the generation of tip static electricity, reducing the risk of electrostatic discharge, and improving the reliability and stability of the pixel driving circuit 11.

[0143] The second chamfered edge S02 may be a straight line, which is simple in design and easy to implement. In other embodiments, the second chamfered edge S02 may also be a curve, thereby providing a smoother transition between the second edge S2 and the fourth edge S4, reducing electric field concentration, and further preventing static electricity at the tip, which is not specifically limited in the embodiments of the present invention.

[0144] It should be noted that, in this embodiment, the length of the second chamfered boundary S02 in the first direction X can be set to be less than or equal to half the length of the first connecting section 31 in the first direction X, so as to ensure that the third section 23 has sufficient length in the first direction X and ensure the electrical connection performance between the third section 23 and the first connecting section 31.

[0145] Continue to refer Fig.21 , Fig.23 and Fig.24 Optionally, the pixel driving circuit 11 further includes a first capacitor C1, and the first capacitor C1 includes a first electrode plate c11. The first electrode M31 further includes a third subdivision 23 extending along the second direction Y, the first subdivision 21 and the third subdivision 23 are connected, and the second subdivision 22 and the third subdivision 23 are arranged along the first direction X. The boundary of the first subdivision 21 close to the first capacitor C1 is a fifth boundary S5, and the fifth boundary S5 extends along the first direction X. The boundary of the third subdivision 23 close to the second subdivision 22 is a first boundary S1, and the first boundary S1 extends along the second direction Y. The fifth boundary S5 is adjacent to the first boundary S1.

[0146] The structure and connection relationship of the first capacitor C1 may refer to the above embodiment and will not be described in detail here.

[0147] In this embodiment, if Fig.21 , Fig.23 and Fig.24 As shown, in the second direction Y, the fifth boundary S5 of the first division 21 near the first capacitor C1 extends along the first direction X. In the first direction X, the first boundary S1 of the third division 23 near the second division 22 extends along the second direction Y. Among them, the fifth boundary S5 is adjacent to the first boundary S1, that is, the fifth boundary S5 is directly connected to the first boundary S1, and there is no gap or other boundary between the fifth boundary S5 and the first boundary S1. At this time, the chamfer design is not adopted between the fifth boundary S5 and the first boundary S1, which can increase the distance between the adjacent position of the fifth boundary S5 and the first boundary S1 and the second division 22, thereby reducing the parasitic capacitance between the first electrode M31 and the second electrode M32 of the first driving transistor M3, reducing unnecessary coupling power consumption; at the same time, it can also reduce the mutual interference of the voltage between the first electrode M31 and the second electrode M32 of the first driving transistor M3, thereby helping to achieve accurate control of the working state of the first driving transistor M3, reducing the control difficulty of the pixel driving circuit 11, and thus helping to improve the driving ability of the pixel driving circuit 11.

[0148] For example, Fig.21 , Fig.23 and Fig.24 As shown, when the first direction X is perpendicular to the second direction Y, the angle θ5 between the fifth boundary S5 and the first boundary S1 can be a right angle, that is, θ5=90°, which increases the effective spacing between the junction of the first section 21 and the third section 23 and the second section 22, and reduces the parasitic capacitance between the first electrode M31 and the second electrode M32 of the first driving transistor M3, and is conducive to making the layout of the pixel driving circuit 11 more compact, thereby saving space, but is not limited to this, and the embodiments of the present invention do not make specific limitations on this.

[0149] Continue to refer Fig.21 , Fig.23 and Fig.24Optionally, the pixel driving circuit 11 further includes a first capacitor C1, and the first capacitor C1 includes a first electrode plate c11. Along the first direction X, the boundary of the second subdivision 22 close to the first electrode plate c11 is the sixth boundary S6, and the sixth boundary S6 extends along the second direction Y. Along the second direction Y, the boundary of the second subdivision 22 close to the first electrode plate c11 is the seventh boundary S7, and the seventh boundary S7 extends along the first direction X. The second subdivision 22 further includes a third chamfered boundary S03, and the third chamfered boundary S03 connects the sixth boundary S6 and the seventh boundary S7 respectively. The angle θ6 between the third chamfered boundary S03 and the sixth boundary S6 is an obtuse angle, and the angle θ7 between the third chamfered boundary S03 and the seventh boundary S7 is an obtuse angle.

[0150] The structure and connection relationship of the first capacitor C1 may refer to the above embodiment and will not be described in detail here.

[0151] In this embodiment, if Fig.21 , Fig.23 and Fig.24 As shown, in the first direction X, the sixth boundary S6 of the second section 22 close to the first electrode plate c11 extends along the second direction Y. In the second direction Y, the seventh boundary S7 of the second section 22 close to the first electrode plate c11 extends along the first direction X. The sixth boundary S6 and the seventh boundary S7 are connected by the third chamfered boundary S03, and the angle θ6 between the third chamfered boundary S03 and the sixth boundary S6 is greater than 90°, and the angle θ7 between the third chamfered boundary S03 and the seventh boundary S7 is greater than 90°, so that the sixth boundary S6 and the seventh boundary S7 are connected by chamfering, so that the distance between the second section 22 and the first electrode plate c11 can be increased at the position of the third chamfered boundary S03, the parasitic capacitance between the second electrode M32 of the first driving transistor M3 and the first electrode plate c11 is reduced, and the mutual interference of the voltage between the second electrode M32 of the first driving transistor M3 and the first electrode plate c11 is reduced. Furthermore, since the first electrode plate c11 is electrically connected to the third division 23, the potentials on the first electrode plate c11 and the third division 23 are the same, thereby reducing the parasitic capacitance between the second electrode M32 of the first driving transistor M3 and the first electrode plate c11, and indirectly reducing the mutual interference of the voltages between the second electrode M32 and the first electrode M31 of the first driving transistor M3, thereby helping to accurately control the working state of the first driving transistor M3, reducing the control difficulty of the pixel driving circuit 11, and further facilitating improving the driving capability of the pixel driving circuit 11.

[0152] The third chamfered edge S03 may be a straight line, which is simple in design and easy to implement. In other embodiments, the third chamfered edge S03 may also be a curve, thereby providing a smoother transition between the sixth edge S6 and the seventh edge S7, which is beneficial to reducing electric field concentration and preventing static electricity at the tip, which is not specifically limited in the embodiments of the present invention.

[0153] It should be noted that, in this embodiment, the length of the third chamfered boundary S03 in the first direction X can be set to be less than or equal to half the length of the second division 22 in the first direction X, so as to ensure that the second division 22 has a sufficient setting area, so that the second division 22 has a smaller resistance. Then, when the first driving transistor M3 is working, the first driving transistor M3 can output a larger current, which is beneficial to improving the output capacity of the first driving transistor M3.

[0154] In addition, in this embodiment, the spacing between the second section 22 and the first plate c11 in a direction parallel to the plane where the substrate is located can be set to be greater than or equal to 1 μm, so as to ensure that the parasitic capacitance between the second electrode M32 of the first driving transistor M3 and the first plate c11 is small. Further, the spacing between the second section 22 and the first plate c11 in a direction parallel to the plane where the substrate is located can be set to be greater than or equal to 2.5 μm, so as to ensure that the parasitic capacitance between the second electrode M32 of the first driving transistor M3 and the first plate c11 is still maintained at a low level under the condition of process errors, which is not specifically limited in this embodiment of the present invention.

[0155] Continue to refer Fig.21 , Fig.23 and Fig.24 Optionally, the first electrode plate c11 includes a main body section 32 and a first connection section 31 connected to each other, and the main body section 32 and the first connection section 31 are arranged along the second direction Y. The second section 22 and the first connection section 31 are arranged along the first direction X, and the second section 22 and the main body section 32 are arranged along the second direction Y. The boundary of the first connection section 31 close to the second section 22 is the third boundary S3, and the third boundary S3 extends along the second direction Y. The boundary of the main body section 32 close to the second section 22 is the eighth boundary S8, and the eighth boundary S8 extends along the first direction X. The first electrode plate c11 also includes a fourth chamfered boundary S04, and the fourth chamfered boundary S04 connects the third boundary S3 and the eighth boundary S8 respectively. The angle θ8 between the fourth chamfered boundary S04 and the third boundary S3 is an obtuse angle, and the angle θ9 between the fourth chamfered boundary S04 and the eighth boundary S8 is an obtuse angle.

[0156] Specifically, Fig.21 , Fig.23 and Fig.24As shown, the main body division 32 and the first driving transistor M3 are arranged along the second direction Y, a first connecting division 31 connected to the main body division 32 is provided on the first electrode c11, and a third division 23 connected to the first division 21 is provided on the first electrode M31. The main body division 32, the first connecting division 31 and the third division 23 are sequentially arranged along the second direction Y and electrically connected, thereby realizing the electrical connection between the first electrode c11 of the first capacitor C1 and the first electrode M31 of the first driving transistor M3.

[0157] Among them, the second division 22 and the first connecting division 31 are arranged along the first direction X, and the second division 22 and the main body division 32 are arranged along the second direction Y, so as to avoid the second division 22 and the first connecting division 31 from overlapping in a direction perpendicular to the plane of the substrate, thereby reducing the parasitic capacitance between the second electrode M32 of the first driving transistor M3 and the first plate c11, and reducing the mutual interference of the voltage between the second electrode M32 of the first driving transistor M3 and the first plate c11.

[0158] In the first direction X, the third boundary S3 of the first connection section 31 close to the second section 22 extends along the second direction Y. In the second direction Y, the eighth boundary S8 of the main body section 32 close to the second section 22 extends along the first direction X. The third boundary S3 and the eighth boundary S8 are connected by the fourth chamfered boundary S04, and the angle θ8 between the fourth chamfered boundary S04 and the third boundary S3 is greater than 90°, and the angle θ9 between the fourth chamfered boundary S04 and the eighth boundary S8 is greater than 90°, so that the third boundary S3 and the eighth boundary S8 are connected by chamfering, which can reduce the process difficulty, and also help to reduce the film defects of the first electrode c11 at the position of the fourth chamfered boundary S04, and improve the film quality.

[0159] The fourth chamfered edge S04 can be a straight line, which is simple in design and easy to implement. In other embodiments, the fourth chamfered edge S04 can also be a curve, so as to provide a smoother transition between the third edge S3 and the eighth edge S8, which helps to reduce the process difficulty and further improve the film quality. The embodiment of the present invention does not specifically limit this.

[0160] It should be noted that, in this embodiment, the length of the fourth chamfered boundary S04 in the first direction X can be set to be less than or equal to half the length of the first connecting section 31 in the first direction X, which is beneficial to ensure that the third section 23 has sufficient length in the first direction X and ensure the electrical connection performance between the third section 23 and the first electrode c11.

[0161] Fig.25 for Fig.15 A schematic diagram of the structure of another first metal layer in the display panel shown in FIG. Fig.26 for Fig.15 A schematic diagram of the structure of another semiconductor layer in a display panel shown in FIG. Fig. 27 for Fig.15 A schematic diagram of the structure of another second metal layer in the display panel shown in FIG. Fig.28 for Fig.15 A schematic diagram of the structure of another third metal layer in the display panel shown in FIG. Fig.29 for Fig.15 A schematic diagram of the structure of another fourth metal layer in the display panel shown in FIG. Fig.30 for Fig.15 Another schematic diagram of the stacked structure of all film layers in the display panel shown is a schematic diagram of the stacked structure from the first semiconductor layer to the anode layer.

[0162] in, Figure 25-Figure 30 The film structure shown can correspond to Figure 3 The pixel driving circuit 11 shown in FIG.

[0163] like Figure 7-Figure 30 As shown, optionally, the first driving transistor M3 is an amplitude driving transistor PAM_M3. The distance between the vertical projection of the gate PWM_M30 of the pulse width driving transistor PWM_M3 on the substrate and the vertical projection of the first pole PWM_M31 of the pulse width driving transistor PWM_M3 on the substrate is greater than 0. The distance between the vertical projection of the gate of the pulse width driving transistor PWM_M3 on the substrate and the vertical projection of the second pole PWM_M32 of the pulse width driving transistor PWM_M3 on the substrate is greater than 0.

[0164] Specifically, Figure 7-Figure 13 , Figure 21-24 As shown, in the amplitude adjustment module PAM, the amplitude driving transistor PAM_M3 can be set as the first driving transistor M3, and the parasitic capacitance formed between the gate of the amplitude driving transistor PAM_M3 and the source or drain of the amplitude driving transistor PAM_M3 is reduced by reducing the overlapping area between the gate of the amplitude driving transistor PAM_M3 and the source or drain of the amplitude driving transistor PAM_M3, so as to reduce unnecessary coupling power consumption; at the same time, the mutual interference of the voltage between the gate of the amplitude driving transistor PAM_M3 and the source or drain of the amplitude driving transistor PAM_M3 can also be reduced, so as to help achieve precise control of the working state of the amplitude driving transistor PAM_M3, reduce the control difficulty of the pixel driving circuit 11, and further help to improve the driving capability of the pixel driving circuit 11, but it is not limited to this.

[0165] Furthermore, if Figure 7-Figure 30As shown, in the pulse width modulation module PWM, the first pole PWM_M31 of the pulse width driving transistor PWM_M3 can be set as the source, and the second pole PWM_M32 of the pulse width driving transistor PWM_M3 can be set as the drain; or, the first pole PWM_M31 of the pulse width driving transistor PWM_M3 can be set as the drain, and the second pole PWM_M32 of the pulse width driving transistor PWM_M3 can be set as the source.

[0166] In this embodiment, the gate PWM_M30 of the pulse width driving transistor PWM_M3 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3 do not have an overlapping area in a direction perpendicular to the plane where the substrate is located, and the gate PWM_M30 of the pulse width driving transistor PWM_M3 and the second pole PWM_M32 of the pulse width driving transistor PWM_M3 do not have an overlapping area in a direction perpendicular to the plane where the substrate is located, so as to reduce the parasitic capacitance between the gate PWM_M30 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3, and reduce the pulse width driving transistor The parasitic capacitance between the gate PWM_M30 and the second pole PWM_M32 of the pulse width driving transistor PWM_M3 can be reduced, thereby reducing unnecessary coupling power consumption; at the same time, the mutual interference of the voltage between the gate PWM_M30 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3, and between the gate PWM_M30 and the second pole PWM_M32 of the pulse width driving transistor PWM_M3 can be reduced, thereby helping to accurately control the working state of the pulse width driving transistor PWM_M3, reducing the control difficulty of the pixel driving circuit 11, and thus helping to improve the driving ability of the pixel driving circuit 11.

[0167] Continue to refer Figure 3 , Figure 7-Figure 30Optionally, the pulse width modulation module PWM also includes a first pulse width light emitting control transistor PWM_M1, a second pulse width light emitting control transistor PWM_M6 and a pulse width storage capacitor PWM_C1. The first pole PWM_M11 of the first pulse width light emitting control transistor PWM_M1 is electrically connected to the first power line PWM_VDD, the second pole PWM_M12 of the first pulse width light emitting control transistor PWM_M1 is electrically connected to the first pole PWM_M31 of the pulse width driving transistor PWM_M3, and the gate PWM_M10 of the first pulse width light emitting control transistor PWM_M1 is electrically connected to the pulse width light emitting control signal line PWM_EM. The first pole PWM_M61 of the second pulse width light emitting control transistor PWM_M6 is electrically connected to the second pole PWM_M32 of the pulse width driving transistor PWM_M3, the second pole PWM_M62 of the second pulse width light emitting control transistor PWM_M6 is electrically connected to the amplitude adjustment module PAM, the gate PWM_M60 of the second pulse width light emitting control transistor PWM_M6 is electrically connected to the pulse width light emitting control signal line PWM_EM, and the pulse width storage capacitor PWM_C1 is electrically connected to the gate PWM_M30 of the pulse width driving transistor PWM_M3. Along the second direction Y, the first pulse width light emitting control transistor PWM_M1 and the second pulse width light emitting control transistor PWM_M6 are both located on the side of the second pole PWM_M32 of the pulse width driving transistor PWM_M3 away from the first pole PWM_M31 of the pulse width driving transistor PWM_M3. Along the first direction X, the arrangement direction of the first pulse width light emitting control transistor PWM_M1 and the second pulse width light emitting control transistor PWM_M6 is the same as the arrangement direction of the pulse width driving transistor PWM_M3 and the pulse width storage capacitor PWM_C1.

[0168] Specifically, Figure 3 , Figure 7-Figure 30 As shown, in the pulse width modulation module PWM, the first pulse width light emitting control transistor PWM_M1 is connected in series between the first power line PWM_VDD and the first electrode PWM_M31 of the pulse width driving transistor PWM_M3, and the gate PWM_M10 of the first pulse width light emitting control transistor PWM_M1 receives the first pulse width light emitting control signal provided by the pulse width light emitting control signal line PWM_EM.

[0169] In the pulse width modulation module PWM, the second pulse width light emitting control transistor PWM_M6 is connected in series between the second pole PWM_M32 of the pulse width driving transistor PWM_M3 and the amplitude adjustment module PAM, for example, the second pulse width light emitting control transistor PWM_M6 is connected in series between the second pole PWM_M32 of the pulse width driving transistor PWM_M3 and the gate PAM_M30 of the amplitude driving transistor PAM_M3 in the amplitude adjustment module PAM, at this time, the second pole PWM_M62 of the second pulse width light emitting control transistor PWM_M6 is electrically connected to the gate PAM_M30 of the amplitude driving transistor PAM_M3. At the same time, the gate PWM_M60 of the second pulse width light emitting control transistor PWM_M6 receives the first pulse width light emitting control signal provided by the pulse width light emitting control signal line PWM_EM.

[0170] Further, under the control of the first pulse width light-emitting control signal, the first pulse width light-emitting control transistor PWM_M1 can be turned on to transmit the first power supply voltage provided by the first power line PWM_VDD to the first pole PWM_M31 of the pulse width driving transistor PWM_M3; at the same time, the second pulse width light-emitting control transistor PWM_M6 can also be turned on to connect the second pole PWM_M32 of the pulse width driving transistor PWM_M3 with the amplitude adjustment module PAM, and then connect the first power line PWM_VDD with the amplitude adjustment module PAM, so as to transmit the first power supply voltage provided by the first power line PWM_VDD to the amplitude adjustment module PAM.

[0171] Among them, when the second pole PWM_M62 of the second pulse width light-emitting control transistor PWM_M6 is electrically connected to the gate PAM_M30 of the amplitude driving transistor PAM_M3, the second pulse width light-emitting control transistor PWM_M6 is turned on, which can make the second pole PWM_M32 of the pulse width driving transistor PWM_M3 and the gate PAM_M30 of the amplitude driving transistor PAM_M3 connected, and then make the first power line PWM_VDD and the gate PAM_M30 of the amplitude driving transistor PAM_M3 connected, so as to transmit the first power supply voltage provided by the first power line PWM_VDD to the gate PAM_M30 of the amplitude driving transistor PAM_M3, so as to control the amplitude driving transistor PAM_M3 to be cut off, so as to realize the control of the duration of the driving current provided by the amplitude adjustment module PAM.

[0172] Furthermore, the pulse width storage capacitor PWM_C1 can be connected in series between the sweep signal line SWEEP and the gate PWM_M30 of the pulse width driving transistor PWM_M3. The pulse width storage capacitor PWM_C1 is used to receive the pulse width data signal written to the gate PWM_M30 of the pulse width driving transistor PWM_M3 and maintain the potential of the gate PWM_M30 of the pulse width driving transistor PWM_M3.

[0173] Continue to refer Figure 7 , Fig.21 and Fig.30 In this embodiment, in the second direction Y, the first pulse width light emitting control transistor PWM_M1 and the second pulse width light emitting control transistor PWM_M6 are both located at the lower side of the second pole PWM_M32 of the pulse width driving transistor PWM_M3, and the first pole PWM_M31 of the pulse width driving transistor PWM_M3 is located at the upper side of the second pole PWM_M32 of the pulse width driving transistor PWM_M3. At the same time, in the first direction X, the first pulse width light emitting control transistor PWM_M1 is located at the left side of the second pulse width light emitting control transistor PWM_M6, and the pulse width driving transistor PWM_M3 can also be located at the left side of the pulse width storage capacitor PWM_C1. With such a configuration, the connection path between the first pole PWM_M31 of the pulse width driving transistor PWM_M3 and the second pole PWM_M12 of the first pulse width light emitting control transistor PWM_M1 can bypass the gate PWM_M30 of the pulse width driving transistor PWM_M3, thereby achieving no overlapping area between the first pole PWM_M31 and the gate PWM_M30 of the pulse width driving transistor PWM_M3 in a direction perpendicular to the plane where the substrate is located, reducing the parasitic capacitance between the first pole PWM_M31 and the gate PWM_M30 of the pulse width driving transistor PWM_M3, thereby reducing unnecessary coupling power consumption; at the same time, the mutual interference of the voltage between the first pole PWM_M31 and the gate PWM_M30 of the pulse width driving transistor PWM_M3 can also be reduced, thereby facilitating precise control of the working state of the pulse width driving transistor PWM_M3, reducing the control difficulty of the pixel driving circuit 11, and thereby facilitating improving the driving capability of the pixel driving circuit 11.

[0174] It should be noted that the arrangement direction of the pulse width driving transistor PWM_M3 and the pulse width storage capacitor PWM_C1 may refer to the arrangement direction of the center of gravity of the pulse width driving transistor PWM_M3 and the center of gravity of the pulse width storage capacitor PWM_C1 in the first direction X, wherein the center of gravity refers to the mass-weighted average position of all particles on the film structure, that is, the mass distribution center of the film structure.

[0175] Continue to refer Figure 7 , Fig.21 and Fig.30 Optionally, in order to make the layout of the pixel driving circuit 11 more compact and reduce the size of the pixel driving circuit 11, in the second direction Y, there may be an overlap between the pulse width driving transistor PWM_M3 and the pulse width storage capacitor PWM_C1, but it is not limited to this and the embodiment of the present invention does not make specific limitations on this.

[0176] Continue to refer Figure 3 , Figure 7-Figure 30 Optionally, the first power line PWM_VDD extends along the first direction X. Along the second direction Y, the first pulse width light emitting control transistor PWM_M1 and the second pulse width light emitting control transistor PWM_M6 are both located on a side of the first power line PWM_VDD away from the pulse width driving transistor PWM_M3.

[0177] Specifically, Figure 7 , Fig.21 and Fig.30 As shown, the second electrode PWM_M62 of the second pulse width light emitting control transistor PWM_M6 is electrically connected to the gate PAM_M30 of the amplitude driving transistor PAM_M3. In this embodiment, the extension direction of the first power line PWM_VDD is set to the first direction X, and in the second direction Y, the first power line PWM_VDD is located on the side of the second pulse width light emitting control transistor PWM_M6 away from the amplitude driving transistor PAM_M3, which can avoid the first power line PWM_VDD and the gate PAM_M30 of the amplitude driving transistor PAM_M3 from overlapping in a direction perpendicular to the plane where the substrate is located, thereby reducing the parasitic capacitance between the first power line PWM_VDD and the gate PAM_M30 of the amplitude driving transistor PAM_M3, and avoiding the first power supply voltage on the first power line PWM_VDD from interfering with the potential of the gate PAM_M30 of the amplitude driving transistor PAM_M3, thereby facilitating accurate control of the working state of the amplitude driving transistor PAM_M3, reducing the control difficulty of the pixel driving circuit 11, and further facilitating improving the driving capability of the pixel driving circuit 11.

[0178] At the same time, if Figure 7 , Fig.21 and Fig.30 As shown, in the second direction Y, the first pulse width light emitting control transistor PWM_M1 is also located on the side of the first power line PWM_VDD away from the pulse width driving transistor PWM_M3, which facilitates the first pulse width light emitting control transistor PWM_M1 and the second pulse width light emitting control transistor PWM_M6 to form an electrical connection with the pulse width light emitting control signal line PWM_EM, thereby facilitating the layout of the pixel driving circuit 11 to be more compact and saving the space occupied by the pixel driving circuit 11.

[0179] Continue to refer Figure 3 , Figure 7-Figure 30Optionally, the pulse width modulation module PWM also includes a pulse width compensation transistor PWM_M4, a pulse width gate reset transistor PWM_M5 and a pulse width storage capacitor PWM_C1. The first pole PWM_M41 of the pulse width compensation transistor PWM_M4 is electrically connected to the second pole PWM_M32 of the pulse width driving transistor PWM_M3, the second pole PWM_M42 of the pulse width compensation transistor PWM_M4 is electrically connected to the gate PWM_M30 of the pulse width driving transistor PWM_M3, and the gate PWM_M40 of the pulse width compensation transistor PWM_M4 is electrically connected to the second scanning signal line PWM_S2. The first pole PWM_M51 of the pulse width gate reset transistor PWM_M5 is electrically connected to the first reset signal line PWM_REF, the second pole PWM_M52 of the pulse width gate reset transistor PWM_M5 is electrically connected to the gate PWM_M30 of the pulse width driving transistor PWM_M3, the gate PWM_M50 of the pulse width gate reset transistor PWM_M5 is electrically connected to the first scanning signal line PWM_S1, and the pulse width storage capacitor PWM_C1 is electrically connected to the gate PWM_M30 of the pulse width driving transistor PWM_M3. Along the second direction Y, the pulse width compensation transistor PWM_M4 and the pulse width gate reset transistor PWM_M5 are both located on the side of the first pole PWM_M31 of the pulse width driving transistor PWM_M3 away from the second pole PWM_M32 of the pulse width driving transistor PWM_M3. Along the first direction X, the arrangement direction of the pulse width gate reset transistor PWM_M5 and the pulse width compensation transistor PWM_M4 is the same as the arrangement direction of the pulse width driving transistor PWM_M3 and the pulse width storage capacitor PWM_C1.

[0180] Specifically, Figure 3 , Figure 7-Figure 30 As shown, in the pulse width modulation module PWM, the pulse width compensation transistor PWM_M4 is connected in series between the gate PWM_M30 and the second pole PWM_M32 of the pulse width driving transistor PWM_M3, and the gate PWM_M40 of the pulse width compensation transistor PWM_M4 receives the second scanning signal provided by the second scanning signal line PWM_S2. Under the control of the second scanning signal, the pulse width compensation transistor PWM_M4 is turned on to connect the gate PWM_M30 and the second pole PWM_M32 of the pulse width driving transistor PWM_M3.

[0181] In the pulse width modulation module PWM, the pulse width gate reset transistor PWM_M5 is connected in series between the gate PWM_M30 of the pulse width driving transistor PWM_M3 and the first reset signal line PWM_REF, and the gate PWM_M50 of the pulse width gate reset transistor PWM_M5 receives the second scanning signal provided by the first scanning signal line PWM_S1. Under the control of the second scanning signal, the pulse width gate reset transistor PWM_M5 is turned on, and the first reset signal provided by the first reset signal line PWM_REF is transmitted to the gate PWM_M30 of the pulse width driving transistor PWM_M3 to reset the potential of the gate PWM_M30 of the pulse width driving transistor PWM_M3.

[0182] Furthermore, the structure and connection relationship of the pulse width storage capacitor PWM_C1, and the positional relationship between the pulse width driving transistor PWM_M3 and the pulse width storage capacitor PWM_C1 may refer to any of the above embodiments, and the embodiment of the present invention does not specifically limit this.

[0183] Continue to refer Figure 7 , Fig.21 and Fig.30 In this embodiment, in the second direction Y, the pulse width compensation transistor PWM_M4 and the pulse width gate reset transistor PWM_M5 are both located on the upper side of the first electrode PWM_M31 of the pulse width driving transistor PWM_M3, and the second electrode PWM_M32 of the pulse width driving transistor PWM_M3 is located on the lower side of the first electrode PWM_M31 of the pulse width driving transistor PWM_M3. At the same time, in the first direction X, the pulse width gate reset transistor PWM_M5 is located on the left side of the pulse width compensation transistor PWM_M4, and the pulse width driving transistor PWM_M3 can also be located on the left side of the pulse width storage capacitor PWM_C1.

[0184] With such arrangement, the connection path between the first pole PWM_M41 of the pulse width compensation transistor PWM_M4 and the second pole PWM_M32 of the pulse width driving transistor PWM_M3 can bypass the first pole PWM_M31 of the pulse width driving transistor PWM_M3, thereby achieving that there is no overlapping area between the second pole PWM_M32 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3 in a direction perpendicular to the plane where the substrate is located. While ensuring that there is no overlapping area between the first pole PWM_M31 and the gate PWM_M30 of the pulse width driving transistor PWM_M3 in a direction perpendicular to the plane where the substrate is located, a short circuit between the second pole PWM_M32 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3 can be avoided.

[0185] Continue to refer Fig. 22Optionally, the gate PWM_M30 of the pulse width driving transistor PWM_M3 includes a fourth subdivision 24 extending along the first direction X and a fifth subdivision 25 extending along the second direction Y, the fourth subdivision 24 and the fifth subdivision 25 are connected to each other, and the fourth subdivision 24 and the fifth subdivision 25 are arranged along the first direction X. Along the second direction Y, the boundary of the fourth subdivision 24 close to the first pole PWM_M31 of the pulse width driving transistor PWM_M3 is a ninth boundary S9, and the ninth boundary S9 extends along the first direction X. Along the first direction X, the boundary of the fifth subdivision 25 close to the first pole PWM_M31 of the pulse width driving transistor PWM_M3 is a tenth boundary S10, and the tenth boundary S10 extends along the second direction Y. The ninth boundary S9 and the tenth boundary S10 are adjacent.

[0186] Specifically, Fig. 22 As shown, the fourth section 24 of the gate PWM_M30 extends along the first direction X, and the fifth section 25 extends along the second direction Y, so that a corner structure is formed on the gate PWM_M30, which facilitates the electrical connection between the gate PWM_M30 and the pulse width storage capacitor PWM_C1.

[0187] In the second direction Y, a ninth boundary S9 of the fourth section 24 close to the first pole PWM_M31 of the pulse width driving transistor PWM_M3 extends along the first direction X. In the first direction X, a tenth boundary S10 of the fifth section 25 close to the first pole PWM_M31 of the pulse width driving transistor PWM_M3 extends along the second direction Y. The ninth boundary S9 and the tenth boundary S10 are adjacent, that is, the ninth boundary S9 and the tenth boundary S10 are directly connected, and there is no gap or other boundary between the ninth boundary S9 and the tenth boundary S10. At this time, no chamfer design is adopted between the ninth boundary S9 and the tenth boundary S10, which is beneficial to increase the distance between the adjacent position of the ninth boundary S9 and the tenth boundary S10 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3, thereby reducing the parasitic capacitance between the first pole PWM_M31 and the gate PWM_M30 of the pulse width driving transistor PWM_M3, and reducing unnecessary coupling power consumption; at the same time, it can also reduce the mutual interference of the voltage between the first pole PWM_M31 and the gate PWM_M30 of the pulse width driving transistor PWM_M3, thereby helping to achieve precise control of the working state of the pulse width driving transistor PWM_M3, reducing the control difficulty of the pixel driving circuit 11, and further helping to improve the driving capability of the pixel driving circuit 11.

[0188] For example, Fig. 22As shown, when the first direction X is perpendicular to the second direction Y, the angle θ10 between the ninth boundary S9 and the tenth boundary S10 can be a right angle, that is, θ10=90°, which increases the effective spacing between the junction of the fourth section 24 and the fifth section 25 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3, and reduces the parasitic capacitance between the first pole PWM_M31 and the gate PWM_M30 of the pulse width driving transistor PWM_M3, thereby making the layout of the pixel driving circuit 11 more compact, thereby saving space, but is not limited to this, and the embodiments of the present invention do not make specific limitations on this.

[0189] Fig.31 A schematic diagram of the structure of a gate and a second connection portion of a pulse width driving transistor provided by an embodiment of the present invention, such as Fig.31 As shown, optionally, the gate PWM_M30 of the pulse width driving transistor PWM_M3 includes a fourth subsection 24 extending along the first direction X and a fifth subsection 25 extending along the second direction Y, the fourth subsection 24 and the fifth subsection 25 are connected to each other, and the fourth subsection 24 and the fifth subsection 25 are arranged along the first direction X. The pulse width modulation module PWM also includes a pulse width storage capacitor PWM_C1, the pulse width storage capacitor PWM_C1 includes a second electrode plate PWM_c12, the second electrode plate PWM_c12 includes a second connection subsection 33 connected to the fifth subsection 25, and the fifth subsection 25 and the second connection subsection 33 are arranged along the second direction Y. Along the first direction X, the distance between the fifth subsection 25 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3 is greater than the distance between the second connection subsection 33 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3.

[0190] The structure and position relationship of the pulse width driving transistor PWM_M3 and the pulse width storage capacitor PWM_C1 may refer to any of the above embodiments, and will not be described in detail here.

[0191] In this embodiment, if Fig.31As shown, the second plate PWM_c12 of the pulse width storage capacitor PWM_C1 is electrically connected to the gate PWM_M30 of the pulse width driving transistor PWM_M3, wherein a second connecting section 33 connected to the fifth section 25 of the gate PWM_M30 is arranged on the second plate PWM_c12, and the fifth section 25 and the second connecting section 33 are arranged along the second direction Y, and the first plate PWM_M31 and the second connecting section 33 of the pulse width driving transistor PWM_M3 are arranged along the first direction X, so as to realize the connection between the second plate PWM_c12 of the pulse width storage capacitor PWM_C1 and the pulse width driving transistor PWM_M3. While the gate PWM_M30 of M_M3 is electrically connected, the second pole plate PWM_c12 of the pulse width storage capacitor PWM_C1 and the gate PWM_M30 of the pulse width driving transistor PWM_M3 are arranged around the first pole PWM_M31, ensuring that there is no overlapping area between the first pole PWM_M31 and the gate PWM_M30, and between the first pole PWM_M31 and the second pole plate PWM_c12 in a direction perpendicular to the plane where the substrate is located, thereby reducing the parasitic capacitance between the gate PWM_M30 of the pulse width driving transistor PWM_M3 and the first pole PWM_M31.

[0192] Furthermore, if Fig.31 As shown, in the first direction X, the spacing L5 between the fifth division 25 and the first pole PWM_M31 is set to be greater than the spacing L6 between the second connection division 33 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3, so as to increase the spacing between the fifth division 25 and the first pole PWM_M31 of the gate PWM_M30 in the first direction X, thereby facilitating the reduction of the parasitic capacitance between the gate PWM_M30 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3, and reducing unnecessary coupling power consumption; at the same time, the mutual interference of the voltage between the gate PWM_M30 and the first pole PWM_M31 of the pulse width driving transistor PWM_M3 can also be reduced, thereby facilitating the precise control of the working state of the pulse width driving transistor PWM_M3, reducing the control difficulty of the pixel driving circuit 11, and further facilitating the improvement of the driving capability of the pixel driving circuit 11.

[0193] The spacing L5 between the fifth subdivision 25 and the first pole PWM_M31 may be set to be greater than or equal to 1 μm, so as to ensure that the parasitic capacitance between the gate PWM_M30 of the pulse width driving transistor PWM_M3 and the first pole PWM_M31 is small. Further, the spacing L5 between the fifth subdivision 25 and the first pole PWM_M31 may be set to be greater than or equal to 2.5 μm, so as to ensure that the parasitic capacitance between the gate PWM_M30 of the pulse width driving transistor PWM_M3 and the first pole PWM_M31 is still maintained at a low level under the condition of process error, which is not specifically limited in the embodiment of the present invention.

[0194] It should be noted that the connection structure, specific shape and size between the fifth division 25 of the gate PWM_M30 and the second connection division 33 of the second plate PWM_c12 can refer to the connection structure, specific shape and size between the third division 23 of the first electrode M31 and the first connection division 31 of the first plate c11 in the above embodiment, so as to ensure the electrical connection performance between the gate PWM_M30 and the second plate PWM_c12 while reducing the signal interference between the gate PWM_M30 and other signal lines or nodes and preventing the generation of tip static electricity, which will not be repeated here.

[0195] Continue to refer Figure 3-Figure 9 , Figure 14-Figure 30 Optionally, the amplitude adjustment module PAM may include a first amplitude light emission control transistor PAM_M1, an amplitude data writing transistor PAM_M2, an amplitude driving transistor PAM_M3, an amplitude compensation transistor PAM_M4, an amplitude gate reset transistor PAM_M5, a second amplitude light emission control transistor PAM_M6, an amplitude reset transistor PAM_M7 and an amplitude storage capacitor PAM_C1.

[0196] The amplitude driving transistor PAM_M3 is connected in series between the second power line PAM_VDD and the light emitting element 12, and the amplitude driving transistor PAM_M3 can generate a driving current based on the amplitude data signal and the second power supply voltage provided by the second power line PAM_VDD to drive the light emitting element 12 to emit light. A constant driving current can be generated by providing an amplitude data signal with the same voltage value to the amplitude driving transistor PAM_M3. It should be noted that for the pixel driving circuit 11 connected to light emitting elements 12 of different colors, amplitude data signals with different voltage values ​​can be provided to the amplitude driving transistor PAM_M3 thereof.

[0197] The amplitude gate reset transistor PAM_M5 is connected in series between the second reset signal line PAM_REF and the gate of the amplitude driving transistor PAM_M3. The gate of the amplitude gate reset transistor PAM_M5 receives the third scanning signal provided by the third scanning signal line PAM_S1. Under the control of the third scanning signal, the amplitude gate reset transistor PAM_M5 is turned on to transmit the second reset signal provided by the second reset signal line PAM_REF to the gate of the amplitude driving transistor PAM_M3 to reset the potential of the gate of the amplitude driving transistor PAM_M3.

[0198] The amplitude data write transistor PAM_M2 is connected in series between the amplitude data signal line PAM_DATA and the first electrode of the amplitude driving transistor PAM_M3. The gate of the amplitude data write transistor PAM_M2 receives the fourth scanning signal provided by the fourth scanning signal line PAM_S2. Under the control of the fourth scanning signal, the amplitude data write transistor PAM_M2 is turned on to transmit the amplitude data signal provided by the amplitude data signal line PAM_DATA to the first electrode of the amplitude driving transistor PAM_M3.

[0199] The amplitude compensation transistor PAM_M4 is connected in series between the second electrode of the amplitude driving transistor PAM_M3 and the gate of the amplitude driving transistor PAM_M3. The gate of the amplitude compensation transistor PAM_M4 receives the third scanning signal provided by the third scanning signal line PAM_S1. Under the control of the third scanning signal, the amplitude compensation transistor PAM_M4 is turned on to connect the second electrode of the amplitude driving transistor PAM_M3 and the gate of the amplitude driving transistor PAM_M3.

[0200] The amplitude data writing transistor PAM_M2 and the amplitude compensation transistor PAM_M4 can be turned on under the control of the same third scanning signal to transmit the amplitude data signal provided by the amplitude data signal line PAM_DATA to the gate of the amplitude driving transistor PAM_M3, wherein the threshold voltage of the amplitude driving transistor PAM_M3 is provided to its gate in a self-compensating manner, which can eliminate the influence of the threshold voltage of the amplitude driving transistor PAM_M3 on the magnitude of the driving current generated by it.

[0201] The first amplitude light emitting control transistor PAM_M1 is connected in series between the second power line PAM_VDD and the amplitude driving transistor PAM_M3. The gate of the first amplitude light emitting control transistor PAM_M1 receives the amplitude light emitting control signal provided by the amplitude light emitting control signal line PAM_EM. Under the control of the amplitude light emitting control signal, the first amplitude light emitting control transistor PAM_M1 is turned on to transmit the second power supply voltage provided by the second power line PAM_VDD to the first electrode of the driving transistor PAM_M3.

[0202] The second amplitude light emitting control transistor PAM_M6 is connected in series between the amplitude driving transistor PAM_M3 and the anode of the light emitting element 12. The gate of the second amplitude light emitting control transistor PAM_M6 receives the amplitude light emitting control signal provided by the amplitude light emitting control signal line PAM_EM. Under the control of the amplitude light emitting control signal, the second amplitude light emitting control transistor PAM_M6 is turned on to connect the path between the amplitude driving transistor PAM_M3 and the light emitting element 12.

[0203] The first amplitude light emitting control transistor PAM_M1 and the second amplitude light emitting control transistor PAM_M6 can be turned on under the control of the same amplitude light emitting control signal to connect the driving current path between the second power line PAM_VDD and the light emitting element 12 .

[0204] The amplitude reset transistor PAM_M7 is connected in series to the anode of the light-emitting element 12 and the third reset signal line PAM_INIT. The gate of the amplitude reset transistor PAM_M7 receives the fourth scanning signal provided by the fourth scanning signal line PAM_S2. Under the control of the fourth scanning signal, the amplitude reset transistor PAM_M7 is turned on to transmit the third reset signal provided by the third reset signal line PAM_INIT to the anode of the light-emitting element 12 to reset the potential of the anode of the light-emitting element 12.

[0205] The amplitude storage capacitor PAM_C1 is connected in series between the second power line PAM_VDD and the gate PAM_M30 of the amplitude driving transistor PAM_M3, and is used to receive the amplitude data signal written to the gate PAM_M30 of the amplitude driving transistor PAM_M3 and maintain the potential of the gate PAM_M30 of the amplitude driving transistor PAM_M3, so that the amplitude driving transistor PAM_M3 continues to provide a constant driving current.

[0206] Continue to refer Figure 3-Figure 9 , Figure 14-Figure 30 Optionally, the pulse width modulation module PWM may include a first pulse width light emission control transistor PWM_M1, a pulse width data writing transistor PWM_M2, a pulse width driving transistor PWM_M3, a pulse width compensation transistor PWM_M4, a pulse width gate reset transistor PWM_M5, a second pulse width light emission control transistor PWM_M6 and a pulse width storage capacitor PWM_C1.

[0207] The pulse width driving transistor PWM_M3 is connected in series between the first power line PWM_VDD and the gate of the amplitude driving transistor PAM_M3, and is used to transmit the first power supply voltage provided by the first power line PWM_VDD to the gate of the amplitude driving transistor PAM_M3 to control the amplitude driving transistor PAM_M3 to be cut off, so as to control the conduction time of the amplitude driving transistor PAM_M3, that is, to control the time of the driving current, so that the light-emitting element 12 presents the brightness of the corresponding gray scale.

[0208] The pulse width gate reset transistor PWM_M5 is connected in series between the gate PWM_M30 of the pulse width driving transistor PWM_M3 and the first reset signal line PWM_REF. The gate of the pulse width gate reset transistor PWM_M5 receives the second scanning signal provided by the first scanning signal line PWM_S1. Under the control of the second scanning signal, the pulse width gate reset transistor PWM_M5 is turned on and the first reset signal provided by the first reset signal line PWM_REF is transmitted to the gate of the pulse width driving transistor PWM_M3 to reset the potential of the gate of the pulse width driving transistor PWM_M3.

[0209] The pulse width data writing transistor PWM_M2 is connected in series between the pulse width data signal line PWM_DATA and the first electrode of the pulse width driving transistor PWM_M3. The gate of the pulse width data writing transistor PWM_M2 receives the second scanning signal provided by the second scanning signal line PWM_S2. Under the control of the second scanning signal, the pulse width data writing transistor PWM_M2 is turned on to transmit the pulse width data signal provided by the pulse width data signal line PWM_DATA to the first electrode of the pulse width driving transistor PWM_M3.

[0210] The pulse width compensation transistor PWM_M4 is connected in series between the gate and the second electrode of the pulse width driving transistor PWM_M3. The gate PWM_M40 of the pulse width compensation transistor PWM_M4 receives the second scanning signal provided by the second scanning signal line PWM_S2. Under the control of the second scanning signal, the pulse width compensation transistor PWM_M4 is turned on to connect the gate and the second electrode of the pulse width driving transistor PWM_M3.

[0211] Further, the pulse width data writing transistor PWM_M2 and the pulse width compensation transistor PWM_M4 can be turned on under the control of the same second scanning signal to transmit the pulse width data signal provided by the pulse width data signal line PWM_DATA to the gate of the pulse width driving transistor PWM_M3. The threshold voltage of the pulse width driving transistor PWM_M3 is provided to its gate in a self-compensation manner, which can reduce or eliminate the influence of different pulse width driving transistors PWM_M3 in the display panel on the display uniformity due to different threshold voltages.

[0212] The first pulse width light emitting control transistor PWM_M1 is connected in series between the first power line PWM_VDD and the first pole PWM_M31 of the pulse width driving transistor PWM_M3. The gate of the first pulse width light emitting control transistor PWM_M1 receives the first pulse width light emitting control signal provided by the pulse width light emitting control signal line PWM_EM. Under the control of the first pulse width light emitting control signal, the first pulse width light emitting control transistor PWM_M1 is turned on to transmit the first power supply voltage provided by the first power line PWM_VDD to the first pole of the pulse width driving transistor PWM_M3.

[0213] The second pulse width light emitting control transistor PWM_M6 is connected in series between the second electrode of the pulse width driving transistor PWM_M3 and the gate of the amplitude driving transistor PAM_M3 in the amplitude adjustment module PAM. The gate of the second pulse width light emitting control transistor PWM_M6 receives the first pulse width light emitting control signal provided by the pulse width light emitting control signal line PWM_EM. Under the control of the first pulse width light emitting control signal, the second pulse width light emitting control transistor PWM_M6 is turned on to connect the first power line PWM_VDD and the gate of the amplitude driving transistor PAM_M3, and transmit the first power supply voltage provided by the first power line PWM_VDD to the gate of the amplitude driving transistor PAM_M3, so as to control the amplitude driving transistor PAM_M3 to be cut off, thereby controlling the duration of the driving current provided by the amplitude adjustment module PAM.

[0214] The pulse width storage capacitor PWM_C1 is connected in series between the sweep signal line SWEEP and the gate of the pulse width driving transistor PWM_M3. The pulse width storage capacitor PWM_C1 is used to receive the pulse width data signal written to the gate of the pulse width driving transistor PWM_M3 and maintain the potential of the gate of the pulse width driving transistor PWM_M3.

[0215] The sweep signal line SWEEP is used to provide a sweep signal, and the sweep signal can be in the form of a triangular wave. For example, the sweep signal can be linearly reduced from a high level to a low level, or the sweep signal can be linearly increased from a low level to a high level. When the pulse of the sweep signal is applied to the pulse width storage capacitor PWM_C1, through the bootstrap effect of the pulse width storage capacitor PWM_C1, the potential on the other plate of the pulse width storage capacitor PWM_C1 (the plate connected to the gate of the pulse width driving transistor PWM_M3) changes synchronously accordingly, that is, the pulse change of the sweep signal can be reflected to the potential of the gate of the pulse width driving transistor PWM_M3 through the pulse width storage capacitor PWM_C1, and the potential of the gate of the pulse width driving transistor PWM_M3 changes linearly synchronously.

[0216] The working process of the pixel driving circuit 11 may include but is not limited to a first resetting stage, a first data writing stage, a second resetting stage, a second data writing stage and a light emitting stage.

[0217] In the first reset stage, the third scan signal provided by the third scan signal line PAM_S1 controls the amplitude gate reset transistor PAM_M5 to turn on, and the second reset signal provided by the second reset signal line PAM_REF is transmitted to the gate of the amplitude driving transistor PAM_M3 through the amplitude gate reset transistor PAM_M5, then the potential of the gate of the amplitude driving transistor PAM_M3 is the same as the potential of the second reset signal.

[0218] In the first data writing stage, the fourth scanning signal provided by the fourth scanning signal line PAM_S2 controls the amplitude data writing transistor PAM_M2 and the amplitude compensation transistor PAM_M4 to be turned on, and the amplitude data signal provided by the amplitude data signal line PAM_DATA is written into the gate of the amplitude driving transistor PAM_M3. The potential of the gate of the amplitude driving transistor PAM_M3 also includes the threshold voltage of the self-compensated amplitude driving transistor PAM_M3, which can eliminate the influence of the threshold voltage of the amplitude driving transistor PAM_M3 on the magnitude of the driving current generated by it.

[0219] At the same time, in the first data writing stage, optionally, the fourth scanning signal provided by the fourth scanning signal line PAM_S2 controls the amplitude reset transistor PAM_M7 to turn on, so as to transmit the third reset signal provided by the third reset signal line PAM_INIT to the anode of the light-emitting element 12, thereby resetting the potential of the anode of the light-emitting element 12.

[0220] In the second reset stage, the second scanning signal provided by the first scanning signal line PWM_S1 controls the pulse width gate reset transistor PWM_M5 to turn on, and the first reset signal provided by the first reset signal line PWM_REF is transmitted to the gate of the pulse width driving transistor PWM_M3 through the pulse width gate reset transistor PWM_M5, then the potential of the gate of the pulse width driving transistor PWM_M3 is the same as the potential of the first reset signal.

[0221] In the second data writing phase, the second scanning signal provided by the second scanning signal line PWM_S2 controls the pulse width data writing transistor PWM_M2 and the pulse width compensation transistor PWM_M4 to be turned on, and the pulse width data signal provided by the pulse width data signal line PWM_DATA is written into the gate of the pulse width driving transistor PWM_M3. The potential of the gate of the pulse width driving transistor PWM_M3 also includes the threshold voltage of the self-compensated pulse width driving transistor PWM_M3, which can reduce or eliminate the influence of different pulse width driving transistors PWM_M3 in the display panel on the display uniformity due to different threshold voltages.

[0222] In the light-emitting stage, the amplitude light-emitting control signal provided by the amplitude light-emitting control signal line PAM_EM controls the first amplitude light-emitting control transistor PAM_M1 and the second amplitude light-emitting control transistor PAM_M6 to be turned on, and the first pulse width light-emitting control signal provided by the pulse width light-emitting control signal line PWM_EM controls the first pulse width light-emitting control transistor PWM_M1 and the second pulse width light-emitting control transistor PWM_M6 to be turned on. The voltage value of the sweep signal provided by the sweep signal line SWEEP changes linearly, and is reflected to the gate of the pulse width driving transistor PWM_M3 through the bootstrap effect of the pulse width storage capacitor PWM_C1, so that the potential of the gate of the pulse width driving transistor PWM_M3 changes synchronously.

[0223] Taking the pulse width driving transistor PWM_M3 using a P-type transistor as an example, the frequency sweep signal can be linearly reduced from a high level to a low level.

[0224] Among them, when the pulse width driving transistor PWM_M3 is in the cut-off state, the first power supply voltage provided by the first power line PWM_VDD will not be transmitted to the gate of the amplitude driving transistor PAM_M3. The amplitude driving transistor PAM_M3 generates a driving current based on the amplitude data signal provided by the amplitude data signal line PAM_DATA and the second power supply voltage provided by the second power line PAM_VDD, so that the light-emitting element 12 emits light.

[0225] Furthermore, in the process of linear reduction of the sweep frequency signal, the potential of the gate of the pulse width driving transistor PWM_M3 decreases synchronously. When the gate potential of the pulse width driving transistor PWM_M3 changes to be equivalent to or less than the source potential (i.e., the first power supply voltage provided by the first power line PWM_VDD), the pulse width driving transistor PWM_M3 is turned on, thereby transmitting the first power supply voltage provided by the first power line PWM_VDD to the gate of the amplitude driving transistor PAM_M3, so that the amplitude driving transistor PAM_M3 is turned off, and the amplitude driving transistor PAM_M3 no longer provides a driving current to the light-emitting element 12, thereby driving the light-emitting element 12 to stop emitting light.

[0226] Continue to refer Figure 14-Figure 21 Optionally, the pulse width regulation module PWM also includes a sweeping transistor PWM_M7, which is connected in series between the sweeping constant voltage signal line SWEEP_GND and the pulse width storage capacitor PWM_C1 (for example, the plate in the pulse width storage capacitor PWM_C1 connected to the sweeping signal line SWEEP), and the gate of the sweeping transistor PWM_M7 receives the second scanning signal provided by the second scanning signal line PWM_S2. Under the control of the second scanning signal, the sweeping transistor PWM_M7 is turned on to transmit the sweeping constant voltage provided by the sweeping constant voltage signal line SWEEP_GND to the pulse width storage capacitor PWM_C1. The sweeping constant voltage can be the same as the high level of the sweeping signal, or the same as the low level of the sweeping signal. At this time, the swept frequency constant voltage signal line SWEEP_GND and the swept frequency signal line SWEEP both provide signals to one plate of the pulse width storage capacitor PWM_C1 (for example, the plate in the pulse width storage capacitor PWM_C1 connected to the swept frequency signal line SWEEP), which can further ensure the stability of the plate potential of the pulse width storage capacitor PWM_C1 and reduce the signal disturbance caused by peripheral signals.

[0227] Continue to refer Figure 14-Figure 21Optionally, the amplitude adjustment module PAM also includes an eighth transistor PAM_M8, ​​which is connected in series between the amplitude storage capacitor PAM_C1 and the second power line PAM_VDD. The gate of the eighth transistor PAM_M8 receives a first pulse width light-emitting control signal provided by the pulse width light-emitting control signal line PWM_EM. Under the control of the first pulse width light-emitting control signal, the eighth transistor PAM_M8 is turned on to transmit the second power supply voltage provided by the second power line PAM_VDD to the amplitude storage capacitor PAM_C1, thereby applying the second power supply voltage to the amplitude adjustment module PAM in the light-emitting stage to provide a driving current to the light-emitting element 12.

[0228] Continue to refer Figure 14-Figure 21 Optionally, the amplitude adjustment module PAM also includes a ninth transistor PAM_M9 and a tenth transistor PAM_M10, the ninth transistor PAM_M9 is connected in series between the first power line PWM_VDD and the amplitude storage capacitor PAM_C1, the gate of the ninth transistor PAM_M9 receives the third scan signal provided by the third scan signal line PAM_S1, and under the control of the third scan signal, the ninth transistor PAM_M9 is turned on to transmit the first power voltage provided by the first power line PWM_VDD to the amplitude storage capacitor PAM_C1; the tenth transistor PAM_M10 is also connected in series between the first power line PWM_VDD and the amplitude storage capacitor PAM_C1, the gate of the tenth transistor PAM_M10 receives the fourth scan signal provided by the fourth scan signal line PAM_S2, and under the control of the fourth scan signal, the tenth transistor PAM_M10 is turned on to transmit the first power voltage provided by the first power line PWM_VDD to the amplitude storage capacitor PAM_C1, thereby applying the first power voltage to the amplitude adjustment module PAM in the first reset phase and the first data writing phase.

[0229] Continue to refer Figure 14-Figure 21 Optionally, the amplitude adjustment module PAM also includes a second capacitor PAM_C2, which is connected in series between the third reset signal line PAM_INIT and the amplitude storage capacitor PAM_C1 and can be used to stabilize the plate potential of the amplitude storage capacitor PAM_C1.

[0230] Optionally, in the pixel driving circuit 11, some transistors are dual-gate transistors, wherein the dual-gate transistor may include two transistors connected in series, and two gates of the dual-gate transistor receive the same control signal.

[0231] For example, Figure 3 and Fig.14As shown, the amplitude compensation transistor PAM_M4 and the amplitude gate reset transistor PAM_M5 in the amplitude adjustment module PAM can adopt dual-gate transistors to reduce the leakage current of the amplitude compensation transistor PAM_M4 and the amplitude gate reset transistor PAM_M5, thereby reducing the influence of the leakage current on the potential of the gate of the amplitude driving transistor PAM_M3.

[0232] For example, Figure 3 and Fig.14 As shown, the pulse width compensation transistor PWM_M4 and the pulse width gate reset transistor PWM_M5 in the pulse width modulation module PWM can adopt dual-gate transistors to reduce the leakage current in the pulse width compensation transistor PWM_M4 and the pulse width gate reset transistor PWM_M5, thereby reducing the influence of the leakage current on the potential of the gate of the pulse width driving transistor PWM_M3.

[0233] It should be noted that, in the above embodiments, Figure 3 An exemplary circuit structure of 13T2C (i.e., comprising 13 transistors and 2 capacitors) is shown. Fig.14 A circuit structure of 17T3C (including 17 transistors and 3 capacitors) is exemplarily illustrated, but is not limited thereto and is not specifically limited in the embodiments of the present invention.

[0234] Continue to refer Figure 15-Figure 30 Optionally, the active layer of the first amplitude light emitting control transistor PAM_M1, the amplitude data writing transistor PAM_M2, the amplitude driving transistor PAM_M3, the amplitude compensation transistor PAM_M4, the amplitude gate reset transistor PAM_M5, the second amplitude light emitting control transistor PAM_M6, the amplitude reset transistor PAM_M7, the first pulse width light emitting control transistor PWM_M1, the pulse width data writing transistor PWM_M2, the pulse width driving transistor PWM_M3, the pulse width compensation transistor PWM_M4, the pulse width gate reset transistor PWM_M5 and the second pulse width light emitting control transistor PWM_M6 can be located in the semiconductor layer POLY.

[0235] The bottom gates of the first amplitude light emitting control transistor PAM_M1, the amplitude data writing transistor PAM_M2, the amplitude driving transistor PAM_M3, the amplitude compensation transistor PAM_M4, the amplitude gate reset transistor PAM_M5, the second amplitude light emitting control transistor PAM_M6, the amplitude reset transistor PAM_M7, the first pulse width light emitting control transistor PWM_M1, the pulse width data writing transistor PWM_M2, the pulse width driving transistor PWM_M3, the pulse width compensation transistor PWM_M4, the pulse width gate reset transistor PWM_M5 and the second pulse width light emitting control transistor PWM_M6 can be located in the first metal layer M0.

[0236] The first amplitude light emitting control transistor PAM_M1, the amplitude data writing transistor PAM_M2, the amplitude driving transistor PAM_M3, the amplitude compensation transistor PAM_M4, the amplitude gate reset transistor PAM_M5, the second amplitude light emitting control transistor PAM_M6, the amplitude reset transistor PAM_M7, the first pulse width light emitting control transistor PWM_M1, the pulse width data writing transistor PWM_M2, the pulse width driving transistor PWM_M3, the pulse width compensation transistor PWM_M4, the pulse width gate reset transistor PWM_M5 and the top gate of the second pulse width light emitting control transistor PWM_M6, as well as the amplitude storage capacitor PAM_C1 and one plate of the pulse width storage capacitor PWM_C1 can be located in the second metal layer GAT.

[0237] The second metal layer GAT may also include a first scan signal line PWM_S1, a second scan signal line PWM_S2, a frequency sweep signal line SWEEP, a first power line PWM_VDD, a pulse width light emitting control signal line PWM_EM, a third reset signal line PAM_INIT, a third scan signal line PAM_S1, a fourth scan signal line PAM_S2 and an amplitude light emitting control signal line PAM_EM extending along the first direction X.

[0238] The third metal layer MC may include the other plates of the amplitude storage capacitor PAM_C1 and the pulse width storage capacitor PWM_C1 , and the first reset signal line PWM_REF and the second reset signal line PAM_REF extending along the first direction X.

[0239] The fourth metal layer SD1 may include a pulse width data signal line PWM_DATA and an amplitude data signal line PAM_DATA extending along the second direction Y.

[0240] Continue to refer Figure 15-Figure 21 Optionally, active layers of the frequency sweep transistor PWM_M7, the eighth transistor PAM_M8, ​​the ninth transistor PAM_M9 and the tenth transistor PAM_M10 may be located in the semiconductor layer POLY.

[0241] Bottom gates of the frequency sweep transistor PWM_M7 , the eighth transistor PAM_M8 , the ninth transistor PAM_M9 , and the tenth transistor PAM_M10 may be located in the first metal layer M0 .

[0242] The top gates of the frequency scanning transistor PWM_M7 , the eighth transistor PAM_M8 , the ninth transistor PAM_M9 , and the tenth transistor PAM_M10 , and one plate of the second capacitor PAM_C2 may be located in the second metal layer GAT.

[0243] The second metal layer GAT may further include a swept frequency constant voltage signal line SWEEP_GND extending along the first direction X.

[0244] The third metal layer MC may further include another electrode plate of the second capacitor PAM_C2.

[0245] It should be noted that the specific film layer settings of the display panel can be adaptively adjusted according to actual needs, such as adding or removing some film layers, and the embodiments of the present invention do not specifically limit this.

[0246] Continue to refer Figure 7 , Fig.21 and Fig.30 Optionally, there is an overlapping area between the routing extending along the first direction X and the routing extending along the second direction Y. In the overlapping area, the overlapping area between the routing extending along the first direction X and the routing extending along the second direction Y can be reduced by reducing the line width of the routing extending along the first direction X and / or reducing the line width of the routing extending along the second direction Y, thereby reducing the parasitic capacitance formed between the routing extending along the first direction X and the routing extending along the second direction Y, and further reducing unnecessary coupling power consumption; at the same time, the mutual interference of the voltage between the routing extending along the first direction X and the routing extending along the second direction Y can also be reduced, thereby facilitating accurate control of the potential of each node, reducing the control difficulty of the pixel driving circuit 11, and thereby facilitating improving the driving capability of the pixel driving circuit 11.

[0247] For example, Figure 16-Figure 21 as well as Figure 25-Figure 30 As shown, optionally, the pulse width data writing transistor PWM_M2 is connected to the first electrode PWM_M31 of the pulse width driving transistor PWM_M3 through the first signal line a1 extending along the second direction Y, and the sweep signal line SWEEP extends along the first direction X. In the direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the first signal line a1 and the sweep signal line SWEEP is the first area Z1, and the line width of the first signal line a1 in the first area Z1 is set to be smaller than the line width of the first signal line a1 in the area other than the first area Z1, so as to narrow the first signal line a1 in the first area Z1, thereby reducing the overlapping area between the first signal line a1 and the sweep signal line SWEEP, and further reducing the parasitic capacitance formed between the first signal line a1 and the sweep signal line SWEEP.

[0248] like Figure 16-Figure 21 as well as Figure 25-Figure 30As shown, optionally, the pulse width compensation transistor PWM_M4 is connected to the second electrode PWM_M32 of the pulse width driving transistor PWM_M3 through a second signal line a2 extending along the second direction Y, and the sweep signal line SWEEP extends along the first direction X. In a direction perpendicular to the plane where the substrate is located, the overlapping area of ​​the second signal line a2 and the sweep signal line SWEEP is the second area Z2, and the line width of the second signal line a2 in the second area Z2 is set to be smaller than the line width of the second signal line a2 in the area other than the second area Z2, so as to narrow the second signal line a2 in the second area Z2, thereby reducing the overlapping area between the second signal line a2 and the sweep signal line SWEEP, and further reducing the parasitic capacitance formed between the second signal line a2 and the sweep signal line SWEEP.

[0249] like Figure 16-Figure 21 as well as Figure 25-Figure 30 As shown, optionally, the first electrode PWM_M31 of the pulse width driving transistor PWM_M3 is connected to the first pulse width emission control transistor PWM_M1 through a third signal line a3 extending along the second direction Y, the first power line PWM_VDD extends along the first direction X, and the pulse width emission control signal line PWM_EM extends along the first direction X. Along a direction perpendicular to the plane where the substrate is located, the overlapping area of ​​the third signal line a3 and the first power line PWM_VDD is the third area Z3, and the overlapping area of ​​the third signal line a3 and the pulse width light-emitting control signal line PWM_EM is the fourth area Z4. The line width of the third signal line a3 in the third area Z3 and the fourth area Z4 is set to be smaller than the line width of the third signal line a3 in areas other than the third area Z3 and the fourth area Z4, so as to narrow the third signal line a3 in the third area Z3 and the fourth area Z4, thereby reducing the overlapping area between the third signal line a3 and the first power line PWM_VDD and the pulse width light-emitting control signal line PWM_EM, and further reducing the parasitic capacitance formed between the third signal line a3 and the first power line PWM_VDD and the pulse width light-emitting control signal line PWM_EM.

[0250] like Figure 16-Figure 21 as well as Figure 25-Figure 30As shown, optionally, the second pulse width light emitting control transistor PWM_M6 is connected to the second electrode PWM_M32 of the pulse width driving transistor PWM_M3 through a fourth signal line a4 extending along the second direction Y, and the first power line PWM_VDD extends along the first direction X. In a direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the fourth signal line a4 and the first power line PWM_VDD is the fifth area Z5, and the line width of the fourth signal line a4 in the fifth area Z5 is set to be smaller than the line width of the fourth signal line a4 in the area other than the fifth area Z5, so as to narrow the fourth signal line a4 in the fifth area Z5, thereby reducing the overlapping area between the fourth signal line a4 and the first power line PWM_VDD, and further reducing the parasitic capacitance formed between the fourth signal line a4 and the first power line PWM_VDD.

[0251] like Figure 25-Figure 30 As shown, optionally, the line width of the first power line PWM_VDD in the third area Z3 and the fifth area Z5 is smaller than the line width of the first power line PWM_VDD in areas other than the third area Z3 and the fifth area Z5, so as to narrow the first power line PWM_VDD in the third area Z3 and the fifth area Z5, thereby reducing the overlapping area between the first power line PWM_VDD and the third signal line a3 and the fourth signal line a4, and further reducing the parasitic capacitance formed between the first power line PWM_VDD and the third signal line a3 and the fourth signal line a4.

[0252] like Figure 16-Figure 21 as well as Figure 25-Figure 30 As shown, optionally, the second pulse width light emitting control transistor PWM_M6 is connected to the amplitude storage capacitor PAM_C1 through the fifth signal line a5 extending along the second direction Y, and the fourth scanning signal line PAM_S2 extends along the first direction X. In the direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the fifth signal line a5 and the fourth scanning signal line PAM_S2 is the sixth area Z6, and the line width of the fifth signal line a5 in the sixth area Z6 is set to be smaller than the line width of the fifth signal line a5 in the area other than the sixth area Z6, so as to narrow the fifth signal line a5 in the sixth area Z6, thereby reducing the overlapping area between the fifth signal line a5 and the fourth scanning signal line PAM_S2, and further reducing the parasitic capacitance formed between the fifth signal line a5 and the fourth scanning signal line PAM_S2.

[0253] like Figure 16-Figure 21 as well as Figure 25-Figure 30As shown, optionally, the frequency scanning transistor PWM_M7 is connected to the third reset signal line PAM_INIT through a sixth signal line a6 extending along the second direction Y, the second reset signal line PAM_REF extends along the first direction X, and the third scanning signal line PAM_S1 extends along the first direction X. Along the direction perpendicular to the plane of the substrate, the overlapping area of ​​the sixth signal line a6 and the second reset signal line PAM_REF is the seventh area Z7, and the overlapping area of ​​the sixth signal line a6 and the third scanning signal line PAM_S1 is the eighth area Z8. The line width of the sixth signal line a6 in the seventh area Z7 and the eighth area Z8 is set to be smaller than the line width of the sixth signal line a6 in areas other than the seventh area Z7 and the eighth area Z8, so as to narrow the sixth signal line a6 in the seventh area Z7 and the eighth area Z8, thereby reducing the overlapping area between the sixth signal line a6, the second reset signal line PAM_REF and the third scanning signal line PAM_S1, and further reducing the parasitic capacitance formed between the sixth signal line a6, the second reset signal line PAM_REF and the third scanning signal line PAM_S1.

[0254] like Figure 16-Figure 21 as well as Figure 25-Figure 30 As shown, optionally, the amplitude data signal line PAM_DATA extends along the second direction Y, the fourth scan signal line PAM_S2 extends along the first direction X, and the amplitude light emitting control signal line PAM_EM extends along the first direction X. Along the direction perpendicular to the plane where the substrate is located, the overlapping area of ​​the amplitude data signal line PAM_DATA and the fourth scanning signal line PAM_S2 is the ninth area Z9, and the overlapping area of ​​the amplitude data signal line PAM_DATA and the amplitude light-emitting control signal line PAM_EM is the tenth area Z10. The line width of the amplitude data signal line PAM_DATA in the ninth area Z9 and the tenth area Z10 is set to be smaller than the line width of the amplitude data signal line PAM_DATA in areas other than the ninth area Z9 and the tenth area Z10, so as to narrow the amplitude data signal line PAM_DATA in the ninth area Z9 and the tenth area Z10, thereby reducing the overlapping area between the amplitude data signal line PAM_DATA and the fourth scanning signal line PAM_S2 and the amplitude light-emitting control signal line PAM_EM, and further reducing the parasitic capacitance formed between the amplitude data signal line PAM_DATA and the amplitude light-emitting control signal line PAM_EM.

[0255] like Figure 16-Figure 21 as well as Figure 25-Figure 30As shown, optionally, the pulse width compensation transistor PWM_M4 is connected to the pulse width storage capacitor PWM_C1 through the eighth signal line a8 extending along the second direction Y, and the sweep signal line SWEEP extends along the first direction X. In the direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the eighth signal line a8 and the sweep signal line SWEEP is the twelfth area Z12. The line width of the eighth signal line a8 in the twelfth area Z12 is set to be smaller than the line width of the eighth signal line a8 in the area other than the twelfth area Z12, so as to narrow the eighth signal line a8 in the twelfth area Z12, thereby reducing the overlapping area between the eighth signal line a8 and the sweep signal line SWEEP, and further reducing the parasitic capacitance formed between the eighth signal line a8 and the sweep signal line SWEEP.

[0256] like Figure 16-Figure 21 as well as Figure 25-Figure 30 As shown, optionally, the pulse width compensation transistor PWM_M4 is connected to the pulse width storage capacitor PWM_C1 through the eighth signal line a8 extending along the second direction Y, and the second scanning signal line PWM_S2 extends along the first direction X. In the direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the eighth signal line a8 and the second scanning signal line PWM_S2 is the thirteenth area Z13. The line width of the eighth signal line a8 in the thirteenth area Z13 is set to be smaller than the line width of the eighth signal line a8 in the area other than the thirteenth area Z13, so as to narrow the eighth signal line a8 in the thirteenth area Z13, thereby reducing the overlapping area between the eighth signal line a8 and the second scanning signal line PWM_S2, and further reducing the parasitic capacitance formed between the eighth signal line a8 and the second scanning signal line PWM_S2.

[0257] like Figure 16-Figure 21As shown, optionally, the ninth transistor PAM_M9 is connected to the first power line PWM_VDD through the ninth signal line a9 extending along the second direction Y, the pulse width light emitting control signal line PWM_EM extends along the first direction X, the third reset signal line PAM_INIT extends along the first direction X, the second reset signal line PAM_REF extends along the first direction X, and the third scan signal line PAM_S1 extends along the first direction X. In the direction perpendicular to the plane where the substrate is located, the overlapping area of ​​the ninth signal line a9 and the pulse width light emitting control signal line PWM_EM is the fifteenth area Z15, the overlapping area of ​​the ninth signal line a9 and the third reset signal line PAM_INIT is the sixteenth area Z16, the overlapping area of ​​the ninth signal line a9 and the second reset signal line PAM_REF is the seventeenth area Z17, and the overlapping area of ​​the ninth signal line a9 and the third scan signal line PAM_S1 is the eighteenth area Z18. The line width of the ninth signal line a9 in the fifteenth area Z15, the sixteenth area Z16, the seventeenth area Z17 and the eighteenth area Z18 is set to be smaller than the line width of the ninth signal line a9 in areas other than the fifteenth area Z15, the sixteenth area Z16, the seventeenth area Z17 and the eighteenth area Z18, so as to narrow the ninth signal line a9 in the fifteenth area Z15, the sixteenth area Z16, the seventeenth area Z17 and the eighteenth area Z18, thereby reducing the overlapping area between the ninth signal line a9 and the pulse width light emitting control signal line PWM_EM, the third reset signal line PAM_INIT, the second reset signal line PAM_REF and the third scanning signal line PAM_S1, and further reducing the parasitic capacitance formed between the ninth signal line a9 and the pulse width light emitting control signal line PWM_EM, the third reset signal line PAM_INIT, the second reset signal line PAM_REF and the third scanning signal line PAM_S1.

[0258] Continue to refer Figure 7 , Fig.21 and Fig.30Optionally, there is an overlapping area between the routing extending along the first direction X and the routing extending along the second direction Y. In the overlapping area, an opening can be provided on the routing extending along the first direction X, and the opening overlaps with the routing extending along the second direction Y in a direction perpendicular to the plane where the substrate is located, and / or an opening is provided on the routing extending along the second direction Y, and the opening overlaps with the routing extending along the first direction X in a direction perpendicular to the plane where the substrate is located, so as to reduce the overlapping area between the routing extending along the first direction X and the routing extending along the second direction Y, thereby reducing the parasitic capacitance formed between the routing extending along the first direction X and the routing extending along the second direction Y, and further reducing unnecessary coupling power consumption; at the same time, the mutual interference of voltage between the routing extending along the first direction X and the routing extending along the second direction Y can also be reduced, thereby facilitating accurate control of the potential of each node, reducing the control difficulty of the pixel driving circuit 11, and thereby facilitating improving the driving capability of the pixel driving circuit 11.

[0259] For example, Figure 16-Figure 21 as well as Figure 25-Figure 30 As shown, optionally, the second amplitude light emitting control transistor PAM_M6 is connected to the light emitting element through the seventh signal line a7 extending along the second direction Y, and the amplitude light emitting control signal line PAM_EM extends along the first direction X. In the direction perpendicular to the plane where the substrate is located, the overlapping area of ​​the seventh signal line a7 and the amplitude light emitting control signal line PAM_EM is the eleventh area Z11, and the amplitude light emitting control signal line PAM_EM is provided with a first opening h1 in the eleventh area Z11, and in the direction perpendicular to the plane where the substrate is located, the first opening h1 at least partially overlaps with the seventh signal line a7, thereby reducing the overlapping area between the amplitude light emitting control signal line PAM_EM and the seventh signal line a7, and further reducing the parasitic capacitance formed between the amplitude light emitting control signal line PAM_EM and the seventh signal line a7.

[0260] like Figure 16-Figure 21As shown, optionally, the amplitude data signal line PAM_DATA extends along the second direction Y, and the amplitude light emitting control signal line PAM_EM extends along the first direction X. In the direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the amplitude data signal line PAM_DATA and the amplitude light emitting control signal line PAM_EM is the tenth area Z10, and the amplitude light emitting control signal line PAM_EM is provided with a second opening h2 in the tenth area Z10, and in the direction perpendicular to the plane where the substrate substrate is located, the second opening h2 at least partially overlaps with the amplitude data signal line PAM_DATA, thereby reducing the overlapping area between the amplitude light emitting control signal line PAM_EM and the amplitude data signal line PAM_DATA, and further reducing the parasitic capacitance formed between the amplitude light emitting control signal line PAM_EM and the amplitude data signal line PAM_DATA.

[0261] like Figure 16-Figure 21 As shown, optionally, the first electrode PWM_M31 of the pulse width driving transistor PWM_M3 is connected to the first pulse width light emitting control transistor PWM_M1 through a third signal line a3 extending along the second direction Y, and the first power line PWM_VDD extends along the first direction X. In a direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the third signal line a3 and the first power line PWM_VDD is a third area Z3. The first power line PWM_VDD is provided with a third opening h3 in the third area Z3, and in a direction perpendicular to the plane where the substrate substrate is located, the third opening h3 at least partially overlaps with the third signal line a3, thereby reducing the overlapping area between the first power line PWM_VDD and the third signal line a3, and further reducing the parasitic capacitance formed between the first power line PWM_VDD and the third signal line a3.

[0262] like Figure 16-Figure 21 As shown, optionally, the second pulse width light emitting control transistor PWM_M6 is connected to the second pole PWM_M32 of the pulse width driving transistor PWM_M3 through a fourth signal line a4 extending along the second direction Y, and the first power line PWM_VDD extends along the first direction X. In a direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the fourth signal line a4 and the first power line PWM_VDD is the fifth area Z5. The first power line PWM_VDD is provided with a fourth opening h4 in the fifth area Z5, and in a direction perpendicular to the plane where the substrate substrate is located, the fourth opening h4 at least partially overlaps with the fourth signal line a4, thereby reducing the overlapping area between the first power line PWM_VDD and the fourth signal line a4, and further reducing the parasitic capacitance formed between the first power line PWM_VDD and the fourth signal line a4.

[0263] like Figure 16-Figure 21As shown, optionally, the pulse width data writing transistor PWM_M2 is connected to the first pole PWM_M31 of the pulse width driving transistor PWM_M3 through the first signal line a1 extending along the second direction Y, and the frequency sweeping signal line SWEEP extends along the first direction X. In the direction perpendicular to the plane where the substrate is located, the overlapping area of ​​the first signal line a1 and the frequency sweeping signal line SWEEP is the first area Z1. The frequency sweeping signal line SWEEP is provided with a fifth opening h5 in the first area Z1, and in the direction perpendicular to the plane where the substrate is located, the fifth opening h5 at least partially overlaps with the first signal line a1, thereby reducing the overlapping area between the frequency sweeping signal line SWEEP and the first signal line a1, and further reducing the parasitic capacitance formed between the frequency sweeping signal line SWEEP and the first signal line a1.

[0264] like Figure 16-Figure 21 As shown, optionally, the pulse width compensation transistor PWM_M4 is connected to the second pole PWM_M32 of the pulse width driving transistor PWM_M3 through a second signal line a2 extending along the second direction Y, and the frequency sweeping signal line SWEEP extends along the first direction X. In a direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the second signal line a2 and the frequency sweeping signal line SWEEP is the second area Z2. The frequency sweeping signal line SWEEP is provided with a sixth opening h6 in the second area Z2, and in a direction perpendicular to the plane where the substrate substrate is located, the sixth opening h6 at least partially overlaps with the second signal line a2, thereby reducing the overlapping area between the frequency sweeping signal line SWEEP and the second signal line a2, and further reducing the parasitic capacitance formed between the frequency sweeping signal line SWEEP and the second signal line a2.

[0265] like Figure 16-Figure 21 As shown, optionally, the pulse width compensation transistor PWM_M4 is connected to the pulse width storage capacitor PWM_C1 through the eighth signal line a8 extending along the second direction Y, and the sweep signal line SWEEP extends along the first direction X. In the direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the eighth signal line a8 and the sweep signal line SWEEP is the twelfth area Z12. The sweep signal line SWEEP is provided with a seventh opening h7 in the twelfth area Z12, and in the direction perpendicular to the plane where the substrate substrate is located, the seventh opening h7 at least partially overlaps with the eighth signal line a8, thereby reducing the overlapping area between the sweep signal line SWEEP and the eighth signal line a8, and further reducing the parasitic capacitance formed between the sweep signal line SWEEP and the eighth signal line a8.

[0266] like Figure 16-Figure 21As shown, optionally, the pulse width data signal line PWM_DATA extends along the second direction Y, and the swept frequency constant voltage signal line SWEEP_GND extends along the first direction X. In the direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the pulse width data signal line PWM_DATA and the swept frequency constant voltage signal line SWEEP_GND is the fourteenth area Z14. The swept frequency constant voltage signal line SWEEP_GND is provided with an eighth opening h8 in the fourteenth area Z14, and in the direction perpendicular to the plane where the substrate substrate is located, the eighth opening h8 at least partially overlaps with the pulse width data signal line PWM_DATA, thereby reducing the overlapping area between the swept frequency constant voltage signal line SWEEP_GND and the pulse width data signal line PWM_DATA, and further reducing the parasitic capacitance formed between the swept frequency constant voltage signal line SWEEP_GND and the pulse width data signal line PWM_DATA.

[0267] like Figure 16-Figure 21 As shown, optionally, the ninth transistor PAM_M9 is connected to the first power line PWM_VDD through a ninth signal line a9 extending along the second direction Y, and the third reset signal line PAM_INIT extends along the first direction X. In a direction perpendicular to the plane where the substrate substrate is located, the overlapping area of ​​the ninth signal line a9 and the third reset signal line PAM_INIT is the sixteenth area Z16. The third reset signal line PAM_INIT is provided with a ninth opening h9 in the sixteenth area Z16, and in a direction perpendicular to the plane where the substrate substrate is located, the ninth opening h9 at least partially overlaps with the ninth signal line a9, thereby reducing the overlapping area between the third reset signal line PAM_INIT and the ninth signal line a9, and further reducing the parasitic capacitance formed between the third reset signal line PAM_INIT and the ninth signal line a9.

[0268] Continue to refer Figure 16-Figure 21 Optionally, in a direction perpendicular to the plane where the substrate is located, the first plate PAM_c11 and the second plate PAM_c12 of the amplitude storage capacitor PAM_C1 at least partially overlap. The first plate PAM_c11 includes a first opening structure 61, and the second plate PAM_c12 includes a second opening structure 62, and in a direction perpendicular to the plane where the substrate is located, the first opening structure 61 and the second opening structure 62 at least partially overlap, so that the light transmittance of the display panel can be improved.

[0269] Continue to refer Figure 16-Figure 21Optionally, in a direction perpendicular to the plane where the substrate is located, the first plate PWM_c11 and the second plate PWM_c12 of the pulse width storage capacitor PWM_C1 at least partially overlap. The first plate PWM_c11 includes a third opening structure 63, the second plate PWM_c12 includes a fourth opening structure 64, and in a direction perpendicular to the plane where the substrate is located, the third opening structure 63 and the fourth opening structure 64 at least partially overlap, so that the light transmittance of the display panel can be improved.

[0270] Continue to refer Figure 15-Figure 30 Optionally, the first plate PAM_c11 of the amplitude storage capacitor PAM_C1 can be located in the third metal layer MC, and the second plate PAM_c12 of the amplitude storage capacitor PAM_C1 can be located in the second metal layer GAT. In a direction perpendicular to the plane where the substrate is located, the first plate PAM_c11 of the amplitude storage capacitor PAM_C1 covers the second plate PAM_c12 of the amplitude storage capacitor PAM_C1, and in a direction parallel to the plane where the substrate is located, the boundary of the first plate PAM_c11 of the amplitude storage capacitor PAM_C1 and the second plate PAM_c12 of the amplitude storage capacitor PAM_C1 are located. The distance between the boundaries of the second plate PAM_c12 of the storage capacitor PAM_C1 is greater than 0, for example, greater than or equal to 0.5 μm, or further greater than or equal to 1 μm. With this arrangement, when the alignment between the first plate PAM_c11 and the second plate PAM_c12 of the amplitude storage capacitor PAM_C1 is inaccurate due to process errors, it can be ensured that there is a sufficient overlapping area between the first plate PAM_c11 and the second plate PAM_c12 of the amplitude storage capacitor PAM_C1, thereby improving the stability of the capacitance value of the amplitude storage capacitor PAM_C1.

[0271] Similarly, if Figure 15-Figure 30As shown, optionally, the first plate PWM_c11 of the pulse width storage capacitor PWM_C1 may be located in the third metal layer MC, and the second plate PWM_c12 of the pulse width storage capacitor PWM_C1 may be located in the second metal layer GAT. In a direction perpendicular to the plane where the substrate is located, the first plate PWM_c11 of the pulse width storage capacitor PWM_C1 covers the second plate PWM_c12 of the pulse width storage capacitor PWM_C1, and in a direction parallel to the plane where the substrate is located, the distance between the boundary of the first plate PWM_c11 of the pulse width storage capacitor PWM_C1 and the boundary of the second plate PWM_c12 of the pulse width storage capacitor PWM_C1 is greater than 0, for example, greater than or equal to 0.5μm, or further greater than or equal to 1μm. In this way, when the alignment between the first plate PWM_c11 and the second plate PWM_c12 of the pulse width storage capacitor PWM_C1 is inaccurate due to process errors, it can be ensured that there is a sufficient overlapping area between the first plate PWM_c11 and the second plate PWM_c12 of the pulse width storage capacitor PWM_C1, thereby improving the stability of the capacitance value of the pulse width storage capacitor PWM_C1.

[0272] Continue to refer Figure 7 , Fig.21 and Fig.30 Optionally, in the amplitude adjustment module PAM, the amplitude storage capacitor PAM_C1 and the amplitude driving transistor PAM_M3 are arranged along the second direction Y; in the second direction Y, the first amplitude light emitting control transistor PAM_M1 and the second amplitude light emitting control transistor PAM_M6 are both located on the side of the amplitude driving transistor PAM_M3 away from the amplitude storage capacitor PAM_C1, and the first amplitude light emitting control transistor PAM_M1 and the second amplitude light emitting control transistor PAM_M6 are arranged along the first direction X, wherein the arrangement direction of the first amplitude light emitting control transistor PAM_M1 and the second amplitude light emitting control transistor PAM_M6 is the same as the arrangement direction of the first pulse width light emitting control transistor PWM_M1 and the second pulse width light emitting control transistor PWM_M6. Such a configuration is conducive to making the layout of the pixel driving circuit 11 more compact, thereby saving space, but is not limited to this, and the embodiment of the present invention does not make specific limitations on this.

[0273] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig.32 A schematic diagram of a display device according to an embodiment of the present invention is shown in FIG. Fig.32 As shown, the display device 50 includes the display panel 51 described in any embodiment of the present invention. Therefore, the display device 50 provided in the embodiment of the present invention has the technical effect of the technical solution in any of the above embodiments, and the structures that are the same or corresponding to the above embodiments and the explanation of terms are no longer repeated here.

[0274] Fig.33 A schematic diagram of the structure of another display device provided by an embodiment of the present invention is shown in FIG. Fig.33 As shown, the display device provided in the embodiment of the present invention may be a spliced ​​display device, such as a frameless spliced ​​display device, which includes at least two of the above-mentioned display panels 51 to be applicable to a large-screen display device with a display function.

[0275] The at least two display panels 51 may be arranged along the first direction X, or the at least two display panels 51 may be arranged along the second direction Y, but the present invention is not limited thereto and the present invention does not specifically limit this.

[0276] The display device 50 provided in the embodiment of the present invention can be Fig.31 The mobile phone shown can also be Fig.32 The spliced ​​display device shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not specifically limit this.

[0277] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0278] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: It includes a base substrate and a pixel driving circuit located on one side of the base substrate; The pixel driving circuit includes a first driving transistor; The first driving transistor includes a first electrode and a second electrode; The first electrode includes a first subsection extending along a first direction; The second electrode includes a second portion extending along a second direction; The first direction and the second direction intersect; The first sub-portion includes a first segment and a second segment arranged along the first direction, and a vertical projection of the second segment on the substrate overlaps with a vertical projection of the second sub-portion on the substrate; Along the first direction, an area per unit length of the second segment is smaller than an area per unit length of the first segment.

2. The display panel according to claim 1, characterized in that: The first electrode is a gate electrode, and the second electrode is a source electrode or a drain electrode.

3. The display panel according to claim 1, characterized in that: The second section includes a first connecting portion connected to the first section; The length of the first connecting portion along the second direction is d1, and the length of the first section along the second direction is D, wherein d1<D.

4. The display panel according to claim 3, characterized in that: The second section further includes a second connecting portion connected to the first section; The length of the second connection portion along the second direction is d2, wherein d1+d2<D.

5. The display panel according to claim 4, characterized in that: The first connection portion and the second connection portion are arranged along the second direction, and a first hollow portion is provided between the first connection portion and the second connection portion; A vertical projection of the first hollow portion on the base substrate overlaps with a vertical projection of the second portion on the base substrate.

6. The display panel according to claim 1, characterized in that: The length of the second segment along the second direction is equal to the length of the first segment along the second direction; The second section includes at least one second hollow portion, and a vertical projection of the second hollow portion on the base substrate overlaps with a vertical projection of the second sub-portion on the base substrate.

7. The display panel according to claim 1, characterized in that: The pixel driving circuit further includes a first capacitor, wherein the first capacitor includes a first plate; The first electrode further includes a third subsection extending along the second direction, the first subsection and the third subsection are connected, and the second subsection and the third subsection are arranged along the first direction; The first electrode plate includes a first connecting section connected to the third section, and the third section and the first connecting section are arranged along the second direction; Along the first direction, a distance between the third section and the second section is greater than a distance between the first connecting section and the second section.

8. The display panel according to claim 7, characterized in that: A length of the third section in the first direction is smaller than a length of the first connecting section in the first direction.

9. The display panel according to claim 7, characterized in that: The boundary of the third subsection close to the second subsection is a first boundary, and the boundary of the third subsection away from the second subsection is a second boundary; A boundary of the first connection section close to the second section is a third boundary, and a boundary of the first connection section away from the second section is a fourth boundary; Along the first direction, the first boundary is located on a side of the third boundary away from the second section, and the second boundary is located on a side of the fourth boundary close to the second section.

10. The display panel according to claim 7, characterized in that: A boundary of the third subsection close to the second subsection is a first boundary, and the first boundary extends along the second direction; A boundary of the first connecting section close to the second section is a third boundary, and the third boundary extends along the second direction; The first connection sub-portion further includes a first chamfered edge, and the first chamfered edge connects the third edge and the first edge respectively; An included angle between the first chamfered boundary and the third boundary is an obtuse angle, and an included angle between the first chamfered boundary and the first boundary is an obtuse angle.

11. The display panel according to claim 9, characterized in that: The second boundary extends along the second direction; The fourth boundary extends along the second direction; The first connection sub-portion further includes a second chamfered edge, and the second chamfered edge connects the fourth edge and the second edge respectively; An included angle between the second chamfered boundary and the fourth boundary is an obtuse angle, and an included angle between the second chamfered boundary and the second boundary is an obtuse angle.

12. The display panel according to claim 1, characterized in that: The pixel driving circuit further includes a first capacitor, wherein the first capacitor includes a first plate; The first electrode further includes a third subsection extending along the second direction, the first subsection and the third subsection are connected, and the second subsection and the third subsection are arranged along the first direction; A boundary of the first subsection close to the first capacitor is a fifth boundary, and the fifth boundary extends along the first direction; A boundary of the third subsection close to the second subsection is a first boundary, and the first boundary extends along the second direction; The fifth boundary is adjacent to the first boundary.

13. The display panel according to claim 1, characterized in that: The pixel driving circuit further includes a first capacitor, wherein the first capacitor includes a first plate; Along the first direction, a boundary of the second section close to the first electrode plate is a sixth boundary, and the sixth boundary extends along the second direction; Along the second direction, a boundary of the second section close to the first electrode plate is a seventh boundary, and the seventh boundary extends along the first direction; The second subsection further includes a third chamfered boundary, wherein the third chamfered boundary connects the sixth boundary and the seventh boundary respectively; An included angle between the third chamfered boundary and the sixth boundary is an obtuse angle, and an included angle between the third chamfered boundary and the seventh boundary is an obtuse angle.

14. The display panel according to claim 13, characterized in that: The first electrode plate comprises a main body section and a first connecting section connected to each other, and the main body section and the first connecting section are arranged along the second direction; The second sub-section and the first connecting sub-section are arranged along the first direction, and the second sub-section and the main body sub-section are arranged along the second direction; A boundary of the first connecting section close to the second section is a third boundary, and the third boundary extends along the second direction; A boundary of the main body section close to the second section is an eighth boundary, and the eighth boundary extends along the first direction; The first electrode plate further includes a fourth chamfered edge, the fourth chamfered edge respectively connecting the third edge and the eighth edge; An included angle between the fourth chamfered boundary and the third boundary is an obtuse angle, and an included angle between the fourth chamfered boundary and the eighth boundary is an obtuse angle.

15. The display panel according to claim 1, characterized in that: The pixel driving circuit also includes a pulse width adjustment module and an amplitude adjustment module; The pulse width adjustment module includes a pulse width driving transistor, the amplitude adjustment module includes an amplitude driving transistor, and the pulse width driving transistor is electrically connected to the gate of the amplitude driving transistor; The first driving transistor includes at least one of the amplitude driving transistor and the pulse width driving transistor.

16. The display panel according to claim 15, characterized in that: The first driving transistor is the amplitude driving transistor; The distance between the vertical projection of the gate electrode of the pulse width driving transistor on the substrate and the vertical projection of the first electrode of the pulse width driving transistor on the substrate is greater than 0; A distance between a vertical projection of a gate electrode of the pulse width driving transistor on the substrate and a vertical projection of a second electrode of the pulse width driving transistor on the substrate is greater than 0.

17. The display panel according to claim 16, characterized in that: The pulse width adjustment module also includes a first pulse width light emitting control transistor, a second pulse width light emitting control transistor and a pulse width storage capacitor; The first electrode of the first pulse width light emitting control transistor is electrically connected to the first power supply line, the second electrode of the first pulse width light emitting control transistor is electrically connected to the first electrode of the pulse width driving transistor, and the gate of the first pulse width light emitting control transistor is electrically connected to the pulse width light emitting control signal line; The first electrode of the second pulse width light emitting control transistor is electrically connected to the second electrode of the pulse width driving transistor, the second electrode of the second pulse width light emitting control transistor is electrically connected to the amplitude adjustment module, and the gate of the second pulse width light emitting control transistor is electrically connected to the pulse width light emitting control signal line; The pulse width storage capacitor is electrically connected to the gate of the pulse width driving transistor; Along the second direction, the first pulse width light emitting control transistor and the second pulse width light emitting control transistor are both located on a side of the second pole of the pulse width driving transistor away from the first pole of the pulse width driving transistor; Along the first direction, the arrangement direction of the first pulse width light emitting control transistor and the second pulse width light emitting control transistor is the same as the arrangement direction of the pulse width driving transistor and the pulse width storage capacitor.

18. The display panel according to claim 17, characterized in that: The first power line extends along the first direction; Along the second direction, the first pulse width light emitting control transistor and the second pulse width light emitting control transistor are both located on a side of the first power line away from the pulse width driving transistor.

19. The display panel according to claim 16, characterized in that: The pulse width modulation module also includes a pulse width compensation transistor, a pulse width gate reset transistor and a pulse width storage capacitor; The first electrode of the pulse width compensation transistor is electrically connected to the second electrode of the pulse width driving transistor, the second electrode of the pulse width compensation transistor is electrically connected to the gate of the pulse width driving transistor, and the gate of the pulse width compensation transistor is electrically connected to the second scanning signal line; The first electrode of the pulse width gate reset transistor is electrically connected to the first reset signal line, the second electrode of the pulse width gate reset transistor is electrically connected to the gate of the pulse width driving transistor, and the gate of the pulse width gate reset transistor is electrically connected to the first scanning signal line; The pulse width storage capacitor is electrically connected to the gate of the pulse width driving transistor; Along the second direction, the pulse width compensation transistor and the pulse width gate reset transistor are both located on a side of the first electrode of the pulse width driving transistor away from the second electrode of the pulse width driving transistor; Along the first direction, the arrangement direction of the pulse width gate reset transistor and the pulse width compensation transistor is the same as the arrangement direction of the pulse width driving transistor and the pulse width storage capacitor.

20. The display panel according to claim 16, characterized in that: The gate of the pulse width driving transistor includes a fourth section extending along the first direction and a fifth section extending along the second direction, the fourth section and the fifth section are connected to each other, and the fourth section and the fifth section are arranged along the first direction; Along the second direction, a boundary of the fourth section close to the first electrode of the pulse width driving transistor is a ninth boundary, and the ninth boundary extends along the first direction; Along the first direction, a boundary of the fifth subsection close to the first electrode of the pulse width driving transistor is a tenth boundary, and the tenth boundary extends along the second direction; The ninth boundary and the tenth boundary are adjacent to each other.

21. The display panel according to claim 16, characterized in that: The gate of the pulse width driving transistor includes a fourth section extending along the first direction and a fifth section extending along the second direction, the fourth section and the fifth section are connected to each other, and the fourth section and the fifth section are arranged along the first direction; The pulse width regulation module further includes a pulse width storage capacitor, and the pulse width storage capacitor includes a second electrode plate; The second electrode plate includes a second connecting sub-section connected to the fifth sub-section, and the fifth sub-section and the second connecting sub-section are arranged along the second direction; Along the first direction, a distance between the fifth section and the first electrode of the pulse width driving transistor is greater than a distance between the second connecting section and the first electrode of the pulse width driving transistor.

22. A display device, characterized in that: A display panel comprising any one of claims 1-21.

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