Back contact bc solar cell structure and method of manufacturing the same

Abstract

The application belongs to the technical field of solar power generation, and particularly relates to a back contact BC solar cell structure and a preparation method thereof. The back N area of the cell is provided with a tunneling SiO2 layer and a phosphorus-doped N+poly layer with high crystallization rate and low parasitic absorption; the P area is sequentially provided with an i:a-Si layer, a P:a-Si layer and a P-uc-SiO x C y layer; the front of the cell is provided with a stack of gradient silicon nitride anti-reflection passivation films; the back N area of the application adopts a SiO2 layer and a N+poly field structure with high crystallization rate and low parasitic absorption to replace the traditional HBC i:a-Si+N:a:Si field structure to improve the current density; the back N area adopts a textured light-trapping structure to replace a polishing structure to improve the current density; the metal electrode contact area is increased to reduce the contact resistance and improve the fill factor; a low-temperature silicon nitride anti-reflection film is added to the upper layer of the TCO transparent conductive film to improve the passivation and the current density; the P area N area isolation area silicon nitride covering anti-reflection improves the passivation and the current density, improves the back efficiency of the cell, and improves the bifacial rate.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of solar power generation, and particularly relates to a back contact BC solar cell structure and a preparation method thereof. BACKGROUND

[0002] Photovoltaic power generation is a system for directly converting solar energy into electrical energy by using solar cells according to the principle of photovoltaic effect, wherein the basic structure of the solar cell is a large-area planar PN junction. When sunlight irradiates on the PN junction, the PN junction absorbs light energy to excite electrons and holes, and then generates a voltage in the PN junction to realize photoelectric conversion. Therefore, the core structure for realizing the conversion between solar energy and electrical energy in a crystalline silicon cell is the PN junction.

[0003] With the PERC cell gradually approaching the limit efficiency of 24.5%, the industry has begun to seek the next generation of crystalline silicon cell technology, and the current mainstream promotion includes Topcon (tunneling oxide passivation contact), HJT (heterojunction), and IBC (interdigitated back contact) technology. Different from Topcon and HJT which improve the cell efficiency by changing the passivation method, the IBC cell is to transfer all the cell grid lines to the back surface, reduce the grid line shading area, improve the current density, and increase the cell efficiency. The IBC cell is a platform technology, and is stacked with Topcon technology as TBC and stacked with HJT technology as HBC.

[0004] The HBC cell inherits the difficulties of the production processes of HJT and IBC, such as long process, complex process, narrow process window, etc., and the TBC cell needs to solve the problems of back electrode isolation and polysilicon passivation uniformity. Due to the great difference between the technical routes of the two cell structures, the existing scheme can only prepare one of the cell structures that change the passivation method and reduce the grid lines.

[0005] Therefore, how to provide a cell structure that takes into account the advantages of TBC cells and HBC cells is a technical problem that needs to be solved in the field.

[0006] It should be noted that the above information disclosed in the background section is only used to understand the background of the present application, and therefore, the above description is not considered as information of the prior art. SUMMARY

[0007] The embodiments of the present disclosure at least provide a back contact BC solar cell structure and a preparation method thereof.

[0008] In a first aspect, the embodiments of the present disclosure provide a preparation method of a back contact (BC) solar cell, comprising the following steps: step S1, performing double-side texturing on a silicon wafer to prepare a clean silicon wafer surface with a low-reflectivity pyramid-textured surface; step S2, from bottom to top, oxidizing the back surface of the silicon wafer to prepare a tunneling SiO2 layer, then depositing a phosphorus-doped N+ poly layer on the tunneling SiO2 layer from bottom to top, and then from top to bottom, depositing a phosphorus-doped N+ poly layer on the front surface of the silicon wafer, and then depositing a SiO2 mask layer on the phosphorus-doped N+ poly layer from top to bottom; step S3, performing laser oxidation on the phosphorus-doped N+ poly layer on the back surface of the silicon wafer to prepare a SiO2 mask layer; step S4, performing alkali cleaning on the silicon wafer to remove the tunneling SiO2 layer and the phosphorus-doped N+ poly layer in the region without the SiO2 mask layer on the back surface and the SiO2 mask layer on the front surface, and to etch and expose the silicon substrate on the back surface; step S5, performing high-temperature annealing on the silicon wafer to crystallize and activate amorphous silicon, push the doped atoms, form an N+ front passivation field and an N+ inner extension layer on the front surface and the back surface of the silicon wafer respectively, remove the SiO2 layer on the front surface after high-temperature oxidation, and perform acid washing; step S6, depositing an i:a-Si layer on the back surface of the silicon wafer after acid washing from top to bottom, and then depositing a P:a-Si layer on the deposited surface after HPT cleaning; step S7, preparing a patterned mask on the amorphous surface of the P region on the back surface of the silicon wafer by inkjet printing; step S8, removing the amorphous silicon in the P region on the back surface of the silicon wafer without the patterned mask by ion etching; step S9, cleaning the silicon wafer by ultrasonic cleaning with an organic solvent and removing the patterned mask on the back surface; step S10, performing HPT cleaning on the back surface of the silicon wafer and depositing a TCO transparent conductive film; step S11, isolating the N region and the P region on the back surface of the silicon wafer by laser etching; step S12, depositing an aluminum oxide layer on the front surface of the silicon wafer, and then depositing a stack of gradient silicon nitride anti-reflection passivation films on the front surface and the back surface of the silicon wafer respectively; step S13, locally opening a window of the stack of gradient silicon nitride anti-reflection passivation films on the N region and the P region on the back surface of the silicon wafer to expose the TCO transparent conductive film, and screen printing a low-temperature metal paste in the opening area.

[0009] In an optional embodiment, the surface reflectivity of the polished silicon wafer in step S1 is 9-12%; the size of the tower is 1-3 μm, and the height of the tower is 0.5-3 μm.

[0010] In an optional embodiment, in step S2, the thickness of the tunneling SiO2 layer on the back surface of the silicon wafer is 0.8-1.5 nm, the thickness of the phosphorus-doped N+ poly layer is 50-300 nm, the doping concentration is 1E+20 cm -3 ~2E+21 cm -3The thickness of the SiO2 mask layer on the front surface of the silicon wafer is 10-50nm, the thickness of the phosphorus-doped N+ poly layer is 5-10nm, and the doping concentration is 1E+19cm -3 ~1E+20cm -3 .

[0011] In an alternative embodiment, in the step S3, the thickness of the SiO2 mask layer on the back surface of the silicon wafer is 5-15nm, and the width of the oxidation region is 100-400μm.

[0012] In an alternative embodiment, in the step S4, the reflectivity of the etched region is 35-45%, the mesa size of the etched region is 5-15μm, and the etching depth of the etched region is 0.5-2μm.

[0013] In an alternative embodiment, in the step S5, the temperature of the high-temperature crystallization promotion is 850-910℃, the time of the high-temperature crystallization promotion is 30-60min, the temperature of the high-temperature oxidation is 800-850℃, and the time of the high-temperature oxidation is 10-30min.

[0014] In an alternative embodiment, in the step S6, i: the thickness of the a-Si layer is 2-10nm; the P:a-Si layer comprises a P:a-Si sublayer and a P-uc-SiO x C y sublayer; wherein the thickness of the P:a-Si sublayer is 10-20nm, and the doping concentration is 1E+18cm -3 ~5E+18cm -3 : the thickness of the P-uc-SiO x C y sublayer is 20-50nm, and the doping concentration is 5E+18cm -3 ~2E+19cm -3 .

[0015] In an alternative embodiment, in the step S7, the width of the patterned mask prepared by the ink is 100-500μm, and the height is 10-20μm.

[0016] In an alternative embodiment, in the step S11, the laser power is 300-600W, and the etching width is 10-20μm.

[0017] In an alternative embodiment, in the step S13, the width of the laser slotting is 10-30μm.

[0018] The back contact BC solar cell preparation method has the following advantages:

[0019] 1. The P region amorphous interdigital arrangement structure of the application is prepared by inkjet printing + ion etching preparation + organic cleaning, and the hydrogenated amorphous silicon is not contacted with any acid and alkali, so that the performance failure risk is extremely low;

[0020] 2. The N region poly of the application is prepared by in-situ doping PVD plating film, without plating and expansion, and without additional plating and expansion process;

[0021] 3. The N region and the P region of the application adopt different morphologies, which are more conducive to laser slotting positioning and recognition, preparation of N region poly P region amorphous interdigital arrangement structure, and reduction of battery leakage and offset risk;

[0022] 4. The process of the application does not use laser to bombard hydrogenated amorphous, so that the performance failure risk is extremely low.

[0023] In the second aspect, the disclosure also provides a back contact BC solar cell structure prepared by the method as described above, wherein the back surface N region of the cell is provided with a tunneling SiO2 layer and a high-crystallinity low-parasitic-absorption phosphorus-doped N+ poly layer; the P region is sequentially provided with an i: a-Si layer, a P: a-Si sublayer and a P-uc-SiOxCy sublayer; and the front surface of the cell is provided with a stack of gradient silicon nitride anti-reflection passivation films. x C y

[0024] The back contact BC solar cell structure has the following advantages:

[0025] 1. The back surface N region of the application adopts a tunneling SiO2 layer and a high-crystallinity low-parasitic-absorption N+ poly field structure to replace the traditional HBC i: a-Si + N: a-Si field structure to improve the current density, the back surface N region adopts a textured light-trapping structure to replace a polished structure to improve the current density, the metal electrode contact area is increased to reduce the contact resistance and improve the fill factor, a low-temperature silicon nitride anti-reflection film is added to the upper layer of the TCO transparent conductive film to improve the passivation and the current density, the nitrogen-containing silicon nitride covering anti-reflection film is used in the isolation area of the P region and the N region to improve the passivation and the current density, the i: a-Si + P: a-Si + P-uc-SiOxCy emitter film layer structure is used in the P region to replace the traditional i: a-Si + P: a-Si, the introduction of microcrystalline boron-doped carbon-doped silicon oxide reduces the parasitic absorption of the film layer and improves the current density, the back surface efficiency of the cell is improved, and the bifaciality is improved;

[0026] ​2. The front surface uses low-temperature graded SiNx+aluminum oxide passivation anti-reflection film to replace intrinsic amorphous silicon+SiNx to reduce amorphous silicon parasitic absorption, the back surface N region uses a textured light-trapping structure to replace a polished structure to improve current density, a low-temperature silicon nitride anti-reflection film is added to the upper layer of the TCO transparent conductive film to improve passivation and current density, silicon nitride anti-reflection is covered in the P region N region isolation region to improve passivation and current density, the i:a-Si+P:a-Si+P-uc-SiOxCy emitter film layer structure is used in the P region to replace the traditional i:a-Si+P:a-Si, the introduction of microcrystalline boron-doped carbon silicon oxide reduces the film layer parasitic absorption, improves the current density of the battery, reduces the optical loss of the BC battery as a whole, and improves the current density of the battery as a whole;

[0027] 3. The present application only uses amorphous silicon passivation interface and prepares an emitter in the back surface P region junction area, uses Al2O3+SiNx passivation interface on the front surface, and uses SiO2+poly structure passivation interface in the back surface N region, compared with the traditional HBC battery covered with amorphous silicon, the risk of ultraviolet attenuation is greatly reduced;

[0028] 4. The present battery structure uses water vapor and acid and alkali resistant SiNx film layer covering on the front and back surfaces, and there is no TCO exposed to water vapor and acid and alkali, so the assembly packaging difficulty is low, and the failure risk is reduced;

[0029] 5. The present application uses SiO2+poly passivation contact structure in the N region junction area, and in the high-temperature annealing and crystallization process of poly, the gettering effect is improved to improve the silicon wafer quality, and no additional gettering process is needed for the preparation of the traditional HBC battery;

[0030] 6. The present application uses amorphous silicon passivation in the back surface P region junction area, and uses low-temperature prepared silicon nitride to reduce the damage of aluminum oxide on the front surface, and the upper limit of the overall passivation is higher than that of the traditional TBC battery, and is not inferior to that of the HBC battery;

[0031] 7. After laser grooving isolation of the N region and the P region, the insulating material SiNx is used for secondary isolation, which greatly reduces the risk of BC battery leakage.

[0032] Other features and advantages of the present application will be set forth in the specification, and in part will become apparent from the specification, or will be learned from the practice of the present application. The objects and other advantages of the present application will be realized and achieved by the structure particularly pointed out in the specification, claims, and drawings.

[0033] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are specifically described below, and the accompanying drawings are referred to. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to illustrate the technical solutions in the specific embodiments of the present application or the prior art more clearly, the accompanying drawings needed to be used in the description of the specific embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0035] Figure 1 A process flow schematic diagram provided for the embodiments of the present disclosure;

[0036] Figure 2 A battery structure schematic diagram provided for the embodiments of the present disclosure;

[0037] Figure 3 A process flow schematic diagram provided for the embodiments of the present disclosure;

[0038] Figure 4 A battery structure schematic diagram provided for the embodiments of the present disclosure;

[0039] Figure 5 A battery structure schematic diagram provided for the embodiments of the present disclosure;

[0040] Figure 6 A process flow schematic diagram provided for the embodiments of the present disclosure;

[0041] Figure 7 A battery structure schematic diagram provided for the embodiments of the present disclosure;

[0042] Figure 8 A battery structure schematic diagram provided for the embodiments of the present disclosure;

[0043] Figure 9 A process flow schematic diagram provided for the embodiments of the present disclosure;

[0044] Figure 10 A battery structure schematic diagram provided for the embodiments of the present disclosure;

[0045] Figure 11 A battery structure schematic diagram provided for the embodiments of the present disclosure;

[0046] Figure 12 A process flow schematic diagram provided for the embodiments of the present disclosure;

[0047] Figure 13 A battery structure schematic diagram provided for the embodiments of the present disclosure;

[0048] Figure 14 A process flow schematic diagram provided for the embodiments of the present disclosure;

[0049] Figure 15 A schematic diagram of a battery structure provided for embodiments of the present disclosure;

[0050] Figure 16 A schematic diagram of a process flow provided for embodiments of the present disclosure;

[0051] Figure 17 A schematic diagram of a battery structure provided for embodiments of the present disclosure;

[0052] Figure 18 A schematic diagram of a battery structure provided for embodiments of the present disclosure;

[0053] Figure 19 A schematic diagram of a process flow provided for embodiments of the present disclosure;

[0054] Figure 20 A schematic diagram of a battery structure provided for embodiments of the present disclosure;

[0055] Figure 21 A schematic diagram of a battery structure provided for embodiments of the present disclosure. DETAILED DESCRIPTION

[0056] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be described clearly and completely below with reference to the drawings, obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0057] As used herein, the phrases "in one embodiment", "according to one embodiment", "in some embodiments", and the like generally mean the fact that a particular feature, structure, or characteristic described after the phrase can be included in at least one embodiment of the present disclosure. Therefore, the particular feature, structure, or characteristic can be included in more than one embodiment of the present disclosure, so that these phrases do not necessarily refer to the same embodiment. As used herein, the terms "example", "exemplary", and the like are used as an example, instance, or illustration. Any implementation, aspect, or design described herein as "example" or "exemplary" is not necessarily to be construed as preferred or superior over other implementations, aspects, or designs. On the contrary, the use of the terms "example", "exemplary", and the like is intended to present the concept in a specific manner.

[0058] In this document, example embodiments of the disclosure will be described in greater detail. As used herein, expressions such as "at least one of," when preceding the term "comprising," "including," or "having," denotes the existence of at least one or more of the stated features and does not exclude the existence of additional features. As used herein, the terms "a," "an" and "the" are used interchangeably with "one or more," unless the context clearly indicates otherwise. As used herein, the terms "comprises," "comprising," "includes," "including" and the like are specifically intended to be open-ended terms that do not exclude additional elements or steps. As used herein, the term "exemplary" is used in the sense of being an example, rather than a representation that some or all of the example or exemplary configurations are preferred or advantageous over other configurations. As used herein, the term "or" is intended to mean at least one of the items listed, for example, X or Y means X or Y or both. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. As used herein, the term "wherein" can be used in the sense of "where" or "whereby," that is, to define one or more conditions for the action or to characterize a result of the action (e.g., the result of the method or process). As used herein, the term "if" can be construed to mean "when" or "if," that is, to define one or more conditions for the action or to characterize a result of the action (e.g., the result of the method or process). As used herein, the term "plurality" is intended to mean at least two, for example, two or more, for example, two or more of the same item or two or more of different items.

[0059] The terminology used herein is for the purpose of describing particular example configurations only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and the like are to be construed as open-ended terms that do not exclude additional elements or steps. The terms "coupled" and "coupling" as used herein are intended to mean physically, electrically, and / or communicatively coupled unless otherwise indicated. The terms "includes," "including," and "has" are intended to be inclusive, thus specifying features, steps, operations, elements, and / or components but not precluding the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order in which they are described, unless specifically identified as an order dependency. Additional or alternative steps can be employed.

[0060] Terminology:

[0061] HBC: IBC battery in Chinese is called cross-finger back contact battery. The emitter, back field and corresponding positive and negative electrodes are integrated in the form of cross-finger on the back of the battery. This structure avoids the metal grid electrode from blocking the light, maximizes the use of incident light, and improves the short-circuit current of the battery. HBC technology combines HJT technology and IBC technology, which can improve the current density and battery efficiency without losing passivation.

[0062] The characteristics of IBC battery are that there is no electrode on the front of the battery, and the positive and negative electrode grids are integrated in the form of cross-finger on the back. The main features of the battery are: 1. High minority carrier lifetime silicon wafer is used to avoid carrier recombination before transmission to the PN junction; 2. The positive and negative electrodes are integrated on the back, and the grid pattern morphology is designed with a large window; 3. Front surface field design with anti-reflection coating, which maximizes optical utilization and reduces front surface recombination; 4. Back N area, P area cross-finger arrangement, P area (emitter) collects holes, N area (back field) captures electrons.

[0063] IBC cell advantages: 1. No grid line obstruction on the front side, high photon absorption level, high current density; 2. Combined with HJT technology, improve cell current density and cell efficiency without passivation loss; 3. Combined with Topcon technology, both positive and negative electrodes can be prepared with passivation contact structure without significant current density loss, and the passivation level is improved; 4. Both positive and negative electrodes are on the back side, which can increase the grid line width, reduce the contact resistance, improve the FF, and have no significant effect on the current; 5. The cell has no grid line design on the front side, the cell is beautiful, and the BIPV (photovoltaic building integration) application scene has obvious advantages.

[0064] BC cell disadvantages: 1. Low double-sided rate of the cell (grid line integrated on the back side, resulting in increased shading area on the back side, and large difference in efficiency between the front and back sides); 2. Complex process, many processes, expensive equipment, high cost, and low yield (traditional HBC cell preparation process includes: texturing cleaning--front i:a-Si--front SiNx--back i:a-Si--back P:a-Si--back mask--laser slotting--etching--back i:a-Si--back N:a-Si--laser film opening--etching--back TCO--laser film opening to isolate PN area--printing and curing--light injection) (conventional TBC cell preparation process includes: double-sided polishing-tunnel oxide layer preparation-intrinsic poly deposition-boron diffusion-laser ablation-alkali polishing-tunnel oxide layer preparation-intrinsic poly deposition-phosphorus diffusion-laser ablation-alkali washing-laser ablation-single-sided chain acid-texturing-anti-reflective passivation film-printing and sintering); 3. The poly interdigital arrangement structure of the back N area and P area is difficult to prepare (laser is difficult to accurately position the film opening area and film opening depth); 4. BC cell has higher requirements for silicon wafer quality and front body passivation (carriers need to pass through the front surface and body area of the silicon wafer to reach the back side, and defects in the front body of the cell will recombine carriers before reaching the PN junction).

[0065] Prior art one: Xuzhou Ple New Energy (patent number CN 115050855 A)

[0066] Scheme steps: 1. Double-sided texturing; 2. Backside polishing; 3. Double-sided deposition of i:a-Si; 4. Backside patterned boron paste printing and drying; 5. Backside patterned phosphorus paste printing and drying; 6. N area and P area laser doping; 7. Ultrasonic cleaning of slurry with organic water mixed solution; 8. Backside TCO deposition; 9. Laser slotting to isolate N area and P area; 10. Front side deposition of SiO / SiON / SiN stacked film; 11. Screen printing, curing and sintering.

[0067] Concept: 1. From top to bottom: SiN / SiON / SiO---i:a-Si---textured surface---silicon base---polished surface---i:a-Si---P:a-Si---N:a:Si---TCO---silver paste HBC cell structure;

[0068] 2. Battery backside deposition i: a-Si, boron paste and phosphorus paste are printed using a screen cross, then dried, laser doped, and cleaned to complete the battery backside N area P area poly fork arrangement structure.

[0069] Disadvantages:

[0070] 1. Use doped paste as a doping source. The doped paste has special fluidity, corrosion, etc., and needs to use professional scrapers, glue scrapers, and special non-metal mesh, which is not market mass production auxiliary materials.

[0071] 2. The doped paste often adds more organic solvents to meet the printing needs, realizes solidification, and the organic solvents affect the boron and phosphorus doping diffusion effect, and the diffusion uniformity is poor.

[0072] 3. The doped paste often adds more organic solvents to meet the printing needs, and the smell is large, the ventilation requirement is high, and the protection measures for employees are high.

[0073] 4. Laser boron and phosphorus paste doping amorphous silicon, it is difficult to control the doping amount and doping depth, and it is easy to damage the bottom layer of hydrogenated amorphous silicon, affecting the passivation of the battery.

[0074] 5. The ARC anti-reflection film prepared by using >200℃ high temperature on the front surface is easy to cause the passivation of amorphous silicon to decline.

[0075] 6. The anti-reflection passivation film layer design of SiNx+i: a-Si on the front surface has large parasitic absorption and large battery current loss.

[0076] 7. The amorphous silicon in this process flow is exposed for a long time without protective film, which affects the passivation of the battery.

[0077] Prior art two: Aikang (CN 218849510 U)

[0078] Steps: 1. Cleaning and texturing; 2. Preparing silicon oxide and intrinsic amorphous silicon on the back; 3. High-temperature phosphorus diffusion, crystallizing amorphous silicon on the back into phosphorus-doped polycrystalline silicon; 4. Laser etching; 5. Poly cleaning to remove plating and expansion, alkali etching, and laser ablation to N-type silicon base; 6. Intrinsic amorphous silicon deposition on the front surface; 7. Silicon nitride preparation on the front surface; 8. Back mask-slotted-deposited-etched technology to prepare intrinsic amorphous silicon and P: a-Si; 9. Back mask-slotted-deposited-etched technology to prepare TCO; 10. Screen electrode printing and curing.

[0079] Concept:

[0080] The back N region and P region are prepared by traditional mask-slot-deposition-etching method, and the N region uses SiO and N+poly polo passivation contact structure to replace the battery structure of i:a-Si+N:a:Si.

[0081] Disadvantages:

[0082] 1. The front surface uses SiNx+i:a-Si antireflection passivation film layer design, which has large parasitic absorption and large battery current loss.

[0083] 2. The interface H passivation effect of the back N region using SiO and N+poly polo passivation contact structure is poor.

[0084] 3. The N+poly preparation of the back N region uses high-temperature tube type equipment, which has winding expansion and winding plating.

[0085] The above-mentioned defects are the results of the inventors after practice and careful research, therefore, the discovery process of the above-mentioned problems and the solutions proposed by the present disclosure to solve the above-mentioned problems should be the contributions of the inventors to the present disclosure in the process of the present disclosure.

[0086] It should be noted that similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0087] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

[0088] Step S1, double-sided texturing of the silicon wafer to prepare a low reflectivity pyramid textured surface and a clean silicon wafer surface, please refer to the process flow shown in Figure 1 to obtain a silicon wafer as shown in Figure 2 The specific process is as follows:

[0089] The silicon wafer surface is cleaned with a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to remove dirt on the surface, process temperature: 55-70℃, process time: 2-5min;

[0090] Water washing is used to remove surface drug residues and dirt, cleaning time: 2-3min;

[0091] A mixed solution of potassium hydroxide (1%-10%) and additives (0.5%-5%) is used to form a low reflectivity pyramid textured surface on the silicon wafer surface and remove cutting damage, process temperature: 60-85℃, process time (3-5min);

[0092] Washing with water to remove the surface of the drug residue and dirty, cleaning time: 2min-3min;

[0093] Washing with a mixture of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) solution to remove the surface of the silicon wafer, process temperature: 55-70℃, process time: 2min-5min;

[0094] Washing with water to remove the surface of the drug residue and dirty, cleaning time: 2min-3min;

[0095] Washing with a mixture of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%) solution to remove the surface of the silicon wafer, process temperature: room temperature, process time: 3min-5min;

[0096] Washing with water to remove the surface of the drug residue and dirty, cleaning time: 2min-3min;

[0097] Washing with a mixture of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%) solution to remove the surface of the silicon wafer, process temperature: room temperature, process time: 3min-5min;

[0098] The silicon wafer is placed in the drying tank, high temperature blowing, drying the surface of the silicon wafer, blowing gas: nitrogen or compressed air, temperature: 80-100℃, drying time: 5-15min;

[0099] The silicon wafer weight loss: 0.3-0.6g; (with 182.2 size silicon wafer as an example)

[0100] The surface reflectivity: 9%-12%;

[0101] The tower base size: 1-3um;

[0102] The tower height: 0.5-3um.

[0103] Step S2, the back of the silicon wafer is deposited with a layer of tunneling SiO2 and a layer of phosphorus doped poly, and the front is deposited with a layer of phosphorus doped poly and a layer of SiO2 mask, please refer to Figure 3 The process flow shown in the figure, get as Figure 4 The silicon wafer, the specific process is as follows:

[0104] The back of the silicon wafer is first oxidized from bottom to top by using flat plate type PECVD method to prepare a layer of tunneling SiO2, then a layer of phosphorus doped poly is deposited on the back of the silicon wafer from bottom to top by using flat plate type PVD method, then a layer of phosphorus doped poly is deposited on the front of the silicon wafer from top to bottom by using flat plate type PVD method, and finally a layer of SiO2 mask is deposited on the front of the silicon wafer from top to bottom by using flat plate type PVD method;

[0105] The textured silicon wafer is placed on a hollow carrier plate. Valve 1 is opened and the wafer is transferred into the loading chamber for evacuation. Valve 2 is opened and the wafer is transferred to the PECVD1 reaction chamber 1 to oxidize the silicon wafer surface from bottom to top, thus preparing a layer of tunneled SiO2.

[0106] Open valve 3 and the carrier plate is transferred into transition chamber 1 (gas isolation). Open valve 4 and it is first transferred to buffer chamber 1, then to PVD1 reaction chamber 2 for backside deposition of phosphorus-doped poly from bottom to top, then to PVD2 reaction chamber 3 for frontside deposition of phosphorus-doped poly from bottom to top, then to PVD3 reaction chamber 4 for frontside deposition of SiO2 mask from bottom to top, and finally to buffer chamber 2 to complete the film preparation.

[0107] Open valve 5, the carrier plate is transferred to unloading chamber 1, atmospheric backfill is used with N2, open valve 6, the carrier plate is transferred out of the chamber, and the silicon wafer is collected.

[0108] PECVD1 Reaction Chamber 1: PECVD oxidation of silicon wafers, using oxygen as the process gas, process temperature: 150℃-350℃, process pressure: 5Pa-20Pa, power: 100W-500W;

[0109] PVD1 Reaction Chamber 2: When preparing phosphorus-doped poly by PVD, silicon target and argon are used as working gas, phosphine is used as doping gas, process temperature: 150℃-300℃, process pressure: 0.3Pa-2Pa, power: 10000W-40000W;

[0110] PVD2 reaction chamber 3: When preparing phosphorus-doped poly by PVD, silicon target and argon are used as working gas, phosphine is used as doping gas, process temperature: 150℃-300℃, process pressure: 0.3Pa-2Pa, power: 10000W-40000W;

[0111] PVD3 reaction chamber 4: When preparing SiO2 by PVD, silicon target and argon are used as working gas, and O2 is used as doping gas. Process temperature: 150℃-300℃, process pressure: 0.3Pa-2Pa, power: 10000W-40000W.

[0112] Backside tunneling silicon oxide: Thickness: 0.8nm-1.5nm;

[0113] Backside phosphorus-doped poly: Thickness: 50nm-300nm; Doping concentration: 1E+20cm -3 ~2E+21cm -3 ;

[0114] Phosphorus-doped poly front: Thickness: 5nm-10nm; Doping concentration: 1E+19cm -3 ~1E+20cm -3 ;

[0115] Frontside silicon oxide mask: thickness: 10nm-50nm;

[0116] Device structure:

[0117] The vacuum blocking technology of "transition-isolation-coating-isolation" meets the process pressure of different film layer preparation, avoids the process abnormality caused by "gas stringing" between process gases of different film layer preparation, and meets the film layer preparation of different film layers and different process modes by a single machine. The four-in-one machine prepares SiO2 by back PECVD, phosphorus-doped poly by front and back PVD, and SiO2 by front PVD.

[0118] Transition cavity function: adjust pressure, meet different process pressure conditions switching / different process cavity gas medium blocking;

[0119] Buffer cavity function: secondary isolation and blocking of different gas media.

[0120] Step S3, back N zone laser oxidation to prepare a patterned silicon oxide mask, to obtain a silicon wafer as shown in Figure 5 The specific process is as follows:

[0121] The laser-induced oxidation technology is used to form a patterned silicon oxide mask on the poly of the back N zone of the silicon wafer. The cell is placed on a water platform, a pulsed ultraviolet nanosecond laser is used, and the polycrystalline silicon is locally oxidized to prepare a patterned silicon oxide mask.

[0122] Laser power: 300W-600W;

[0123] Silicon oxide mask: thickness: 5nm-15nm, oxidation area width: 100um-400um, can be freely adjusted.

[0124] Step S4, alkali stripping to remove the tunnel oxide layer and phosphorus-doped poly in the backside SiO2 mask-free area, and etching the silicon substrate to a certain depth, please refer to the process flow shown in Figure 6 to obtain a silicon wafer as shown in Figure 7 The specific process is as follows:

[0125] A mixed solution of potassium hydroxide (1%-10%) and alkali stripping additive (0.5%-5%) is used for cleaning. The potassium hydroxide etches and removes the tunnel oxide layer and phosphorus-doped poly in the backside SiO2 mask-free area, and continues to etch the silicon substrate to a certain depth. Process temperature: 55°C-70°C, process time: 0.5min-1.5min;

[0126] Water washing is used to remove surface drug residues and dirt, and the cleaning time is 2min-3min;

[0127] The silicon wafer surface is cleaned with a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to remove additive residues. Process temperature: 55℃-70℃, process time: 2min-5min.

[0128] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0129] A mixed solution of hydrofluoric acid (0.1%-2%), hydrochloric acid (0.1%-2%), and O3 (10ppm-50ppm) is used to clean the silicon wafer surface. At the same time, the weak etching system of O3 and HF lubricates the silicon wafer surface, reduces burr defects on the silicon wafer surface, and is more conducive to amorphous silicon passivation. Process temperature: 15℃-25℃, process time: 2min-3min.

[0130] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0131] The silicon wafer surface is cleaned using a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%). Process temperature: room temperature; process time: 3 min-5 min.

[0132] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0133] Slow lifting is used to remove dirt from the surface of the silicon wafer, allowing the silicon wafer to dehydrate. The cleaning time is 0.5 min to 1 min, and the cleaning temperature is 20℃ to 70℃.

[0134] Place the silicon wafer in a drying tank and blow it at high temperature to dry the surface of the silicon wafer. The blowing gas is nitrogen or compressed air, the temperature is 80℃-100℃, and the drying time is 5min-15min.

[0135] Cleaning method: The silicon wafer is vertically inserted into the solution, and the direction of the laser line on the silicon wafer is perpendicular to the solution surface. The removal of chemical residues on the silicon wafer surface is not affected by the morphology of the trench on the back side.

[0136] Reflectivity of corroded areas: 35%-45%;

[0137] Size of the corroded tower base: 5um-15um;

[0138] Corrosion depth in the corroded area: 0.5um-2um.

[0139] Step S5: The silicon wafer is placed in a high-temperature annealing furnace tube. At a specific temperature and time, the amorphous silicon is first crystallized at high temperature to activate and advance the doped atoms. Then, the front-side N+ poly atoms are oxidized at high temperature to PSG. The oxide layers formed during annealing on both sides are removed using a mixed solution of hydrofluoric acid and hydrochloric acid, resulting in the desired product. Figure 8 The silicon wafer shown is manufactured using the following process:

[0140] The silicon wafer is inserted horizontally or vertically into a quartz boat, passed through a silicon carbide slurry, and transported to a high-temperature furnace tube;

[0141] The doped amorphous silicon film is crystallized into polycrystalline silicon by high-temperature annealing, and the backside phosphorus atoms are activated to reduce the film layer resistivity and penetrate the silicon oxide to form an N+back field; the frontside phosphorus atoms are activated to advance to the silicon wafer to form an N+front passivation field;

[0142] High-temperature oxygen oxidation, thin poly on the frontside is oxidized to SiO2 and then removed, and the thick poly on the backside has no effect;

[0143] The silicon wafer surface is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3-5 minutes;

[0144] The surface drug residue and dirt are removed by water washing, and the cleaning time is 2-3 minutes;

[0145] The silicon wafer surface is cleaned with a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%), the process temperature is room temperature, and the process time is 3-5 minutes;

[0146] The silicon wafer is placed in a drying tank and dried at high temperature, the blowing gas is nitrogen or compressed air, the temperature is 80-100°C, and the drying time is 5-15 minutes;

[0147] The cleaning method is that the silicon wafer is vertically inserted into the solution, the laser line direction of the silicon wafer is perpendicular to the solution surface, and the silicon wafer surface drug residue is separated without being affected by the backside trench morphology;

[0148] The high-temperature crystallization promotion temperature is 850-910°C;

[0149] The high-temperature crystallization promotion time is 30-60 minutes;

[0150] The high-temperature oxidation temperature is 800-850°C;

[0151] The high-temperature oxidation time is 10-30 minutes.

[0152] Step S6, i-a:Si / P:a-Si deposition on the backside of the silicon wafer, please refer to the process flow shown in Figure 9 to obtain a silicon wafer as shown in Figure 10 The specific process is as follows:

[0153] The backside of the silicon wafer after pickling is first deposited with i:a-Si from top to bottom by using a flat plate type PECVD method, and then the deposited surface is cleaned by HPT (H ion cleaning). Then, the backside of the silicon wafer is first deposited with P:a-Si from top to bottom by using a flat plate type PECVD method, including one layer of P:a-Si and one layer of P-uc-SiOx C y );

[0154] After the double-sided alkali polishing of the silicon wafer, the silicon wafer is placed on the hollow carrier plate, the door valve 7 is opened, and the transmission enters the loading cavity to be evacuated, the door valve 8 is opened, and the transmission enters the buffer preheating cavity 3, and then the transmission enters the PECVD 2 reaction cavity 5 to deposit i-a:Si from top to bottom, and then the transmission enters the HPT cleaning buffer cavity 4 to clean the deposited surface by H ions, and the preparation of i:a-Si is completed;

[0155] The door valve 9 is opened, the carrier plate is transmitted into the transition cavity 2 (gas isolation), the door valve 10 is opened, and the transmission enters the buffer 5 first, and then the transmission enters the PECVD 3 reaction cavity 6 to deposit a layer of P:a-Si and a layer of P-uc-SiOxCy from top to bottom, and then the transmission enters the buffer 6, and the preparation of P:a-Si is completed; x C y The door valve 9 is opened, the carrier plate is transmitted into the transition cavity 2 (gas isolation), the door valve 10 is opened, and the transmission enters the buffer 5 first, and then the transmission enters the PECVD 3 reaction cavity 6 to deposit a layer of P:a-Si and a layer of P-uc-SiOxCy from top to bottom, and then the transmission enters the buffer 6, and the preparation of P:a-Si is completed;

[0156] The door valve 11 is opened, the carrier plate is transmitted into the unloading cavity 2, and the nitrogen is backfilled to the atmosphere, the door valve 12 is opened, and the carrier plate is transmitted out of the cavity;

[0157] The PECVD 2 reaction cavity 5: i:a-Si is prepared by the PECVD method, using SiH4 and H2 as process gases, process temperature: 100-250℃, process pressure: 10-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50-300W;

[0158] The PECVD 3 reaction cavity 6: P:a-Si is prepared by the PECVD method, and P:a-Si is divided into two layers: conventional B-doped amorphous silicon (P-a:Si) and B-doped microcrystalline carbon silicon oxide (P-uc-SiOxCy); x C y );

[0159] The conventional B-doped amorphous silicon (P:a-Si) is prepared by using SiH4, H2 and B2H6 as process gases, process temperature: 100-250℃, process pressure: 10-50Pa, SiH4:H2:B2H6(2%) flow ratio: 1:20:5-1:30:15, power: 50-300W;

[0160] The B-doped microcrystalline carbon silicon oxide (P-uc-SiOxCy) is prepared by using SiH4, H2, B2H6, CO2 and TMB as process gases, process temperature: 100-250℃, process pressure: 50-100Pa, SiH4:H2:B2H6(2%) flow ratio: 1:30:10-1:60:30, CO2 and TMB as micro-doped gases flow: 5-20sccm, power: 300-500W;

[0161] HPT cleaning buffer cavity 4: using PECVD method to ionize H, clean the deposited surface of silicon wafer, using H2 as process gas,

[0162] Process temperature: 100-250℃, process pressure: 50-100Pa, power: 50-400W;

[0163] i: a-Si thickness: 2-10nm, freely adjustable;

[0164] P: a-Si thickness: 10-20nm, P-uc-SiO x C y Thickness: 20-50nm, thickness freely adjustable;

[0165] P: a-Si doping concentration: 1E+18cm -3 -5E+18cm -3 : P-uc-SiO x C y Doping concentration: 5E+18cm -3 -2E+19cm -3 , doping amount freely adjustable.

[0166] Step S7, using inkjet printing technology to prepare a patterned mask on the amorphous surface of P area, to obtain a silicon wafer as shown in Figure 11 , the specific process is as follows:

[0167] Using non-contact inkjet printing technology, printing ink on the back of the silicon wafer P area amorphous non-contact, forming a patterned ink mask;

[0168] Ink width: 100-500um

[0169] Ink height: 10-20um.

[0170] Step S8, ion etching to remove the amorphous silicon in the back of the ink mask area, please refer to Figure 12 , the process flow is shown in the silicon wafer as shown in Figure 13 , the specific process is as follows:

[0171] Using RIE ion etching technology to remove the amorphous silicon in the back of the ink mask area, and etching part of the ink mask;

[0172] After non-contact inkjet printing, the silicon wafer is placed on the hollow carrier plate with the back up, the door valve 13 is opened, and the transmission is carried out to the loading cavity 3 to be evacuated, the door valve 14 is opened, and the transmission is carried out to the ion etching cavity to carry out ion etching, the door valve 15 is opened, and the transmission is carried out to the unloading cavity 3, and the nitrogen is backfilled to the atmosphere, and the door valve 16 is opened, and the carrier plate is transmitted out of the cavity;

[0173] Ion etching cavity: using nitrogen trifluoride as working gas, radio frequency power excitation plasma, bombard silicon wafer back, etching amorphous silicon without mask area.

[0174] Step S9, organic solvent ultrasonic cleaning silicon wafer, remove back ink mask, please refer to Figure 14 The process flow shown in the figure, get as Figure 15 The wafer, the specific process is as follows:

[0175] Using isopropyl alcohol + water mixed solution ultrasonic cleaning, remove back ink mask, cleaning time: 2min-3min, cleaning temperature: 40℃-60℃;

[0176] Using water washing to remove surface drug residue and dirt, cleaning time: 2min-3min;

[0177] Using slow pull to remove the surface dirt of silicon wafer, make the silicon wafer dehydrated, cleaning time 0.5min-1min, cleaning temperature: 20℃-70℃;

[0178] The silicon wafer is placed in the drying tank, high temperature blowing, drying the surface of the silicon wafer, blowing gas: nitrogen or compressed air, temperature: 80℃-100℃, drying time: 5min-15min.

[0179] Step S10, the back of the silicon wafer is cleaned by HPT, and a layer of TCO transparent conductive film is deposited on the back, please refer to Figure 16 The process flow shown in the figure, get as Figure 17 The wafer, the specific process is as follows:

[0180] Using flat plate type PECVD method to HPT (H ion cleaning) on the back of the silicon wafer, and then depositing a layer of TCO transparent conductive film;

[0181] The cleaned silicon wafer is placed in the hollow carrier plate with the back up, the door valve 17 is opened, the loading is vacuumized, the door valve 18 is opened, the HPT cleaning buffer cavity 7 is entered, and the silicon wafer is cleaned by H ion;

[0182] The door valve 19 is opened, the carrier plate is transmitted to the transition cavity 2 to be evacuated (gas isolation), the door valve 20 is opened, the carrier plate is transmitted to the buffer cavity 2 (secondary isolation), the carrier plate is transmitted to the PVD 4 reaction cavity 7, a layer of TCO is deposited from bottom to top, and then the carrier plate is transmitted to the buffer cavity 9 to complete the preparation of TCO transparent conductive film;

[0183] The door valve 21 is opened, the carrier plate is transmitted to the unloading cavity 4, nitrogen is used to refill the atmosphere, the door valve 22 is opened, and the carrier plate is transmitted out of the cavity.

[0184] Step S11, laser etching TCO, N area P area isolation, get as Figure 18 The wafer, the specific process is as follows:

[0185] Using laser ablation technology, the TCO at the junction of the back P region and N region is patterned and etched, the cell is placed on a water platform, and a pulsed ultraviolet nanosecond laser is used to pattern and etch the TCO at the junction of the back P region and N region;

[0186] Laser power: 300w-600w;

[0187] Etching width: 10um-20um, freely adjustable.

[0188] Step S12, depositing aluminum oxide on the front surface, and depositing a layer of gradient silicon nitride on the front and back surfaces to reduce reflection and passivation, please refer to the process flow shown in Figure 19 The silicon wafer shown in Figure 20 The specific process is as follows:

[0189] First, a layer of aluminum oxide is deposited on the front surface of the silicon wafer using a flat plate or tube ALD or flat plate PECVD method, and then a layer of silicon nitride is deposited on the front and back surfaces of the silicon wafer using a flat plate PECVD method.

[0190] After laser ablation isolation, the silicon wafer is placed on the hollow carrier with the front surface facing up, the door valve 23 is opened, the carrier is transferred to the preheating loading cavity 5 for preheating and evacuation, the door valve 24 is opened, the carrier is transferred to the PECVD 4 reaction cavity 8, and a layer of aluminum oxide is deposited on the front surface from top to bottom using PECVD method, and the preparation of aluminum oxide is completed;

[0191] Open door valve 25, the carrier is first transferred to the transition cavity 3, evacuated (gas isolation), open door valve 26, then transferred to the buffer cavity 10, and then transferred to the PECVD 5 reaction cavity 9, deposited on the front surface from top to bottom and on the back surface from bottom to top, a layer of high H content SiNx, a layer of high Si content SiNx, and a layer of high N content SiNx, and then transferred to the buffer cavity 11, to complete the preparation of double-sided gradient silicon nitride antireflection passivation film;

[0192] Open door valve 26, the carrier is transferred to the unloading cavity 5, and the atmosphere is filled with nitrogen, open door valve 27, the carrier is transferred out of the cavity;

[0193] PECVD 4 reaction cavity 8: aluminum oxide is prepared by PECVD method, using trimethylaluminum and laughing gas as working gas, process temperature: 150-250℃, process pressure: 20-50Pa, trimethylaluminum / laughing gas flow ratio: 1:1-3:1, power: 100-500W;

[0194] PECVD 5 reaction cavity 9: SiNx gradient passivation antireflection film is prepared by PECVD method, which is divided into three layers;

[0195] SiNx-1: high H content silicon nitride is prepared by using SiH4, H2 and NH3 as process gas, high H2 ratio, high pressure and high power, passivation of silicon wafer interface, process temperature: 100-250℃, process pressure: 80-120Pa, SiH4 / NH3 / H2 flow ratio: 1:1:6-2:2:20, power: 200-300W;

[0196] SiNx-2: high Si content and high density silicon nitride is prepared by using SiH4 and NH3 as process gas, high SiH4 ratio, low pressure and low power, protection of high H content silicon nitride, and low power coating to reduce passivation damage of SiNx-1, process temperature: 100-250℃, process pressure: 30-50Pa, SiH4 / NH3 flow ratio: 2:1-6:1, power: 100-200W;

[0197] SiNx-3: high N content silicon nitride is prepared by using SiH4 and NH3 as process gas, high NH3 ratio, low pressure and low power, reduction of overall film layer refractive index, reduction of positive surface reflectivity, and improvement of current density, process temperature: 100-250℃, process pressure: 30-50Pa, SiH4 / NH3 flow ratio: 1:2-1:6, power: 100-200W;

[0198] Step S13: laser slotting, local windowing of N region and P region SiNx, exposing TCO, slotting area screen printing low temperature metal paste curing light injection, obtaining a silicon wafer as shown in Figure 21 The specific process is as follows:

[0199] Laser slotting technology is used to locally window N region and P region SiNx, exposing TCO;

[0200] Metal paste is printed in the windowed area of the back N region and P region;

[0201] After printing, the silicon wafer is transferred to a curing oven for drying and curing, and ohmic contact is formed with TCO;

[0202] The battery is transferred to an annealing furnace for annealing and light injection, H is excited, and passivation is improved;

[0203] BC battery preparation is completed;

[0204] Laser slotting width: 10-30um.

[0205] In summary, the present application uses a tunneling SiO2 layer and a high-crystallization rate N+ poly field structure with low parasitic absorption to replace the traditional HBC i:a-Si+N:a:Si field structure to improve current density, uses a textured light-trapping structure to replace a polished structure to improve current density, increases the contact area of the metal electrode to reduce contact resistance and improve the fill factor, adds a low-temperature silicon nitride anti-reflection film to the upper layer of the TCO transparent conductive film to improve passivation and current density, covers the P region and N region isolation region with silicon nitride to reduce reflection and improve passivation and current density, uses an i:a-Si+P:a-Si+P-uc-SiOxCy emitter film layer structure to replace the traditional i:a-Si+P:a-Si, and introduces microcrystalline boron-doped carbon-doped silicon oxide to reduce film layer parasitic absorption and improve current density, thereby improving the back surface efficiency of the battery and improving the bifacial rate.

[0206] Based on the above ideal embodiments according to the present application, through the above description, relevant personnel can make various changes and modifications without deviating from the technical idea of the present application. The technical scope of the present application is not limited to the content of the specification, and must be determined according to the scope of the claims.

Claims

1. A method of fabricating a back contact (BC) solar cell, characterized by, It comprises the following steps: Step S1, double-side texturing is performed on the silicon wafer to prepare a clean silicon wafer surface with a low-reflectivity pyramid texturing pattern; Step S2, a tunneling SiO2 layer is prepared on the back surface of the silicon wafer by oxidation from bottom to top, a phosphorus-doped N+poly layer is deposited on the tunneling SiO2 layer from bottom to top, a phosphorus-doped N+poly layer is deposited on the front surface of the silicon wafer from top to bottom, and a SiO2 mask layer is deposited on the phosphorus-doped N+poly layer from top to bottom; Step S3, laser oxidation is performed on the phosphorus-doped N+poly layer on the back surface of the silicon wafer to prepare a SiO2 mask layer; Step S4, alkaline cleaning is performed on the silicon wafer to remove the tunneling SiO2 layer and the phosphorus-doped N+poly layer in the region without the SiO2 mask layer on the back surface and the SiO2 mask layer on the front surface, and the silicon substrate on the back surface is exposed by etching; Step S5, high-temperature annealing is performed on the silicon wafer to crystallize and activate amorphous silicon, promote the doping atoms, form N+front passivation field and N+inner extension layer on the front and back surfaces of the silicon wafer respectively, remove the SiO2 mask layer after high-temperature oxidation of the phosphorus-doped N+poly layer on the front surface to obtain a FSF layer, and perform acid washing treatment; Step S6, an i:a-Si layer is deposited on the back surface of the silicon wafer after acid washing from top to bottom, and a P:a-Si layer is deposited on the deposited surface after HPT cleaning; Step S7, a patterned mask is prepared on the amorphous surface of the P region on the back surface of the silicon wafer by inkjet printing; Step S8, ion etching is used to remove the amorphous silicon in the P region on the back surface of the silicon wafer without the patterned mask; Step S9, the silicon wafer is cleaned by ultrasonic cleaning with an organic solvent, and the patterned mask on the back surface is removed; Step S10, HPT cleaning is performed on the back surface of the silicon wafer, and a TCO transparent conductive film is deposited; Step S11, laser etching is performed on the back surface of the silicon wafer to isolate the N region and the P region; Step S12, an aluminum oxide layer is deposited on the front surface of the silicon wafer, and a stack of gradient silicon nitride anti-reflection passivation films is deposited on the front and back surfaces of the silicon wafer respectively; Step S13, laser grooving is used to locally open a window in the stack of gradient silicon nitride anti-reflection passivation films on the N region and the P region on the back surface of the silicon wafer to expose the TCO transparent conductive film, and low-temperature metal paste is screen printed in the grooving area and solidified by light injection; In the step S6, The thickness of the i:a-Si layer is 2-10 nm; The P:a-Si layer includes a P:a-Si sublayer and a P-uc-SiO x C y sublayer; Wherein The thickness of the P: a-Si layer is 10-20 nm and the doping concentration is 1E+18 cm -3 ~5E+18 cm -3 : The P-uc-SiO x C y The thickness of the layer is 20-50 nm and the doping concentration is 5E+18 cm -3 ~ 2E+19 cm -3 .

2. The preparation method of the back contact BC solar cell according to claim 1, characterized in that: The reflectivity of the polished silicon wafer surface in the step S1 is 9-12%; The size of the tower base is 1-3 μm, and the height of the tower is 0.5-3 μm.

3. The preparation method of the back contact BC solar cell according to claim 1, characterized in that: In the step S2, The thickness of the tunneling SiO2 layer located at the back of the silicon wafer is 0.8-1.5 nm, the thickness of the phosphorus-doped N+poly layer is 50-300 nm, and the doping concentration is 1E+20 cm -3 ~2E+21 cm -3 : The thickness of the SiO2 mask layer on the front surface of the silicon wafer is 10-50 nm, the thickness of the phosphorus-doped N+ poly layer is 5-10 nm, and the doping concentration is 1E+19 cm -3 ~1E+20 cm -3 .

4. The preparation method of the back contact BC solar cell according to claim 1, characterized in that: In the step S3, The thickness of the SiO2 mask layer on the back surface of the silicon wafer is 5-15 nm, and the width of the oxidation region is 100-400 μm.

5. The preparation method of the back contact BC solar cell according to claim 1, characterized in that: In the step S4, The reflectivity of the etched region is 35-45%. The tower base of the etched area is 5-15 μm; The etching depth of the etched area is 0.5-2 μm.

6. The method for preparing the back contact BC solar cell according to claim 1, wherein: in the step S5, the temperature of the high-temperature crystallization is 850-910 ℃; the time of the high-temperature crystallization is 30-60 min; the temperature of the high-temperature oxidation is 800-850 ℃; the time of the high-temperature oxidation is 10-30 min.

7. The method for preparing the back contact BC solar cell according to claim 1, wherein: in the step S7, the width of the patterned mask prepared from the ink is 100-500 μm, and the height is 10-20 μm.

8. The method for preparing the back contact BC solar cell according to claim 1, wherein: in the step S11, the laser power is 300-600 W, and the etching width is 10-20 μm; in the step S13, the width of the laser grooving is 10-30 μm.

9. A back contact BC solar cell structure prepared by the method according to any one of claims 1-8, wherein: the back N area of the cell is provided with a tunneling SiO2 layer and a phosphorus-doped N+ poly layer with high crystallization rate and low parasitic absorption; The P region is provided with i: a-Si layer, P: a-Si sublayer and P-uc-SiO in turn x C y sublayer the front of the cell is provided with a stack of gradient silicon nitride antireflection passivation films.

Images