Hbc solar cell structure and its non-amorphous damage-free preparation method

Abstract

The application belongs to the technical field of crystalline silicon solar cells, and particularly relates to an HBC solar cell structure and a non-amorphous damage preparation method thereof, which comprises the following steps: step S1, polishing both sides of a silicon wafer; step S2, depositing an i:a-Si layer, a P:a-Si layer, a high work function TCO layer and an i:a-Si mask layer on the back of the silicon wafer from top to bottom; step S3, laser oxidizing the P area of the back of the silicon wafer; step S4, wet cleaning the back of the silicon wafer; step S5, depositing an i:a-Si layer, an N:a-Si layer, a low work function TCO layer and an i:a-Si mask layer on the back of the silicon wafer from top to bottom; step S6, laser oxidizing the N area of the back of the silicon wafer; step S7, cleaning the back of the silicon wafer and texturing the front of the silicon wafer; step S8, preparing an aluminum oxide layer and a silicon nitride layer on the front and back of the silicon wafer, and filling an isolation area of an isolation interdigital arrangement structure; step S9, laser opening a mask on the back of the silicon wafer; and step S10, printing metal paste in a windowed area to complete the preparation of the solar cell.

Description

Technical Field

[0001] This invention belongs to the field of crystalline silicon solar cell technology, specifically relating to an HBC solar cell structure and its amorphous damage-free fabrication method. Background Technology

[0002] Photovoltaic power generation is a system that directly converts sunlight into electrical energy using solar cells based on the photovoltaic effect. The basic structure of a solar cell is a large-area planar PN junction. When sunlight shines on the PN junction, the junction absorbs the light energy and excites electrons and holes, subsequently generating a voltage in the PN junction, thus achieving photoelectric conversion. Therefore, the core structure for converting sunlight into electrical energy in crystalline silicon cells is the PN junction.

[0003] As PERC cells gradually approach their efficiency limit of 24.5%, the industry has begun to seek next-generation crystalline silicon cell technologies. Currently, the mainstream technologies being promoted include Topcon (tunneling oxide passivation contact), HJT (heterojunction), and IBC (interdigitated back contact). Unlike Topcon and HJT, which improve cell efficiency by changing the passivation method, IBC cells move all the cell grid lines to the back side, reducing the grid line shading area, increasing current density, and thus increasing cell efficiency. IBC cells are a platform technology; when combined with Topcon technology, it forms TBC, and when combined with HJT technology, it forms HBC.

[0004] However, the existing HBC battery fabrication process is complex, and the amorphous interdigitated structure of the N and P regions on the back side is particularly difficult to fabricate and is easily damaged. Therefore, how to provide a fabrication method for HBC batteries that can reduce damage to the amorphous interdigitated structure is a technical problem that urgently needs to be solved in this field.

[0005] It should be noted that the information disclosed in this background section is only for understanding the background technology of the present application concept, and therefore, the above description is not considered to constitute prior art information. Summary of the Invention

[0006] This disclosure provides at least one HBC solar cell structure and its amorphous damage-free fabrication method.

[0007] In a first aspect, embodiments of this disclosure provide a method for fabricating an HBC solar cell without amorphous damage, comprising the following steps: Step S1, double-sided polishing of a silicon wafer to prepare a clean silicon wafer surface with a lubricating alkali polishing tower-based morphology; Step S2, deposition of an i:a-Si layer on the back side of the silicon wafer from top to bottom, followed by HPT cleaning of the deposited surface and subsequent deposition of a P:a-Si layer, a high work function TCO layer, and an i:a-Si mask layer from top to bottom; Step S3, laser oxidation of the P-region on the back side of the silicon wafer to form a patterned silicon oxide mask on the outer side of the outer i:a-Si mask layer; Step S4, wet cleaning of the back side of the silicon wafer to remove the deposited layers of the patterned silicon oxide mask and the unmasked areas, and etching the silicon substrate and cleaning the silicon wafer; Step S5, deposition of an i:a-Si layer on the back side of the silicon wafer from top to bottom, followed by HPT cleaning of the deposited surface. After cleaning, an N:a-Si layer, a low work function TCO layer, and an i:a-Si mask layer are deposited sequentially from top to bottom. Step S6 involves laser oxidation of the N-region on the back side of the silicon wafer, forming a patterned silicon oxide mask outside the outer i:a-Si mask layer. Step S7 involves cleaning the back side of the silicon wafer to expose the N-region and P-region TCO layers and fabricating an interdigitated structure separating the P-region amorphous high work function TCO layer and the N-region amorphous low work function TCO layer. Simultaneously, texturing is performed on the front side of the silicon wafer. Step S8 involves sequentially fabricating an aluminum oxide layer and a silicon nitride layer on the front and back sides of the silicon wafer, filling the isolation areas of the interdigitated structure. Step S9 involves laser delamination of the back side of the silicon wafer, creating partial windows to expose the high work function TCO layer and the low work function TCO layer. Step S10 involves printing metal paste in the windowed area on the back side of the silicon wafer, curing it, and then photoinjecting it to complete the cell fabrication.

[0008] In one optional embodiment, the reflectivity of the polished silicon wafer surface in step S1 is 30-45%; the size of the tower base is 5-15 μm.

[0009] In one optional embodiment, the thickness of the i:a-Si layer in step S2 is 2-10 nm; the P:a-Si layer comprises P:a-Si layering and P-uc-SiO. x C y Layering; wherein the thickness of the P:a-Si layer is 10-20 nm, and the doping concentration is 1E+18 cm⁻¹. -3 ~5E+18cm -3 The P-uc-SiO x C y The thickness of the layer is 20-50 nm, and the doping concentration is 5E+18 cm⁻¹. -3 ~2E+19cm -3The high work function TCO layer has a thickness of 70-150 nm and a sheet resistance of 50-120 Ω. The target material of the high work function TCO layer includes In2O3 and SnO2 in a mass ratio of (90-95):(5-10). The thickness of the i:a-Si mask layer is 20-40 nm.

[0010] In one optional embodiment, the thickness of the patterned silicon oxide mask in steps S3 and S6 is 5-15 nm, and the width of the oxide region is 150-500 μm.

[0011] In one optional embodiment, in step S4, the reflectivity of the corroded area is 35-45%; the size of the tower base of the corroded area is 8-15 μm; and the corrosion depth of the corroded area is 0.5-2 μm.

[0012] In one optional embodiment, the thickness of the i:a-Si layer in step S5 is 2-10 nm; the N:a-Si layer includes N:a-Si layering and N-uc-Si layering; wherein the thickness of the N:a-Si layering is 10-20 nm, and the doping concentration is 1E+18 cm⁻¹. -3 ~5E+18cm -3 The thickness of the N-uc-Si layer is 20-50 nm, and the doping concentration is 5E+18 cm⁻¹. -3 ~2E+19cm -3 The thickness of the low work function TCO layer is 70-150 nm, and the sheet resistance is 50-120 Ω. The target material of the low work function TCO layer includes In2O3 and SnO2 with a mass ratio of (95-98):(2-5). The thickness of the i:a-Si mask layer is 20-40 nm.

[0013] In one optional embodiment, the thickness of the alumina layer in step S8 is 2-20 nm, and the thickness of the silicon nitride layer is 10-40 nm.

[0014] In one optional implementation, the width of the membrane opening in step S9 is 10-50 μm.

[0015] Secondly, this disclosure also provides an HBC solar cell structure prepared by the method described above, wherein the back side of the cell includes an isolated interdigitated structure of an amorphous high work function TCO layer in the P region and an amorphous low work function TCO layer in the N region, and the isolation regions of the P region and the N region are filled with an aluminum oxide layer and a silicon nitride layer.

[0016] Thirdly, embodiments of this disclosure also provide a photovoltaic module that employs the HBC solar cell structure as described above.

[0017] The beneficial effects of this invention are that the HBC solar cell structure and its amorphous damage-free fabrication method adopt a TCO layer + i:a-Si mask layer + laser oxidation and selective etching cleaning process, which protects the amorphous TCO layer in the N and P regions from direct laser contact and acid-base contact, ensuring no damage to the amorphous silicon and greatly improving the upper limit of cell efficiency. In addition, the isolated interdigitated arrangement structure of the P-region amorphous high work function TCO layer and the N-region amorphous low work function TCO layer on the back also overcomes the problem of matching the work function of the amorphous TCO in the N and P regions on the back of the traditional HBC cell with the TCO, improving the cell current and fill factor, and improving the bifaciality.

[0018] Other features and advantages of the invention will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention are realized and obtained through the structures particularly pointed out in the description and the drawings.

[0019] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0021] Figure 1 A process flow diagram of an HBC solar cell provided in this disclosure embodiment;

[0022] Figure 2 This is a schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0023] Figure 3 A process flow diagram of an HBC solar cell provided in this disclosure embodiment;

[0024] Figure 4 This is a schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0025] Figure 5 This is a schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0026] Figure 6 A process flow diagram of an HBC solar cell provided in this disclosure embodiment;

[0027] Figure 7 This is a schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0028] Figure 8 A process flow diagram of an HBC solar cell provided in this disclosure embodiment;

[0029] Figure 9 This is a schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0030] Figure 10 This is a schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0031] Figure 11 A process flow diagram of an HBC solar cell provided in this disclosure embodiment;

[0032] Figure 12 This is a schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0033] Figure 13 A process flow diagram of an HBC solar cell provided in this disclosure embodiment;

[0034] Figure 14 This is a schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0035] Figure 15 This is a schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure;

[0036] Figure 16 This is a schematic diagram of the structure of an HBC solar cell provided in an embodiment of the present disclosure. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] As used herein, the phrases “in one embodiment,” “according to one embodiment,” “in some embodiments,” etc., generally refer to the fact that a particular feature, structure, or characteristic following the phrase can be included in at least one embodiment of this disclosure. Therefore, a particular feature, structure, or characteristic can be included in more than one embodiment of this disclosure, such that these phrases do not necessarily refer to the same embodiment. As used herein, the terms “example,” “exemplary,” etc., are used to “serve as an example, instance, or illustration.” Any implementation, aspect, or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or superior to other implementations, aspects, or designs. Rather, the use of the terms “example,” “exemplary,” etc., is intended to present concepts in a specific manner.

[0039] In this document, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. As used herein, expressions such as “at least one of…” modify the entire list of elements when following a list of elements, rather than individual elements in the list. For example, the expression “at least one of a, b, and c” should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0040] The terminology used herein is for the purpose of describing specific exemplary configurations only and is not intended to be limiting. As used herein, the singular articles “a,” “an,” and “the” may also be intended to include plural forms unless otherwise clearly stated herein. The terms “comprising,” “including,” and “having” are inclusive and thus specify the presence of features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein should not be construed as requiring them to be performed in the specific order discussed or shown, unless specifically identified as such. Additional or alternative steps may be employed.

[0041] The IBC battery is characterized by the absence of electrodes on the front side, with the positive and negative electrode grids integrated in a forked pattern on the back side. Its main features include: 1. Utilizing a high minority carrier lifetime silicon wafer to prevent carrier recombination before reaching the PN junction; 2. Integration of positive and negative electrodes on the back side with a large design window for the grid pattern; 3. Front-side anti-reflection stacking and front surface field design to maximize optical utilization and reduce front surface recombination; 4. Forked arrangement of N-region and P-region on the back side, with the P-region (emitter) collecting holes and the N-region (back field) capturing electrons; 5. Combining with thin-film heterojunction (HJT) technology to fabricate the N-region field electrode and P-region emitter, improving the battery's passivation level.

[0042] The advantages of IBC cells are: 1. No grid lines obstructing the front, resulting in high photon absorption and high current density; 2. Combined with HJT technology, the current density and efficiency of the cells are improved without passivation loss; 3. Both positive and negative electrodes are on the back, which can increase the grid line width, reduce contact resistance, improve FF, and has no significant impact on the current; 4. The grid-free design on the front of the cell makes it aesthetically pleasing and provides significant advantages for BIPV (Building Integrated Photovoltaics) applications.

[0043] The challenges of HBC cells include: 1. Low bifaciality (the grid lines are integrated on the back side, resulting in an increased back-side shading area and a significant difference in efficiency between the front and back sides); 2. Complex processes, numerous steps, expensive equipment, high costs, and low yield (traditional HBC cell fabrication processes include: texturing and cleaning -- front i:a-Si -- front SiNx -- back i:a-Si -- back P:a-Si -- back mask -- laser grooving -- etching -- back i:a-Si -- back N:a-Si -- laser film removal -- etching -- back TCO -- laser film removal to isolate the PN region -- printing and curing -- light injection); 3. The fabrication of the amorphous interdigitated structure of the N and P regions on the back side is difficult (it is difficult to accurately locate the film removal area and the film removal depth with a laser); 4. HBC cells have high requirements for silicon wafer quality and front surface passivation (carriers need to pass through the front surface and body regions of the silicon wafer to reach the back side after separation from the PN junction; defects in the front surface of the cell can cause carrier recombination before the carriers reach the PN junction).

[0044] Prior art 1: Patent No. CN 115050855 A

[0045] Solution steps: 1. Double-sided texturing; 2. Back-side polishing; 3. Double-sided deposition of ia:Si; 4. Back-side patterned boron paste printing and drying; 5. Back-side patterned phosphate paste printing and drying; 6. N-region and P-region laser doping; 7. Organic-water mixed solution ultrasonic cleaning of the paste; 8. Back-side TCO deposition; 9. Laser grooving to isolate N-region and P-region; 10. Front-side deposition of SiO / SiON / SiN laminated film; 11. Screen printing, curing, and sintering.

[0046] Concept: 1. From top to bottom: SiN / SiON / SiO---ia:Si---textured---silicon-based---polished---ia:Si---Pa:Si---Na:Si---TCO---silver paste HBC cell structure;

[0047] 2. Si is deposited on the back of the battery. Boron paste and phosphorus paste are cross-printed using a stencil. After drying, laser doping, and cleaning, the poly finger-like arrangement structure of the N and P regions on the back of the battery is completed.

[0048] shortcoming:

[0049] 1. Using doped slurry as the doping source, the doped slurry has special fluidity and corrosiveness, so it requires the use of professional doctor blades, adhesive scrapers, and special non-metallic mesh cloth, which are not mass-produced auxiliary materials on the market;

[0050] 2. To meet printing requirements, doped pastes often contain a large amount of organic solvents to achieve curing. However, organic solvents can affect the diffusion effect of boron and phosphorus doping, resulting in poor diffusion uniformity.

[0051] 3. To meet printing requirements, adulterated pastes often contain a large amount of organic solvents, resulting in a strong odor. This necessitates high levels of ventilation and protective measures for employees.

[0052] 4. Laser boron phosphorus paste doping of amorphous silicon is difficult to control in terms of doping amount and depth, which can easily damage the underlying hydrogenated amorphous silicon and affect cell passivation.

[0053] 5. The ARC antireflective coating on the front side is prepared at a high temperature of >200℃, which can easily lead to a decrease in amorphous silicon passivation;

[0054] 6. The front side adopts a SiNx+ia:Si antireflection passivation film design, which has large parasitic absorption and large battery current loss;

[0055] 7. In this process, amorphous silicon is exposed for a long time without a protective film, which affects the passivation of the battery.

[0056] Prior Art 2: CN 218849510 U

[0057] The process steps are as follows: 1. Cleaning and texturing; 2. Preparation of silicon oxide and intrinsic amorphous silicon on the back side; 3. High-temperature phosphorus diffusion to crystallize the amorphous silicon on the back side into phosphorus-doped polycrystalline silicon; 4. Laser etching; 5. Poly cleaning to remove the plating and diffusion, alkaline polishing to clean the laser ablation area until the N-type silicon substrate is reached; 6. Deposition of intrinsic amorphous silicon on the front side; 7. Preparation of silicon nitride on the front side; 8. Preparation of intrinsic amorphous silicon and P:a-Si using back-side mask-grooving-deposition-etching technology; 9. Preparation of TCO using back-side mask-grooving-deposition-etching technology; 10. Screen printing and curing of electrodes.

[0058] concept:

[0059] The back N-region and P-region are prepared using the traditional mask-groove-deposition-etching method. The N-region uses a polo passivation contact structure of SiO and N+poly to replace the i:a-Si+N:a:Si battery structure.

[0060] shortcoming:

[0061] 1. The front side adopts a SiNx+ia:Si antireflection passivation film design, which has large parasitic absorption and large battery current loss;

[0062] 2. The passivation effect at the interface of the SiO and N+poly polo passivation contact structure in the N region on the back side is poor.

[0063] 3. The back N-region N+poly is prepared using a high-temperature tubular device, which involves wrapping and plating.

[0064] The shortcomings of the above solutions are the result of the inventor's practical experience and careful research. Therefore, the discovery process of the above problems and the solutions proposed in this disclosure below should be considered as the inventor's contribution to this disclosure.

[0065] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0066] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0067] Step S1 involves double-sided polishing of the silicon wafer to prepare a slippery alkali polishing tower base morphology and a clean silicon wafer surface. Please refer to [link to relevant documentation]. Figure 1 The process flow shown yields the following results: Figure 2 The silicon wafer shown is manufactured using the following process:

[0068] The silicon wafer surface is cleaned with a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-15%) to remove dirt. Process temperature: 55℃-70℃, process time: 2min-5min.

[0069] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0070] A mixed solution of potassium hydroxide (1%-10%) and additives (0.5%-5%) is used to polish the surface of silicon wafers to form an alkaline polishing tower-based morphology and remove cutting damage. The process temperature is 60℃-85℃ and the process time is 3min-5min.

[0071] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0072] The silicon wafer surface is cleaned with a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to remove additive residues. Process temperature: 55℃-70℃, process time: 2min-5min.

[0073] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0074] A mixed solution of hydrofluoric acid (0.1%-2%), hydrochloric acid (0.1%-2%), and O3 (10ppm-50ppm) is used to clean the silicon wafer surface. At the same time, the weak etching system of O3 and HF lubricates the silicon wafer surface, reduces burr defects on the silicon wafer surface, and is more conducive to amorphous silicon passivation. Process temperature: 15℃-25℃, process time: 2min-3min.

[0075] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0076] The silicon wafer surface is cleaned using a mixed solution of hydrofluoric acid (1%-10%) and hydrochloric acid (1%-10%). Process temperature: room temperature; process time: 3 min-5 min.

[0077] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0078] Slow lifting is used to remove dirt from the surface of the silicon wafer, allowing the silicon wafer to dehydrate. The cleaning time is 0.5 min to 1 min, and the cleaning temperature is 20℃ to 70℃.

[0079] Place the silicon wafer in a drying tank and blow it at high temperature to dry the surface of the silicon wafer. The blowing gas is nitrogen or compressed air, the temperature is 80℃-100℃, and the drying time is 5min-15min.

[0080] Silicon wafer weight reduction: 0.3g-0.6g; (taking a 182.2mm silicon wafer as an example)

[0081] Surface reflectivity: 30%-45%;

[0082] Tower base size: 5um-15um.

[0083] Step S2, mask deposition of ia:Si / Pa:Si / high work function TCO-1 / ia:Si on the back side of the silicon wafer, please refer to [link / reference needed]. Figure 3 The process flow shown yields the following results: Figure 4 The silicon wafer shown is manufactured using the following process:

[0084] A planar PECVD method is used to first deposit a layer of ia:Si on the back side of a double-sided alkaline polished silicon wafer from top to bottom. Then, HPT (H ion cleaning) is performed on the deposited surface. Next, a planar PECVD method is used to deposit Pa:Si on the back side of the silicon wafer from top to bottom. The deposition includes one layer of Pa:Si and one layer of P-uc-SiO. x C y Then, a TCO layer is deposited on the back of the silicon wafer from top to bottom using a planar PVD method, and finally, a ia:Si layer is deposited on the back of the silicon wafer using a planar PECVD method.

[0085] After double-sided alkaline polishing, the silicon wafer is placed on a cutout carrier plate. Valve 1 is opened, and the wafer is transferred into loading chamber 1 for evacuation. Valve 2 is opened, and the wafer is transferred into buffer preheating chamber 1. Then, it is transferred to PECVD 1 reaction chamber 1 for deposition of ia:Si from top to bottom. Finally, it is transferred to buffer HPT cleaning chamber 2 for H ion cleaning of the deposited surface, thus completing the preparation of ia:Si.

[0086] Open valve 3 and the carrier plate is transferred into transition chamber 1 (air-evacuated and isolated). Open valve 4 and transfer the plate to buffer 3 first, then to PECVD2 reaction chamber 2 to deposit a layer of Pa:Si and a layer of P-uc-SiOxCy from top to bottom. Then transfer the plate to buffer 4 to complete the Pa:Si preparation.

[0087] Open valve 5, the carrier plate is first transferred to transition chamber 2 (air-evacuated gas isolation), open valve 6, then transferred to buffer 5 (secondary isolation), then transferred to PVD1 reaction chamber 3 to deposit a layer of TCO from top to bottom, and then transferred to buffer 6 to complete the TCO preparation;

[0088] Open valve 7, the carrier plate is first transferred to transition chamber 3, open valve 8, then transferred to buffer chamber 7, then transferred to PECVD3 reaction chamber 4, a layer of ia:Si mask is deposited from top to bottom, and finally transferred to buffer chamber 8 to complete the preparation of ia:Si mask;

[0089] Open valve 9, the carrier plate is transferred to unloading chamber 1, nitrogen is used to backfill the atmosphere, open valve 10, and the carrier plate is transferred out of the chamber.

[0090] PECVD1 Reaction Chamber 1: PECVD method for preparing ia:Si, using SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0091] PECVD 2 Reaction Chamber 2: PECVD method for preparing Pa:Si, Pa:Si is divided into two layers: conventional boron-doped amorphous silicon (Pa:Si) and boron-doped microcrystalline silicon carbide (P-uc-SiO2). x C y );

[0092] Conventional preparation of boron-doped amorphous silicon (Pa:Si) using SiH4, H2, and B2H6 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2:B2H6 (2%) flow ratio: 1:20:5-1:30:15, power: 50W-300W;

[0093] B-doped microcrystalline silicon carbide (P-uc-SiOxCy) was prepared using SiH4, H2, B2H6, CO2, and TMB as process gases. The process temperature was 100℃-250℃, the process pressure was 50Pa-100Pa, the SiH4:H2:B2H6 (2%) flow ratio was 1:30:10-1:60:30, the flow rates of CO2 and TMB as micro-doped gases were 5sccm-20sccm, and the power was 300W-500W.

[0094] HPT Cleaning Buffer Chamber 2: H₂ is used to ionize hydrogen gas via PECVD to clean the deposited surface of the silicon wafer, with H₂ as the process gas.

[0095] Process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W;

[0096] PVD1 Reaction Chamber 3: When preparing P-zone TCO-1 using the PVD method, a high work function ITO target (In2O3 / SnO2 mass ratio: 90:10-95:5) is used, and argon and oxygen are used as working gases. The process temperature is 100-250℃, the process pressure is 0.2Pa-2Pa, the Ar / O2 flow ratio is 200:1-100:1, and the power is 5000W-40000W.

[0097] PECVD3 reaction chamber 4: PECVD method to prepare ia:Si mask, using SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0098] i: a-Si thickness: 2nm-10nm, freely adjustable;

[0099] P: a-Si thickness: 10nm-20nm, P-uc-SiO x C y Thickness: 20nm-50nm, thickness can be freely adjusted;

[0100] P: a-Si doping concentration: 1E+18cm -3 ~5E+18cm -3 P-uc-SiO x C y Doping concentration: 5E+18cm -3 ~2E+19cm -3 The doping amount can be freely adjusted;

[0101] i: a-Si mask thickness: 20nm-40nm, freely adjustable;

[0102] P-region TCO thickness: 70nm-150nm;

[0103] P-zone TCO sheet resistance: 50-120;

[0104] P-zone TCO-1 uses ITO target material ratio: high work function ITO target (In2O3 / SnO2 mass ratio: 90:10-95:5).

[0105] Specifically, a vacuum blocking technology of "transition-isolation-coating-isolation" is adopted to meet the process pressure of different film layer preparation, while avoiding process abnormalities caused by "cross-gas" between different film layer preparation process gases. A single machine can meet the preparation of different film layers, combining i:a-Si deposition & P:a-Si deposition & HPT cleaning & TCO deposition & i:a-Si mask deposition into one.

[0106] Specifically, the function of the transition chamber is to adjust the pressure to meet the switching requirements of different process pressure conditions / to block the gas medium in different process chambers.

[0107] Specifically, the buffer chamber serves as a secondary isolation and barrier between different gaseous media.

[0108] Step S3: A patterned mask is prepared by laser oxidation of the P-region on the back side, resulting in the following... Figure 5 The silicon wafer shown is manufactured using the following process:

[0109] A patterned silicon oxide mask is formed on the surface of the i:a-Si mask in the P region on the back of a silicon wafer using laser-induced oxidation technology. The battery is placed on a horizontal platform, the camera is positioned on the silicon wafer, and an ultraviolet picosecond laser is used to locally oxidize amorphous silicon to prepare the patterned silicon oxide mask.

[0110] Laser power: 10W-30W;

[0111] Silicon oxide mask: thickness: 5nm-15nm, oxide region width: 150um-500um, freely adjustable.

[0112] Step S4, wet cleaning, to remove i: a-Si mask / TCO-1 / P: a-Si / P-uc-SiO2 from the areas without SiO2 mask. x C y / i: a-Si and etching of silicon substrate to a certain depth, while simultaneously deep cleaning the silicon wafer, please refer to [link / reference]. Figure 6 The process flow shown yields the following results: Figure 7 The silicon wafer shown is manufactured using the following process:

[0113] The process involves cleaning with a potassium hydroxide (1%-10%) solution, etching the back side of the SiO2-free mask area (i:a-Si mask) with potassium hydroxide, at a process temperature of 55℃-70℃ and a process time of 0.5min-1.5min.

[0114] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0115] The silicon wafer surface is cleaned with hydrochloric acid (1%-10%) solution to remove alkaline residue and TCO-1 in the unmasked area; process temperature: room temperature, process time: 3min-5min;

[0116] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0117] A mixed solution of H2O:HCl:H2O2-4:1:1-6:1:1 is used to deeply clean the surface of silicon wafers and remove residual metal ions generated by the dissolution of TCO-1; process temperature: 60℃-85℃, cleaning time: 5min-10min;

[0118] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0119] Cleaning was performed using a mixed solution of potassium hydroxide (1%-10%) and alkaline polishing additive (0.5%-5%). Potassium hydroxide was used to etch the unmasked area on the back side: i:a-Si / P:a-Si / P-uc-SiO x C y The process involves etching to a certain depth, with a process temperature of 55℃-70℃ and a process time of 0.5min-1.5min.

[0120] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0121] The silicon wafer surface is cleaned with a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to remove additive residues. Process temperature: 55℃-70℃, process time: 2min-5min.

[0122] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0123] The silicon wafer surface is cleaned with hydrofluoric acid (1%-10%) solution to remove alkali residue and silicon oxide mask; process temperature: room temperature, process time: 3 min-5 min;

[0124] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0125] Slow lifting is used to remove dirt from the surface of the silicon wafer, allowing the silicon wafer to dehydrate. The cleaning time is 0.5 min to 1 min, and the cleaning temperature is 20℃ to 70℃.

[0126] Place the silicon wafer in a drying tank and blow it at high temperature to dry the surface of the silicon wafer. The blowing gas is nitrogen or compressed air, the temperature is 80℃-100℃, and the drying time is 5min-15min.

[0127] Cleaning method: The silicon wafer is vertically inserted into the solution, and the direction of the laser line on the silicon wafer is perpendicular to the solution surface. The removal of chemical residues on the silicon wafer surface is not affected by the morphology of the trench on the back side.

[0128] Cleaning method: The silicon wafer is vertically inserted into the solution, and the direction of the laser line on the silicon wafer is perpendicular to the solution surface. The removal of chemical residues on the silicon wafer surface is not affected by the morphology of the trench on the back side.

[0129] By utilizing the selective corrosion of TCO by HCl and HF, and the fact that TCO is soluble in HCl but insoluble in HF, an interdigitated structure of P-region amorphous + high-function TCO-1 / N-region amorphous + low-function TCO-2 was prepared.

[0130] Reflectivity of corroded areas: 35%-45%;

[0131] Size of the corroded tower base: 8um-15um;

[0132] Corrosion depth in the corroded area: 0.5um-2um.

[0133] Step S5, deposition of the mask ia:Si / Na:Si / N-uc-Si / low work function TCO-2 / ia:Si on the back side of the silicon wafer, please refer to [link / reference]. Figure 8 The process flow shown yields the following results: Figure 9 The silicon wafer shown is manufactured using the following process:

[0134] The process involves first depositing a layer of ia:Si on the back side of the cleaned silicon wafer from top to bottom using a planar PECVD method, followed by HPT (H ion cleaning) on ​​the deposited surface. Then, a layer of Na:Si (including one layer of Na:Si and one layer of N-uc-Si) is deposited on the back side of the silicon wafer from top to bottom using a planar PECVD method. Next, a layer of TCO is deposited on the back side of the silicon wafer from top to bottom using a planar PVD method. Finally, a layer of ia:Si is deposited on the back side of the silicon wafer using a planar PECVD method.

[0135] After double-sided alkaline polishing, the silicon wafer is placed on a cutout carrier plate. The gate valve 11 is opened, and the wafer is transferred into the loading chamber 2 for evacuation. The gate valve 12 is opened, and the wafer is transferred into the buffer preheating chamber 9. Then, it is transferred to the PECVD4 reaction chamber 5 to deposit ia:Si from top to bottom. Finally, it is transferred to the buffer HPT cleaning chamber 10 to clean the deposited surface with H ions, thus completing the ia:Si preparation.

[0136] Open valve 13 and the carrier plate is transferred into transition chamber 4 (air-evacuated gas isolation). Open valve 14 and transfer it first to buffer 11, then to PECVD 5 reaction chamber 6 to deposit a layer of Na:Si and a layer of N-uc-Si from top to bottom. Then transfer it to buffer 12 to complete the preparation of Pa:Si.

[0137] Open valve 15, the carrier plate is first transferred to transition chamber 5 (air-evacuated gas isolation), open valve 16, then transferred to buffer 13 (secondary isolation), then transferred to PVD2 reaction chamber 7 to deposit a layer of TCO from top to bottom, then transferred to buffer 14 to complete TCO preparation;

[0138] Open valve 17, the carrier plate is first transferred to transition chamber 6, open valve 18, then transferred to buffer chamber 15, then transferred to PECVD6 reaction chamber 8, a layer of ia:Si mask is deposited from top to bottom, and finally transferred to buffer chamber 16 to complete the preparation of ia:Si mask;

[0139] Open valve 19, the carrier plate is transferred to unloading chamber 2, nitrogen is used to backfill the atmosphere, open valve 20, and the carrier plate is transferred out of the chamber.

[0140] PECVD4 Reaction Chamber 5: PECVD method to prepare ia:Si, using SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0141] PECVD5 reaction chamber 6: PECVD method to prepare Na:Si, Na:Si is divided into two layers: conventional P-doped amorphous silicon (Na:Si) and P-doped microcrystalline silicon (N-uc-Si);

[0142] Conventional preparation of P-doped amorphous silicon (Na:Si) using SiH4, H2, and PH3 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2:PH3 (2%) flow ratio: 1:20:5-1:30:15, power: 50W-300W;

[0143] P-doped microcrystalline silicon (N-uc-Si) was prepared using SiH4, H2, and PH3 as process gases. The process temperature was 100℃-250℃, the process pressure was 50Pa-100Pa, the SiH4:H2:PH3 (2%) flow ratio was 1:30:10-1:60:30, and the power was 300W-500W.

[0144] HPT Cleaning Buffer Chamber 10: H₂ is used to ionize hydrogen gas via PECVD to clean the deposited surface of the silicon wafer, with H₂ as the process gas.

[0145] Process temperature: 100℃-250℃, process pressure: 50Pa-100Pa, power: 50W-400W;

[0146] PVD1 Reaction Chamber 3: When preparing N-zone TCO-2 using the PVD method, a low work function ITO target (In2O3 / SnO2 mass ratio: 97:3) is used, and argon and oxygen are used as working gases. The process temperature is 100-250℃, the process pressure is 0.2Pa-2Pa, the Ar / O2 flow ratio is 200:1-100:1, and the power is 5000W-40000W.

[0147] PECVD6 reaction chamber 8: PECVD method for preparing ia:Si mask, using SiH4 and H2 as process gases, process temperature: 100℃-250℃, process pressure: 10Pa-50Pa, SiH4:H2 flow ratio: 1:10-1:30, power: 50W-300W;

[0148] i: a-Si thickness: 2nm-10nm, freely adjustable;

[0149] N: a-Si thickness: 10nm-20nm, N-uc-Si thickness: 20nm-50nm, thickness can be freely adjusted;

[0150] N: a-Si doping concentration: 1E+18cm -3 ~5E+18cm -3 N-uc-Si doping concentration: 5E+18cm -3 ~2E+19cm -3 The doping amount can be freely adjusted;

[0151] i: a-Si mask thickness: 20nm-40nm, freely adjustable;

[0152] P-region TCO thickness: 70nm-150nm;

[0153] P-zone TCO sheet resistance: 50-120;

[0154] P-zone TCO-2 uses ITO target material ratio: low work function ITO target (In2O3 / SnO2 mass ratio: 97:3).

[0155] Step S6: A patterned mask is prepared by laser oxidation of the N-region on the back side, resulting in the following... Figure 10 The silicon wafer shown is manufactured using the following process:

[0156] A patterned silicon oxide mask is formed on the surface of the i:a-Si mask in the N region on the back of a silicon wafer using laser-induced oxidation technology. The battery is placed on a horizontal platform, the camera is positioned on the silicon wafer, and an ultraviolet picosecond laser is used to locally oxidize amorphous silicon to prepare the patterned silicon oxide mask.

[0157] Laser power: 10W-30W;

[0158] Silicon oxide mask: thickness: 5nm-15nm, oxide region width: 150um-500um, freely adjustable.

[0159] Step S7: Removal of the back-side SiO2 mask region i: a-Si mask / low work function TCO-2, removal of the back-side SiO2 mask, texturing of the front side, removal of the back-side i: a-Si mask, fabrication of a P-region amorphous + high work function TCO-1 / N-region amorphous + low work function TCO-2 isolated interdigitated structure. Please refer to [link to relevant documentation]. Figure 11 The process flow shown yields the following results: Figure 12 The silicon wafer shown is manufactured using the following process:

[0160] The process involves cleaning with a potassium hydroxide (1%-10%) solution, etching the back side of the SiO2-free mask area (i:a-Si mask) with potassium hydroxide, at a process temperature of 55℃-70℃ and a process time of 0.5min-1.5min.

[0161] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0162] The silicon wafer surface is cleaned with hydrochloric acid (1%-10%) solution to remove alkaline residue and TCO-2 in the unmasked area; process temperature: room temperature, process time: 3min-5min;

[0163] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0164] A mixed solution of H2O:HCl:H2O2-4:1:1-6:1:1 is used to deeply clean the surface of silicon wafers and remove residual metal ions generated by the dissolution of TCO-12; process temperature: 60℃-85℃, cleaning time: 5min-10min;

[0165] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0166] The silicon wafer surface is cleaned with hydrofluoric acid (1%-10%) solution to remove the silicon oxide mask; process temperature: room temperature; process time: 3-5 minutes.

[0167] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0168] A mixed solution of potassium hydroxide (1%-10%) and texturing additive (0.5%-5%) is used for cleaning to form a pyramidal textured surface on the front side of the silicon wafer. At the same time, the i:a-Si mask on the back side is removed, and an interdigitated structure of P-region amorphous + high work function TCO-1 / N-region amorphous + low work function TCO-2 is formed. Process temperature: 55℃-70℃, process time: 0.5min-1.5min.

[0169] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0170] The silicon wafer surface is cleaned with a mixed solution of potassium hydroxide (1%-10%) and hydrogen peroxide (5%-20%) to remove additive residues. Process temperature: 55℃-70℃, process time: 2min-5min.

[0171] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0172] The silicon wafer surface is cleaned with a hydrofluoric acid (1%-10%) solution to remove alkaline residue; process temperature: room temperature; process time: 3-5 minutes.

[0173] Use water to remove surface drug residues and dirt; cleaning time: 2-3 minutes.

[0174] Slow lifting is used to remove dirt from the surface of the silicon wafer, allowing the silicon wafer to dehydrate. The cleaning time is 0.5 min to 1 min, and the cleaning temperature is 20℃ to 70℃.

[0175] Place the silicon wafer in a drying tank and blow it at high temperature to dry the surface of the silicon wafer. The blowing gas is nitrogen or compressed air, the temperature is 80℃-100℃, and the drying time is 5min-15min.

[0176] Cleaning method: The silicon wafer is vertically inserted into the solution, and the direction of the laser line on the silicon wafer is perpendicular to the solution surface. The removal of chemical residues on the silicon wafer surface is not affected by the morphology of the trench on the back side.

[0177] Cleaning method: The silicon wafer is vertically inserted into the solution, and the direction of the laser line on the silicon wafer is perpendicular to the solution surface. The removal of chemical residues on the silicon wafer surface is not affected by the morphology of the trench on the back side.

[0178] By utilizing the selective corrosion of TCO by HCl and HF, and the fact that TCO dissolves in HCl but is insoluble in HF, an isolated interdigitated structure of P-region amorphous + high work function TCO-1 / N-region amorphous + low work function TCO-2 was prepared.

[0179] Step S8: Alumina-silicon nitride passivation antireflection films are fabricated on the front and back sides of the silicon wafer. The interdigitated isolation regions of the P-region amorphous + high work function TCO-1 and N-region amorphous + low work function TCO-2 structures are filled with alumina-silicon nitride insulating material. Please refer to [link to relevant documentation]. Figure 13 The process flow shown yields the following results: Figure 14 The silicon wafer shown is manufactured using the following process:

[0180] First, an aluminum oxide layer is deposited on the front side of the silicon wafer using a planar or tubular ALD or a planar PECVD method. Then, a silicon nitride stacked gradient film is deposited on the front and back sides of the silicon wafer using a planar PECVD method. The interdigitated isolation region of the P-region amorphous + high work function TCO-1 / N-region amorphous + low work function TCO-2 structure is filled with aluminum oxide silicon nitride insulating material.

[0181] After cleaning, the silicon wafer is placed face up on the cutout carrier plate. The gate valve 21 is opened, and the carrier plate is transferred to the preheating loading chamber 3 for preheating. The gate valve 22 is opened, and the carrier plate is transferred to the PECVD7 reaction chamber 9. A layer of alumina is deposited from top to bottom on the front side and from top to bottom on the back side using the PECVD method to complete the alumina preparation.

[0182] Open valve 23, the carrier plate is first transferred to transition chamber 7, evacuated (air evacuation for air isolation), open valve 24, then transferred to buffer chamber 18, then transferred to PECVD 8 reaction chamber 10, the front side is deposited from top to bottom, the back side is deposited from bottom to top, a layer of high H content SiNx, a layer of high Si content SiNx, a layer of high N content SiNx, then transferred to buffer chamber 11, completing the preparation of double-sided stacked gradient silicon nitride antireflection passivation film;

[0183] Open valve 25, the carrier plate is transferred to unloading chamber 3, nitrogen is used to backfill the atmosphere, open valve 26, the carrier plate is transferred out of the chamber;

[0184] PECVD7 Reaction Chamber 9: Alumina is prepared by PECVD, using trimethylaluminum and nitrous oxide as working gases. Process temperature: 150℃-250℃, process pressure: 20Pa-50Pa, trimethylaluminum / nitrous oxide flow ratio: 1:1-3:1, power: 100W-500W.

[0185] PECVD8 Reaction Chamber 10: A SiNx stacked gradient passivation antireflection film was prepared by PECVD, consisting of three layers;

[0186] SiNx-1: High-H content silicon nitride is prepared using SiH4, H2, and NH3 as process gases under high pressure and high power with a high H2 ratio, and the silicon wafer interface is passivated. Process temperature: 100℃-250℃, process pressure: 80Pa-120Pa, SiH4 / NH3 / H2 flow ratio: 1:1:6-2:2:20; power: 200W-300W.

[0187] SiNx-2: Using SiH4 and NH3 as process gases, high-Si content and high-density silicon nitride are prepared by low pressure and low power with a high SiH4 ratio, protecting high-H content silicon nitride. At the same time, low-power coating reduces passivation damage to SiNx-1. Process temperature: 100℃-250℃, process pressure: 30Pa-50Pa, SiH4 / NH3 flow ratio: 2:1-6:1.

[0188] SiNx-3: Using SiH4 and NH3 as process gases, high N content silicon nitride is prepared under low pressure and low power with a high NH3 ratio, which reduces the overall film refractive index, reduces the front reflectivity of the battery, and increases the current density. Process temperature: 100℃-250℃, process pressure: 30Pa-50Pa, SiH4 / NH3 flow ratio: 1:2-1:6.

[0189] Alumina thickness: 2nm-20nm;

[0190] Silicon nitride thickness: 10nm-40nm.

[0191] Step S9: Laser film opening, locally opening the N-region and P-region alumina and silicon nitride to expose TCO, resulting in... Figure 15 The silicon wafer shown is manufactured using the following process:

[0192] Using laser ablation technology, the N- and P-region alumina and silicon nitride are partially opened to expose the TCO. The battery is placed on a horizontal platform, the camera positions the silicon wafer, and a UV picosecond laser is used to locally pattern the alumina and silicon nitride.

[0193] Laser power: 10W-30W;

[0194] Film opening width: 10um-50um.

[0195] Step S10: Screen printing, curing, and light injection are performed to obtain the desired result. Figure 16 The silicon wafer shown is manufactured using the following process:

[0196] Metal paste is printed in the windowed areas of the N and P zones on the back side;

[0197] After printing, the silicon wafer is transferred to a curing oven, dried and cured, forming an ohmic contact with the TCO.

[0198] The battery is transferred to the annealing furnace, where annealing light is injected to excite hydrogen and improve passivation.

[0199] The HBC battery fabrication was completed.

[0200] In summary, the proposed HBC solar cell structure and its amorphous damage-free fabrication method employ a TCO layer + i:a-Si mask layer + laser oxidation and selective etching cleaning process. This process protects the amorphous TCO layers in the N and P regions from direct laser contact and acid / alkali contact, ensuring no damage to the amorphous silicon and significantly improving the upper limit of cell efficiency. Furthermore, the interdigitated arrangement of the high work function amorphous TCO layer in the P region and the low work function amorphous TCO layer in the N region on the back overcomes the traditional challenge of matching the work function of the amorphous TCO layers in the N and P regions on the back of HBC cells with the TCO layer, improving the cell's current and fill factor, and increasing the bifaciality.

[0201] Based on the above-described preferred embodiments of the present invention, and through the foregoing description, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A non-amorphous damage-free preparation method of HBC solar cell, characterized in that, The method comprises the following steps: S1. polishing both sides of the silicon wafer to prepare a clean silicon wafer surface with a lubricating alkali polishing tower base topography; S2. depositing an i:a-Si layer on the back of the silicon wafer from top to bottom, performing HPT cleaning on the deposited surface, and then sequentially depositing a P:a-Si layer, a high work function TCO layer, and an i:a-Si mask layer from top to bottom; S3. laser oxidizing the P region of the back of the silicon wafer to form a patterned silicon oxide mask outside the outer i:a-Si mask layer; S4. wet cleaning the back of the silicon wafer to remove the patterned silicon oxide mask and the deposited layer in the unmasked area, and etching the silicon base and cleaning the silicon wafer; S5. depositing an i:a-Si layer on the back of the silicon wafer from top to bottom, performing HPT cleaning on the deposited surface, and then sequentially depositing an N:a-Si layer, a low work function TCO layer, and an i:a-Si mask layer from top to bottom; S6. laser oxidizing the N region of the back of the silicon wafer to form a patterned silicon oxide mask outside the outer i:a-Si mask layer; S7. cleaning the back of the silicon wafer to expose the TCO layers of the N and P regions and prepare an isolated interdigital arrangement structure of the amorphous high work function TCO layer in the P region and the amorphous low work function TCO layer in the N region, and texturing the front of the silicon wafer; S8. sequentially preparing an aluminum oxide layer and a silicon nitride layer on the front and back of the silicon wafer, and filling the isolation region of the isolated interdigital arrangement structure; S9. laser opening the mask on the back of the silicon wafer to partially window to expose the high work function TCO layer and the low work function TCO layer; S10. printing metal paste on the windowed area of the back of the silicon wafer and solidifying light injection to complete the preparation of the cell.

2. The preparation method of claim 1, wherein the reflectivity of the polished silicon wafer surface in step S1 is 30-45%; and the size of the tower base is 5-15 μm.

3. The preparation method of claim 1, wherein in step S2, the thickness of the i:a-Si layer is 2-10 nm; the high work function TCO layer has a thickness of 70-150 nm and a square resistance of 50-120; the target material of the high work function TCO layer comprises In2O3 and SnO2 in a mass ratio of (90-95):(5-10); and the thickness of the i:a-Si mask layer is 20-40 nm.

4. The preparation method of claim 1, wherein in steps S3 and S6, the thickness of the patterned silicon oxide mask is 5-15 nm, and the width of the oxidized region is 150-500 μm.

5. The preparation method of claim 1, wherein in step S4, the reflectivity of the etched region is 35-45%; the size of the tower base of the etched region is 8-15 μm; and the etching depth of the etched region is 0.5-2 μm.

6. The preparation method of claim 1, wherein in step S5, the thickness of the i:a-Si layer is 2-10 nm; the N:a-Si layer comprises an N:a-Si sublayer and an N-uc-Si sublayer; and the thickness of the i:a-Si mask layer is 20-40 nm. ​ The P:a-Si layer includes a P:a-Si sublayer and a P-uc-SiO x C y sublayer; ​ The thickness of the P: a-Si layer is 10-20 nm and the doping concentration is 1E+18 cm -3 ~5E+18 cm -3 : The P-uc-SiO x C y The thickness of the layer is 20-50 nm and the doping concentration is 5E+18 cm -3 ~ 2E+19 cm -3 ; ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The thickness of the N: a-Si layer is 10-20 nm and the doping concentration is 1E+18 cm -3 ~5E+18 cm -3 : The N-uc-Si layer has a thickness of 20-50 nm and a doping concentration of 5E+18 cm -3 ~2E+19 cm -3 ; The thickness of the low work function TCO layer is 70-150 nm, and the square resistance is 50-120; The target material of the low work function TCO layer comprises In2O3 and SnO2 in a mass ratio of (95-98):(2-5); The thickness of the i:a-Si mask layer is 20-40 nm.

7. The preparation method of claim 1, wherein, In the step S8 The thickness of the aluminum oxide layer is 2-20 nm, and the thickness of the silicon nitride layer is 10-40 nm.

8. The preparation method of claim 1, wherein, In the step S9 The width of the opened film is 10-50 μm.

9. An HBC solar cell structure prepared by the method of any one of claims 1-8, wherein, The back surface of the cell comprises an isolated interdigital arrangement structure of a P region amorphous high work function TCO layer and an N region amorphous low work function TCO layer, and The isolated regions of the P region and the N region are filled with an aluminum oxide layer and a silicon nitride layer.

10. A photovoltaic module, characterized by, The HBC solar cell structure of claim 9 is adopted.

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