Host endpoint adaptive compute combinability

Abstract

Embodiments herein describe a processor system including an integrated adaptive accelerator. In one embodiment, the processor system includes a plurality of core complex chiplets, each including one or more processing cores for a host CPU. Further, the processor system includes an accelerator chiplet. The processor system may assign one or more of the core complex chiplets to the accelerator chiplet to form an IO device, while the remaining core complex chiplets form the CPU for the host. In this manner, the accelerator may be integrated into the processor system of the host rather than the accelerator and the CPU have separate computer resources, so hardware resources may be partitioned between the CPU and the accelerator depending on the need of a particular application executed by the host.

Description

Technical Field

[0001] Examples of the present disclosure are generally directed to a processor system that includes processing chiplets that can be assigned to a central processing unit (CPU) of a host or to an accelerator chiplet to form an integrated IO device. Background Art

[0002] Current acceleration devices such as data processing units (DPUs) (e.g., input / output (IO) devices) include different components such as I / O gateways, processor subsystems, networks on chip (NoCs), storage and data accelerators, data processing engines, and programmable logic (PL). Currently, DPUs use PCIe connections to connect to the host's processor complex. The host processing power and the embedded processing power of the DPU are independently specified. For some workloads, the DPU may have more computational processing than required to perform its tasks, thereby wasting power and space in the computing system. For other workloads, the DPU may not have enough computational processing power to perform its tasks, thereby becoming a bottleneck. Summary of the invention

[0003] One embodiment describes a computing system that includes a processor system in a host, the processor system including a substrate, a plurality of core complex chiplets, an accelerator chiplet, and a composable agent, the plurality of core complex chiplets each including at least one processor core, the composable agent being configured to assign at least one of the plurality of core complex chiplets to the accelerator chiplet to form an IO device, while the remaining plurality of core complex chiplets form a central processing unit (CPU) for the host.

[0004] Another embodiment described herein is a processor system including a plurality of core complex chiplets, each including at least one processor core, an accelerator chiplet, and an interconnect that connects the plurality of core complex chiplets to each other and to the accelerator chiplet. The interconnect includes a composable agent configured to assign at least one of the plurality of core complex chiplets to the accelerator chiplet to form an IO device, while the remaining plurality of core complex chiplets form a central processing unit (CPU) for a host.

[0005] Another embodiment described herein is a method comprising: selecting at least one core complex chiplet among a plurality of core complex chiplets to be assigned to an IO device while assigning the remaining core complex chiplets among the plurality of core complex chiplets to a CPU of a host, removing the selected core complex chiplet as a peer of the remaining core complex chiplets among the plurality of core complex chiplets; and adding the selected core complex chiplet to the IO device, wherein the plurality of core complex chiplets are disposed on the same substrate as an accelerator chiplet also assigned to the IO device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] In order to be able to understand in detail the manner in which the above features are described, a more specific description briefly summarized above may be obtained by reference to example implementations, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical example implementations and therefore should not be considered to limit the scope thereof.

[0007] Figure 1 A processor system including an integrated adaptable accelerator according to one embodiment is illustrated.

[0008] Figure 2 is a flow chart for adding a processing core to an integrated accelerator, according to one embodiment.

[0009] Figure 3 is a block diagram of a processor system according to one embodiment.

[0010] Figure 4 A processor system including an integrated adaptable accelerator according to one embodiment is illustrated.

[0011] Figure 5 A processor system including an integrated adaptable accelerator according to one embodiment is illustrated.

[0012] Figure 6 A processor system including a plurality of integrated adaptable accelerators according to one embodiment is illustrated.

[0013] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements of one example may be beneficially incorporated in other examples. DETAILED DESCRIPTION

[0014] Various features are described below with reference to the accompanying drawings. It should be noted that the drawings may or may not be drawn to scale, and elements of similar structure or function are represented by similar reference numerals in all drawings. It should be noted that the drawings are intended only to facilitate the description of the features. They are not intended to be an exhaustive description of the specification nor to limit the scope of the claims. In addition, the illustrated examples do not necessarily have all the aspects or advantages shown. The aspects or advantages described in conjunction with a particular example are not necessarily limited to that example, and may be practiced in any other example even if not so illustrated or so explicitly described.

[0015] The embodiments herein describe a processor system including an integrated adaptive accelerator. In one embodiment, the processor system includes a plurality of core complex chiplets, each of which contains one or more processing cores for a host CPU. In addition, the processor system includes an accelerator chiplet (e.g., a smart network card, a database accelerator, an artificial intelligence (AI) accelerator, a graphics processor unit (GPU), etc.). The processor system can assign one or more of these core complex chiplets to the accelerator chiplet to form an IO device, while the remaining core complex chiplets form a CPU for the host. For example, the number of core complex chiplets assigned to the accelerator can be determined in response to whether the application executed by the host will require more computer resources from the CPU or from the accelerator. For accelerator-intensive applications, more core complex chiplets can be assigned to accelerators and IO devices, while for CPU-intensive applications, fewer (or no) core complex chiplets are assigned to accelerators.

[0016] In this way, the accelerator can be integrated into the host's processor system, rather than the accelerator and CPU having independent computing resources, so that hardware resources can be divided between the CPU and the accelerator depending on the needs of the specific application executed by the host.

[0017] Figure 1 A processor system 100 including an integrated adaptive accelerator according to one embodiment is illustrated. In this example, the processor system 100 includes a substrate 105 on which a plurality of core complex chiplets 110, interconnects 120, and accelerator chiplets 115 are disposed. In one embodiment, the core complex chiplets 110, the interconnects 120, and the accelerator chiplets 115 are separate integrated circuits (ICs). Each of the core complex chiplets 110 and the accelerator chiplets 115 can be connected to the interconnects 120 using traces in the substrate 105. That is, the interconnects 120 enable the core complex chiplets 110 to communicate with each other and allow the chiplets 110 to communicate with the accelerator chiplets 115. However, in other embodiments, the core complex chiplets 110 can also be directly connected to each other.

[0018] The interconnect 120 allows the core complex chiplet 110 to be assigned to other chiplets in the chiplet 110 to form a CPU 140 for a host, or to be assigned to an accelerator chiplet 115 to form an IO device 130. That is, each core complex chiplet 110 can be assigned as a peer of the other chiplets 110 to form a CPU 140, or can be separated from the other chiplets 110 to be assigned to an IO device 130. When a core complex chiplet 110 is assigned to an IO device 130, the coherent connections between the core complex chiplet and the other chiplets 110 are separated and therefore no longer considered peers. Instead, the core complex chiplet 110 may no longer share the same memory space or run the same operating system as the other chiplets 110 in the CPU 140, but instead rely on different interrupt semantics. This is in Figure 3 Discussed in more detail in .

[0019] In one embodiment, the core complex chiplet 110 is a duplicate IC, e.g., having the same number of processing cores and other hardware circuits. However, the accelerator chiplet 115 may be different from the core complex chiplet 110. For example, the accelerator chiplet 115 may include dedicated circuits for performing accelerator tasks, such as a network interface (in the case where the accelerator chiplet 115 is a DPU or database accelerator), a dedicated data processing engine (e.g., for performing network or AI tasks), programmable logic for additional user configurability, a host interface for managing memory requests and interrupts with the interconnect 120, etc. In one embodiment, the accelerator chiplet 115 does not include an embedded processor (e.g., a processor core). That is, in systems where the accelerator chiplet 115 and the IO device 130 are not integrated into the host's processor system 100, these accelerators may include their own processor cores (e.g., general processing units) as well as dedicated accelerator engines. However, because the processing system 100 can assign one or more of the core complex chiplets 110 to the accelerator chiplet 115, the accelerator chiplet 115 no longer requires its own processor system, thereby saving space and power in the processor system 100. In other embodiments, however, it may be advantageous to still include a processor core in the accelerator chiplet 115.

[0020] The interconnect 120 includes a composable agent 125 that assigns the core complex chiplets 110 to the accelerator chiplets 115. In this embodiment, the agent 125 has assigned the core complex chiplets 110A and 110C to the accelerator chiplets 115 to form the IO device 130. Conversely, the composable agent 125 has assigned the core complex chiplets 110B and 110D-G to form the CPU 140. In one embodiment, the composable agent 125 makes this assignment when the computing system is booting.

[0021] In one embodiment, this assignment can change. For example, if the workload changes and the IO device 130 no longer requires as many computing resources to perform its acceleration tasks, the composable agent 125 can remove the core compute chiplet 110C from the IO device 130 and reassign the core compute chiplet to the CPU 140. In this way, each core complex chiplet in the core complex chiplet 110 can be assigned to an integrated IO device 130 or a CPU 140.

[0022] Furthermore, it is not necessary to have a separate interconnect 120 IC as shown. In other embodiments, the functions performed by the interconnect 120 can be performed using hardware on the core complex chiplet 110 and the accelerator chiplet 115. The substrate 105 can include an interconnect network for selectively connecting the core complex chiplet 110 and the accelerator chiplet 115. For example, portions of the interconnect 120 can also be distributed on each core complex chiplet 110, with the substrate connection 105 implementing a multi-core complex connection to create a CPU 140.

[0023] In another embodiment, the accelerator chiplet 115 or the circuitry in the chiplet is part of the interconnect 120. That is, the accelerator chiplet 115 can be integrated into the same IC as the interconnect 120, rather than as a separate IC. Figure 1 In other words, the interconnect 120 (which may include Figure 1 The composable agent 125 and other circuits shown) can be part of the same IC as the accelerator chiplet 115.

[0024] Figure 2200 is a flow chart of a method 200 for adding a processing core to an integrated accelerator according to one embodiment. At box 205, the workload of the CPU and the accelerator is determined. The determination can be performed by a user application executing on a host, a system administrator, or a processor system. For example, the composable agent can rely on historical data to determine the workload of the CPU and the accelerator. Or the composable agent can determine what type of user applications are or will be executed on the host, which can then be used to estimate the workload of the CPU and the accelerator when these applications are executed. Alternatively, a silicon manufacturer can create different product sets, each of which has a different mix of processor cores as part of an I / O device 130, and a static configuration of the composable agent 125, each of which has different computing resources for the CPU 140 for different workloads.

[0025] For example, a control plane heavy workload (such as a non-aggregated storage workload) can use significantly more processing power when compared to a data plane heavy workload, where the accelerators perform most of the computations while the processor cores in the CPU are lightly loaded. By determining (or estimating) the workload on the CPU and accelerator, the composable agent can determine how much computing resources each will require.

[0026] At block 210, the composable agent selects at least one of the core complex chiplets to assign to the IO device. That is, the composable agent selects at least one core complex chiplet to add to the accelerator chiplet to form the IO device. The number of core complex chiplets assigned to the IO device may depend on the workload of the IO device. For heavier workloads, additional core complex chiplets may be assigned to the IO device. For lighter loads, fewer (or no) core complex chiplets are assigned to the IO device.

[0027] At box 215, the combinable agent removes the selected core complex chiplet as a peer of the remaining core complex chiplets. For example, the agent may deactivate the connection between the selected core complex chiplet and the chiplet used to form the CPU. These connections can be cache coherent connections and inter-processor interrupt connections between the selected core complex chiplets. In addition, the hardware in the selected core complex chiplet can be reconfigured so that it behaves as a processor core in an IO device rather than a peer processor in a CPU. For example, the selected core complex chiplet may issue a read and write memory request to an IO memory management unit (MMU) in the interconnect. In addition, even if the selected core complex chiplet is physically part of the host processing system, the selected core complex chiplet can also use a message signaled interrupt (MSI) to signal an interrupt to the host processing system (e.g., an interconnect). The MSI can be generated by the core complex, or the interconnect can translate the core complex interrupt into an MSI to the host processing system. However, MSI is only one example of a suitable IO interrupt protocol that can be used.

[0028] At block 220, the composable agent adds the selected core complex chiplet to the IO device. For example, the interconnect may establish a communication path between the selected core complex chiplet and the accelerator chiplet so that the core complex chiplet acts like a processor subsystem integrated into an accelerator. With the established communication path, the core complex chiplet may run an operating system independent of the operating system running on the CPU. The resources of the operating system may now include the accelerator chiplet, which uses the communication path established between the selected core complex chiplet and the accelerator chiplet.

[0029] At block 225, the method 400 determines whether the workload has changed. This may be the workload on the CPU or the workload on the IO device. For example, the workload on the CPU may have increased, causing the composable agent to determine to move a core complex chiplet previously assigned to the IO device to the CPU. Or the workload on the IO device may have increased, causing the composable agent to move a core complex chiplet previously assigned to the CPU to the IO device.

[0030] At block 230, the composable agent adjusts the number of core complex chiplets assigned to the IO device. This may include adding more core complex chiplets to the IO device, or removing core complex chiplets from the IO device. This adjustment of core complex chiplets may occur upon restarting the computing system, or it may be possible to adjust the number of core complex chiplets assigned to the IO device without having to restart the computing system.

[0031] Figure 3is a block diagram of a processor system 300 according to one embodiment. Like the processor system 100, the processor system 300 includes a core complex chiplet 110, an interconnect 120, and an accelerator chiplet 115. In this example, the core complex chiplet 110 has a coherent interconnect and an IO interconnect to the interconnect 120. In one embodiment, the coherent interconnect is used when the core complex chiplet 110 is part of a CPU, but the IO interconnect is used when the core complex chiplet 110 is part of an IO device.

[0032] The core complex chiplet 110 includes a processing core 305, coherent hardware 310, and IO hardware 315. The coherent hardware 310 includes circuits or firmware used when the core complex chiplet 110 is a peer in a CPU, while the IO hardware 315 includes circuits or firmware used when the core complex chiplet 110 is part of an IO device. For example, when acting as part of a CPU, the coherent hardware 310 may perform memory read and write requests as a cache coherent peer of the other core complex chiplets 110 forming the CPU. However, when acting as part of an IO domain, the IO hardware 315 submits requests to read and write data to the IO MMU 320 in the interconnect 120, similar to the accelerator chiplet 115 and other IO devices. In addition, the core complex chiplet 110 may receive page table translations from the IO MMU 320 and access the CPU memory when acting as part of an IO device, rather than maintaining page tables with the other core complex chiplets 110 forming the CPU. The composable agent 125 may assign at least one of the memory ports 330 as IO domain memory. When part of the IO domain, the core complex chiplet 110 may run an operating system independent of the operating system running on the CPU and maintain its own page table mapping to the IO domain memory. In addition, the IO hardware 315 may support IO device interrupt semantics (e.g., MSI) that are subordinate to the interrupts used by the coherent hardware 310. The interrupt semantics may send interrupts to the interrupt manager 325 in the interconnect 120, which handles interrupts received from chiplets in the IO devices.

[0033] The interconnect 120 includes a composable agent 125, an IO MMU 320, and an interrupt manager 325 and a memory port 330. As described above, the composable agent 125 selects and assigns a core complex chiplet 110 to a CPU or an IO device. In addition, the composable agent 125 can inform the IO MMU 320, the interrupt manager 325, and the memory port 330 which of the core complex chiplets 110 is part of the CPU and which is part of the IO device. These circuits can then use appropriate techniques to send data and handle interrupts.

[0034] In one embodiment, the interconnect 120 may include programmable logic to manage translation of the core complex chiplet 110 between the coherent interconnect and the IO interconnect (or path), translation between homogeneous core interrupts and IO device semantic interrupts (e.g., MSI), and translation between homogeneous core MMU and IO device semantic IO translation lookaside buffers (IOTLBs) performed by the IO MMU 320. For example, the programmable logic may implement a bridge between core interrupt semantics used when the core complex chiplet 110 is part of a CPU and IO message interrupt semantics used when the core complex chiplet 110 is part of an IO device. The programmable logic may also include a bridge for translating between core page table walks used when the core complex chiplet 110 is part of a CPU and IO PCIe address translation services (ATS) used, for example, when the core complex chiplet 110 is part of an IO device. The bridge may translate core page table accesses into PCIe ATS messages, and then the data structure received in the ATS response is modified to be presented as a native to core instruction set architecture (ISA) page table.

[0035] The accelerator chiplet 115 includes an acceleration circuit 335, a host interface 340, and a network interface 345. The acceleration circuit 335 may include an acceleration engine (e.g., a data processing engine, a cryptographic engine, a compression engine, an AI engine, etc.), programmable logic, or a combination thereof. The acceleration circuit 335 may be any circuit that performs an acceleration task assigned by a host (e.g., a CPU). For example, the core complex chiplet 110 forming the CPU (or software executed on the chiplet 110) may offload acceleration tasks to the accelerator chiplet 115 using the interconnect 120.

[0036] The host interface 340 enables the accelerator chiplet 115 to communicate with the interconnect 120 via the IO interconnect. The host interface 340 may use a PCIe or Universal Interconnect Express (UCIe) connection to communicate with the interconnect 120. The host interface 340 may use a cache coherent protocol to communicate with the interconnect 120 and the core complex chiplet 110 assigned to the CPU, such as a fast compute link (CXL). TM ) or accelerator cache coherent interconnect While these protocols enable the accelerators 120 and any core-complex chiplets 110 assigned to IO devices to be cache-coherent with the core-complex chiplets 110 that form the CPU, they remain subordinate to those core-complex chiplets 110 .

[0037] The network interface 345 enables the accelerator chiplet 115 to communicate with a network (e.g., a local area network (LAN) or a wide area network (WAN)). In this example, the accelerator chiplet 115 may be a DPU or a database accelerator. However, in embodiments where the accelerator is an AI or cryptographic accelerator that does not communicate with a network, the network interface 345 may be omitted.

[0038] Figure 4 A processor system including an integrated adaptable accelerator according to one embodiment is illustrated. For simplicity, Figure 4 The processor system in FIG. 1 illustrates only the core complex chiplet 110 and the accelerator chiplet 115 , but does not illustrate the interconnects that may also be present.

[0039] In this example, the processor system includes two accelerator chiplets 115A and 115B. In one embodiment, the accelerator chiplets 115 are the same type of accelerator (e.g., two DPU chiplets or two database accelerators). In one embodiment, the accelerator chiplets 115 can be the same integrated circuit. For example, the processor system can be designed to perform an application that requires a specific accelerator task to be performed by the accelerator chiplet 115. Therefore, the processor system can include two accelerator chiplets in the accelerator chiplet 115, rather than one accelerator chiplet. Figure 1 Only one accelerator chiplet is shown.

[0040] As described above, one or more of the core complex chiplets 110 may be assigned to the accelerator chiplet 115 to form the IO device 405. In this example, the core complex chiplet 110A is assigned to the accelerator chiplets 115A and 115B, and the core complex chiplets 110B-110D form the CPU 410 for the host. However, in other embodiments, more than one of the core complex chiplets 110 may be assigned to the IO device 405, or no core complex chiplet 110 may be assigned to the IO device 405, in which case the accelerator tasks are performed only by the accelerator chiplets 115A and 115B.

[0041] Figure 5 A processor system including an integrated adaptable accelerator according to one embodiment is illustrated. For simplicity, Figure 5 The processor system in FIG. 1 illustrates only the core complex chiplet 110 and the accelerator chiplet 115 , but does not illustrate the interconnects that may also be present.

[0042] Similar to Figure 4, here, the processor system includes two accelerator chiplets 115A and 115B. In one embodiment, the accelerator chiplets 115 are the same type of accelerators (e.g., two DPU chiplets or two database accelerators). In one embodiment, the accelerator chiplets 115 can be the same integrated circuit. However, Figure 4 different, Figure 5 It is illustrated that one of the accelerator chiplets can be assigned as part of the CPU 510. Thus, Figure 5 It is illustrated that in addition to assigning the core complex chiplet 110 to the IO device 505, the accelerator chiplet 115 may be assigned to the CPU 510. For example, the current workload of the IO device 505 may be much less than the workload on the CPU 510. Therefore, the composable agent may reassign the accelerator chiplet 115B to the CPU 510 while letting the accelerator chiplet 115A perform the function of the IO device 505.

[0043] The accelerator chiplet 115B can act as a peer processor to other core complex chiplets 110 in a processor system. To this end, the accelerator chiplet 115 may also include coherent interconnects with the core complex chiplet 110, as well as hardware to support interrupt and memory management protocols used by the core complex chiplet 110 when it is part of the CPU 510.

[0044] although Figure 5 505, but if the workload of the IO device 505 and the CPU 510 changes, the composable agent can reassign the accelerator chiplet 115B to the IO device 505. Therefore,

[0045] Figure 5 It is illustrated that the accelerator chiplet 115 can be designed to support a coherent operation mode and an IO operation mode, like the core complex chiplet 110 .

[0046] Figure 6 A processor system including multiple integrated adaptable accelerators according to one embodiment is illustrated. For simplicity, Figure 6 The processor system in FIG. 1 illustrates only the core complex chiplet 110 and the accelerator chiplet 115 , but does not illustrate the interconnects that may also be present.

[0047] Figure 6 The processor system in includes accelerator chiplet 605 and accelerator chiplet 610, which are different accelerators (i.e., chiplets 605 and 610 are different). For example, accelerator chiplet 605 can be an accelerator of a different type than accelerator chiplet 610. For example, accelerator chiplet 605 can be a DPU, while accelerator chiplet 610 is an AI accelerator. Therefore, Figure 6It is illustrated that a processor system may include multiple accelerator chiplets of different types.

[0048] In addition, accelerator chiplets can be used to form different IO devices. In this example, the accelerator chiplet 605 and the core complex chiplet 110A form an IO device 615, while the accelerator chiplet 610 and the core complex chiplet 110B form an IO device 620. The remaining core complex chiplets 110 form a CPU 625 for the host. The composable agent can assign core complex chiplets 110 in response to the individual workloads of the IO devices. For example, if the IO device 615 has (or is expected to have) a larger workload than the IO device 620, the composable agent can assign two core complex chiplets 110 to the IO device 620. Therefore, Figure 6 The illustrated processor system may include any number of different types of accelerators to support any number of different types of IO devices. In addition, these IO devices may also include any number of core complex chiplets 110 depending on their workloads.

[0049] In the foregoing, reference is made to the embodiments presented in this disclosure. However, the scope of the present disclosure is not limited to the specifically described embodiments. On the contrary, any combination of the described features and elements (whether or not involving different embodiments) is contemplated as implementing and practicing the contemplated embodiments. In addition, although the embodiments disclosed herein may achieve advantages over other possible solutions or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit the scope of the present disclosure. Therefore, the foregoing aspects, features, embodiments and advantages are merely illustrative and are not considered to be elements or limitations of the appended claims unless expressly stated in the claims.

[0050] As will be appreciated by those skilled in the art, the embodiments disclosed herein may be embodied as systems, methods, or computer program products. Thus, various aspects may take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software and hardware aspects, all of which may be generally referred to herein as a "circuit," "module," or "system." Additionally, various aspects may take the form of a computer program product embodied in one or more computer-readable media having computer-readable program code embodied thereon.

[0051] Any combination of one or more computer-readable media may be utilized. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example but not limited to, an electrical, magnetic, optical, electromagnetic, infrared or semiconductor system, device or apparatus, or any suitable combination of the foregoing. More specific examples (not a complete list) of computer-readable storage media would include the following: an electrical connector having one or more wires, a portable computer floppy disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium is any tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device or apparatus.

[0052] A computer readable signal medium may include a propagated data signal having computer readable program code embodied therein (e.g., in baseband or as part of a carrier wave). Such a propagated signal may take any of a variety of forms, including but not limited to electromagnetic, optical, or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0053] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0054] The computer program code for performing operations for various aspects of the present disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​(such as Java, Smalltalk, C++, etc.) and conventional procedural programming languages ​​(such as "C" programming language or similar programming languages). The program code can be executed entirely on the user's computer, partially on the user's computer, as an independent software package, partially on the user's computer and partially on a remote computer or completely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any type of network (including a local area network (LAN) or a wide area network (WAN)), or can be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0055] Aspects of the present disclosure are described below with reference to flowchart illustrations and / or block diagrams of the methods, devices (systems) and computer program products of the embodiments presented in the present disclosure. It should be understood that each frame of the flowchart illustration and / or block diagram and the combination of frames in the flowchart illustration and / or block diagram can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device to produce a machine, so that instructions executed by a processor of a computer or other programmable data processing device create components for implementing the functions / actions specified in one or more frames of a flowchart and / or block diagram.

[0056] These computer program instructions may also be stored in a computer-readable medium that can direct a computer, other programmable data processing apparatus, or other device to function in a specific manner, so that the instructions stored in the computer-readable medium produce an article of manufacture including instructions for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0057] The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operating steps to be performed on the computer, other programmable apparatus, or other devices to produce a computer-implemented method, so that the instructions executed on the computer or other programmable apparatus provide a process for implementing the functions / actions specified in one or more boxes of the flowchart and / or block diagram.

[0058] The flow chart and block diagram in the figure illustrate the possible concrete implementation architecture, functionality and operation of the system, method and computer program product according to various examples of the present invention.In this regard, each frame in the flow chart or block diagram may represent the module, segment or part of one or more executable instructions for realizing the specified logical function of the instruction.In some alternative implementations, the function pointed out in the frame may not occur in the order pointed out in the figure.For example, depending on the functionality involved, the two frames shown in succession can actually be performed substantially at the same time, or these frames can sometimes be performed in reverse order.It will also be noted that each frame in the block diagram and / or flow chart illustration and the combination of the frames in the block diagram and / or flow chart illustration can be realized by a system based on special hardware that performs a specified function or action or performs a combination of special hardware and computer instructions.

[0059] The technology disclosed herein can be demonstrated in the following non-limiting examples.

[0060] Embodiment 1. A processor system in a host, the processor system comprising: a substrate; a plurality of core complex chiplets, each of the plurality of core complex chiplets comprising at least one processor core; an accelerator chiplet; and a composable agent, the composable agent being configured to assign at least one of the plurality of core complex chiplets to the accelerator chiplet to form an IO device, while the remaining plurality of core complex chiplets form a central processing unit (CPU) for the host.

[0061] Embodiment 2. The processor system of embodiment 1, wherein the plurality of core complex chiplets are replicated integrated circuits, wherein the accelerator chiplet is implemented using an integrated circuit different from the replicated integrated circuits.

[0062] Embodiment 3. A processor system according to embodiment 2, wherein the accelerator chiplet does not include any processor core.

[0063] Embodiment 4. A processor system according to embodiment 3, wherein the accelerator chiplet is combined with at least one of the multiple core complex chiplets to form a data processing unit (DPU).

[0064] Embodiment 5. According to the processor system described in Embodiment 1, the processor system also includes: an interconnect, which is arranged on the substrate and implemented using an integrated circuit, and the integrated circuit is separated from the multiple core complex chiplets and the accelerator chiplet, wherein the interconnect is configured to allow each of the multiple core complex chiplets to communicate with each other and allow the multiple core complex chiplets to communicate with the accelerator chiplet.

[0065] Embodiment 6. A processor system according to embodiment 5, wherein the interconnect comprises a first circuit and a second circuit, the first circuit supporting interrupt semantics used by the multiple core complex chiplets forming the CPU and interrupt semantics used by at least one of the multiple core complex chiplets assigned to the IO device, and the second circuit supporting memory access used by the multiple core complex chiplets forming the CPU and memory access used by at least one of the multiple core complex chiplets assigned to the IO device.

[0066] Embodiment 7. According to the processor system described in Embodiment 1, the processor system also includes: an interconnect, which is configured to allow each core complex chiplet in the multiple core complex chiplets to communicate with each other, and to allow the multiple core complex chiplets to communicate with the accelerator chiplet, wherein the interconnect and the accelerator chiplet are part of the same integrated circuit.

[0067] Embodiment 8. A processor system according to embodiment 1, wherein after assigning at least one of the multiple core complex chiplets to the accelerator chiplet, the composable agent is configured to reassign at least one of the multiple core complex chiplets to the CPU so that the at least one of the multiple core complex chiplets is no longer part of the IO device.

[0068] Embodiment 9. A processor system according to embodiment 1, wherein the composable agent is configured to assign an additional core complex chiplet among the multiple core complex chiplets to the IO device so that the IO device includes multiple core complex chiplets among the multiple core complex chiplets.

[0069] Embodiment 10. A processor system, the processor system comprising: a plurality of core complex chiplets, each of the plurality of core complex chiplets comprising at least one processor core; an accelerator chiplet; and an interconnect, the interconnect connecting the plurality of core complex chiplets to each other and to the accelerator chiplet, the interconnect comprising: a combinable agent, the combinable agent being configured to assign at least one of the plurality of core complex chiplets to the accelerator chiplet to form an IO device, while the remaining plurality of core complex chiplets form a central processing unit (CPU) for a host.

[0070] Embodiment 11. A processor system according to embodiment 10, wherein the multiple core complex chiplets are replicated integrated circuits, wherein the accelerator chiplet is implemented using an integrated circuit different from the replicated integrated circuit, and wherein the interconnect is implemented using an integrated circuit separate from the multiple core complex chiplets.

[0071] Embodiment 12. A processor system according to embodiment 10, wherein the accelerator chiplet does not include any processor core.

[0072] Embodiment 13. A processor system according to embodiment 10, wherein the interconnect comprises a first circuit and a second circuit, the first circuit supporting interrupt semantics used by the multiple core complex chiplets forming the CPU and interrupt semantics used by at least one core complex chiplet among the multiple core complex chiplets assigned to the IO device, and the second circuit supporting memory access used by the multiple core complex chiplets forming the CPU and memory access used by the multiple core complex chiplets assigned to the IO device.

[0073] Embodiment 14. A method, comprising: selecting at least one core complex chiplet among a plurality of core complex chiplets to be assigned to an IO device, while assigning the remaining core complex chiplets among the plurality of core complex chiplets to a CPU of a host; removing the selected core complex chiplet as a peer of the remaining core complex chiplets among the plurality of core complex chiplets; and adding the selected core complex chiplet to the IO device, wherein the plurality of core complex chiplets are arranged on the same substrate as an accelerator chiplet also assigned to the IO device.

[0074] Embodiment 15. A method according to embodiment 14, wherein the plurality of core complex chiplets are replicated integrated circuits, wherein the accelerator chiplet is implemented using an integrated circuit different from the replicated integrated circuit.

[0075] Embodiment 16. The method of embodiment 14, wherein each core complex chiplet of the plurality of core complex chiplets comprises at least one processor core, wherein the accelerator chiplet does not comprise any processor core.

[0076] Embodiment 17. A method according to embodiment 14, wherein the accelerator chip is combined with at least one of the plurality of core complex chiplets to form a DPU.

[0077] Embodiment 18. The method of Embodiment 14, wherein the interconnect is disposed on the substrate and is implemented using an integrated circuit separate from the plurality of core complex chiplets and the accelerator chiplet.

[0078] Embodiment 19. The method according to embodiment 14 further comprises: determining the workload of the CPU and the IO device, wherein the workload determines the number of the plurality of core complex chiplets to be assigned to the IO device and the CPU.

[0079] Embodiment 20. The method according to embodiment 19 further comprises: determining that the workload of at least one of the CPU and the IO device has changed; and adjusting the number of the plurality of core complex chiplets assigned to the IO device.

[0080] While the foregoing is directed to particular examples, other and further examples may be devised without departing from the basic scope of the invention, and the scope of the invention is determined by the following claims.

Claims

1. A processor system in a host, the processor system comprising: substrate; a plurality of core complex chiplets, each of the plurality of core complex chiplets comprising at least one processor core; Accelerator chiplets; and A composable agent is configured to assign at least one of the plurality of core complex chiplets to the accelerator chiplet to form an IO device, while the remaining plurality of core complex chiplets form a central processing unit (CPU) for the host.

2. The processor system of claim 1 , wherein the plurality of core complex chiplets are replicated integrated circuits, wherein the accelerator chiplet is implemented using an integrated circuit different from the replicated integrated circuit.

3. The processor system of claim 2, wherein the accelerator chiplet does not include any processor cores.

4. The processor system according to claim 1, further comprising: An interconnect is disposed on the substrate and implemented using an integrated circuit that is separate from the plurality of core complex chiplets and the accelerator chiplet, wherein the interconnect is configured to allow each of the plurality of core complex chiplets to communicate with each other and to allow the plurality of core complex chiplets to communicate with the accelerator chiplet.

5. The processor system according to claim 1, further comprising: An interconnect configured to allow each of the plurality of core complex chiplets to communicate with each other and to allow the plurality of core complex chiplets to communicate with the accelerator chiplet, wherein the interconnect and the accelerator chiplet are part of the same integrated circuit.

6. A processor system according to claim 1, wherein after assigning at least one of the multiple core complex chiplets to the accelerator chiplet, the composable agent is configured to reassign at least one of the multiple core complex chiplets to the CPU so that the at least one of the multiple core complex chiplets is no longer part of the IO device.

7. The processor system of claim 1, wherein the composable agent is configured to assign an additional one of the plurality of core complex chiplets to the IO device such that the IO device includes a plurality of the plurality of core complex chiplets.

8. A processor system, the processor system comprising: a plurality of core complex chiplets, each of the plurality of core complex chiplets comprising at least one processor core; Accelerator chiplets; and an interconnect connecting the plurality of core complex chiplets to each other and to the accelerator chiplet, the interconnect comprising: A composable agent is configured to assign at least one of the plurality of core complex chiplets to the accelerator chiplet to form an IO device, while the remaining plurality of core complex chiplets form a central processing unit (CPU) for a host.

9. The processor system of claim 8, wherein the plurality of core complex chiplets are replicated integrated circuits, wherein the accelerator chiplet is implemented using an integrated circuit different from the replicated integrated circuit, and wherein the interconnect is implemented using an integrated circuit separate from the plurality of core complex chiplets.

10. The processor system of claim 8, wherein the accelerator chiplet does not include any processor cores.

11. A processor system according to claim 8, wherein the interconnect comprises a first circuit and a second circuit, wherein the first circuit supports interrupt semantics used by the multiple core complex chiplets forming the CPU and interrupt semantics used by at least one core complex chiplet among the multiple core complex chiplets assigned to the IO device, and the second circuit supports memory access used by the multiple core complex chiplets forming the CPU and memory access used by the multiple core complex chiplets assigned to the IO device.

12. A method comprising: selecting at least one core complex chiplet of the plurality of core complex chiplets to be assigned to an IO device while assigning the remaining core complex chiplets of the plurality of core complex chiplets to a CPU of a host; removing the selected core complex chiplet as a peer of the remaining core complex chiplets in the plurality of core complex chiplets; as well as The selected core complex chiplets are added to the IO device, wherein the plurality of core complex chiplets are disposed on a same substrate as accelerator chiplets also assigned to the IO device.

13. The method of claim 12, wherein the plurality of core complex chiplets are replicated integrated circuits, wherein the accelerator chiplet is implemented using an integrated circuit different from the replicated integrated circuits; wherein each core complex chiplet of the plurality of core complex chiplets comprises at least one processor core, wherein the accelerator chiplet does not include any processor core; wherein the accelerator chip is combined with the at least one core complex chiplet of the plurality of core complex chiplets to form a DPU; and Wherein the interconnect is disposed on the substrate and is implemented using an integrated circuit separate from the plurality of core complex chiplets and the accelerator chiplet.

14. The method according to claim 12, further comprising: A workload of the CPU and the IO device is determined, wherein the workload determines a number of the plurality of core complex chiplets to be assigned to the IO device and the CPU.

15. The method according to claim 14, further comprising: determining that the workload of at least one of the CPU and the IO device has changed; as well as The number of the plurality of core complex chiplets assigned to the IO device is adjusted.

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