Synthesis for layer roi processing

Abstract

Aspects presented herein relate to methods and apparatus for display processing, including devices, such as DPUs. The apparatus may obtain a plurality of layers associated with at least one frame, where each layer of the plurality of layers includes a set of layer regions, where each layer region of the set of layer regions includes a plurality of pixels. The apparatus may also assign each layer region of the set of layer regions to a corresponding component of a set of components in the DPU pipeline. Further, the apparatus may utilize the corresponding component in the set of components in the DPU pipeline to adjust a portion of the plurality of pixels in at least one layer region in the set of layer regions. The device may also synthesize the set of layer regions including the at least one layer region with the adjusted portion of the plurality of pixels.

Description

Technical Field

[0001] The present disclosure relates generally to processing systems and, more particularly, to one or more techniques for display processing. Background Art

[0002] Computing devices typically perform graphics and / or display processing (e.g., using a graphics processing unit (GPU), a central processing unit (CPU), a display processor, etc.) to render and display visual content. Such computing devices may include, for example, computer workstations, mobile phones (such as smart phones), embedded systems, personal computers, tablet computers, and video game consoles. The GPU is configured to execute a graphics processing pipeline that includes one or more processing stages that operate together to execute graphics processing commands and output frames. The central processing unit (CPU) can control the operation of the GPU by issuing one or more graphics processing commands to the GPU. Modern CPUs are typically capable of executing multiple applications concurrently, each of which may require the use of a GPU during execution. The display processor is configured to convert digital information received from the CPU into analog values, and may issue commands to a display panel to display visual content. A device that provides content for visual presentation on a display may utilize a GPU and / or a display processor.

[0003] The GPU of a device may be configured to perform processes in a graphics processing pipeline. Additionally, a display processor or display processing unit (DPU) may be configured to perform processes for display processing. However, with the advent of wireless communications and smaller handheld devices, the need for improved graphics or display processing continues to increase. Summary of the invention

[0004] The following presents the summary of one or more aspects in order to provide a basic understanding of these aspects. This summary is not an extensive overview of all contemplated aspects, and is neither intended to identify the key or important elements of all aspects, nor to describe the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to a more detailed description presented later.

[0005] In one aspect of the present disclosure, a method, a computer-readable medium, and a device are provided. The device may be a display processing unit (DPU), a graphics processing unit (GPU), a central processing unit (CPU), or any device that can perform display processing. The device may obtain multiple layers associated with at least one frame, wherein each layer of the multiple layers includes a layer region set, wherein each layer region in the layer region set includes multiple pixels. The device may also assign each layer region in the layer region set to a corresponding component in a component set in a display processing unit (DPU) pipeline. In addition, the device may use the corresponding component in the component set in the DPU pipeline to adjust a portion of the multiple pixels in at least one layer region in the layer region set. The device may also synthesize the layer region set including the at least one layer region with the adjusted portion of the multiple pixels. In addition, the device may process the synthesized output of the layer region set after synthesizing the layer region set, wherein the synthesis of the layer region set results in the synthesized output of the layer region set. The device may also send the processed output of the synthesis of the layer region set.

[0006] The details of one or more examples of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will become apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating an example content generation system.

[0008] Figure 2 An example graphics processing unit (GPU) is illustrated.

[0009] Figure 3 An example display framework including a display processor and a display is illustrated.

[0010] Figure 4 is a diagram illustrating an example mask layer for display processing.

[0011] Figure 5 is a diagram illustrating an example layer composition scheme for display processing.

[0012] Figure 6 is a diagram illustrating example layers used for display processing.

[0013] Figure 7 is a diagram illustrating example layers used for display processing.

[0014] Figure 8 is a diagram illustrating example display processing unit (DPU) hardware for display processing.

[0015] Fig. 9is a diagram illustrating an example layer composition scheme for display processing.

[0016] Fig.10 is a communication flow diagram illustrating example communications between a DPU, a GPU, and a display.

[0017] Fig.11 is a flow chart showing an example method of processing.

[0018] Fig.12 is a flow chart showing an example method of processing. DETAILED DESCRIPTION

[0019] Some types of display processing devices (e.g., mobile devices, computers, TVs, or other consumer devices) can utilize complex multiple content layouts in a single display processing layer. That is, for the graphics or display stack in the operating system of the device, there may be a single display processing layer (i.e., a display layer or layer associated with display processing). For example, there may be at least one display layer that can be associated with the screen or frame of the display processing device, so that the display panel at the device can be divided between display layers. In addition, for content or end users, there may be multiple content entities in the display processing layer. This may be due to operating system limitations and / or application rendering / resource management limitations. Using a single display processing layer can provide improved performance and / or flexibility for applications. Further, some types of applications may choose to use a single display processing layer for rendering. In addition, it may be beneficial to provide color processing capabilities on a per-region basis (i.e., for each region of interest (ROI) in the layer). The color processing capabilities based on each region can be utilized with certain types of display processing unit (DPU) architectures. In addition, for devices, it may be beneficial to provide color processing at multiple sub-layer levels (i.e., for different ROIs in the layer) within a single display processing layer. In some cases, certain aspects of the DPU (e.g., DPU hardware) may process layers and / or utilize layers as basic processing units in display processing operations. That is, the DPU hardware may provide support for image processing or color processing on a per-layer basis. However, some types of DPU hardware may not support image processing or color processing for multiple sub-layer ROIs. For example, the DPU hardware may provide image processing for each layer of granularity, but may not be able to provide support for multiple sub-layer ROIs for image processing or color processing. Various aspects of the present disclosure may provide the ability to perform image processing or color processing on a per-region basis within a display layer. That is, the various aspects presented herein may support image processing or color processing for each region of interest (ROI) in a single display layer. For example, various aspects of the present disclosure may support image processing or color processing at multiple sub-layer levels (i.e., for different ROIs in a layer) within a single display layer. For example, various aspects of the present disclosure may provide support in the DPU hardware to allow image / color processing for multiple sub-layer ROIs within a single display layer. In addition, in some cases, various aspects of the present disclosure may provide solutions to single-layer image processing specifications for certain types of applications. For example, a single display processing layer may provide improved performance and / or flexibility to applications.Thus, aspects presented herein may provide solutions for advanced display processing conditions, as well as help improve performance and / or flexibility of display processing.

[0020] Various aspects of the system, device, computer program product and method will be described more fully below with reference to the accompanying drawings. However, the present disclosure can be embodied in many different forms and should not be interpreted as being limited to any specific structure or function presented throughout the present disclosure. On the contrary, these aspects are provided so that the present disclosure will be thorough and complete, and the scope of the present disclosure will be fully conveyed to those skilled in the art. Based on the teachings of this article, it should be understood by those skilled in the art that the scope of the present disclosure is intended to cover any aspect of the system, device, computer program product and method disclosed herein, whether it is implemented independently of other aspects of the present disclosure or implemented in combination with other aspects of the present disclosure. For example, any number of aspects set forth herein can be used to implement a device or practice method. In addition, the scope of the present disclosure is intended to cover such a device or method that is practiced using other structures, functions, or structures and functions other than or different from the various aspects of the disclosure set forth herein. Any aspect disclosed herein can be embodied by one or more elements of the claims.

[0021] Although various aspects are described herein, many variations and permutations of these aspects fall within the scope of the present disclosure. Although some potential benefits and advantages of various aspects of the present disclosure are mentioned, the scope of the present disclosure is not intended to be limited to specific benefits, uses or objectives. On the contrary, various aspects of the present disclosure are intended to be widely applicable to different wireless technologies, system configurations, networks and transmission protocols, some of which are illustrated by way of example in the drawings and the description below. The specific embodiments and drawings merely illustrate the present disclosure rather than limit it, and the scope of the present disclosure is defined by the attached claims and their equivalent technical solutions.

[0022] Several aspects are presented with reference to various devices and methods. These devices and methods are described in the following detailed description and illustrated in the accompanying drawings by various blocks, components, circuits, processes, algorithms, etc. (collectively referred to as "elements"). These elements can be implemented using electronic hardware, computer software, or any combination thereof. Whether these elements are implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system.

[0023] For example, an element or any part of an element or any combination of elements may be implemented as a "processing system" including one or more processors (which may also be referred to as a processing unit). Examples of processors include microprocessors, microcontrollers, graphics processing units (GPUs), general purpose GPUs (GPGPUs), central processing units (CPUs), application processors, digital signal processors (DSPs), reduced instruction set computing (RISC) processors, systems on chip (SOCs), baseband processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), programmable logic devices (PLDs), state machines, gated logic devices, discrete hardware circuits, and other suitable hardware configured to perform the various functions described in this disclosure. One or more processors in a processing system may execute software. Software may be broadly interpreted as meaning instructions, instruction sets, codes, code segments, program codes, programs, subroutines, software components, applications, software applications, software packages, routines, subroutines, objects, executable files, threads of execution, procedures, functions, etc., whether expressed in software, firmware, middleware, microcode, hardware description languages, or other terms. The term "application" may refer to software. As described herein, one or more technologies may refer to an application, i.e., software, configured to perform one or more functions. In such examples, the application may be stored in a memory (e.g., an on-chip memory of a processor, a system memory, or any other memory). The hardware described herein (such as a processor) may be configured to execute an application. For example, an application may be described as including a code that, when executed by hardware, causes the hardware to perform one or more technologies described herein. As an example, the hardware may access the code from the memory and execute the code accessed from the memory to perform one or more technologies described herein. In some examples, components are identified in the present disclosure. In such examples, the components may be hardware, software, or a combination thereof. Each component may be a separate component or a subcomponent of a single component.

[0024] Therefore, in one or more examples described herein, the described functions can be implemented in hardware, software, or any combination thereof. If implemented with software, the functions can be stored or encoded on a computer-readable medium as one or more instructions or codes. Computer-readable media include computer storage media. Storage media can be any available media that can be accessed by a computer. As an example and not limitation, such computer-readable media may include random access memory (RAM), read-only memory (ROM), electrically erasable programmable ROM (EEPROM), optical disk storage device, magnetic disk storage device, other magnetic storage devices, a combination of computer-readable media of the above type, or any other medium that can be used to store instructions or data structure forms that can be accessed by a computer.

[0025] In summary, this disclosure describes techniques for having a graphics processing pipeline in a single device or multiple devices to improve rendering of graphics content and / or reduce load on a processing unit (i.e., any processing unit, such as a GPU, configured to perform one or more of the techniques described herein). For example, this disclosure describes techniques for performing graphics processing in any device that utilizes graphics processing. Other example benefits are described throughout this disclosure.

[0026] As used herein, instances of the term "content" may refer to "graphic content," "images," and vice versa. This is true regardless of whether these terms are used as adjectives, nouns, or other parts of speech. In some examples, as used herein, the term "graphic content" may refer to content produced by one or more processes of a graphics processing pipeline. In some examples, as used herein, the term "graphic content" may refer to content produced by a processing unit configured to perform graphics processing. In some examples, as used herein, the term "graphic content" may refer to content produced by a graphics processing unit.

[0027] In some examples, as used herein, the term "display content" may refer to content generated by a processing unit configured to perform display processing. In some examples, as used herein, the term "display content" may refer to content generated by a display processing unit. Graphics content may be processed to become display content. For example, a graphics processing unit may output graphics content (such as a frame) to a buffer (which may be referred to as a frame buffer). The display processing unit may read graphics content (such as one or more frames) from the buffer and perform one or more display processing techniques thereon to generate display content. For example, the display processing unit may be configured to perform synthesis on one or more rendering layers to generate a frame. As another example, the display processing unit may be configured to synthesize, blend or otherwise combine two or more layers into a single frame. The display processing unit may be configured to perform scaling on the frame, such as zooming in or out. In some examples, a frame may refer to a layer. In other examples, a frame may refer to two or more layers that have been blended together to form the frame, that is, the frame includes two or more layers, and the frame including two or more layers may be subsequently blended.

[0028] Figure 11 is a block diagram illustrating an example content generation system 100 configured to implement one or more techniques of the present disclosure. The content generation system 100 includes a device 104. The device 104 may include one or more components or circuits for performing various functions described herein. In some examples, one or more components of the device 104 may be components of a SOC. The device 104 may include one or more components configured to perform one or more techniques of the present disclosure. In the example shown, the device 104 may include a processing unit 120, a content encoder / decoder 122, and a system memory 124. In some aspects, the device 104 may include several components, such as a communication interface 126, a transceiver 132, a receiver 128, a transmitter 130, a display processor 127, and one or more displays 131. References to the display 131 may refer to one or more displays 131. For example, the display 131 may include a single display or multiple displays. The display 131 may include a first display and a second display. The first display may be a left-eye display, and the second display may be a right-eye display. In some examples, the first display and the second display may receive different frames for presentation thereon. In other examples, the first display and the second display may receive the same frame for presentation thereon. In further examples, the results of the graphics processing may not be displayed on the device, for example, the first display and the second display may not receive any frames for presentation thereon. Instead, the frames or graphics processing results may be passed to another device. In some aspects, this situation is referred to as split rendering.

[0029] Processing unit 120 may include internal memory 121. Processing unit 120 may be configured to perform graphics processing, such as in graphics processing pipeline 107. Content encoder / decoder 122 may include internal memory 123. In some examples, device 104 may include a display processor (such as display processor 127) to perform one or more display processing techniques on one or more frames generated by processing unit 120 before being presented by one or more displays 131. Display processor 127 may be configured to perform display processing. For example, display processor 127 may be configured to perform one or more display processing techniques on one or more frames generated by processing unit 120. One or more displays 131 may be configured to display or otherwise present frames processed by display processor 127. In some examples, one or more displays 131 may include one or more of the following: a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, a projection display device, an augmented reality display device, a virtual reality display device, a head mounted display, or any other type of display device.

[0030] Memory external to the processing unit 120 and the content encoder / decoder 122, such as the system memory 124, may be accessible to the processing unit 120 and the content encoder / decoder 122. For example, the processing unit 120 and the content encoder / decoder 122 may be configured to read from and / or write to the external memory, such as the system memory 124. The processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to the system memory 124 via a bus. In some examples, the processing unit 120 and the content encoder / decoder 122 may be communicatively coupled to each other via the bus or a different connection.

[0031] The content encoder / decoder 122 may be configured to receive graphics content from any source, such as the system memory 124 and / or the communication interface 126. The system memory 124 may be configured to store the received encoded or decoded graphics content. The content encoder / decoder 122 may be configured to receive the encoded or decoded graphics content in the form of encoded pixel data, for example, from the system memory 124 and / or the communication interface 126. The content encoder / decoder 122 may be configured to encode or decode any graphics content.

[0032] Internal memory 121 or system memory 124 may include one or more volatile or non-volatile memories or storage devices. In some examples, internal memory 121 or system memory 124 may include RAM, SRAM, DRAM, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic data media, or optical storage media, or any other type of memory.

[0033] According to some examples, the internal memory 121 or the system memory 124 may be a non-transitory storage medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagation signal. However, the term "non-transitory" should not be interpreted to mean that the internal memory 121 or the system memory 124 is non-removable or that its contents are static. For example, the system memory 124 may be removed from the device 104 and moved to another device. For another example, the system memory 124 may not be removable from the device 104.

[0034] The processing unit 120 may be a central processing unit (CPU), a graphics processing unit (GPU), a general purpose GPU (GPGPU), or any other processing unit that may be configured to perform graphics processing. In some examples, the processing unit 120 may be integrated into the motherboard of the device 104. In some examples, the processing unit 120 may be present on a graphics card installed in a port in the motherboard of the device 104, or may be otherwise incorporated into a peripheral device configured to interoperate with the device 104. The processing unit 120 may include one or more processors, such as one or more microprocessors, GPUs, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the processing unit 120 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 121), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0035] The content encoder / decoder 122 may be any processing unit configured to perform content decoding. In some examples, the content encoder / decoder 122 may be integrated into the mainboard of the device 104. The content encoder / decoder 122 may include one or more processors, such as one or more microprocessors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), arithmetic logic units (ALUs), digital signal processors (DSPs), video processors, discrete logic, software, hardware, firmware, other equivalent integrated or discrete logic circuits, or any combination thereof. If the technology is partially implemented in software, the content encoder / decoder 122 may store instructions for the software in a suitable non-transitory computer-readable storage medium (e.g., internal memory 123), and may use one or more processors to execute instructions in hardware to perform the technology of the present disclosure. Any of the above (including hardware, software, a combination of hardware and software, etc.) may be considered to be one or more processors.

[0036] In some aspects, the content generation system 100 may include a communication interface 126. The communication interface 126 may include a receiver 128 and a transmitter 130. The receiver 128 may be configured to perform any receiving functions described herein with respect to the device 104. Additionally, the receiver 128 may be configured to receive information from another device, such as eye or head position information, rendering commands, or positioning information. The transmitter 130 may be configured to perform any sending functions described herein with respect to the device 104. For example, the transmitter 130 may be configured to send information to another device, which may include a request for content. The receiver 128 and the transmitter 130 may be combined into a transceiver 132. In such examples, the transceiver 132 may be configured to perform any receiving functions and / or sending functions described herein with respect to the device 104.

[0037] See again Figure 1 In some aspects, the display processor 127 may include a synthesis component 198 configured to obtain a plurality of layers associated with at least one frame, wherein each layer of the plurality of layers includes a set of layer regions, wherein each layer region of the set of layer regions includes a plurality of pixels. The synthesis component 198 may also be configured to assign each layer region of the set of layer regions to a corresponding component of a set of components in a display processing unit (DPU) pipeline. The synthesis component 198 may also be configured to adjust a portion of a plurality of pixels in at least one layer region of the set of layer regions using a corresponding component of a set of components in the DPU pipeline. The synthesis component 198 may also be configured to synthesize the set of layer regions including at least one layer region with the adjusted portion of the plurality of pixels. The synthesis component 198 may also be configured to process the synthesized output of the set of layer regions after synthesizing the set of layer regions, wherein the synthesis of the set of layer regions results in the synthesized output of the set of layer regions. The synthesis component 198 may also be configured to send the processed output of the synthesis of the set of layer regions. Although the following description may focus on display processing, the concepts described herein may be applicable to other similar processing techniques.

[0038] As described herein, a device such as device 104 may refer to any device, apparatus or system configured to perform one or more technologies described herein. For example, a device may be a server, a base station, a user equipment, a client device, a station, an access point, a computer (e.g., a personal computer, a desktop computer, a laptop computer, a tablet computer, a computer workstation or a mainframe computer), a final product, an apparatus, a phone, a smart phone, a server, a video game platform or console, a handheld device (e.g., a portable video game device or a personal digital assistant (PDA)), a wearable computing device (e.g., a smart watch, an augmented reality device or a virtual reality device), a non-wearable device, a display or display device, a television, a television set-top box, an intermediate network device, a digital media player, a video streaming device, a content streaming device, a vehicle-mounted computer, any mobile device, any device configured to generate graphics content, or any device configured to perform one or more technologies described herein. The process herein may be described as being performed by a specific component (e.g., a GPU), but in further embodiments, other components (e.g., a CPU) consistent with the disclosed embodiments may be used to perform.

[0039] The GPU may process multiple types of data or data packets in the GPU pipeline. For example, in some aspects, the GPU may process two types of data or data packets, such as context register packets and draw call data. The context register packet may be a collection of global state information, such as information about global registers, shaders, or constant data, which may adjust how the graphics context is to be processed. For example, the context register packet may include information about the color format. In some aspects of the context register packet, there may be a bit indicating which workload belongs to the context register. In addition, there may be multiple functions or programs running simultaneously and / or in parallel. For example, a function or program may describe an operation, such as a color mode or color format. Therefore, the context register may define multiple states of the GPU.

[0040] The context state can be used to determine how a single processing unit (e.g., a vertex fetcher (VFD), a vertex shader (VS), a shader processor, or a geometry processor) operates and / or in which mode the processing unit operates. To this end, the GPU can use context registers and programming data. In some aspects, the GPU can generate workloads (e.g., vertex or pixel workloads) in a pipeline based on the context register definition of the mode or state. Certain processing units (e.g., VFDs) can use these states to determine certain functions, such as how to assemble vertices. Since these modes or states may change, the GPU may need to change the corresponding context. In addition, the workload corresponding to the mode or state may follow the changed mode or state.

[0041] Figure 2 An example GPU 200 is illustrated in accordance with one or more techniques of this disclosure. Figure 2 As shown, GPU 200 includes a command processor (CP) 210, a draw call group 212, a VFD 220, a VS 222, a vertex cache (VPC) 224, a triangle setup engine (TSE) 226, a rasterizer (RAS) 228, a Z pass engine (ZPE) 230, a pixel interpolator (PI) 232, a fragment shader (FS) 234, a rendering back end (RB) 236, a second level (L2) cache (UCHE) 238, and a system memory 240. Although Figure 2 GPU 200 is shown to include processing units 220 to 238, but GPU 200 may include multiple additional processing units. Additionally, processing units 220 to 238 are merely examples, and any combination or order of processing units may be used with a GPU according to the present disclosure. GPU 200 also includes command buffer 250, context register group 260, and context state 261.

[0042] like Figure 2 As shown, the GPU may parse the command buffer into context register packets (e.g., context register packets 260) and / or draw call data packets (e.g., draw call packets 212) using a CP (e.g., CP 210) or a hardware accelerator. Subsequently, the CP 210 may transmit the context register packets 260 or the draw call packets 212 to a processing unit or block in the GPU through a separate path. In addition, the command buffer 250 may alternate different states of context registers and draw calls. For example, the command buffer may be constructed in the following manner: context registers of context N, draw calls of context N, context registers of context N+1, and draw calls of context N+1.

[0043] The GPU can render images in a variety of different ways. In some instances, the GPU can use rendering and / or tile rendering to render images. In a tile rendering GPU, the image can be divided or split into different parts or tiles. After the image is divided, each part or tile can be rendered separately. The tile rendering GPU can divide the computer graphics image into a grid format so that each part of the grid (i.e., tile) is rendered separately. In some aspects, during the binning process, the image can be divided into different boxes or tiles. In some aspects, during the binning process, a visibility stream can be constructed in which visible primitives or drawing calls can be identified. In contrast to tile rendering, direct rendering does not divide the frame into smaller boxes or tiles. On the contrary, in direct rendering, the entire frame is rendered at once. Additionally, some types of GPUs may allow both tile rendering and direct rendering.

[0044] Figure 3is a block diagram 300 illustrating an example display framework including a processing unit 120 , a system memory 124 , a display processor 127 , and a display 131 , as may be identified in connection with device 104 .

[0045] The GPU may be included in a device that provides content for visual presentation on a display. For example, the processing unit 120 may include a GPU 310 configured to render graphics data for display on a computing device (e.g., device 104), which may be a computer workstation, a mobile phone, a smart phone or other smart device, an embedded system, a personal computer, a tablet computer, a video game console, etc. The operation of the GPU 310 may be controlled based on one or more graphics processing commands provided by the CPU 315. The CPU 315 may be configured to execute multiple applications concurrently. In some cases, each of the multiple applications executed concurrently may utilize the GPU 310 at the same time. The processing technology may be performed by outputting frames via the processing unit 120 over a physical or wireless communication channel.

[0046] System memory 124, which may be executed by processing unit 120, may include user space 320 and kernel space 325. User space 320 (sometimes referred to as "application space") may include software applications and / or application frameworks. For example, software applications may include operating systems, media applications, graphics applications, workspace applications, etc. The application framework may include a framework used by one or more software applications, such as libraries, services (e.g., display services, input services, etc.), application program interfaces (APIs), etc. Kernel space 325 may further include a display driver 330. Display driver 330 may be configured to control display processor 127. For example, display driver 330 may cause display processor 127 to synthesize a frame and send data of the frame to a display.

[0047] Display processor 127 includes display control block 335 and display interface 340. Display processor 127 may be configured to manipulate functions of display 131 (e.g., based on input received from display driver 330). Display control block 335 may be further configured to output image frames to display 131 via display interface 340. In some examples, display control block 335 may additionally or alternatively perform post-processing of image data provided based on execution of processing unit 120 on system memory 124.

[0048] The display interface 340 may be configured to cause the display 131 to display an image frame. The display interface 340 may output image data to the display 131 according to an interface protocol such as, for example, MIPIDSI (Mobile Industry Processor Interface, Display Serial Interface). That is, the display 131 may be configured according to the MIPIDSI standard. The MIPIDSI standard supports a video mode and a command mode. In an example where the display 131 operates in the video mode, the display processor 127 may continuously refresh the graphics content of the display 131. For example, the entire graphics content may be refreshed at each refresh cycle (e.g., line by line). In an example where the display 131 operates in the command mode, the display processor 127 may write the graphics content of the frame to the buffer 350.

[0049] In some such examples, display processor 127 may not continuously refresh the graphics content of display 131. Instead, display processor 127 may use vertical synchronization (Vsync) pulses to coordinate the rendering and consumption of graphics content at buffer 350. For example, when a Vsync pulse is generated, display processor 127 may output new graphics content to buffer 350. Thus, the generation of a Vsync pulse may indicate that current graphics content has been rendered at buffer 350.

[0050] Based on the display controller 345, the display client 355, and the buffer 350, the frame is displayed at the display 131. The display controller 345 may receive image data from the display interface 340 and store the received image data in the buffer 350. In some examples, the display controller 345 may output the image data stored in the buffer 350 to the display client 355. Thus, the buffer 350 may represent a local memory to the display 131. In some examples, the display controller 345 may output the image data received from the display interface 340 directly to the display client 355.

[0051] The display client 355 may be associated with a touch panel that senses interactions between a user and the display 131. When a user interacts with the display 131, one or more sensors in the touch panel may output a signal to the display controller 345 indicating which of the one or more sensors has sensor activity, the duration of the sensor activity, the pressure applied to the one or more sensors, etc. The display controller 345 may use the sensor output to determine the manner in which the user is interacting with the display 131. The display 131 may further be associated with / include other devices that operate in conjunction with the display client 355, such as a camera, a microphone, and / or a speaker.

[0052] Some processing techniques of device 104 may be performed through three stages (e.g., stage 1: rendering stage; stage 2: composition stage; and stage 3: display / delivery stage). However, other processing techniques may combine the composition stage and the display / delivery stage into a single stage, such that the processing technique may be performed based on a total of two stages (e.g., stage 1: rendering stage; and stage 2: composition / display / delivery stage). During the rendering stage, GPU 310 may process a content buffer based on the execution of an application that generates content on a pixel-by-pixel basis. During the composition and display stages, pixel elements may be assembled to form a frame that is delivered to a physical display panel / subsystem (e.g., display 131) that displays the frame.

[0053] Instructions (e.g., software instructions) executed by a CPU or instructions executed by a display processor may cause the CPU or display processor to search and / or generate a synthesis strategy for synthesizing a frame based on dynamic priorities and runtime statistics associated with one or more synthesis strategy groups. A frame to be displayed by a physical display device (such as a display panel) may include multiple layers. In addition, the synthesis of a frame may be based on combining multiple layers into a frame (e.g., based on a frame buffer). After combining multiple layers into a frame, the frame may be provided to a display panel for display on the display panel. The process of combining each layer in a plurality of layers into a frame may be referred to as synthesis, frame synthesis, synthesis procedure, synthesis process, etc.

[0054] The frame synthesis procedure or synthesis strategy may correspond to a technique for synthesizing different layers in a plurality of layers into a single frame. The plurality of layers may be stored in a double data rate (DDR) memory. Each layer in the plurality of layers may further correspond to a separate buffer. A synthesizer or hardware synthesizer (HWC) associated with a block or function may determine the input of each layer / buffer and execute the frame synthesis procedure to generate an output indicating a synthesized frame. That is, the input may be a layer, and the output may be a frame synthesis procedure for synthesizing a frame to be displayed on a display panel.

[0055] Some aspects of display processing may utilize different types of mask layers, such as shape mask layers. A mask layer is a layer that can represent a portion of a display or display panel. For example, an area of ​​a mask layer may correspond to an area of ​​a display, but the entire mask layer may depict a portion of the content that is actually displayed at the display or panel. For example, a mask layer may include a top portion and a bottom portion of a display area, but the middle portion of the mask layer may be empty. In some examples, there may be multiple mask layers to represent different portions of the display area. In addition, for certain portions of the display area, the content of different mask layers may overlap with each other. Thus, a mask layer may represent a portion of a display area that may or may not overlap with other mask layers.

[0056] Figure 44 is a diagram illustrating an example mask layer for display processing. More specifically, diagram 400 depicts one type of mask layer that can represent portions of a display panel. Figure 4 As shown, diagram 400 includes a mask layer 402, which includes a top region 410 and a bottom region 420. The top region 410 includes regions 411, 412, 413, and 414, and the bottom region 420 includes regions 421, 422, 423, and 424. Figure 4 As depicted, mask layer 402 may represent different areas displayed on the display panel.

[0057] Some types of displays may use a certain type of mask layer (e.g., a shape mask layer) to reshape the display frame. For example, the mask layer may reshape the display frame to provide a more optimized visual shape at the display panel (e.g., improved rounded corners, improved circular shape, improved rectangular shape, etc.). These types of mask layers (e.g., shape mask layers) may be processed by software (e.g., graphics processing unit (GPU) software or central processing unit (CPU) software), or by hardware (e.g., display processing unit (DPU) hardware). In addition, these mask layers may be processed by other specific types of hardware logic modules (e.g., modules in display driver integrated circuits (DDICs) or bridge chips). In some aspects, these types of mask layers (e.g., shape mask layers) may be based on a certain unit, such as a pixel. That is, the shape generation base unit of the shape mask layer may be a single pixel.

[0058] Some aspects of display processing can utilize frame buffers to cache or store the composite output of the GPU. For example, after synthesis at the GPU, the display layer can be cached or stored in a frame buffer. In some aspects, the synthesis hardware (HW) or software (SW) stack can use a frame buffer target to cache the synthesis output (e.g., GPU synthesis output or CPU synthesis output). The cached synthesis output can then be transmitted to another processor (e.g., DPU) as an input layer. The frame buffer can have multiple different color formats, such as red (R) green (G) blue (B) α (A) (RGBA) format (e.g., RGBA8888 format). Moreover, the frame buffer can have a specific size (e.g., 32-bit triple buffer). For example, at the beginning of the display / graphics subsystem design, the frame buffer can be created as an RGBA8888 format and a 32-bit triple buffer. In some cases, if the frame layer does not use a specific synthesis (e.g., GPU or client synthesis), the frame buffer can be ignored. Moreover, the layer (e.g., a frame layer or display layer associated with the display process) can be directly extracted and synthesized. For example, a DPU or hardware synthesizer may extract the layers directly and then synthesize the layers.

[0059] Figure 5 5 is a diagram illustrating an example of a layer composition scheme for display processing. More specifically, diagram 500 depicts layer composition of display layers, where some layers (e.g., layers of a particular composition) are cached in a frame buffer and some layers are fetched and composed directly by the DPU. Figure 5 As shown, diagram 500 includes layer 510 , layer 511 , layer 512 , layer 513 , a frame buffer 530 (eg, an RGBA8888 format frame buffer), a DPU 540 , and a display 550 . Figure 5 It is depicted that layers synthesized at the GPU (i.e., layers associated with GPU synthesis) can be cached or stored in a frame buffer. For example, layer 510, layer 511, and layer 512 can be synthesized at the GPU and then cached / stored at frame buffer 530. Alternatively, layers that are not synthesized at the GPU (i.e., layers associated with non-GPU synthesis) can be directly extracted and synthesized at the DPU. For example, layer 513 can be directly extracted and synthesized at DPU 540. That is, layer 510, layer 511, and layer 512 can be a particular type of synthesis (e.g., GPU synthesis), while layer 513 can be another type of synthesis (non-GPU synthesis). After being cached / stored in frame buffer 530, layer 510, layer 511, and layer 512 can be transmitted to DPU 540. Further, after processing at DPU 540, layers 510 to 513 can be transmitted to display 550.

[0060] Some types of display processing devices (e.g., mobile devices, computers, TVs, or other consumer devices) can utilize complex multiple content layouts in a single display processing layer. That is, for the graphics or display stack in the operating system of the device, there may be a single display processing layer (i.e., a display layer or layer associated with display processing). For example, there may be at least one display layer that can be associated with the screen or frame of the display processing device, so that the display panel at the device can be divided between display layers. In addition, for content or end users, there may be multiple content entities in the display processing layer. This may be due to operating system limitations and / or application rendering / resource management limitations. Using a single display processing layer can provide improved performance and / or flexibility for applications. Further, some types of applications may choose to use a single display processing layer for rendering. In addition, it may be beneficial to provide color processing capabilities on a per-region basis (i.e., for each region of interest (ROI) in the layer). The color processing capabilities based on each region can be utilized with certain types of display processing unit (DPU) architectures. In addition, for devices, it may be beneficial to provide color processing at multiple sub-layer levels (i.e., for different ROIs in the layer) within a single display processing layer.

[0061] Figure 6600 is a diagram illustrating an example of layers for display processing. More specifically, diagram 600 depicts display layers 602 (e.g., layers of a particular composition) in a screen or frame at a display device. Additionally, the display layers at the display device may include different regions of interest or areas (ROIs). Figure 6 As shown, display layer 602 includes region 610 and region 611. Each of region 610 and region 611 may be associated with a region of interest (ROI) or a region for color processing.

[0062] Figure 7 700 is another example of a layer for display processing. More specifically, diagram 700 depicts a display layer 702 (eg, a layer of a particular composition) in a screen or frame at a display device, where the layer includes different regions or ROIs. Figure 7 As shown, display layer 702 includes region 710, region 711, and region 712. Each of regions 710, 711, and 712 may be associated with a region of interest (ROI) (eg, a ROI for color processing) or a region in the layer. Figure 6 and Figure 7 Examples of different regions or ROIs of display layers in a screen or frame are shown.

[0063] Figure 8 8 is a diagram 800 illustrating example DPU hardware for display processing. More specifically, diagram 800 depicts DPU hardware 802 for supporting different types of display processing, such as image processing or color processing. Figure 8As shown, the DPU hardware 802 includes a bus interface 810, a color converter 820, multiple delay buffer components (e.g., delay buffer component 830, delay buffer component 831, delay buffer component 832, delay buffer component 833, delay buffer component 834, delay buffer component 835, delay buffer component 836, delay buffer component 837, delay buffer component 838 and delay buffer component 839) and multiple image processing components (e.g., image processing component 840, image processing component 841, image processing component 842, image processing component 843, image processing component 844, image processing component 845, image processing component 846, image processing component 847, image processing component 848 and image processing component 849). The DPU hardware 802 also includes a crossbar switch 850, a multi-layer mixer (e.g., layer mixer 860, layer mixer 861, layer mixer 862, layer mixer 863, layer mixer 864, and layer mixer 865), a frame processing component (e.g., frame processing component 870 and frame processing component 871), and multiple physical display processing components (e.g., physical display processing component 880, physical display processing component 881, physical display processing component 882, and physical display processing component 883).

[0064] In some cases, certain aspects of the DPU (e.g., DPU hardware) may process layers and / or utilize layers as basic processing units in display processing operations. That is, the DPU hardware may provide support for image processing or color processing on a per-layer basis. However, some types of DPU hardware may not support image processing or color processing for multiple sub-layer ROIs. For example, the DPU hardware may provide image processing for each layer of granularity, but may not be able to provide support for multiple sub-layer ROIs for image processing or color processing. Therefore, it may be beneficial to provide image processing or color processing for multiple sub-layer ROIs within a display layer. For example, it may be beneficial to provide DPU hardware that supports image / color processing for multiple sub-layer ROIs within a single layer.

[0065] Aspects of the present disclosure may provide the ability to perform image processing or color processing on a per-region basis within a display layer. That is, the aspects presented herein may support image processing or color processing for each region of interest (ROI) in a single display layer. For example, aspects of the present disclosure may support image processing or color processing at multiple sub-layer levels (i.e., for different ROIs in a layer) within a single display layer. For example, aspects of the present disclosure may provide support in DPU hardware to allow image / color processing for multiple sub-layer ROIs within a single display layer. In addition, in some cases, aspects of the present disclosure may provide solutions to single-layer image processing specifications for certain types of applications. For example, a single display processing layer may provide improved performance and / or flexibility to applications. Therefore, the aspects presented herein may provide solutions for advanced display processing conditions, as well as help improve the performance and / or flexibility of display processing.

[0066] In some cases, aspects of the present disclosure may divide a single display layer into multiple synthesis stages for image / color processing. For example, a single display layer may be divided into multiple regions or ROIs for image / color processing at the DPU hardware. Specific layout information for ROIs in the display layer may be obtained using multiple different procedures. For example, layout information for ROIs in the display layer may be obtained from operating system framework resources and / or layout management services. In addition, an application or game may provide location / positioning information or coordinates for layout information for ROIs in the display layer. In addition, layout information for ROIs in the display layer may be obtained based on runtime layer content analysis.

[0067] In some aspects presented herein, for each region or ROI in a single layer, the region or ROI may be allocated or assigned to a corresponding synthesis stage. In addition, the region or ROI may be assigned to a component in a DPU pipeline (e.g., a processing pipeline or a source surface processor pipeline (SSPP)) for specific image / color post-processing. This allocation or assignment may be based on other types of components (e.g., a three-dimensional (3D) lookup table (LUT) or other components for display processing). The DPU hardware may extract the region or ROI of the layer and perform specific processing and synthesis. Compared to the original layer display hierarchy, this region or ROI may be assigned to a higher level in the display hierarchy (i.e., Z order or Z-order). Z-order may refer to a process for sorting which items in a display application appear visually in front of other items. Thereafter, in the next synthesis stage, the entire layer (i.e., excluding the previous region or ROI) may be extracted and synthesized at a lower level in the display hierarchy (i.e., Z order or Z-order). For example, the layer may be assigned to a lower level in the display hierarchy because it corresponds to a background layer. Thus, a single display layer may be divided into multiple sub-layer regions or ROIs, and additional compositing stages may be added for any new sub-layers (i.e., new sub-layers that are logically added).

[0068] Fig. 9 900 is a diagram illustrating an example of a layer composition scheme for display processing. More specifically, diagram 900 depicts a composition scheme including display layers 902 with different ROIs, corresponding composition stages, and corresponding components in DPU hardware 925. Fig. 9 As shown in , diagram 900 includes a display layer 902 having several regions or ROIs (e.g., region 910, region 911, and region 912) and multiple synthesis stages (e.g., synthesis stage 920, synthesis stage 921, synthesis stage 922, and synthesis stage 923). Fig. 9 As illustrated in , the DPU hardware 925 includes a bus interface 926, a color converter 928, a plurality of delay buffer components (e.g., delay buffer component 930, delay buffer component 931, delay buffer component 932, and delay buffer component 933), and a plurality of image processing components (e.g., image processing component 940, image processing component 941, image processing component 942, and image processing component 943). The DPU hardware 925 also includes a crossbar switch 950, a multi-layer mixer (e.g., layer mixer 960, layer mixer 961, layer mixer 962, and layer mixer 963), a frame processing component (e.g., frame processing component 970 and frame processing component 971), and a plurality of physical display processing components (e.g., physical display processing component 980, physical display processing component 981, physical display processing component 982, and physical display processing component 983). Although in Fig. 9925 may include Figure 8 All components (and the same number of components) in the same components as the DPU hardware 802 in the DPU. In some aspects, the latency buffer component or image processing component may correspond to a processing pipeline or source surface processor pipeline (SSPP) in the DPU.

[0069] like Fig. 9 As depicted, display layer 902 may be included in a plurality of display layers obtained from a GPU, a CPU, an application, or a game. For example, the DPU may obtain a plurality of layers (including display layer 902) associated with at least one screen or frame at a display device, wherein each of the plurality of layers includes a layer region or a set of ROIs, and wherein each of the layer regions or the set of ROIs includes a plurality of pixels. Each of the layer regions (e.g., region 910, region 911, and region 912) in the layer regions in display layer 902 may correspond to a specific component (e.g., one of latency buffer components 930-933 or image processing components 940-943) and / or a specific synthesis stage (e.g., one of synthesis stages 920-923) in DPU hardware 925. For example, each layer region in the set of layer regions may be assigned to a corresponding component in a set of components in a DPU pipeline. For example, region 910 may be allocated or assigned to delay buffer component 930 or image processing component 940, region 911 may be allocated or assigned to delay buffer component 931 or image processing component 941, and region 912 may be allocated or assigned to delay buffer component 932 or image processing component 942. Thereafter, a portion of pixels in at least one layer region may be adjusted using the corresponding components. For example, a portion of pixels in region 910 may be adjusted using delay buffer component 930 or image processing component 940, a portion of pixels in region 911 may be adjusted using delay buffer component 931 or image processing component 941, and / or a portion of pixels in region 912 may be adjusted using delay buffer component 932 or image processing component 942.

[0070] like Fig. 9As shown, regions or ROIs may also be associated with specific synthesis stages. For example, region 910 may be associated with synthesis stage 920, region 911 may be associated with synthesis stage 921, and region 912 may be associated with synthesis stage 922. The synthesis stage may also be associated with a corresponding component that adjusts a portion of pixels in at least one layer region. For example, the corresponding component may be associated with a synthesis stage (e.g., synthesis stage 920-923) for a specific color processing region (e.g., regions 910-912). For example, a delay buffer component 930 or an image processing component 940 may be associated with synthesis stage 920 of region 910, a delay buffer component 931 or an image processing component 941 may be associated with synthesis stage 921 of region 911, and a delay buffer component 932 or an image processing component 942 may be associated with synthesis stage 922 of region 912. That is, the DPU may synthesize a set of layer regions (e.g., regions 910-912) including at least one layer region with the adjusted portion of a plurality of pixels. In addition, the entire layer except the region or ROI (e.g., regions 910-912) may be associated with a corresponding component (e.g., delay buffer component 933 or image processing component 943) and a synthesis stage (e.g., synthesis stage 923). The synthesis stage (synthesis stage 920-923) may include a blending stage, so that synthesizing a layer region set including at least one layer region with the adjusted portion of multiple pixels may include: blending the layer region set including at least one layer region with the adjusted portion of multiple pixels. In addition, the synthesis of the layer region set may result in an output of the synthesis of the layer region set, and the DPU may process the output of the synthesis of the layer region set after synthesizing the layer region set.

[0071] Aspects of the present disclosure may include multiple benefits or advantages. For example, the various aspects presented herein may utilize DPU hardware to provide a multi-color / image ROI processing solution for a single display layer. That is, the various aspects presented herein may support image processing or color processing for each region or ROI in a single display layer. For example, various aspects of the present disclosure may support image processing or color processing at multiple sub-layer levels (i.e., for different ROIs in a layer) within a single display layer. For example, various aspects of the present disclosure may provide support in DPU hardware to allow image / color processing for multiple sub-layer ROIs within a single display layer. In addition, in some cases, various aspects of the present disclosure may provide solutions to single-layer image processing specifications for certain types of applications or games. That is, the various aspects presented herein may solve single-layer image processing specifications for different applications or games. For example, a single display processing layer may provide improved performance and / or flexibility to applications or games. Therefore, the various aspects presented herein may provide solutions for advanced display processing conditions, and help improve the performance and / or flexibility of display processing. In some cases, aspects presented herein may adjust a layer stack and / or a composition stage (eg, a blending stage) to add a region or ROI of a single display layer to the layer stack and / or composition stage.

[0072] Fig.10 FIG. 1 is a communication flow diagram 1000 showing a process according to one or more techniques of the present disclosure. Fig.10 As shown, diagram 1000 includes example communications between a DPU 1002 (or other display processor), a GPU / CPU 1004, and a display 1006, in accordance with one or more techniques of this disclosure.

[0073] At 1010, the DPU 1002 may obtain a plurality of layers associated with at least one frame (e.g., the DPU 1002 may obtain layer 1012 from the GPU / CPU 1004), wherein each layer in the plurality of layers includes a set of layer regions, wherein each layer region in the set of layer regions includes a plurality of pixels. In some aspects, obtaining the plurality of layers may include: receiving the plurality of layers from at least one of a graphics processing unit (GPU), a central processing unit (CPU), an application, or a game. For example, the DPU may receive the plurality of layers from at least one of a GPU, a CPU, an application, or a game. The set of layer regions in each of the plurality of layers corresponds to a set of portions of each of the plurality of layers or a set of regions of interest (ROIs) for each of the plurality of layers. In addition, the at least one frame may be associated with at least one of display processing, image processing, frame processing, or color processing. In some aspects, the plurality of pixels in each layer region in the set of layer regions are associated with metadata, a layer hierarchy, a Z order, or a Z coordinate. Furthermore, each layer region of the set of layer regions may include a corresponding pixel resolution such that the corresponding pixel resolution of at least one first layer region of the set of layer regions is different from the corresponding pixel resolution of at least one second layer region of the set of layer regions.

[0074] At 1020, the DPU 1002 may assign each layer region in the layer region set to a corresponding component in the component set in a display processing unit (DPU) pipeline. In some aspects, assigning each layer region in the layer region set to a corresponding component in the component set may include mapping each layer region in the layer region set to a corresponding component in the component set, so that each layer region in the layer region set is assigned to the corresponding component based on the mapping. For example, the DPU may map each layer region in the layer region set to a corresponding component in the component set. Each layer region in the layer region set may be mapped to a corresponding component in the component set based on a corresponding processing task associated with each layer region in the layer region set. In addition, each layer region in the layer region set may be mapped to a corresponding component in the component set based on a position of each layer region in the layer region set or a coordinate set of each layer region in the layer region set.

[0075] At 1030, the DPU 1002 may adjust a portion of the plurality of pixels in at least one layer region in the set of layer regions using a corresponding component in the set of components in the DPU pipeline. The portion of the plurality of pixels in at least one layer region may be adjusted based on processing the plurality of pixels in the at least one layer region. In addition, the plurality of pixels in the at least one layer region may be processed based on display processing, image processing, frame processing, or color processing.

[0076] At 1040, the DPU 1002 may composite the set of layer regions including the at least one layer region with the adjusted portion of the plurality of pixels. In some aspects, composite the set of layer regions including the at least one layer region with the adjusted portion of the plurality of pixels may include blending the set of layer regions including the at least one layer region with the adjusted portion of the plurality of pixels. For example, the DPU may blend at least some of the layer regions in the set of layer regions including the at least one layer region with the adjusted portion of the plurality of pixels.

[0077] At 1050, the DPU 1002 may process a composite output of the set of layer regions after composite the set of layer regions, wherein the composite output of the set of layer regions results in the composite output of the set of layer regions. In some aspects, processing the composite output of the set of layer regions may include adjusting a pixel value of each of a plurality of pixels in the composite output of the set of layer regions. For example, the DPU may adjust a pixel value of each of a plurality of pixels in the composite output of the set of layer regions.

[0078] At 1060, the DPU 1002 may send the composited processed output of the set of layer regions (eg, the DPU 1002 may send output 1062 to the display 1006). The composited processed output of the set of layer regions may be sent to a display or panel.

[0079] Fig.11 1100 is a flowchart of an example method of display processing according to one or more techniques of the present disclosure. The method may be performed by a DPU (or other display processor), a GPU (or other graphics processor), a CPU (or other central processing unit), a DDIC, an apparatus for display processing, a wireless communication device, and / or an executable combination. Figures 1 to 10 The examples are performed using any device that displays the process.

[0080] At 1102, the DPU may obtain a plurality of layers associated with at least one frame, wherein each layer of the plurality of layers includes a set of layer regions, wherein each layer region of the set of layer regions includes a plurality of pixels, such as in combination with Figures 1 to 10 For example, Fig.10 As described in step 1010 of the embodiment, the DPU 1002 may obtain a plurality of layers associated with at least one frame, wherein each layer in the plurality of layers includes a set of layer regions, wherein each layer region in the set of layer regions includes a plurality of pixels. In addition, step 1102 may be performed by Figure 1, executed by the display processor 127 in the layer area set. In some aspects, obtaining multiple layers may include: receiving multiple layers from at least one of a graphics processing unit (GPU), a central processing unit (CPU), an application, or a game. For example, the DPU may receive multiple layers from at least one of a GPU, a CPU, an application, or a game. The set of layer regions in each of the multiple layers corresponds to a set of portions of each of the multiple layers or a set of regions of interest (ROIs) for each of the multiple layers. In addition, at least one frame may be associated with at least one of display processing, image processing, frame processing, or color processing. In some aspects, multiple pixels in each layer area in the layer area set are associated with metadata, a layer hierarchy, a Z order, or a Z coordinate. In addition, each layer area in the layer area set may include a corresponding pixel resolution, so that the corresponding pixel resolution of at least one first layer area in the layer area set is different from the corresponding pixel resolution of at least one second layer area in the layer area set.

[0081] At 1104, the DPU may assign each layer region in the set of layer regions to a corresponding component in the set of components in the display processing unit (DPU) pipeline, such as in conjunction with Figures 1 to 10 For example, Fig.10 As described in 1020 of the embodiment, DPU 1002 may assign each layer region in the set of layer regions to a corresponding component in the set of components in the display processing unit (DPU) pipeline. In addition, step 1104 may be performed by Figure 1 Executed by the display processor 127 in the layer area set. In some aspects, assigning each layer area in the layer area set to a corresponding component in the component set may include: mapping each layer area in the layer area set to a corresponding component in the component set, so that each layer area in the layer area set is assigned to the corresponding component based on the mapping. For example, the DPU may map each layer area in the layer area set to a corresponding component in the component set. Each layer area in the layer area set may be mapped to a corresponding component in the component set based on a corresponding processing task associated with each layer area in the layer area set. In addition, each layer area in the layer area set may be mapped to a corresponding component in the component set based on the position of each layer area in the layer area set or a coordinate set of each layer area in the layer area set.

[0082] At 1106, the DPU may adjust a portion of a plurality of pixels in at least one layer region in the set of layer regions using a corresponding component in the set of components in the DPU pipeline, such as in combination with Figures 1 to 10 For example, Fig.10As described in 1030 of the embodiment, the DPU 1002 may adjust a portion of the plurality of pixels in at least one layer region in the layer region set using a corresponding component in the component set in the DPU pipeline. In addition, step 1106 may be performed by Figure 1 The display processor 127 in the embodiment of the present invention is executed. A portion of the plurality of pixels in the at least one layer area can be adjusted based on processing the plurality of pixels in the at least one layer area. In addition, the plurality of pixels in the at least one layer area can be processed based on display processing, image processing, frame processing or color processing.

[0083] At 1108, the DPU may synthesize a layer region set including at least one layer region with the adjusted portion of the plurality of pixels, such as in combination with Figures 1 to 10 For example, Fig.10 As described in step 1040 of the embodiment, the DPU 1002 synthesizes a layer region set including at least one layer region with the adjusted portion of the plurality of pixels. In addition, step 1108 may be performed by Figure 1 The DPU may be executed by the display processor 127 in the DPU. In some aspects, compositing the set of layer regions including at least one layer region with the adjusted portion of the plurality of pixels may include blending the set of layer regions including at least one layer region with the adjusted portion of the plurality of pixels. For example, the DPU may blend at least some of the layer regions in the set of layer regions including at least one layer region with the adjusted portion of the plurality of pixels.

[0084] Fig.12 1200 is a flowchart of an example method of display processing according to one or more techniques of the present disclosure. The method may be performed by a DPU (or other display processor), a GPU (or other graphics processor), a CPU (or other central processing unit), a DDIC, an apparatus for display processing, a wireless communication device, and / or an executable combination. Figures 1 to 10 The examples are performed using any device that displays the process.

[0085] At 1202, the DPU may obtain a plurality of layers associated with at least one frame, wherein each layer of the plurality of layers includes a set of layer regions, wherein each layer region of the set of layer regions includes a plurality of pixels, such as in combination with Figures 1 to 10 For example, Fig.10 As described in 1010 of the embodiment, the DPU 1002 may obtain a plurality of layers associated with at least one frame, wherein each layer in the plurality of layers includes a layer region set, wherein each layer region in the layer region set includes a plurality of pixels. In addition, step 1202 may be performed by Figure 1, executed by the display processor 127 in the layer area set. In some aspects, obtaining multiple layers may include: receiving multiple layers from at least one of a graphics processing unit (GPU), a central processing unit (CPU), an application, or a game. For example, the DPU may receive multiple layers from at least one of a GPU, a CPU, an application, or a game. The set of layer regions in each of the multiple layers corresponds to a set of portions of each of the multiple layers or a set of regions of interest (ROIs) for each of the multiple layers. In addition, at least one frame may be associated with at least one of display processing, image processing, frame processing, or color processing. In some aspects, multiple pixels in each layer area in the layer area set are associated with metadata, a layer hierarchy, a Z order, or a Z coordinate. In addition, each layer area in the layer area set may include a corresponding pixel resolution, so that the corresponding pixel resolution of at least one first layer area in the layer area set is different from the corresponding pixel resolution of at least one second layer area in the layer area set.

[0086] At 1204, the DPU may assign each layer region in the set of layer regions to a corresponding component in the set of components in the display processing unit (DPU) pipeline, such as in conjunction with Figures 1 to 10 For example, Fig.10 As described in 1020 of the embodiment, DPU 1002 may assign each layer region in the set of layer regions to a corresponding component in the set of components in the display processing unit (DPU) pipeline. In addition, step 1204 may be performed by Figure 1 Executed by the display processor 127 in the layer area set. In some aspects, assigning each layer area in the layer area set to a corresponding component in the component set may include: mapping each layer area in the layer area set to a corresponding component in the component set, so that each layer area in the layer area set is assigned to the corresponding component based on the mapping. For example, the DPU may map each layer area in the layer area set to a corresponding component in the component set. Each layer area in the layer area set may be mapped to a corresponding component in the component set based on a corresponding processing task associated with each layer area in the layer area set. In addition, each layer area in the layer area set may be mapped to a corresponding component in the component set based on the position of each layer area in the layer area set or a coordinate set of each layer area in the layer area set.

[0087] At 1206, the DPU may adjust a portion of a plurality of pixels in at least one layer region in the set of layer regions using a corresponding component in the set of components in the DPU pipeline, such as in combination with Figures 1 to 10 For example, Fig.10As described in 1030 of the embodiment, the DPU 1002 may use corresponding components in the component set in the DPU pipeline to adjust a portion of the plurality of pixels in at least one layer region in the layer region set. In addition, step 1206 may be performed by Figure 1 The display processor 127 in the embodiment of the present invention is executed. A portion of the plurality of pixels in the at least one layer area can be adjusted based on processing the plurality of pixels in the at least one layer area. In addition, the plurality of pixels in the at least one layer area can be processed based on display processing, image processing, frame processing or color processing.

[0088] At 1208, the DPU may synthesize a layer region set including at least one layer region with the adjusted portion of the plurality of pixels, such as in combination with Figures 1 to 10 For example, Fig.10 As described in step 1040 of the embodiment, the DPU 1002 synthesizes a layer region set including at least one layer region with the adjusted portion of the plurality of pixels. In addition, step 1208 may be performed by Figure 1 The DPU may be executed by the display processor 127 in the DPU. In some aspects, compositing the set of layer regions including at least one layer region with the adjusted portion of the plurality of pixels may include blending the set of layer regions including at least one layer region with the adjusted portion of the plurality of pixels. For example, the DPU may blend at least some of the layer regions in the set of layer regions including at least one layer region with the adjusted portion of the plurality of pixels.

[0089] At 1210, the DPU may process the synthesized output of the layer region set after synthesizing the layer region set, wherein the synthesis of the layer region set results in the synthesized output of the layer region set, such as in combination with Figures 1 to 10 For example, Fig.10 As described in step 1050 of the embodiment, the DPU 1002 may process the synthesized output of the layer region set after synthesizing the layer region set, wherein the synthesis of the layer region set results in the synthesized output of the layer region set. In addition, step 1210 may be performed by Figure 1 The DPU may be executed by the display processor 127 in the process. In some aspects, processing the synthesized output of the set of layer regions may include: adjusting the pixel value of each of the plurality of pixels in the synthesized output of the set of layer regions. For example, the DPU may adjust the pixel value of each of the plurality of pixels in the synthesized output of the set of layer regions.

[0090] At 1212, the DPU may send a composite processed output of a set of layer regions, such as a combination of Figures 1 to 10 For example, Fig.10 As described in 1060 of the embodiment, the DPU 1002 may send the processed output of the synthesis of the layer region set. In addition, step 1212 may be performed by Figure 1The display processor 127 in the embodiment of the present invention is executed. The processed output of the synthesis of the set of layer regions can be sent to a display or panel.

[0091] In various configurations, a method or apparatus for display processing is provided. The apparatus may be a DPU (or other display processor), a GPU (or other graphics processor), a CPU (or other central processing unit), a DDIC, an apparatus for display processing, and / or some other processor that can perform display processing. In various aspects, the apparatus may be a display processor 127 within the device 104, or may be some other hardware within the device 104 or another device. The apparatus (e.g., the display processor 127) may include a component for obtaining a plurality of layers associated with at least one frame, wherein each of the plurality of layers includes a set of layer regions, wherein each layer region in the set of layer regions includes a plurality of pixels. The apparatus (e.g., the display processor 127) may also include a component for assigning each layer region in the set of layer regions to a corresponding component in a set of components in a display processing unit (DPU) pipeline. The apparatus (e.g., the display processor 127) may also include a component for adjusting a portion of a plurality of pixels in at least one layer region in the set of layer regions using a corresponding component in a set of components in a DPU pipeline. The apparatus (e.g., display processor 127) may also include means for compositing a layer region set including at least one layer region with the adjusted portion of the plurality of pixels. The apparatus (e.g., display processor 127) may also include means for processing a composite output of the layer region set after compositing the layer region set. The apparatus (e.g., display processor 127) may also include means for transmitting the composite processed output of the layer region set.

[0092] The subject matter described herein can be implemented to achieve one or more benefits or advantages. For example, the display processing techniques described can be used by a DPU, a display processor, a GPU, a CPU, or some other processor that can perform display processing to implement the ROI processing synthesis techniques described herein. Compared with other display processing techniques, this can also be implemented at a low cost. In addition, the display processing techniques herein can improve or accelerate data processing or execution. In addition, the display processing techniques herein can improve resource or data utilization and / or resource efficiency. Additionally, various aspects of the present disclosure can utilize ROI processing synthesis techniques to improve memory bandwidth efficiency and / or increase processing speed at a DPU or GPU.

[0093] It should be understood that the specific order or hierarchy of the blocks in the disclosed process / flowchart is merely an illustration of the exemplary method. It should be understood that the specific order or hierarchy of the blocks in the process / flowchart can be rearranged based on design preferences. In addition, some blocks can be combined or omitted. The attached method claims provide the elements of each block in a sample order, but are not meant to be limited to the specific order or hierarchy provided.

[0094] The foregoing description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects. Therefore, the claims are not intended to be limited to the various aspects shown herein, but should be given the full scope consistent with the language of the claims, wherein unless otherwise specified, reference to an element in the singular is not intended to mean "one and only one", but rather "one or more". The word "exemplary" is used herein to mean "used as an example, instance, or illustration". Any aspect described herein as "exemplary" is not necessarily to be interpreted as being preferred or having advantages over other aspects.

[0095] Unless specifically stated otherwise, the term “some” refers to one or more, and the term “or” may be interpreted as “and / or” if the context does not dictate otherwise. Combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” include any combination of A, B, and / or C, which may include multiple A, multiple B, or multiple C. Specifically, combinations such as “at least one of A, B, or C,” “one or more of A, B, or C,” “at least one of A, B, and C,” “one or more of A, B, and C,” and “A, B, C, or any combination thereof” may be only A, only B, only C, A and B, A and C, B and C, or A and B and C, where any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of various aspects described throughout this disclosure that are known or will later become known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be dedicated to the public, regardless of whether such disclosure is explicitly stated in the claims. Words such as "module," "mechanism," "element," and "device" cannot replace the word "component." Therefore, no claim element will be understood to be a part-plus-function unless the element is explicitly stated using the phrase "component for..."

[0096] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored or sent as one or more instructions or codes on a computer-readable medium.

[0097] According to the present disclosure, the term "or" may be understood as "and / or" in the absence of context dictating otherwise. Additionally, while phrases such as "one or more" or "at least one" may have been used for some features disclosed herein but not for other features, features not using such language may be understood to have such implicit meanings in the absence of context dictating otherwise.

[0098] In one or more examples, the functions described herein may be implemented in hardware, software, firmware, or any combination thereof. For example, although the term "processing unit" is used throughout this disclosure, such processing unit may be implemented in hardware, software, firmware, or any combination thereof. If any function, processing unit, technique, or other module described herein is implemented in software, the function, processing unit, technique, or other module described herein may be stored on a computer-readable medium or sent on a computer-readable medium as one or more instructions or codes. Computer-readable media may include computer data storage media and communication media, including any media that facilitates the transfer of computer programs from one place to another. In this way, computer-readable media may generally correspond to (1) a non-transient tangible computer-readable storage medium or (2) a communication medium such as a signal or carrier wave. Data storage media may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in this disclosure. As an example and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM, or other optical disk storage devices, magnetic disk storage devices, or other magnetic storage devices. Disk and disc as used herein include compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc, where disks usually reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media. A computer program product may include a computer-readable medium.

[0099] The code may be executed by one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), arithmetic logic units (ALUs), field programmable logic arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Therefore, the term "processor" as used herein may refer to any of the above structures or any other structure suitable for implementing the techniques described herein. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0100] The technology of the present disclosure can be implemented in a variety of devices or apparatuses, including wireless mobile phones, integrated circuits (ICs) or IC groups (e.g., chipsets). Various components, modules, or units are described in the present disclosure to emphasize the functional aspects of devices configured to perform the disclosed technology, but they do not necessarily need to be implemented by different hardware units. On the contrary, as described above, the various units can be combined in any hardware unit, or provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware. Therefore, the term "processor" as used herein can refer to any of the above structures or any other structure suitable for implementing the technology described herein. Similarly, these technologies can be fully implemented in one or more circuits or logic elements.

[0101] The following aspects are merely illustrative and may be combined with other aspects or teachings described herein without limitation.

[0102] Aspect 1 is a device for display processing, the device comprising a memory and at least one processor coupled to the memory, and at least partially based on information stored in the memory, the at least one processor is configured to: obtain multiple layers associated with at least one frame, wherein each layer of the multiple layers comprises a layer region set, wherein each layer region in the layer region set comprises a plurality of pixels; assign each layer region in the layer region set to a corresponding component in a component set in a display processing unit (DPU) pipeline; adjust a portion of the plurality of pixels in at least one layer region in the layer region set using the corresponding component in the component set in the DPU pipeline; and synthesize the layer region set including the at least one layer region with the adjusted portion of the plurality of pixels.

[0103] Aspect 2 is an apparatus according to Aspect 1, wherein in order to assign each layer area in the layer area set to the corresponding component in the component set, the at least one processor is configured to: map each layer area in the layer area set to the corresponding component in the component set, so that each layer area in the layer area set is assigned to the corresponding component based on the mapping.

[0104] Aspect 3 is an apparatus according to aspect 2, wherein each layer region in the set of layer regions is mapped to the corresponding component in the set of components based on a corresponding processing task associated with each layer region in the set of layer regions.

[0105] Aspect 4 is an apparatus according to Aspect 2, wherein each layer region in the layer region set is mapped to the corresponding component in the component set based on the position of each layer region in the layer region set or the coordinate set of each layer region in the layer region set.

[0106] Aspect 5 is an apparatus according to any one of Aspects 1 to 4, wherein the synthesis of the set of layer regions results in the synthesized output of the set of layer regions, and wherein the at least one processor is further configured to: process the synthesized output of the set of layer regions after synthesizing the set of layer regions.

[0107] Aspect 6 is an apparatus according to Aspect 5, wherein in order to process the synthesized output of the set of layer regions, the at least one processor is configured to: adjust the pixel value of each of the multiple pixels in the synthesized output of the set of layer regions.

[0108] Aspect 7 is the apparatus according to aspect 5, wherein the at least one processor is further configured to: transmit the synthesized processed output of the set of layer regions.

[0109] Clause 8 is the apparatus of clause 7, wherein the synthesized processed output of the set of layer regions is sent to a display or panel.

[0110] Aspect 9 is a device according to any one of Aspects 1 to 8, wherein in order to synthesize the set of layer regions including the at least one layer region with the adjusted portion of the multiple pixels, the at least one processor is configured to: blend at least some of the layer regions in the set of layer regions including the at least one layer region with the adjusted portion of the multiple pixels.

[0111] Clause 10 is an apparatus according to any one of clauses 1 to 9, wherein the portion of the plurality of pixels in the at least one layer region is adjusted based on processing the plurality of pixels in the at least one layer region.

[0112] Clause 11 is the apparatus according to clause 10, wherein the plurality of pixels in the at least one layer region are processed based on the display processing, image processing, frame processing, or color processing.

[0113] Aspect 12 is a device according to any one of Aspects 1 to 11, wherein the set of layer regions in each of the multiple layers corresponds to a set of portions of each of the multiple layers or a set of regions of interest (ROIs) for each of the multiple layers.

[0114] Clause 13 is an apparatus according to any one of clauses 1 to 12, wherein the plurality of pixels in each layer region in the set of layer regions is associated with metadata, a layer hierarchy, a Z order, or a Z coordinate.

[0115] Aspect 14 is an apparatus according to any one of Aspects 1 to 13, wherein each layer region in the layer region set includes a corresponding pixel resolution, so that the corresponding pixel resolution of at least one first layer region in the layer region set is different from the corresponding pixel resolution of at least one second layer region in the layer region set.

[0116] Aspect 15 is a device according to any one of Aspects 1 to 14, wherein in order to obtain the multiple layers, the at least one processor is configured to: receive the multiple layers from at least one of a graphics processing unit (GPU), a central processing unit (CPU), an application or a game.

[0117] Aspect 16 is an apparatus according to any one of aspects 1 to 15, wherein the at least one frame is associated with at least one of the display processing, image processing, frame processing, or color processing.

[0118] Aspect 17 is an apparatus according to any one of Aspects 1 to 16, wherein the apparatus is a wireless communication device, and the apparatus further includes at least one of an antenna or a transceiver coupled to the at least one processor, wherein the at least one processor is configured to obtain the multiple layers via at least one of the antenna or the transceiver.

[0119] Aspect 18 is a method for implementing the display processing of any one of aspects 1 to 17.

[0120] Aspect 19 is an apparatus for display processing, the apparatus comprising means for implementing any one of aspects 1 to 17.

[0121] Aspect 20 is a computer-readable medium (eg, non-transitory computer-readable medium) storing computer-executable code, which, when executed by at least one processor, causes the at least one processor to implement any one of aspects 1 to 17.

Claims

1. A device for display processing, the device comprising: Memory; as well as at least one processor coupled to the memory and based at least in part on the information stored in the memory, the at least one processor configured to: obtaining a plurality of layers associated with at least one frame, wherein each layer of the plurality of layers comprises a set of layer regions, wherein each layer region of the set of layer regions comprises a plurality of pixels; assigning each layer region in the set of layer regions to a corresponding component in a set of components in a display processing unit (DPU) pipeline; adjusting a portion of the plurality of pixels in at least one layer region in the set of layer regions using the corresponding component in the set of components in the DPU pipeline; as well as The set of layer regions including the at least one layer region is composited with the adjusted portion of the plurality of pixels.

2. The apparatus according to claim 1, wherein in order to assign each layer region in the set of layer regions to the corresponding component in the set of components, the at least one processor is configured to: Each layer region in the set of layer regions is mapped to the corresponding component in the set of components, so that each layer region in the set of layer regions is assigned to the corresponding component based on the mapping. 3 . The apparatus of claim 2 , wherein each layer region in the set of layer regions is mapped to the corresponding component in the set of components based on a corresponding processing task associated with each layer region in the set of layer regions. 4 . The apparatus according to claim 2 , wherein each layer region in the layer region set is mapped to the corresponding component in the component set based on a position of each layer region in the layer region set or a coordinate set of each layer region in the layer region set.

5. The apparatus of claim 1 , wherein the synthesis of the set of layer regions results in an output of the synthesis of the set of layer regions, and wherein the at least one processor is further configured to: The output of the synthesis of the set of layer regions is processed after synthesizing the set of layer regions.

6. The apparatus of claim 5, wherein to process the synthesized output of the set of layer regions, the at least one processor is configured to: A pixel value of each of the plurality of pixels in the composited output of the set of layer regions is adjusted.

7. The apparatus of claim 5, wherein the at least one processor is further configured to: The composited processed output of the set of layer regions is transmitted.

8. The apparatus of claim 7, wherein the composited processed output of the set of layer regions is sent to a display or panel.

9. The apparatus of claim 1 , wherein to composite the set of layer regions including the at least one layer region with the adjusted portion of the plurality of pixels, the at least one processor is configured to: At least some of the set of layer regions including the at least one layer region are blended with the adjusted portion of the plurality of pixels.

10. The apparatus of claim 1, wherein the portion of the plurality of pixels in the at least one layer region is adjusted based on processing the plurality of pixels in the at least one layer region. 11 . The apparatus of claim 10 , wherein the plurality of pixels in the at least one layer region are processed based on the display processing, the image processing, the frame processing, or the color processing. 12 . The apparatus according to claim 1 , wherein the set of layer regions in each of the plurality of layers corresponds to a set of portions of each of the plurality of layers or a set of regions of interest (ROIs) of each of the plurality of layers.

13. The apparatus of claim 1, wherein the plurality of pixels in each layer region in the set of layer regions is associated with metadata, a layer hierarchy, a Z-order, or a Z-coordinate.

14. The device according to claim 1, wherein each layer region in the layer region set comprises a corresponding pixel resolution, so that the corresponding pixel resolution of at least one first layer region in the layer region set is different from the corresponding pixel resolution of at least one second layer region in the layer region set.

15. The apparatus of claim 1, wherein to obtain the plurality of layers, the at least one processor is configured to receive the plurality of layers from at least one of a graphics processing unit (GPU), a central processing unit (CPU), an application, or a game.

16. The apparatus of claim 1, further comprising at least one of an antenna or a transceiver coupled to the at least one processor, wherein the at least one processor is configured to obtain the plurality of layers via the antenna or at least one of the transceivers, and wherein the at least one frame is associated with at least one of the display processing, the image processing, the frame processing, or the color processing.

17. A method of display processing, the method comprising: obtaining a plurality of layers associated with at least one frame, wherein each layer of the plurality of layers comprises a set of layer regions, wherein each layer region of the set of layer regions comprises a plurality of pixels; assigning each layer region in the set of layer regions to a corresponding component in a set of components in a display processing unit (DPU) pipeline; adjusting a portion of the plurality of pixels in at least one layer region in the set of layer regions using the corresponding component in the set of components in the DPU pipeline; as well as The set of layer regions including the at least one layer region is composited with the adjusted portion of the plurality of pixels.

18. The method of claim 17, wherein assigning each layer region in the set of layer regions to the corresponding component in the set of components comprises: Each layer region in the set of layer regions is mapped to the corresponding component in the set of components, so that each layer region in the set of layer regions is assigned to the corresponding component based on the mapping.

19. The method of claim 18, wherein each layer region in the set of layer regions is mapped to the corresponding component in the set of components based on a corresponding processing task associated with each layer region in the set of layer regions.

20. The method of claim 18, wherein each layer region in the set of layer regions is mapped to the corresponding component in the set of components based on a position of each layer region in the set of layer regions or a coordinate set of each layer region in the set of layer regions.

21. The method of claim 17, wherein the synthesis of the set of layer regions results in an output of the synthesis of the set of layer regions, the method further comprising: The output of the synthesis of the set of layer regions is processed after synthesizing the set of layer regions.

22. The method of claim 21 , wherein processing the synthesized output of the set of layer regions comprises: A pixel value of each of the plurality of pixels in the composited output of the set of layer regions is adjusted.

23. The method according to claim 21, further comprising: The composited processed output of the set of layer regions is sent, wherein the composited processed output of the set of layer regions is sent to a display or panel.

24. The method of claim 17, wherein compositing the set of layer regions including the at least one layer region with the adjusted portion of the plurality of pixels comprises: At least some of the set of layer regions including the at least one layer region are blended with the adjusted portion of the plurality of pixels.

25. The method according to claim 17, wherein the portion of the multiple pixels in the at least one layer area is adjusted based on processing of the multiple pixels in the at least one layer area, wherein the multiple pixels in the at least one layer area are processed based on the display processing, image processing, frame processing or color processing.

26. A method according to claim 17, wherein the set of layer regions in each of the multiple layers corresponds to a set of portions of each of the multiple layers or a set of regions of interest (ROIs) for each of the multiple layers, and wherein the multiple pixels in each layer region in the set of layer regions are associated with metadata, a layer hierarchy, a Z order, or a Z coordinate.

27. A method according to claim 17, wherein each layer region in the layer region set includes a corresponding pixel resolution, so that the corresponding pixel resolution of at least one first layer region in the layer region set is different from the corresponding pixel resolution of at least one second layer region in the layer region set.

28. The method of claim 17, wherein obtaining the plurality of layers comprises: The plurality of layers are received from at least one of a graphics processing unit (GPU), a central processing unit (CPU), an application, or a game.

29. The method of claim 17, wherein the at least one frame is associated with at least one of the display processing, image processing, frame processing, or color processing.

30. A computer readable medium storing computer executable code for display processing, the code when executed by a processor causing the processor to: obtaining a plurality of layers associated with at least one frame, wherein each layer of the plurality of layers comprises a set of layer regions, wherein each layer region of the set of layer regions comprises a plurality of pixels; assigning each layer region in the set of layer regions to a corresponding component in a set of components in a display processing unit (DPU) pipeline; adjusting a portion of the plurality of pixels in at least one layer region in the set of layer regions using the corresponding component in the set of components in the DPU pipeline; as well as The set of layer regions including the at least one layer region is composited with the adjusted portion of the plurality of pixels.

Images