Device and method for controlling void fraction of large-area thermal interface connection of power electronic devices

Abstract

The present invention provides a device and method for controlling the void ratio of a large-area thermal interface connection of a power electronic device. In the device part, by optimizing the design of the grid structure shape of the stencil printing module, it is ensured that the organic solvents and water vapor in the solder paste layer can be discharged smoothly, thereby effectively reducing the void ratio during the welding process; in the method part, through the optimization of the reflow soldering process, including the temperature control and vacuum degree optimization in each stage such as the heating process, heat preservation process, pre-reflow and reflow processes, the gas escape time is appropriately extended, so that the void ratio is controlled below 1%, the interface thermal resistance is reduced, and the heat dissipation performance is improved. The present invention simplifies the production process through optimized design and process, is more convenient to operate and has low cost, and is suitable for large-scale production; at the same time, since the void ratio is effectively controlled, the product quality consistency in the production process is guaranteed, and the heat dissipation efficiency and service life of the power electronic device are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of high-power electronic device packaging, and particularly to a device and method for controlling the void ratio of a large-area thermal interface connection of a power electronic device. Background Art

[0002] The third-generation semiconductor materials (such as gallium nitride and silicon carbide) have promoted the development of power electronic devices due to their superior properties such as high bandgap width, high breakdown electric field, high saturated electron velocity, and high thermal conductivity. These materials enable power electronic devices to achieve higher operating frequencies and power densities. The power density of traditional silicon-based power devices is usually in the range of dozens of watts to hundreds of watts per cubic centimeter (W / cm³), while the power density of third-generation semiconductor devices can exceed 1000 W / cm³, and even reach 2000 W / cm³ or higher. However, the high power density causes power electronic devices to generate more heat during operation, so an efficient and stable heat dissipation packaging technology is required to ensure the reliability and lifespan of power electronic devices. The main function of the thermal interface material is to fill the gap between the power module and the heat sink, reduce the contact thermal resistance of the heat transfer interface, enable the heat generated by the power electronic device to be transferred to the heat sink more quickly through the thermal interface material, and thus improve the heat dissipation performance of the power electronic device.

[0003] Currently, widely used thermal interface materials include thermal grease, thermal gel, phase change materials, etc., but the thermal conductivities of these materials are generally lower than 10 W / (m·K), making it difficult to meet the heat dissipation requirements of high-power electronic devices. Lead-free solder-based thermal interface materials have gradually attracted attention and become the key to solving the heat dissipation problem due to their high thermal conductivity, low thermal resistance, and excellent reliability. Currently, common lead-free solders on the market include Sn-3.0Ag-0.5Cu (58 W / (m·K)), Sn-5Sb (28 W / (m·K)), In (80 W / (m·K)), Sn-58Bi (20 W / (m·K)), etc. In addition, Chinese Patent CN115662966A discloses a solder-based thermal interface material that can be used for efficient heat dissipation of power electronic devices. It adjusts the thermal conductivity (60 - 250 W / (m·K)) through a multi-layer composite structure, can achieve "low-temperature connection and high-temperature service", and can achieve efficient and stable heat dissipation of power devices.

[0004] Although the application of lead-free solder thermal interface materials has received attention, the gas generated by the volatilization of organic solvents in the solder paste cannot escape effectively during the reflow process, resulting in voids in the thermal interface connection. The increase in void rate not only affects the mechanical strength and fatigue life of the thermal interface structure, but also increases the junction temperature and thermal resistance of the device, reducing its heat dissipation performance. As the thermal interface interconnection area of power electronic devices continues to increase (for example, the ON Semiconductor VE-Trac double-sided cooling power module, whose thermal interface interconnection area exceeds 48mm×42mm), the control of void rate becomes increasingly difficult. The increase in junction temperature of power electronic devices will significantly increase their failure probability. For every 10°C temperature rise, the failure probability can be doubled. Therefore, controlling the void rate is crucial for lead-free solder thermal interface materials to play the advantage of efficient heat dissipation when interconnecting over a large area.

[0005] Regarding welding void rate control, there are some solutions in the existing technology:

[0006] For example, Chinese patent CN217336087U discloses a large pad solder void structure for a power device, and proposes to control the void rate through a spider web pad design. However, this design increases the complexity and manufacturing cost of the pad, and is not suitable for controlling large-area thermal interface interconnections.

[0007] For another example, Chinese patent CN118951211A discloses a device for reducing solder voids in power modules and its use method, which uses a solder paste printing net with a mesh structure composed of multiple triangular structures to solve problems such as uneven coating thickness of the solder paste layer and high voids. The amount of solder paste layer is reduced by a reserved microchannel, and the thickness of the solder paste layer is thinned at the thicker position by using the collapse effect after reflow to improve the uniformity of the thickness of the solder paste layer. However, this solution has high requirements on the processing accuracy of the steel mesh in actual application and may increase the manufacturing complexity.

[0008] For another example, Chinese patent CN114260530A discloses a welding process for large-area ceramic copper-clad laminates based on IGBT modules, which reduces the void rate by nitrogen filling and vacuum treatment. However, the process is relatively complicated, which limits its application in large-scale production.

[0009] In summary, although the existing technology has reduced the void rate to a certain extent, it still faces the problems of complex manufacturing process, high cost and limited scope of application. Especially in power electronic devices with large-area thermal interface interconnection, the existing solutions are often difficult to meet actual needs. Therefore, it is necessary to provide a device and method for controlling the void rate of large-area thermal interface connection of power electronic devices to solve the above problems. Summary of the invention

[0010] According to the above-mentioned technical problems, a device and method for controlling the void ratio of large-area thermal interface connection of power electronic devices are provided. The present invention mainly uses a specifically designed large-area stencil printing module for lead-free solder paste, and by the shape of the grid structure and optimizing the reflow process, the void ratio of large-area thermal interface connection is greatly reduced, and the void ratio is controlled below 1%.

[0011] The technical means adopted by the present invention are as follows:

[0012] A device for controlling the void ratio of large-area thermal interface connection of power electronic devices, the device includes:

[0013] A stencil printing module, which is used to print the solder paste onto the thermal interface area to be welded on the substrate during the printing process of the large-area thermal interface lead-free solder paste;

[0014] The stencil printing module includes a plurality of grid structures arranged in a matrix with preset sizes. The grid structures are used to divide the printing area of the lead-free solder paste into multiple units, and gas discharge channels for increasing the lead-free solder paste are formed between the units. The size of the grid structure is determined by the interconnect area of the large-area thermal interface lead-free solder paste.

[0015] Further, the grid structure divides the printing area of the lead-free solder paste into multiple uniform units, and the grid structure is square.

[0016] Further, the interconnect area of the large-area thermal interface lead-free solder paste is greater than 20mm×20mm: when the interconnect area is between 20mm×20mm and 40mm×40mm, the length L1 = width W1 = 8 - 10mm of the grid structure, and the gap S1 between the units = 1 - 2mm; when the interconnect area is greater than 40mm×40mm, the length L1 = width W1 = 5 - 10mm of the grid structure, and the gap S1 between the units = 0.5 - 1mm.

[0017] The present invention also provides a method for controlling the void ratio of large-area thermal interface connection of power electronic devices, including the following steps:

[0018] Step 1: Use the above device to print the lead-free solder paste on the thermal interface interconnect area of the upper substrate or the lower substrate to be welded through the stencil printing module;

[0019] Step 2: Install the upper substrate - lead-free solder paste layer - lower substrate interconnect structure obtained in Step 1 into a reflow soldering device, and perform reflow according to the set reflow process curve to complete reflow soldering.

[0020] Further, the upper substrate is one of power electronic devices including a metal-oxide semiconductor field effect transistor power module, an insulated gate bipolar transistor power module, and a silicon carbide power module; the lower substrate is one of aluminum, copper, and copper alloy, which are radiator materials for power electronic devices; the lead-free solder paste layer is a single-layer lead-free solder paste structure or a composite structure including multiple layers of lead-free solder paste.

[0021] Further, the reflow soldering includes the following steps:

[0022] S1. Heating process: Heating the temperature of the reflow furnace from room temperature to the preheating temperature T1 at a certain heating rate.

[0023] S2. Heat preservation process: Heating the temperature of the reflow furnace from T1 to the preheating temperature T2 and then keeping it for heat-up.

[0024] S3. Pre-reflow process: Heating the temperature of the reflow furnace from T2 to the melting point T of the low-temperature solder paste m , and keeping it for heat-up for pre-reflow.

[0025] S4. Reflow process: Heating the temperature of the inner cavity of the reflow furnace from the melting point T of the low-temperature solder paste m to the reflow peak temperature T3 for reflow.

[0026] S5. Cooling process: Cooling the temperature of the inner cavity of the reflow furnace to below the melting point of the solder paste until the cooling is completed.

[0027] Further, in the step S1, the heating rate is 30 - 90 °C / min, and the heating zone time is 50 - 200 s; in the step S2, the heat preservation heating rate is 0.1 - 5 °C / min, and the heat preservation zone time is 200 - 400 s; in the step S3, the heat preservation heating rate is 50 - 90 °C / min, and the pre-reflow zone time is 5 - 50 s; in the step S4, the reflow zone time is 100 - 300 s; in the step S5, the temperature of the inner cavity of the reflow furnace is cooled to 30 - 50 °C below the melting point of the solder paste, and the cooling zone time is 100 - 500 s.

[0028] Further, the target thickness of the lead-free solder paste layer after reflow is 0.01 - 0.2 mm.

[0029] Further, in the step S4, there is also a vacuum pumping process. The vacuum pumping method is to pump vacuum in the reflow zone for 100 - 200 s, and the vacuum degree is 5 - 20 mbar; or a step-by-step vacuum pumping is adopted: first pump the vacuum of the inner cavity of the reflow furnace to a vacuum degree of 50 mbar, keep it for 50 - 100 s, and then pump the cavity vacuum degree to 5 - 20 mbar and keep it for 10 - 50 s.

[0030] Furthermore, the stencil printing module controls the uniform distribution and effective exhaust of lead-free solder paste during the reflow process by adjusting the size of the grid structure and the gap between cells, so that the void rate of the large-area thermal interface connection of power electronic devices can be controlled below 1%.

[0031] Compared with the prior art, the present invention has the following advantages:

[0032] By changing the shape design of the grid structure and optimizing the reflow curve, the present invention increases the exhaust channels for the volatilization of organic solvents in the lead-free solder paste during the reflow process, appropriately extends the gas escape time, and utilizes the vacuum atmosphere to assist in the discharge of volatilized gases, significantly improving the gas discharge effect during the reflow of the lead-free solder paste for the large-area thermal interface, and successfully controlling the void rate below 1%.

[0033] Due to the reduction of the void rate, the thermal resistance of the thermal interface structure is reduced, and the heat dissipation performance of the power electronic device is significantly improved, which directly enhances the working stability of the device and extends its service life. With the improvement of the welding quality, heat can be conducted more efficiently from the power device to the radiator, improving the overall heat dissipation efficiency and ensuring the stable operation of the device under high power density.

[0034] In addition, the technical solution adopted by the present invention is easy to operate and has low cost, and is suitable for large-scale production. The shape design of the stencil printing module and the optimization of the reflow process can be improved on the basis of existing equipment, avoiding the need for high-precision equipment and complex processes, simplifying the entire production process and not increasing additional production costs.

[0035] In summary, the present invention effectively controls the void rate in the large-area thermal interface connection, reduces the interface thermal resistance, improves the heat dissipation performance of the power electronic device, simplifies the production process, and reduces the production cost. It has strong industrial application value, is suitable for large-scale production, and can significantly improve the performance and reliability of power electronic devices.

[0036] Based on the above reasons, the present invention can be widely promoted in the field of high-power electronic device packaging technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0038] Figure 1 It is a schematic diagram of the shape of the stencil printing module in the present invention.

[0039] Figure 2 Schematic diagram of the reflow curve used in the present invention.

[0040] Figure 3 Reflow curve measured in real time in Example 1 of the present invention.

[0041] Figure 4 X-ray void rate detection diagram of the interface connection structure with high-efficiency heat dissipation over a large area obtained in Example 1 of the present invention.

[0042] Figure 5 X-ray void rate detection diagram of the interface connection structure with high-efficiency heat dissipation over a large area obtained in Example 2 of the present invention.

[0043] Figure 6 Reflow curve measured in real time in Example 3 of the present invention.

[0044] Figure 7 X-ray void rate detection diagram of the interface connection structure with high-efficiency heat dissipation over a large area obtained in Example 3 of the present invention.

[0045] Figure 8 Schematic diagram of the shape of the stencil printing module in Comparative Example 1 of the present invention.

[0046] Figure 9 X-ray void rate detection diagram of the interface connection structure with high-efficiency heat dissipation over a large area obtained in Comparative Example 1 of the present invention.

[0047] Figure 10 Schematic diagram of the shape of the stencil printing module in Comparative Example 2 of the present invention.

[0048] Figure 11 X-ray void rate detection diagram of the interface connection structure with high-efficiency heat dissipation over a large area obtained in Comparative Example 2 of the present invention.

[0049] Figure 12 Schematic diagram of the shape of the stencil printing module in Comparative Example 3 of the present invention.

[0050] Figure 13 X-ray void rate detection diagram of the interface connection structure with high-efficiency heat dissipation over a large area obtained in Comparative Example 3 of the present invention.

[0051] Figure 14 Reflow curve measured in real time in Comparative Example 4 of the present invention.

[0052] Figure 15 X-ray void rate detection diagram of the interface connection structure with high-efficiency heat dissipation over a large area obtained in Comparative Example 4 of the present invention.

[0053] Figure 16X-ray void ratio detection diagram of the large-area and high-efficiency heat dissipation interface connection structure obtained in Comparative Example 5 of the present invention. Detailed implementation manners

[0054] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0055] The present invention provides a method for controlling the void ratio of the large-area thermal interface connection of power electronic devices, specifically including the following steps:

[0056] Step 1: Shape design of the stencil printing module for the large-area thermal interface lead-free solder paste:

[0057] Print the lead-free solder paste at the positions to be soldered for the thermal interface interconnection on the upper substrate or the lower substrate, and divide the printing area of the lead-free solder paste into multiple uniform units by using the grid structure of the stencil printing module (the grid structure is preferably a square) to increase the gas discharge channels of the lead-free solder paste. The size of the grid structure is determined by the interconnection area of the lead-free solder paste for the thermal interface;

[0058] The area of the large-area thermal interface lead-free solder paste is greater than 20 mm × 20 mm.

[0059] The upper substrate is one of power electronic devices including a metal-oxide semiconductor field effect transistor power module, an insulated gate bipolar transistor power module, and a silicon carbide power module; the lower substrate is one of aluminum, copper, and copper alloy, which are radiator materials for power electronic devices.

[0060] Among them, the individual size of the grid structure is determined by the interconnection area of the lead-free solder for the thermal interface (as Figure 1 shown), specifically:

[0061] When the interconnection area is between 20 mm × 20 mm and 40 mm × 40 mm, the length L1 = width W1 of the grid structure = 8 - 10 mm, and the gap S1 between units = 1 - 2 mm;

[0062] When the interconnection area is greater than 40 mm × 40 mm, the length L1 = width W1 of the grid structure = 5 - 10 mm, and the gap S1 between units = 0.5 - 1 mm.

[0063] Step 2: Optimization of the reflow process of the large-area thermal interface lead-free solder paste:

[0064] Load the upper substrate - lead - free solder paste layer - lower substrate interconnect structure obtained in Step 1 into a reflow soldering device, and perform reflow according to the set reflow process curve to complete reflow soldering. Among them, the lead - free solder paste layer is a single - layer lead - free solder paste structure or a composite structure including multiple layers of lead - free solder paste.

[0065] Specifically, it includes the following process (as Figure 2 shown):

[0066] S1. Heating process: Heat the temperature inside the reflow furnace cavity from room temperature to the pre - heating temperature T1. The heating rate during the process of heating to T1 is 30 - 90 °C / min, and the time in the heating zone is 50 - 200 s;

[0067] S2. Insulation process: Heat the temperature inside the reflow furnace cavity from T1 to the pre - heating temperature T2. The heating rate during the insulation process after this is 0.1 - 5 °C / min, and the time in the insulation zone is 200 - 400 s;

[0068] S3. Pre - reflow process: Heat the temperature inside the reflow furnace cavity from T2 to the melting point T m of the selected low - temperature solder paste. The heating rate during the insulation process after this is 50 - 90 °C / min, and the time in the pre - reflow zone is 5 - 50 s;

[0069] S4. Reflow process: Heat the temperature inside the reflow furnace cavity from the melting point T m of the low - temperature solder paste to the reflow peak temperature T3. The time in the reflow zone is 100 - 300 s;

[0070] Vacuum pumping process: The vacuum pumping method is to pump vacuum in the reflow zone for 100 - 200 s, and the vacuum degree is 5 - 20 mbar; or adopt step - by - step vacuum pumping: First, pump the cavity to a vacuum degree of 50 mbar and maintain it for 50 - 100 s, then pump the cavity vacuum degree to 5 - 20 mbar and maintain it for 10 - 50 s.

[0071] S5. Cooling process: Cool the temperature inside the reflow furnace cavity to 30 - 50 °C lower than the melting point of the low - temperature solder paste. The time in the cooling zone is 100 - 500 s;

[0072] According to the above steps, the void ratio of the large - area thermal interface connection of the power electronic device can be controlled below 1%.

[0073] Example 1:

[0074] A method for controlling the void ratio of the large - area thermal interface connection of a power electronic device according to the present invention can be realized through the following steps:

[0075] Step 1: Select pure Cu as the upper substrate and pure Cu (heat sink) as the lower substrate, and select the Sn-58Bi single-layer lead-free solder paste structure as the thermal interface material. The welding areas of the upper and lower substrates are both 55 mm × 55 mm. The length L1 and width W1 of the grid structure are 5 mm, the gap S1 between units is 1 mm, and the target thickness of the Sn-58Bi single-layer lead-free solder paste structure after reflow is 0.15 mm. Print the lead-free solder paste on the lower substrate according to the selected grid structure;

[0076] Step 2: Load the upper substrate - Sn-58Bi single-layer lead-free solder paste structure - lower substrate interconnection structure obtained in Step 1 into the reflow soldering device, and perform reflow according to the set reflow process curve. The selected reflow parameters are: the heating zone time is 110 s, the holding zone time is 300 s, the pre-reflow zone time is 20 s, the reflow zone time is 200 s, the cooling zone time is 300 s, the reflow zone is evacuated for 100 s, and the vacuum degree is 20 mbar. The measured reflow curve is as Figure 3 shown.

[0077] X-ray technology utilizes its penetration ability to generate a two-dimensional image of the internal structure of a material by detecting the absorption and scattering characteristics of X-rays inside the material. Since the density differences inside the material will cause different absorption rates of X-rays, high-density regions (such as metals) appear darker or black in the image, while low-density regions (such as voids) appear brighter or white. Process the X-ray image through the open-source ImageJ image processing software to identify and calculate the area of the void region and the total area of the entire thermal interface interconnection region, and the ratio is the void ratio. Based on the above principle, the void ratio of the large-area thermal interface connection structure is detected by X-ray, and the result is as Figure 4 shown. Only a small number of white voids appear in the thermal interface interconnection region within the blue dashed box, and the calculated void ratio in this embodiment is less than 1%.

[0078] Example 2:

[0079] The control method for the void ratio of the large-area thermal interface connection of a power electronic device in the present invention can be realized through the following steps:

[0080] Step 1: Select pure Cu as the upper substrate and pure Cu (heat sink) as the lower substrate, and select the Sn-58Bi single-layer lead-free solder paste structure as the thermal interface material. The welding areas of the upper and lower substrates are both 45 mm × 50 mm. The length L1 and width W1 of the grid structure are 5 mm, the gap S1 between units is 1 mm, and the target thickness of the Sn-58Bi single-layer lead-free solder paste structure after reflow is 0.15 mm. Print the lead-free solder paste on the lower substrate according to the selected grid structure;

[0081] Step 2: Load the upper substrate - Sn - 58Bi single - layer lead - free solder paste structure - lower substrate interconnection structure obtained in Step 1 into a reflow soldering device, and perform reflow according to the set reflow process curve. The selected reflow parameters are: the heating zone time is 110 s, the holding zone time is 300 s, the pre - reflow zone time is 20 s, the reflow zone time is 200 s, the cooling zone time is 300 s, the reflow zone is evacuated for 150 s, and the vacuum degree is 20 mbar.

[0082] Use X - ray to detect the void ratio of the large - area thermal interface connection structure obtained in the above steps. The results are as Figure 5 shown. Only a small amount of white voids appear in the thermal interface interconnection area within the blue dashed box. In this embodiment, the calculated void ratio is less than 1%.

[0083] Example 3:

[0084] A method for controlling the void ratio of a large - area thermal interface connection of a power electronic device according to the present invention can be realized through the following steps:

[0085] Step 1: Select a silicon carbide power module with a pure Cu welding surface as the upper substrate, and a pure Al (heat sink) with a Sn - plated welding surface as the lower substrate. Select the interface structure with high - efficiency heat dissipation proposed in Chinese Patent CN115662966A as the thermal interface material, that is, the lead - free solder paste layer is selected in the form of a composite structure including two layers of lead - free solder paste. Among them, Sn - 58Bi solder paste is selected as the low - temperature solder paste layer. That is, the composite structure of the two layers of lead - free solder paste is Sn - 58Bi low - temperature solder paste layer - metal foam composite material - Sn - 58Bi low - temperature solder paste layer. The welding areas of the upper substrate and the lower substrate are both 30 mm×45 mm. The length L1 and width W1 of the grid structure are 6 mm, the gap S1 between units is 1 mm, and the target thickness of the Sn - 58Bi low - temperature solder paste layer selected in the composite structure of the two layers of lead - free solder paste after reflow is 0.01 mm. Print the lead - free solder paste on the upper substrate and the lower substrate according to the selected grid structure;

[0086] Step 2: Load the upper substrate - composite structure of two layers of lead - free solder paste - lower substrate interconnection structure obtained in Step 1 into a reflow soldering device, and perform reflow according to the set reflow process curve. The selected reflow parameters are: the heating zone time is 90 s, the holding zone time is 230 s, the pre - reflow zone time is 20 s, the reflow zone time is 160 s, the cooling zone time is 300 s, the reflow zone is evacuated for 60 s, and the vacuum degree is 20 mbar. The measured reflow curve is as Figure 6 shown.

[0087] Use X - ray to detect the void ratio of the large - area thermal interface connection structure obtained in the above steps. The results are as Figure 7As shown, no white voids were found in the thermal interface interconnect area within the blue dashed box, and the void ratio in this embodiment is less than 1%.

[0088] Example 4:

[0089] A method for controlling the void ratio of a large-area thermal interface connection of a power electronic device according to the present invention can be achieved through the following steps:

[0090] Step 1: Select a silicon carbide power module with a pure Cu surface to be welded as the upper substrate, and pure Cu (heat sink) as the lower substrate. Select the interface structure with high heat dissipation proposed in Chinese Patent CN115662966A as the thermal interface material, that is, the lead-free solder paste layer is selected in the form of a composite structure including two layers of lead-free solder paste. Among them, Sn-57Bi-1Ag solder paste is selected as the low-temperature solder paste layer, that is, the composite structure of the two layers of lead-free solder paste is Sn-57Bi-1Ag low-temperature solder paste layer - metal foam composite material - Sn-57Bi-1Ag low-temperature solder paste layer. The areas to be welded of both the upper substrate and the lower substrate are 30 mm × 45 mm, the length L1 and width W1 of the grid structure are 5 mm, the gap S1 between units is 1 mm, and the target thickness of the Sn-57Bi-1Ag low-temperature solder paste layer selected in the composite structure of the two layers of lead-free solder paste after reflow is 0.01 mm on average. Print the low-temperature solder paste on the upper substrate and the lower substrate according to the selected grid structure;

[0091] Step 2: Install the upper substrate - composite structure of two layers of lead-free solder paste - lower substrate interconnect structure obtained in Step 1 into a reflow soldering device, and perform reflow according to the set reflow process curve. The selected reflow parameters are: the heating zone time is 90 s, the holding zone time is 230 s, the pre-reflow zone time is 20 s, the reflow zone time is 160 s, the cooling zone time is 300 s, and the reflow zone is evacuated for 50 s, and the vacuum degree is 5 mbar on average.

[0092] Use X-ray to detect and calculate the void ratio of the large-area thermal interface connection structure obtained in the above steps. The void ratio in this embodiment is less than 1%.

[0093] Example 5:

[0094] A method for controlling the void ratio of a large-area thermal interface connection of a power electronic device according to the present invention can be achieved through the following steps:

[0095] Step 1: Select the IGBT power module with a pure Cu welding surface as the upper substrate, and pure Cu (heat sink) as the lower substrate. Select the interface structure with high-efficiency heat dissipation proposed in Chinese Patent CN115662966A as the thermal interface material. That is, the lead-free solder paste layer is selected in the form of a composite structure including two layers of lead-free solder paste. Among them, Sn-58Bi solder paste is selected as the low-temperature solder paste layer. That is, the composite structure of the two layers of lead-free solder paste is Sn-58Bi low-temperature solder paste layer - metal foam composite material - Sn-58Bi low-temperature solder paste layer. The welding areas of the upper and lower substrates are both 50mm×50mm. The length L1 and width W1 of the grid structure are 4mm, and the gap S1 between units is 0.5mm. The target thickness of the Sn-58Bi low-temperature solder paste layer selected in the composite structure of the two layers of lead-free solder paste after reflow is 0.01mm. Print the low-temperature solder paste on the upper and lower substrates according to the selected grid structure;

[0096] Step 2: Install the upper substrate - composite structure of two layers of lead-free solder paste - lower substrate interconnection structure obtained in Step 1 into the reflow soldering device, and perform reflow according to the set reflow process curve. The selected reflow parameters are: the heating zone time is 100s, the holding zone time is 300s, the pre-reflow zone time is 20s, the reflow zone time is 160s, the cooling zone time is 200s, and the reflow zone is evacuated for 120s, and the vacuum degree is 50mbar.

[0097] Use X-ray to detect and calculate the void ratio of the large-area thermal interface connection structure obtained in the above steps. The void ratio in this embodiment is less than 1%.

[0098] Therefore, in the above specific Examples 1 to 5, the control of the void ratio during the reflow of the large-area thermal interface lead-free solder paste is achieved, and the void ratio is all below 1%.

[0099] Comparative Example 1:

[0100] Same as Example 1, the difference is that the shape of the stencil printing module is square (as shown in Figure 8 ), there is no set grid structure in matrix arrangement, the length L1 is 55mm, the width W1 is 55mm, which is the same as the welding areas of the upper and lower substrates, and the reflow process is the same as that of Example 1. Use X-ray to detect the void ratio of the large-area thermal interface connection structure obtained in the above steps. A large number of white voids appear in the thermal interface interconnection area within the blue dotted line box. The calculated void ratio in this embodiment is 13%, and the result is as shown in Figure 9 shown.

[0101] Comparative Example 2:

[0102] Same as Example 1, the difference is that the shape of the grid structure is rectangular (as shown inFigure 10 As shown in the figure, the length L1 is 60 mm, the width W1 is 5 mm, the gap S1 between units is 1 mm, and the reflow process is the same as that in Example 1. The void ratio of the large-area thermal interface connection structure obtained in the above steps is detected by X-ray. A large number of white voids appear in the thermal interface interconnection area within the blue dashed box. The calculated void ratio in this example is 11%. The result is as Figure 11 shown.

[0103] Comparative Example 3:

[0104] Same as Example 1, the difference is that the shape of the grid structure is triangular (as Figure 12 shown), the lengths of both right-angled sides L1 and width W1 are 5 mm, the gap S1 between units is 1 mm, and the reflow process is the same as that in Example 1. The void ratio of the large-area thermal interface connection structure obtained in the above steps is detected by X-ray. A large number of white voids appear in the thermal interface interconnection area within the blue dashed box. The calculated void ratio in this example is 6%. The result is as Figure 13 shown.

[0105] Comparative Example 4:

[0106] Same as Example 2, the difference is that the reflow process parameters are different: the heating zone time is 110 s, the holding zone time is 150 s, the pre-reflow zone time is 20 s, the reflow zone time is 150 s, the cooling zone time is 300 s, the reflow zone is evacuated for 150 s, and the vacuum degree is 20 mbar. The measured reflow curve is as shown in 14. The void ratio of the large-area thermal interface connection structure obtained in the above steps is detected by X-ray. A large number of white voids appear in the thermal interface interconnection area within the blue dashed box. The calculated void ratio in this example is 15%. The result is as Figure 15 shown.

[0107] Comparative Example 5:

[0108] Same as Example 2, the difference is that the reflow process parameters are different: the heating zone time is 110 s, the holding zone time is 150 s, the pre-reflow zone time is 20 s, the reflow zone time is 150 s, the cooling zone time is 300 s, and the reflow zone is not evacuated. The measured reflow curve is as Figure 14 shown. The void ratio of the large-area thermal interface connection structure obtained in the above steps is detected by X-ray. A large number of white voids appear in the thermal interface interconnection area within the blue dashed box. The calculated void ratio in this example is 32%. The result is as Figure 16 shown.

[0109] It can be seen that the combined action of the shape optimization of the grid structure and the reflow process proposed by the present invention is the key to controlling the void ratio below 1% during the reflow process of the large-area thermal interface lead-free solder paste.

[0110] The above embodiments are only preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for controlling the void ratio of a large-area thermal interface connection of a power electronic device, characterized in that, It includes the following steps: Step 1: Shape design of the stencil printing module for the large-area thermal interface low-temperature lead-free solder paste. Print the low-temperature lead-free solder paste at the positions to be soldered for the thermal interface interconnection on the upper substrate or the lower substrate, and divide the printing area of the low-temperature lead-free solder paste into multiple uniform units by using the grid structure of the stencil printing module to increase the gas discharge channels of the low-temperature lead-free solder paste. Among them, the stencil printing module includes a grid structure arranged in a matrix with multiple preset sizes, and the grid structure is square; the size of the grid structure is determined by the interconnection area of the thermal interface low-temperature lead-free solder paste. The area of the thermal interface low-temperature lead-free solder paste is greater than 20 mm × 20 mm; when the interconnection area is between 20 mm × 20 mm and 40 mm × 40 mm, the length L1 = width W1 of the grid structure is 8 - 10 mm, and the gap S1 between the units is 1 - 2 mm. When the interconnection area is greater than 40 mm × 40 mm, the length L1 = width W1 of the grid structure is 5 - 10 mm, and the gap S1 between the units is 0.5 - 1 mm. Step 2: Optimization of the reflow process for the large-area thermal interface low-temperature lead-free solder paste. Load the upper substrate - low-temperature lead-free solder paste layer - lower substrate interconnection structure obtained in Step 1 into the reflow soldering device and perform reflow according to the set reflow process curve to complete the reflow soldering. The reflow soldering includes the following steps: S1. Heating process: Heat the temperature inside the reflow furnace cavity from room temperature to the preheating temperature T1, and the heating rate during the heating to T1 is 30 - 90 °C / min, and the heating zone time is 50 - 200 s. S2. Insulation process: Heat the reflow furnace temperature from T1 to the preheating temperature T2, and the heating rate during insulation is 0.1 - 5 °C / min, and the insulation zone time is 200 - 400 s. S3. Pre-reflow process: Heat the reflow oven temperature from T2 to the melting point T of the low-temperature lead-free solder paste m Perform pre-reflow with a heating rate of 50 - 90 °C / min during heat preservation, and the pre-reflow zone time is 5 - 20 s; S4. Reflow process: Heat the temperature inside the reflow furnace from the melting point T of the low-temperature lead-free solder paste to the reflow peak temperature T3 for reflow, and the time in the reflow zone is 100 - 300 s; m ​ There is also a vacuum pumping process during reflow. The vacuum pumping method is to pump vacuum in the reflow zone for 100 - 200 s, and the vacuum degree is 5 - 20 mbar; or a step-by-step vacuum pumping is adopted: first pump the inside of the reflow furnace cavity to a vacuum degree of 50 mbar and keep it for 50 - 100 s, and then pump the cavity vacuum degree to 5 - 20 mbar and keep it for 10 - 50 s. S5. Cooling process: Cool the temperature inside the reflow furnace cavity to 30 - 50 °C lower than the melting point of the low-temperature lead-free solder paste, and the cooling zone time is 100 - 500 s until the cooling is completed.

2. The method for controlling the void ratio of the large-area thermal interface connection of a power electronic device according to claim 1, characterized in that The upper substrate is one of the power electronic devices including metal-oxide semiconductor field effect transistor power modules, insulated gate bipolar transistor power modules, and silicon carbide power modules.

3. The method for controlling the void ratio of the large-area thermal interface connection of a power electronic device according to claim 1, wherein The lower substrate is one of the heat sink materials for power electronic devices, such as aluminum, copper, and copper alloys.

4. The method for controlling the void fraction of the large-area thermal interface connection of a power electronic device according to claim 1, characterized in that The low-temperature lead-free solder paste layer is a single-layer low-temperature lead-free solder paste structure or a composite structure including multiple layers of low-temperature lead-free solder paste.

5. The method for controlling the void ratio of the large-area thermal interface connection of a power electronic device according to claim 1, characterized in that The target thickness of the low-temperature lead-free solder paste layer after reflow is 0.01 - 0.2 mm.

6. The method for controlling the void fraction of the large-area thermal interface connection of a power electronic device according to claim 1, wherein The stencil printing module controls the uniform distribution and effective exhaust of the low-temperature lead-free solder paste during the reflow process by adjusting the size of the grid structure and the gap between cells, so that the void rate of the large-area thermal interface connection of the power electronic device can be controlled below 1%.

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