A method for generating a thick film layer in an ion trap chip

Abstract

This invention provides a method for generating a thick film layer in an ion trap chip, specifically including: S1: growing a first bonding layer on a substrate of the ion trap chip; S2: growing a second bonding layer on the material required for the thick film layer; S3: bonding the first bonding layer and the second bonding layer through a bonding process; S4: reducing the thickness of the material required for the thick film layer to a preset thickness through a thinning process. This invention avoids the speed limitations caused by using the growth method for the entire ion trap chip, and also solves the problem that the thicker the grown film, the more difficult it is to guarantee its quality.

Description

Technical Field

[0001] This invention belongs to the technical field of ion trap fabrication, and specifically relates to a method for generating a thick film layer in an ion trap chip. Background Technology

[0002] Ion trap systems, with their advantages of long coherence time and high logic operation fidelity, have become important platforms for quantum computing, quantum simulation, and precision measurement. Benefiting from mature semiconductor technology, chip-type ion traps are considered one of the effective ways to realize multi-ion qubit information processing. Compared to traditional manual or semi-manual ion trap fabrication methods, chip-type ion traps are fabricated using mature micro-nano processes, which not only accelerates the fabrication speed and improves the quality of ion traps, but also provides high integration and scalability. This lays the foundation for the standardization and industrialization of ion trap quantum computing in the future.

[0003] To achieve various functions, the ion trap chip used in an ion trap system needs a multi-layered structure. Some layers require considerable thickness (10 micrometers or more). For example, to meet the precision requirements of quantum information processing, the RF loss of the ion trap chip cannot be too high; otherwise, the coherence time of the ions and the fidelity of the operation will not meet practical needs. However, to ensure compatibility with existing technologies, silicon-based ion trap chips are typically used. But silicon has very high RF loss, so a thick silicon dioxide dielectric layer (at least 10 micrometers) is needed to act as a barrier between the RF signal on the ion trap chip and the silicon substrate, thereby reducing RF signal loss and improving the performance of the ion trap chip. Furthermore, to reduce breakdown voltage and the impact of stray charges in the dielectric layer on ion trap performance, the ion trap chip also requires a thick metal electrode layer (10 micrometers or more). However, commonly used growth methods, such as CVD (Chemical Vapor Deposition), sputtering, and evaporation, have significant drawbacks. For example, there are limitations on growth rate; the thicker the film, the longer the growth time. Generally, it takes several hours or even days to grow a thin film layer larger than 10 micrometers. Furthermore, the thicker the film, the more difficult it is to guarantee its quality, such as internal pores, stress-induced cracks, and poor surface roughness.

[0004] Therefore, it is necessary to design a method for generating thick film layers in ion trap chips to solve the above-mentioned technical problems. Summary of the Invention

[0005] To address the above problems, this invention provides a method for generating a thick film layer in an ion trap chip, specifically comprising:

[0006] A method for generating a thick film layer in an ion trap chip, the method comprising:

[0007] S1: Grow the first bonding layer on the substrate of the ion trap chip;

[0008] S2: Grow a second bonding layer on the material required for the thick film layer;

[0009] S3: The first bonding layer and the second bonding layer are bonded together using a bonding process;

[0010] S4: Through a thinning process, the thickness of the material required for the thick film layer is reduced to the preset thickness.

[0011] Furthermore, the thickness of both the first bonding layer and the second bonding layer is 10-100 nanometers.

[0012] Furthermore, in step S1, growing the first bonding layer on the substrate of the ion trap chip further includes the following steps:

[0013] S11. On the substrate of the ion trap chip, a pre-piece with a first conductive material is prepared;

[0014] A first bonding layer having a second conductive material is grown on a pre-existing wafer, the second conductive material being grown on the surface of the first conductive material.

[0015] Furthermore, step S11 specifically includes:

[0016] S111. On the substrate of the ion trap chip, n thin films are grown to form a pre-piece, where n is an integer greater than or equal to 0; wherein, the pre-piece includes a plurality of first through holes that penetrate the pre-piece longitudinally, and the first through holes are filled with a first conductive material by metallization to achieve electrical interconnection between the upper and lower surfaces of the pre-piece.

[0017] S112. A patterned first bonding layer is grown on the surface of the preform, wherein the first bonding layer has a plurality of second through holes, and a second conductive material is contained in the second through holes. The second conductive material is grown on the surface of the first conductive material and is insulated from the first bonding layer.

[0018] Furthermore, in step S2, growing a second bonding layer on the material required for the thick film layer also includes the following steps:

[0019] S21. On a thick film layer having a third conductive material, a second bonding layer having a fourth conductive material is grown.

[0020] Furthermore, step S21 specifically includes:

[0021] S211. Multiple blind holes or multiple third through holes are prepared on the thick film layer, wherein the blind holes or third through holes are filled with a third conductive material by metallization.

[0022] S212. A patterned second bonding layer is grown on the surface of the thick film layer, wherein the second bonding layer has a plurality of fourth through holes, and a fourth conductive material is contained in the fourth through holes. The fourth conductive material is grown on the surface of the third conductive material and is insulated from the second bonding layer.

[0023] Furthermore, the number of blind holes or third through holes is the same as the number of first through holes, and their arrangement positions correspond one-to-one.

[0024] Furthermore, S3: Bonding the first bonding layer to the second bonding layer using a bonding process further includes:

[0025] Before bonding, the fourth conductive material and the second conductive material are aligned by infrared alignment, piecewise alignment or face-to-face alignment and then the bonding process is performed.

[0026] Furthermore, step S4 also includes:

[0027] The thickness of the required material for the thick film layer is reduced to a preset thickness by chemical mechanical polishing, and the roughness is polished to a preset roughness. The preset thickness is below 200 μm and the preset roughness is below 50 nm.

[0028] Furthermore, the method also includes:

[0029] S5: The ion trap chip with a thick film layer obtained after bonding and thinning is annealed in a vacuum at a preset temperature for a preset time to ensure that the first bonding layer and the second bonding layer are bonded to meet the preset requirements. The preset temperature is 250-900℃ and the preset time is 0.5-6h.

[0030] This invention provides a method for generating thick film layers in ion trap chips, which solves the problem of preparing dielectric layers below 200 micrometers in ion trap chips. It avoids the speed limitation caused by using the growth method for the entire ion trap chip, and also solves the problem that the thicker the film, the more difficult it is to guarantee the quality. This lays the foundation for quantum information processing based on ion trap chips.

[0031] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures pointed out in the description, claims and drawings. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings to be used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 A flowchart of a method for generating a thick film layer in an ion trap chip according to an embodiment of the present invention is shown;

[0034] Figure 2 A structural diagram of the preparatory sheet according to an embodiment of the present invention is shown;

[0035] Figure 3 A structural diagram of the growth of the first bonding layer according to an embodiment of the present invention is shown;

[0036] Figure 4 A diagram showing the structure of a thick film layer after fabricating multiple blind holes or multiple third through holes according to an embodiment of the present invention is shown.

[0037] Figure 5 A structural diagram of the growth of the second bonding layer according to an embodiment of the present invention is shown;

[0038] Figure 6 An overall structural diagram of the structure formed after BD bonding according to an embodiment of the present invention is shown;

[0039] Figure 7 An embodiment of the present invention is shown. Figure 6 The overall structure diagram shown is the structure diagram after thinning. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] like Figure 1 As shown, the present invention provides a method for generating a thick film layer in an ion trap chip, the method comprising:

[0042] S1: Grow the first bonding layer 1 on the substrate of the ion trap chip;

[0043] S2: Grow a second bonding layer 3 on the material required for the thick film layer 4;

[0044] S3: The first bonding layer 1 and the second bonding layer 3 are bonded together using a bonding process;

[0045] S4: Through a thinning process, the thickness of the material required for the thick film layer 4 is reduced to a preset thickness.

[0046] The method of the present invention will now be described in detail.

[0047] In some embodiments of the present invention, the substrate material and the materials required for the thick film layer 4 of the ion trap chip are, but are not limited to, silicon wafers, sapphire, glass, metals, semiconductors, alloys, photoresists, etc. For example, in the form of "material of ion trap chip substrate - material required for thick film layer", it can be any of the following combinations:

[0048] Silicon wafer-glass, metal and glass, semiconductor-alloy, semiconductor-glass, photoresist-photoresist, etc.

[0049] In some embodiments of the present invention, the first bonding layer 1 and the second bonding layer 3 are, but are not limited to, materials such as lead-tin, gold-tin, copper-tin, gold-silicon, and gold. Furthermore, in this embodiment, the thickness of both the first bonding layer 1 and the second bonding layer 3 is 10-100 nanometers.

[0050] In some embodiments of the present invention, step S1, growing a first bonding layer 1 on the substrate of the ion trap chip, further includes: S11, preparing a pre-piece (5) having a first conductive material on the substrate of the ion trap chip; growing a first bonding layer (1) having a second conductive material (7) on the pre-piece (5), wherein the second conductive material (7) is grown on the surface of the first conductive material (6). Specifically, it includes:

[0051] S111. On the substrate of the ion trap chip, n thin films are grown to form a preparatory sheet 5 (the method of growth is not described in detail in this invention), where n is an integer greater than or equal to 0; wherein, the preparatory sheet 5 includes a plurality of first through holes that penetrate the preparatory sheet 5 longitudinally, and the first through holes are filled with a first conductive material 6 by metallization (including grouting and curing, side sputtering, electroplating, etc.) to achieve electrical interconnection between the upper and lower surfaces of the preparatory sheet 5; S112. A patterned first bonding layer 1 is grown on the surface of the preparatory sheet 5, wherein the first bonding layer 1 has a plurality of second through holes (9), and the second through holes (9) contain a second conductive material 7, which is grown on the surface of the first conductive material 6, and the second conductive material 7 is insulated from the first bonding layer 1 and is of the same material as the first bonding layer 1.

[0052] In some embodiments of the present invention, before growing the second bonding layer 3 on the material required for the thick film layer 4, if the thickness of the material is 500 micrometers or more, the following steps are further included: polishing the material required for the thick film layer with a thickness of 500 micrometers or more to a thickness of 200-500 micrometers by mechanical polishing to form the thick film layer 4. After forming the thick film layer 4, in step S2, growing the second bonding layer 3 on the material required for the thick film layer 4 further includes: growing the second bonding layer 3 having a fourth conductive material 2 on the thick film layer 4 having a third conductive material (8), specifically including:

[0053] S211. Multiple blind holes or multiple third through holes are prepared on the thick film layer 4, wherein the blind holes or third through holes are filled with a third conductive material 8 by metallization (including grouting and curing, side sputtering, electroplating, etc.).

[0054] S212. A patterned second bonding layer 3 is grown on the surface of the thick film layer 4. The second bonding layer 3 has a plurality of fourth through holes 10. A fourth conductive material 2 is contained in the fourth through holes 10. The fourth conductive material 2 is grown on the surface of the third conductive material 8. The fourth conductive material 2 is insulated from the second bonding layer 3 and is the same material as the second bonding layer 3.

[0055] In steps S1 and S2 above, the number of blind holes or third through holes is the same as the number of first through holes, and their arrangement positions correspond one-to-one.

[0056] In some embodiments of the present invention, S3: bonding the first bonding layer 1 and the second bonding layer 3 by bonding process, further comprising: aligning the fourth conductive material 2 and the second conductive material 7 by infrared alignment, piecewise alignment, and face-to-face alignment before bonding process.

[0057] In some embodiments of the present invention, the material required for the thick film layer 4 is silicon dioxide. However, it should be understood that the material required for the thick film layer 4 is not limited to silicon dioxide. The material required to obtain a thick film layer 4 with a thickness of 10 μm or more (e.g., 10 μm or more) according to the method of this embodiment can also be other materials, such as gold, silicon nitride, sapphire, etc.

[0058] In some embodiments of the present invention, step S4 is further included, namely: thinning the bonded thick film material to a preset thickness by chemical mechanical polishing, the preset thickness exposing the third conductive material 8 in the blind via. Additionally, step S4 further includes: simultaneously thinning the required thickness of the thick film 4 to the preset thickness and polishing the surface to a preset roughness. The preset thickness is below 200 μm, and the preset roughness is below 50 nm.

[0059] In some embodiments of the present invention, after step S4, the method further includes the following steps:

[0060] S5: The ion trap chip with a thick film layer obtained after bonding and thinning is annealed in vacuum at a preset temperature for a preset time to ensure that the first bonding layer 1 and the second bonding layer 3 are bonded to meet preset requirements. The preset temperature is 250–900°C, exemplarily 300°C, and the preset time is 0.5–6 hours, exemplarily 1 hour.

[0061] The above is a description of the method of the present invention. The following is a description in conjunction with... Figures 2-7 The invention will be described using a specific example as follows:

[0062] S1: A first bonding layer 1 is grown on the substrate of the ion trap chip, wherein the substrate material and the material required for the thick film layer of the ion trap chip are both silicon wafers, specifically including: S111, as shown in the figure. Figure 1 As shown, n thin films are grown on the substrate of the ion trap chip to form a pre-piece 5 (i.e., Figure 2 A) in the example Figure 2 As shown, the preparatory sheet 5 includes a plurality of longitudinally penetrating first through holes, the first through holes being filled with a first conductive material 6, at which point the upper and lower surfaces of the preparatory sheet 5 are electrically interconnected; S112, as Figure 3 As described above, a patterned first bonding layer 1 (i.e., ...) is grown on the surface of the preparatory sheet 5. Figure 3 In section B), the first bonding layer 1 has a plurality of second through holes 9. A second conductive material 7 is contained within each second through hole 9. This second conductive material 7 is grown on the surface of the first conductive material 6 and is insulated from the first bonding layer 1.

[0063] The material of the first bonding layer 1 is the same as that of the second conductive material 7, which is made of lead-tin material and has a thickness of 50 nanometers.

[0064] S2: In the thick film layer 4 (i.e. Figure 4 In the case of C), a second bonding layer 3 is grown on the required material (i.e., Figure 5 In step D), since the material required for the thick film layer 4 is less than 200 micrometers thick and is made of silicon dioxide, before growth, the material required for the 500-micrometer thick film layer is polished to a thickness of 200 micrometers to form the thick film layer 4. After forming the thick film layer 4, the following steps are performed: S211, as... Figure 4 As shown, multiple blind holes are prepared on the polished thick film layer 4, wherein the blind holes are filled with a third conductive material 8; S212, as Figure 5As shown, a patterned second bonding layer 3 is grown on the surface of the thick film layer 4. The second bonding layer 3 has a plurality of fourth through holes 10, and a fourth conductive material 2 is contained in the fourth through holes 10. The fourth conductive material 2 is grown on the surface of the third conductive material 8 and is insulated from the second bonding layer 3.

[0065] The material of the second bonding layer 3 is the same as that of the fourth conductive material 2, which is made of lead-tin material and has a thickness of 50 nanometers.

[0066] S3: Before bonding, the fourth conductive material 2 and the second conductive material 7 are aligned using infrared alignment before the bonding process. Through the bonding process, such as... Figure 6 As shown, the first bonding layer 1 and the second bonding layer 3 are BD-bonded, thereby enabling Figure 3 and Figure 5 form Figure 6 A unified structure;

[0067] S4: Through thinning processes, such as Figure 7 As shown, the thickness of the material required for the thick film layer is reduced to 50 μm to form... Figure 7 The chip structure involves polishing the thick film layer to expose the third conductive material 8 in the blind hole, so that the surface of the thick film layer 4 away from the second bonding layer 3 and the surface of the pre-wafer 5 away from the first bonding layer 1 are electrically interconnected. Then, roughness polishing is performed until the surface is polished to 1nm to meet the requirements.

[0068] S5: After bonding and thinning, the ion trap chip with a thick film layer is annealed in a vacuum at a preset temperature of 300℃ for 1 hour to improve the bonding performance of BD after bonding.

[0069] In summary, the core solution of this invention is to address the problem of fabricating dielectric layers of tens of micrometers in ion trap chips, laying the foundation for quantum information processing based on ion trap chips.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of the present invention. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A method for generating a thick film layer in an ion trap chip, characterized in that, The method includes: S1: A first bonding layer (1) is grown on the substrate of the ion trap chip; S2: Grow a second bonding layer (3) on the material required for the thick film layer (4); S3: The first bonding layer (1) and the second bonding layer (3) are bonded together by bonding process; S4: Through a thinning process, the bonded thick film layer (4) material is thinned to a preset thickness by chemical mechanical polishing, so that the third conductive material (8) in the blind hole prepared on the thick film layer (4) is exposed. The surface of the thick film layer (4) away from the second bonding layer (3) and the surface of the pre-piece (5) away from the first bonding layer (1) are electrically interconnected. The pre-piece (5) is prepared on the substrate of the ion trap chip.

2. The method for generating a thick film layer in an ion trap chip according to claim 1, characterized in that, The thickness of the first bonding layer (1) and the second bonding layer (3) is 10-100 nanometers.

3. The method for generating a thick film layer in an ion trap chip according to claim 2, characterized in that, In step S1, the growth of the first bonding layer (1) on the substrate of the ion trap chip also includes the following steps: S11. On the substrate of the ion trap chip, a pre-piece (5) with a first conductive material is prepared; A first bonding layer (1) having a second conductive material (7) is grown on the preparatory sheet (5), the second conductive material (7) being grown on the surface of the first conductive material (6).

4. The method for generating a thick film layer in an ion trap chip according to claim 3, characterized in that, Step S11 specifically includes: S111. On the substrate of the ion trap chip, n thin films are grown to form a pre-piece (5), where n is an integer greater than or equal to 0; wherein, the pre-piece (5) includes a plurality of first through holes that penetrate the pre-piece (5) longitudinally, and the first through holes are filled with a first conductive material (6) by metallization to realize electrical interconnection between the upper and lower surfaces of the pre-piece (5). S112. A patterned first bonding layer (1) is grown on the surface of the preparatory sheet (5), wherein the first bonding layer (1) has a plurality of second through holes (9), and a second conductive material (7) is contained in the second through holes (9). The second conductive material (7) is grown on the surface of the first conductive material (6), and the second conductive material (7) is insulated from the first bonding layer (1).

5. The method for generating a thick film layer in an ion trap chip according to claim 2, characterized in that, In step S2, the growth of the second bonding layer (3) on the material required for the thick film layer (4) also includes the following steps: S21. On the thick film layer (4) having a third conductive material (8), a second bonding layer (3) having a fourth conductive material (2) is grown.

6. The method for generating a thick film layer in an ion trap chip according to claim 5, characterized in that, Step S21 specifically includes: S211. Multiple blind holes or multiple third through holes are prepared on the thick film layer (4), wherein the blind holes or third through holes are filled with a third conductive material (8) by metallization. S212. A patterned second bonding layer (3) is grown on the surface of the thick film layer (4), wherein the second bonding layer (3) has a plurality of fourth through holes (10), and a fourth conductive material (2) is contained in the fourth through holes (10). The fourth conductive material (2) is grown on the surface of the third conductive material (8), and the fourth conductive material (2) is insulated from the second bonding layer (3).

7. The method for generating a thick film layer in an ion trap chip according to claim 3, characterized in that, The number of blind holes or third through holes is the same as the number of first through holes, and their arrangement positions correspond one-to-one.

8. The method for generating a thick film layer in an ion trap chip according to claim 3, characterized in that, S3: The first bonding layer (1) and the second bonding layer (3) are bonded together by a bonding process, which also includes: Before bonding, the fourth conductive material (2) and the second conductive material (7) are aligned by infrared alignment, piecewise alignment or face-to-face alignment and then bonded.

9. A method for generating a thick film layer in an ion trap chip according to any one of claims 1-8, characterized in that, Step S4 also includes: While reducing the thickness of the required material for the thick film layer (4) to a preset thickness by chemical mechanical polishing, the roughness is polished to a preset roughness, wherein the preset thickness is less than 200 μm and the preset roughness is less than 50 nm.

10. A method for generating a thick film layer in an ion trap chip according to any one of claims 1-8, characterized in that, The method further includes: S5: The ion trap chip with a thick film layer (4) obtained after bonding and thinning is annealed in a vacuum at a preset temperature for a preset time so that the first bonding layer (1) and the second bonding layer (3) are bonded to meet the preset requirements. The preset temperature is 250 to 900°C and the preset time is 0.5 to 6 hours.

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