A parallel real-time three-dimensional waveform mapping method for digital oscilloscopes

Abstract

The present invention discloses a parallel real-time three-dimensional waveform mapping method for a digital oscilloscope. The method comprises the following steps: the measured signal is collected by an acquisition system of the digital oscilloscope, and the collected parallel sampling data is converted into serial data by a parallel-to-serial conversion module. The serial data is then sequentially written into K parallel FIFOs, and a sampling point is read from the K parallel FIFOs in each clock cycle to realize parallel real-time three-dimensional waveform mapping from the sampling point to a three-dimensional database. Finally, the mapping results are sequentially connected end to end to form a complete three-dimensional waveform data, which is then uploaded to a host computer for real-time display.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital oscilloscopes, and more particularly, relates to a parallel real-time three-dimensional waveform mapping method for a digital oscilloscope. Background Art

[0002] Digital oscilloscopes are developing towards higher bandwidth, higher sampling rates, higher capture rates, deeper memory, and lower dead time. However, display mapping speed has become a significant constraint. Improving mapping speed is the most economical way to increase capture rates and reduce dead time. Due to limitations in storage hardware (such as DDR), data cannot be simultaneously acquired and written during the data reading phase. Therefore, acquisition and plotting can only be performed serially. Therefore, the period during which data is read falls within the oscilloscope's acquisition dead time. Reducing the drawing time can improve capture rates and reduce acquisition dead time.

[0003] Traditional 3D waveform mapping has three basic steps: Figure 1 As shown, the corresponding address of the sampling point in the 3D database is first calculated based on the sample value size and time sequence. The existing waveform data at that address in the 3D database is then read out, known as a data fetch. Finally, the existing waveform data is incremented by 1, known as a data update operation, and written back to the same address. If this process is followed, performing three-dimensional waveform mapping, with each clock cycle completing one step, the 3D data is first fetched, the next clock cycle updates the 3D data, and the next clock cycle writes the data to the storage unit. Each sampling point requires three clock cycles, making the overall mapping process time-consuming and the drawing process lengthy.

[0004] Since FPGA is a parallel architecture, in order to give full play to its advantages, the drawing process can be implemented in a pipeline manner, such as Figure 2 As shown; pipeline mapping requires the video memory to be a dual-port read-write storage device, but even a dual-port storage device cannot achieve the same continuous or alternating repeated correct mapping because Figure 2 As we can see, the UR1 data storage operation is executed on D1 at T4, and the result of UR1 can only be read at T5. If the address mapped to D2 is the same as that of D1, the result of UR1 cannot be read at T3. In other words, the actual result of UR1 can only be read at A4 (the data corresponding to D4). Similarly, the result of UR1 cannot be read at D3. The ultimate phenomenon is that the results of three mappings of D1, D2, and D3 are the same as the result of one mapping of D1. Only one-third of the operations of multiple consecutive mappings are valid.

[0005] Due to the mapping error of consecutive identical addresses, full data mapping cannot accurately map waveform brightness when deep memory is used (for example, when mapping tens of megabytes of data to the screen, there is a high probability of repeated mapping of consecutive addresses). The pipeline mapping function of non-dual-port external memory is completely invalid. The alternating reading and writing of data to the storage device may require multiple read and write clocks, making the synchronization of single-cycle synchronous RAM more expensive. Summary of the Invention

[0006] The purpose of the present invention is to overcome the shortcomings of the existing technology and provide a parallel real-time three-dimensional waveform mapping method for a digital oscilloscope. The method uses a mapping address conflict management mechanism to map the sampling points in the cache to ensure that multiple sampling points under the same mapping address can be mapped at one time.

[0007] To achieve the above-mentioned object of the invention, the present invention provides a parallel real-time three-dimensional waveform mapping method for a digital oscilloscope, characterized by comprising the following steps:

[0008] (1) Deploy K parallel FIFOs and a three-dimensional database with S columns and T rows in the FPGA of the digital oscilloscope;

[0009] (2) Power on the digital oscilloscope and connect it to the signal to be measured; collect the signal to be measured through the acquisition system of the digital oscilloscope to obtain parallel sampling data; then convert it into serial data through the parallel-to-serial conversion module;

[0010] (3) Write serial data into K parallel FIFOs in sequence;

[0011] (4) Complete parallel real-time three-dimensional waveform mapping from each sampling point in K parallel FIFOs to the three-dimensional database;

[0012] (5) The probability data of each storage unit in the K RAMs are connected end to end in sequence to form a complete three-dimensional waveform data, which is then uploaded to the host computer for real-time display.

[0013] The object of the invention of the present invention is achieved like this:

[0014] The present invention discloses a parallel real-time three-dimensional waveform mapping method for a digital oscilloscope. The method comprises the following steps: collecting a measured signal through an acquisition system of the digital oscilloscope, converting the collected parallel sampling data into serial data through a parallel-to-serial conversion module, sequentially writing the serial data into K parallel FIFOs, and reading a sampling point from the K parallel FIFOs in each clock cycle to realize parallel real-time three-dimensional waveform mapping from the sampling point to a three-dimensional database; finally, the mapping results are sequentially connected end to end to form a complete three-dimensional waveform data, which is then uploaded to a host computer for real-time display.

[0015] At the same time, the parallel real-time three-dimensional waveform mapping method of a digital oscilloscope of the present invention also has the following beneficial effects:

[0016] (1) The mapping of sampling points with address conflicts is completed through a single write operation, which avoids the disadvantage of multiple read and write operations required in traditional methods, achieves speed optimization, and achieves the effect of "mapping one point at a time".

[0017] (2) The parallel mapping method is used to enable each mapping module to draw the same waveform data at the same time, solving the problem of mismatch between high sampling rate and FPGA single-channel data throughput and processing capability.

[0018] (3) The present invention supports the mapping speed-up of a single-port external cache, and the non-dual-port external memory can normally realize the pipeline mapping function, and realizes the transformation from alternating read and write operations to batch read and write operations through the mapping address conflict management mechanism.

[0019] (4) The present invention ensures real-time one-shot mapping under any disordered repetition and supports deep storage full data point mapping. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a traditional three-dimensional waveform mapping block diagram;

[0021] Figure 2 It is a traditional three-dimensional waveform mapping timing diagram;

[0022] Figure 3 This is a schematic diagram of the three-dimensional database address division

[0023] Figure 4 It is a parallel real-time three-dimensional waveform mapping flow chart;

[0024] Figure 5 It is a parallel real-time three-dimensional waveform mapping timing diagram. DETAILED DESCRIPTION

[0025] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, such descriptions will be omitted here.

[0026] Example

[0027] In this embodiment, a parallel real-time three-dimensional waveform mapping method for a digital oscilloscope includes the following steps:

[0028] (1) Deploy the hardware structure in the digital oscilloscope;

[0029] Deploy K parallel FIFOs in the FPGA of the digital oscilloscope;

[0030] According to the resolution S*T of the display screen, a three-dimensional database with S columns and T rows corresponding to the display screen is deployed in the FPGA of the digital oscilloscope. The three-dimensional database is divided into K sub-three-dimensional databases in the order of storage time. Each sub-three-dimensional database consists of a dual-port RAM. Each RAM contains Q storage cells, and each storage cell is set with an initial storage probability. Where Q = (S / K) × T, and the initial storage probability of the storage cell in the j-th column and k-th row in the i-th RAM is p i,jk , i=1,2,…,K, j=1,2,…,S / K, k=1,2,…,T;

[0031] In this embodiment, assuming that the resolution of the display screen is S*T=200*1000, the size of the three-dimensional database is 200 rows and 1000 columns; Figure 3 As shown, the three-dimensional database is divided into K = 10 sub-three-dimensional databases, that is, composed of 10 RAMs. The size of each sub-three-dimensional database composed of RAMs is 200 rows and 100 columns, and each contains 20,000 storage units. For example, the addresses of the storage units in RAM1 are 0, 1, ..., 199, and the storage units with different addresses store their respective initial probabilities.

[0032] (2) Power on the digital oscilloscope and connect it to the signal to be measured; collect the signal to be measured through the acquisition system of the digital oscilloscope to obtain parallel sampling data; then convert it into serial data through the parallel-to-serial conversion module;

[0033] (3) Assume that the serial data has a total of MK sampling points, M = S / K; Figure 4 As shown, 1 to M sampling points of the serial data are stored in FIFO1, M+1 to 2M sampling points are stored in FIFO2, and so on, until all the serial data are stored in the corresponding FIFO;

[0034] In this embodiment, there are 10 FIFOs that cache 10 channels of parallel data at the same time. The data in each FIFO enters the corresponding sub-3D database composed of RAM for mapping. For example, the data in FIFO1 enters RAM1 for mapping in sequence, and so on.

[0035] (4) Parallel real-time three-dimensional waveform mapping;

[0036] (4.1) Set the cache depth of each RAM to N=4; set the cache register and initialize the mapping value of the cache register to ρ=0;

[0037] (4.2) At clock cycle T1, the first sampling point is read from the K parallel FIFOs, denoted as {D1, D M+1 ,D 2M+1 ,…,D (K-1)M+1};

[0038] (4.3) In clock cycle T2, the second sampling point is read from the K parallel FIFOs, denoted as {D2, D M+2 ,D 2M+2 ,…,D (K-1)M+2}, then calculate the address A1 of the first sampling point in the corresponding RAM according to the size of the sampling value of the first sampling point;

[0039] Now we give an arbitrary address A j The general calculation formula is:

[0040] A j =A s +2 n ×(j-1)-Y j

[0041] Where j = 1, 2, ..., M, A s is the mapping base address, Y j is the amplitude of the jth sampling point, and n is the resolution of the ADC.

[0042] Update the storage probability corresponding to the storage unit at address A1 in each RAM to p i,1k +1, and then written back to the memory cell at address A1 after 3 clock cycles;

[0043] (4.4) In clock cycle T3, the third sampling point is read from the K parallel FIFOs, denoted as {D3, D M+3 ,D 2M+3 ,…,D (K-1)M+3}, then calculate the address A2 of the second sampling point in the corresponding RAM according to the size of the sampling value of the second sampling point;

[0044] like Figure 5 As shown, compare the sizes of A2 and A1. If A2 = A1, add 1 to the mapping value ρ in the cache register, otherwise keep it unchanged.

[0045] Update the storage probability corresponding to the storage unit at address A2 in each RAM to p i,2k +ρ+1, and then after N-1 clock cycles, it is written back to the memory cell at address A2 and the mapping value ρ is reset to 0;

[0046] (4.5) At clock cycle T4, the fourth sampling point is read from the K parallel FIFOs, denoted as {D4, D M+4 ,D 2M+4 ,…,D (K-1)M+4}; Then calculate the address A3 of the third sampling point in the corresponding RAM according to the sampling value of the third sampling point;

[0047] like Figure 5 As shown, compare the size of A3 with A2 and A1. If A3 is equal to any one of A2 and A1, then increase the mapping value ρ in the cache register by 1. If A3 is equal to A2 and A1, then increase the mapping value ρ in the cache register by 2. Otherwise, keep it unchanged.

[0048] Update the storage probability corresponding to the storage unit at address A3 in each RAM to p i,3k +ρ+1, and then after N-1 clock cycles, it is written back to the memory cell at address A3 and the mapping value ρ is reset to 0;

[0049] (4.6) and so on. Repeat the above operation. When the number of sample points read reaches the RAM cache depth of 4, the fifth sample point is read from the K parallel FIFOs at clock cycle T5, which is recorded as {D5, D M+5 ,D 2M+5 ,…,D (K-1)M+5}; Then calculate the address A4 of the 4th sampling point in the corresponding RAM according to the size of the sampling value of the 4th sampling point;

[0050] like Figure 5 As shown, compare the size of A4 with A3, A2, and A1. If A4 is equal to any one of them, add 1 to the mapping value ρ in the cache register. If A4 is equal to any two of them, add 2 to the mapping value ρ in the cache register. And so on. If A4 is equal to each of them, add 3 to the mapping value ρ in the cache register. Otherwise, keep it unchanged.

[0051] Update the storage probability corresponding to the storage unit at address A4 in each RAM to p i,4k +ρ+1, and then after 3 clock cycles, it is written back to the memory cell at address A4 and the mapping value ρ=0 is reset;

[0052] (4.7) When the number of sample points read exceeds the RAM cache depth of 4, that is, in the clock cycle T L Read the Lth sampling point from K parallel FIFOs, denoted as {D L ,D M+L ,D 2M+L ,…,D (K-1)M+L}, L>5; then calculate the address A of the L-1th sampling point in the corresponding RAM according to the sampling value of the L-1th sampling point L-1 ;

[0053] Comparison A L-1 With A L-2 ,A L-3 ,…,A L-N If the size of A L-1If A is equal to any of them, the mapping value ρ in the cache register is increased by 1. L-1 If A is equal to any two of them, then add 2 to the mapping value ρ in the cache register, and so on. L-1 If it is equal to each, then increase the mapping value ρ in the cache register by N-1, otherwise keep it unchanged;

[0054] Update each RAM address to A L-1 The storage probability corresponding to the storage unit is p i,(L-1)k +ρ+1, and then write back to address A after N-1 clock cycles L-1 The storage unit is reset and the mapping value ρ is reset to 0;

[0055] (4.8), in this embodiment, if Figure 5 As shown in FIG, assuming that the sixth sampling point is read from the K parallel FIFOs at clock cycle T6, then the address is calculated as A5, and the size of A5 is compared with A4, A3, and A2, and address A1 is eliminated; assuming that the seventh sampling point is read from the K parallel FIFOs at clock cycle T7, then the address is calculated as A6, and the size of A6 is compared with A5, A4, and A3, and address A2 is eliminated; and so on, the above operations are repeated until the three-dimensional mapping of the last sampling point in the K parallel FIFOs is completed; it can be found that starting from clock cycle T5, the cache depth has been reached, and at clock cycle T M+1 No longer read the sampling point, only calculate the address A of the Mth sampling point M , then update each RAM address to A L-1 The storage probability corresponding to the storage unit.

[0056] (5) The probability data of each storage unit in the K RAMs are connected end to end in sequence to form a complete three-dimensional waveform data, which is then uploaded to the host computer for real-time display.

[0057] Although the above describes the illustrative specific embodiments of the present invention to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concepts of the present invention are protected.

Claims

1. A parallel real-time three-dimensional waveform mapping method for a digital oscilloscope, characterized in that: The following steps are involved: (1) Deploy the hardware structure in the digital oscilloscope; Deploy K parallel FIFOs in the FPGA of the digital oscilloscope; According to the resolution S*T of the display screen, a three-dimensional database with S columns and T rows corresponding to the display screen is deployed in the FPGA of the digital oscilloscope. The three-dimensional database is divided into K sub-three-dimensional databases in the order of storage time. Each sub-three-dimensional database consists of a dual-port RAM. Each RAM contains Q storage cells, and each storage cell is set with an initial storage probability. Where Q = (S / K) × T, and the initial storage probability of the storage cell in the j-th column and k-th row in the i-th RAM is p i,jk , i=1,2,…,K, j=1,2,…,S / K, k=1,2,…,T; (2) Power on the digital oscilloscope and connect it to the signal to be measured; collect the signal to be measured through the acquisition system of the digital oscilloscope to obtain parallel sampling data; then convert it into serial data through the parallel-to-serial conversion module; (3) Assume that the serial data has a total of MK sampling points, M = S / K; store 1 to M sampling points of the serial data in FIFO1, store M + 1 to 2M sampling points in FIFO2, and so on, until all the serial data are stored in the corresponding FIFO; (4) Parallel real-time three-dimensional waveform mapping; (4.1) Set the cache depth of each RAM to N; set the cache register and initialize the mapping value of the cache register to ρ = 0; (4.2) At clock cycle T1, the first sampling point is read from the K parallel FIFOs, denoted as {D1, D M+1 ,D 2M+1 ,…,D (K-1)M+1 }; (4.3) In clock cycle T2, the second sampling point is read from the K parallel FIFOs, denoted as {D2, D M+2 ,D 2M+2 ,…,D (K-1)M+2 }, then calculate the address A1 of the first sampling point in the corresponding RAM according to the size of the sampling value of the first sampling point; Update the storage probability corresponding to the storage unit at address A1 in each RAM to p i,k +1, and then write it back to the memory cell at address A1 after N-1 clock cycles; (4.4) In clock cycle T3, the third sampling point is read from the K parallel FIFOs, denoted as {D3, D M+3 ,D 2M+3 ,…,D (K-1)M+3 }, then calculate the address A2 of the second sampling point in the corresponding RAM according to the size of the sampling value of the second sampling point; Compare the sizes of A2 and A1. If A2 = A1, add 1 to the mapping value ρ in the cache register, otherwise keep it unchanged. Update the storage probability corresponding to the storage unit at address A2 in each RAM to p i,2k +ρ+1, and then after N-1 clock cycles, it is written back to the memory cell at address A2 and the mapping value ρ is reset to 0; (4.5) At clock cycle T4, the fourth sampling point is read from the K parallel FIFOs, denoted as {D4, D M+4 ,D 2M+4 ,…,D (K-1)M+4 }; Then calculate the address A3 of the third sampling point in the corresponding RAM according to the sampling value of the third sampling point; Compare A3 with A2 and A1. If A3 is equal to any of A2 and A1, increase the mapping value ρ in the cache register by 1. If A3 is equal to A2 and A1, increase the mapping value ρ in the cache register by 2. Otherwise, keep it unchanged. Update the storage probability corresponding to the storage unit at address A3 in each RAM to p i,3k +ρ+1, and then after N-1 clock cycles, it is written back to the memory cell at address A3 and the mapping value ρ is reset to 0; (4.6) and so on, repeat the above operation, when the number of sample points read reaches the RAM cache depth N, that is, in the clock cycle T N+1 Read the N+1th sampling point from K parallel FIFOs, denoted as {D N ,D M+N ,D 2M+N ,…,D (K-1)M+N }; Then calculate the address A of the N-1th sampling point in the corresponding RAM according to the sampling value of the Nth sampling point N ; Comparison A N With A N-1 ,…,A2,A1 size, if A N If A is equal to any of them, the mapping value ρ in the cache register is increased by 1. N If A is equal to any two of them, then add 2 to the mapping value ρ in the cache register, and so on. N If it is equal to each, then increase the mapping value ρ in the cache register by N-1, otherwise keep it unchanged; Update each RAM address to A N The storage probability corresponding to the storage unit is p i,Nk +ρ+1, and then write back to address A after N-1 clock cycles N The storage unit is reset and the mapping value ρ is reset to 0; (4.7) When the number of sample points read exceeds the RAM cache depth N, that is, in the clock cycle T L Read the Lth sampling point from K parallel FIFOs, denoted as {D L ,D M+L ,D 2M+L ,…,D (K-1)M+L }, L>N+1; then calculate the address A of the L-1th sampling point in the corresponding RAM according to the sampling value of the L-1th sampling point L-1 ; Comparison A L-1 With A L-2 ,A L-3 ,…,A L-N If the size of A L-1 If A is equal to any of them, the mapping value ρ in the cache register is increased by 1. L-1 If A is equal to any two of them, then add 2 to the mapping value ρ in the cache register, and so on. L-1 If it is equal to each, then increase the mapping value ρ in the cache register by N-1, otherwise keep it unchanged; Update each RAM address to A L-1 The storage probability corresponding to the storage unit is p i,(L-1)k +ρ+1, and then write back to address A after N-1 clock cycles L-1 The storage unit is reset and the mapping value ρ is reset to 0; (4.8) Repeat the above operations in this way until the three-dimensional mapping of the last sampling point in the K parallel FIFOs is completed; (5) The probability data of each storage unit in the K RAMs are connected end to end in sequence to form a complete three-dimensional waveform data, which is then uploaded to the host computer for real-time display.

2. The parallel real-time three-dimensional waveform mapping method of a digital oscilloscope according to claim 1, characterized in that: The address A j The calculation method is: HAS j =A s +2 n ×(j-1)-Y j Where j = 1, 2, ..., M, A s is the mapping base address, Y j is the amplitude of the jth sampling point, and n is the resolution of the ADC.

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