GPS modules and electronic devices

Abstract

The present application discloses a GPS module and electronic equipment, belonging to the field of communication technology. The GPS module is provided with a clock output circuit, the clock output circuit comprising: a frequency deviation control unit, the first end of the frequency deviation control unit is used to access the clock signal, the second end of the frequency deviation control unit is used to output the first clock signal of the frequency deviation adaptation GPS module and the satellite communication module; the input end of the clock adjustment unit is connected to the second end of the frequency deviation control unit, the clock adjustment unit is used to enhance the driving current of the first clock signal output by the frequency deviation control unit, and the output end of the clock adjustment unit is used to output the first clock signal after the enhanced driving current to the satellite communication module.

Description

Technical Field

[0001] The present application belongs to the field of communication technology, and specifically relates to a GPS module and electronic equipment. Background Art

[0002] Satellite communication is a technology that uses artificial satellites as relay stations to forward radio waves and achieve communication between two or more devices. The clock in the artificial satellite system is accurate, and the clock frequency deviation requirements for devices that communicate with satellites, such as mobile phones, are relatively high, such as up to ±1.5ppm. The current solutions are to provide accurate clocks to satellite communication ICs by externally attaching a temperature compensated crystal oscillator (TCXO) to the satellite communication integrated circuit (IC). However, attaching an external crystal oscillator to the satellite communication IC will increase the cost. Summary of the invention

[0003] The purpose of the embodiments of the present application is to provide a GPS module and an electronic device that can solve the problem of increased costs due to the external crystal oscillator of the satellite communication IC in the prior art.

[0004] In a first aspect, an embodiment of the present application provides a GPS module, wherein a clock output circuit is provided in the GPS module, and the clock output circuit includes:

[0005] A frequency deviation control unit, wherein a first end of the frequency deviation control unit is used to access a clock signal, and a second end of the frequency deviation control unit is used to output a first clock signal whose frequency deviation is adapted to the GPS module and the satellite communication module;

[0006] A clock adjustment unit, wherein the input end of the clock adjustment unit is connected to the second end of the frequency deviation control unit, the clock adjustment unit is used to enhance the driving current of the first clock signal output by the frequency deviation control unit, and the output end of the clock adjustment unit is used to output the first clock signal after the enhanced driving current to the satellite communication module.

[0007] In a second aspect, an embodiment of the present application provides an electronic device, including a satellite communication module and the GPS module described in the first aspect.

[0008] In an embodiment of the present application, a clock output circuit is provided in the GPS module, and the clock output circuit includes: a frequency deviation control unit, the first end of the frequency deviation control unit is used to access the clock signal, and the second end of the frequency deviation control unit is used to output the first clock signal whose frequency deviation is adapted to the GPS module and the satellite communication module; the input end of the clock adjustment unit is connected to the second end of the frequency deviation control unit, the clock adjustment unit is used to enhance the driving current of the first clock signal output by the frequency deviation control unit, and the output end of the clock adjustment unit is used to output the first clock signal after the enhanced driving current to the satellite communication module. In this way, by adding a clock path to the GPS module, compensating the frequency deviation of the clock signal through the frequency deviation control unit, and then enhancing the driving current of the clock signal through the clock adjustment unit and outputting it to the satellite communication module, the cost of external crystal oscillator in the satellite communication module can be saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is one of the structural schematic diagrams of the clock output circuit in the GPS module provided in the embodiment of the present application;

[0010] Figure 2 This is the second structural diagram of the clock output circuit in the GPS module provided in the embodiment of the present application;

[0011] Figure 3 This is the third structural diagram of the clock output circuit in the GPS module provided in the embodiment of the present application;

[0012] Figure 4 is a schematic diagram of the structure of the PLL provided in an embodiment of the present application;

[0013] Figure 5 This is the fourth structural diagram of the clock output circuit in the GPS module provided in the embodiment of the present application;

[0014] Figure 6 This is the fifth structural diagram of the clock output circuit in the GPS module provided in the embodiment of the present application;

[0015] Figure 7 It is a schematic diagram of the circuit connection structure of the MOS array and the clock buffer provided in an embodiment of the present application;

[0016] Figure 8 is a flowchart of a clock signal output method provided in an embodiment of the present application;

[0017] Fig. 9 is a structural diagram of a clock signal output device provided in an embodiment of the present application;

[0018] Fig.10 is a structural diagram of an electronic device provided in an embodiment of the present application;

[0019] Fig.11 It is a hardware structure diagram of the electronic device provided in the embodiment of the present application. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present application to clearly describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments in the present application belong to the scope of protection of this application.

[0021] The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0022] The clock output circuit and the clock signal output method provided in the embodiments of the present application are described in detail below through specific embodiments and their application scenarios in combination with the accompanying drawings.

[0023] In order to make the embodiments of the present application clearer, the relevant technical knowledge involved in the embodiments of the present application is first introduced as follows:

[0024] Satellite communication is a technology that uses artificial satellites as relay stations to forward radio waves and achieve communication between two or more devices. In environments without base stations such as wilderness, wireless signals are directly sent and received between terminals and satellites (high or low orbit) for data transmission and exchange, supporting voice, short message, and broadband and narrowband data services.

[0025] The clock in the artificial satellite system is accurate, and the clock frequency deviation requirement for devices communicating with the satellite (such as mobile phones) is relatively high (±1.5ppm). The current solutions all use external TCXO to provide accurate clocks for satellite communication ICs.

[0026] The crystal frequency will shift with temperature changes. Thermistor crystals used in electronic equipment systems are generally cut at AT angles. The output frequency of such thermistor crystals changes with temperature, and the crystal output frequency shifts from the nominal frequency. The frequency deviation is generally measured by frequency deviation, frequency deviation (ppm) = (actual frequency - nominal frequency) / nominal frequency * 1000000.

[0027] In the existing electronic equipment system clock architecture, all peripheral clocks are output from the clock IC. However, the clock frequency output by the clock IC is affected by temperature, and the frequency deviation range is within ±10ppm, which cannot meet the satellite communication IC frequency deviation requirement of ±1.5ppm. Therefore, satellite communication ICs currently require external crystal oscillators, which brings cost losses. Secondly, crystals and crystal oscillators are very sensitive to heat and mechanical stress. When laying out crystals and crystal oscillators on the printed circuit board (PCB), heat sources and mechanical stress areas must be avoided. Therefore, adding crystals / crystal oscillators will increase the difficulty of design.

[0028] Based on the above prior art, the present application proposes to add a clock path and a clock buffer inside a GPS module such as a GPS, and output a frequency compensated and enhanced clock signal from the GPS to the satellite communication IC, so as to simplify the design. In the embodiment of the present application, each satellite communication IC can save one crystal oscillator, thereby bringing cost advantages; there is no need to layout multiple crystals / crystal oscillators on the PCB board, which reduces the design difficulty such as thermal and mechanical stress.

[0029] See also Figure 1 , Figure 1 The schematic diagram of the clock output circuit in the GPS module provided in the embodiment of the present application is as follows: Figure 1 As shown, the GPS module 100 is provided with a clock output circuit, and the clock output circuit includes:

[0030] A frequency deviation control unit 11, wherein a first end of the frequency deviation control unit 11 is used to access a clock signal, and a second end of the frequency deviation control unit 11 is used to output a first clock signal of the frequency deviation adaptation GPS module 100 and the satellite communication module;

[0031] A clock adjustment unit 12, wherein the input end of the clock adjustment unit 12 is connected to the second end of the frequency deviation control unit 11, the clock adjustment unit 12 is used to enhance the driving current of the first clock signal output by the frequency deviation control unit 11, and the output end of the clock adjustment unit 12 is used to output the first clock signal after the enhanced driving current to the satellite communication module.

[0032] In the embodiment of the present application, a clock path is added to the GPS module 100 to provide the satellite communication module with a clock signal whose frequency deviation and strength meet the requirements of the satellite communication module, thereby eliminating the need to design an external crystal oscillator in the satellite communication module and saving costs. Figure 1 As shown, the frequency deviation control unit 11 and the clock adjustment unit 12 are both arranged in the GPS module 100 .

[0033] The GPS module 100 may be a global positioning system (GPS) chip such as a GPS IC. The satellite communication module may also be referred to as a satellite communication IC.

[0034] The frequency deviation control unit 11 is used to provide a clock signal with a frequency deviation that meets the frequency deviation requirements of the GPS module 100 and the satellite communication module according to the frequency deviation requirements of the GPS module 100 and the satellite communication module; the clock adjustment unit 12 is used to enhance the driving capability of the clock output, mainly providing a clock signal of appropriate size according to the clock input requirements of the satellite communication module.

[0035] Specifically, the first end of the frequency deviation control unit 11 is used to access the clock signal, such as the clock signal provided by the clock chip, i.e., ClockIC, or directly access the clock signal generated by an external crystal oscillator. The second end of the frequency deviation control unit 11 can be connected to the input end of the clock adjustment unit 12. The second end of the frequency deviation control unit 11 outputs the first clock signal of the frequency deviation adaptation GPS module 100 and the satellite communication module to the clock adjustment unit 12.

[0036] The output end of the clock adjustment unit 12 can be connected to the satellite communication module, and the output end of the clock adjustment unit 12 outputs the first clock signal with enhanced driving current to the satellite communication module.

[0037] Alternatively, if Figure 2 As shown, the frequency deviation control unit 11 is a frequency deviation compensation circuit 111, and the clock adjustment unit 12 includes a first switch Q1 and a clock buffer. The first end of the frequency deviation compensation circuit 111 is used to access the clock signal provided by the clock chip, and the third end of the frequency deviation compensation circuit 111 is used to receive crystal temperature data. The frequency deviation compensation circuit 111 is used to adjust the frequency deviation of the clock signal according to the received crystal temperature data to obtain a first clock signal whose frequency deviation is adapted to the GPS module 100 and the satellite communication module. The first switch Q1 is used to control the on-off between the frequency deviation compensation circuit 111 and the clock buffer.

[0038] In some embodiments, the original clock signal of the GPS module 100 can be used to provide a clock signal to the satellite communication module. The frequency deviation control unit 11 is a frequency deviation compensation circuit 111, which can be a frequency deviation compensation circuit inside the original GPS IC, and is used to compensate the frequency deviation of the connected clock signal to obtain a first clock signal that meets the frequency deviation requirement of the satellite communication module. Specifically, the first end of the frequency deviation compensation circuit 111 can be connected to the clock signal provided by the clock chip, and the third end can receive crystal temperature data, so that the frequency deviation compensation circuit 111 can find the current clock frequency deviation in the frequency-temperature curve according to the received real-time temperature value, and then compensate the clock frequency through the frequency deviation compensation circuit 111 to meet the requirements of the satellite communication module.

[0039] In this embodiment, a branch may be added at the rear end of the frequency offset compensation circuit 111 as a clock source for the newly added clock adjustment unit 12. The clock adjustment unit 12 includes a first switch Q1 and a clock buffer circuit, that is, a switch Q1 and a clock buffer circuit are connected in series on the newly added branch, wherein the clock buffer circuit is used to enhance the driving capability of the clock output, and the first switch Q1 may be a transistor or a switch device, which is used to control the on and off of the clock path to the satellite communication module, for example, when Q1 is turned on, the clock path is opened, and the clock buffer has a clock signal output, and when Q1 is turned off, the clock path is closed, and the clock buffer has no clock signal output.

[0040] Through this implementation, the satellite communication IC can be implemented without an external crystal oscillator. The design can be optimized based on the existing clock circuit of the GPS module, and the GPS module provides a clock signal to the satellite communication module, while avoiding the cost consumption and design difficulty caused by adding a crystal oscillator.

[0041] Optionally, a first end of the frequency deviation compensation circuit 111 is connected to a clock end of a clock chip, a thermistor is connected to the clock chip, a third end of the frequency deviation compensation circuit 111 is connected to an output end of a digital-to-analog converter ADC in the clock chip, an input end of the ADC is connected to the thermistor, and the ADC is used to convert the NTC resistance value inside the thermistor into temperature data.

[0042] That is, in some embodiments, such as Figure 6As shown, the first end of the frequency deviation compensation circuit 111 is connected to the clock chip 30, that is, the clock end of the ClockIC. The clock chip 30 is externally connected to a thermistor crystal 31, and an analog to digital converter (ADC) 32 is internally arranged. The input end of ADC32 is connected to the thermistor crystal 31, and the output end of ADC32 is connected to the third end of the frequency deviation compensation circuit 111. ADC32 can convert the negative temperature coefficient (NTC) resistance value inside the thermistor crystal into the real-time temperature value of the thermistor crystal 31, and transmit the temperature data to the frequency deviation compensation circuit 111. Therefore, the frequency deviation compensation circuit 111 finds the current clock frequency deviation in the frequency-temperature curve according to the received real-time temperature value, and then compensates the clock frequency through the frequency deviation compensation circuit 111 to meet the requirements of the satellite communication module.

[0043] Optionally, the first switch Q1 is a Metal-Oxide-Semiconductor Field-Effect Transistor (MOS) tube Q1, the second end of the frequency deviation compensation circuit 111 is connected to the drain of the first MOS tube Q1, the gate of the first MOS tube Q1 is connected to the satellite communication module, and is used to receive the clock request signal sent by the satellite communication module, the source of the first MOS tube Q1 is connected to the input end of the clock buffer Clock buffer, and the power supply end of the clock buffer Clock buffer is connected to the power supply of the GPS module 100;

[0044] The first MOS transistor Q1 is in a conducting state when receiving a clock request signal sent by the satellite communication module; the first MOS transistor Q1 is in a cut-off state when not receiving a clock request signal sent by the satellite communication module.

[0045] In some embodiments, a MOS tube can be used to control the on-off of the clock path, and the clock request signal sent by the satellite communication module can be used to control the on-off of the first MOS tube Q1. In specific implementation, the first MOS tube Q1 can be set between the frequency offset compensation circuit 111 and the clock buffer Clock buffer, wherein the drain of the first MOS tube Q1 is connected to the second end of the frequency offset compensation circuit 111, the source of the first MOS tube Q1 is connected to the input end of the clock buffer Clock buffer, and the gate of the first MOS tube Q1 is connected to the satellite communication module, and the clock request signal sent by the satellite communication module is received through the gate.

[0046] When the satellite communication module sends a clock request signal (such as a high level), the first MOS tube Q1 is turned on, and the clock signal is output from the frequency offset compensation circuit 111 to the back-end clock buffer, thereby outputting the clock signal to the satellite communication module; when the satellite communication module stops sending the clock request signal (such as a low level), the first MOS tube Q1 is turned off, and the clock signal output by the frequency offset compensation circuit 111 stops being sent to the back-end clock buffer, thereby stopping outputting the clock signal to the satellite communication module. That is, when the clock request signal is a high level, the clock output port of the clock output circuit has a clock signal output; when the clock request signal is a low level, the clock output port of the clock output circuit has no clock signal output.

[0047] The clock buffer power supply is connected to the internal power supply of the GPS module 100, and the size of the clock buffer power supply is the size of the clock output amplitude. Specifically, when a high-level signal is input to the front end of the clock buffer, the output end of the clock buffer also outputs a high level, and the output high level amplitude is the size of the clock buffer power supply. When a low level signal is input to the front end of the clock buffer, the output end of the clock buffer also outputs a low level, that is, 0V.

[0048] Thus, in this embodiment, the clock request signal sent by the satellite communication module can be used to control the output of the clock signal of the clock output circuit, and the internal power supply of the GPS module 100 can be used to power the clock buffer, thereby enhancing the driving capability of the clock output.

[0049] Alternatively, if Figure 3 As shown, the clock output circuit further includes a phase-locked loop (PLL) 13, the second end of the frequency offset compensation circuit 111 is connected to the input end of the PLL 13, and the output end of the PLL 13 is connected to the drain of the first switch Q1.

[0050] That is, in some embodiments, Figure 2 On the basis of the embodiment shown, in order to avoid the influence of frequent switching of the first switch Q1 on the original clock architecture, a PLL X is connected in series on the clock branch. The basic structure of the PLL X is as follows: Figure 4As shown, after the clock signal is input to PLL13, it will pass through the phase detector (PD) and the charge pump (CP) will output a modulation level. After passing through the low-pass filter (Loop Filter), the modulation level controls the voltage-controlled oscillator (VCO) to output the clock frequency. Therefore, the clock signals at the input and output ends of PLL13 are not connected, but converted into a level form in the middle. Only the switch of the charge pump CP needs to be controlled to control the output. Therefore, whether PLL13 outputs the clock signal will not be turned on and off on the input path, thereby avoiding the impact on the original input clock architecture.

[0051] In addition, the multiple (1 / N) of the feedback divider inside PLL13 is set to 1, so PLL13 inputs the output frequency to the phase detector PD without frequency division, and the output frequency is consistent with the output frequency of the frequency offset compensation circuit 111.

[0052] In this way, through this implementation, the impact of the newly added clock output circuit at the back end on the original clock architecture in the GPS module is reduced.

[0053] Alternatively, if Figure 5 As shown, the frequency deviation control unit 11 is a path enabling control unit 112, the clock adjustment unit 12 includes a clock buffer Clock buffer, the power supply end of the clock buffer Clock buffer is connected to the power supply of the GPS module 100; the first end of the path enabling control unit 112 is connected to the external temperature compensated crystal oscillator TCXO;

[0054] Among them, the third end of the path enable control unit 112 is connected to the satellite communication module for receiving a clock request signal sent by the satellite communication module; and / or, the fourth end of the path enable control unit 112 is used to access a system on chip (SoC) control signal, and the SoC control signal is used to control whether the path enable control unit 112 outputs a clock signal to the clock adjustment unit 12.

[0055] In some embodiments, some GPS modules such as GPS chips may not use the clock signal provided by the platform clock IC, but directly use an external TCXO. Since the clock frequency deviation output by the TCXO can meet the frequency deviation requirement of the GPS module 100 such as the GPS IC, the GPS module 100 does not need a frequency deviation compensation circuit, and the frequency deviation control unit 11 is a path enable control unit 112.

[0056] In this embodiment, the GPS IC using the system clock can also move the TCXO originally mounted on the satellite communication module to one end of the GPS IC, and output the clock to the satellite communication IC through the GPS IC. The cost is equivalent to that of the TCXO mounted on the satellite communication module, which saves the cost of the TCXO mounted on the satellite communication IC, but the GPS cold start experience is better, and the TCXO can be started as soon as it is powered on.

[0057] The frequency deviation standard of the clock signal output by the TCXO can also meet the clock requirement of the satellite communication module, so the satellite communication module and the GPS module 100 such as the GPS IC can share the clock signal of the TCXO.

[0058] In specific implementation, a path enabling control unit 112 is added inside the GPS module 100, such as Figure 5 As shown, the module input is the clock signal of TCXO, and there are two output paths, one of which is provided to the GPS module 100 itself, and the other is provided to the satellite clock output path. There are two control schemes for whether the clock signal provided to the satellite clock output path is output: ① Controlled by SoC, when the system determines that the satellite communication module needs to work, SoC sends a control signal to the path enable control unit 112, opens the clock output path, and outputs the clock signal to the satellite communication module through the GPS module 100; ② Controlled by the clock request signal sent by the satellite communication module, that is, the satellite communication module actively sends a clock request signal to the GPS module 100, and the clock request signal is given to the path enable control unit 112, opens the clock output path, and the GPS module 100 outputs the clock signal to the satellite communication module.

[0059] The working principle of the clock buffer circuit is the same as Figure 2 or Figure 3 The embodiments shown are consistent and will not be described in detail here.

[0060] Thus, in this implementation, for a GPS module using an external TCXO, the cost of an external TCXO for a satellite communication module is eliminated, and the GPS module is directly used to output the clock to the satellite communication module. For a GPS module currently using a system clock, the TCXO originally externally mounted on the satellite communication module can be moved to one end of the GPS module, and the clock can be output to the satellite communication module through the GPS IC, making the GPS cold start experience better.

[0061] Alternatively, if Figure 3 and Figure 5As shown, the clock adjustment unit 12 may also include a MOS array, a first end of the MOS array is connected to the power supply of the GPS module 100, a second end of the MOS array is connected to the power supply end of the clock buffer Clock buffer, and the MOS array is used to control the driving current of the clock signal output by the clock buffer Clock buffer.

[0062] That is, in some embodiments, a MOS array can be added to the clock adjustment unit 12, and the MOS array is controlled by the GPS module 100. The MOS array is connected to the clock buffer for power supply, and the driving current of the clock output can be controlled by the number of MOS tubes turned on by the MOS array to adapt to the satellite communication module.

[0063] Specifically, the magnitude of the clock output driving current of the clock output circuit needs to be adjusted according to the PCB routing and the clock input requirements of the satellite communication module.

[0064] For example, when the rising edge / falling edge of the clock signal input to the satellite communication module is too slow due to PCB routing and does not meet the requirements of the satellite communication module, the clock output drive strength of the GPS module 100 can be strengthened, such as increasing the number of MOS tubes turned on in the MOS array to speed up the rising edge / falling edge of the clock signal to meet the clock requirements of the satellite communication module.

[0065] For another example, when the rising edge / falling edge of the clock signal input to the satellite communication module is too fast, or an overshoot / undershoot occurs, the clock output drive strength of the GPS module 100 can be reduced, such as reducing the number of MOS tubes turned on in the MOS array, slowing down the rising edge / falling edge of the clock signal, and reducing the overshoot / undershoot to meet the clock requirements of the satellite communication module.

[0066] Thus, in this implementation, by adding an output drive strength control circuit to the newly added clock adjustment unit, it is possible to facilitate adaptation to the clock input requirement of the external satellite communication module.

[0067] Optionally, the drain of each MOS tube in the MOS array is connected to the power supply of the GPS module 100, the source of each MOS tube is connected to the power supply terminal of the clock buffer, and the gate of each MOS tube is connected to the controller in the GPS module 100, and the controller is used to output a control signal to control the number of MOS tubes turned on in the MOS array.

[0068] In some embodiments, the third end of the MOS array may be connected to a controller in the GPS module 100, and the controller outputs an appropriate control signal to control the conduction state of each MOS transistor in the MOS array. Specifically, Figure 7 As shown, the drain of each MOS tube in the MOS array is connected to the power supply of the GPS module 100, the source of each MOS tube is connected to the power supply of the power supply end of the clock buffer, and the gate of each MOS tube is connected to the controller in the GPS module 100. In this way, the conduction state of each MOS tube can be controlled by controlling the gate level of each MOS tube. For example, the controller outputs a high-level signal to the gate of the MOS tube that needs to be turned on in the MOS array to turn on these MOS tubes, and outputs a low-level signal to the gate of the MOS tube that does not need to be turned on in the MOS array to turn off these MOS tubes, thereby controlling the number of MOS tubes turned on in the MOS array, and the specific number of turned on can be determined according to the driving current intensity of the required clock signal. When the required driving current intensity is greater, the number of MOS tubes turned on in the MOS array can be controlled to be greater.

[0069] Through this implementation, the number of MOS tubes turned on in the MOS array can be effectively controlled, thereby controlling the driving strength of the clock signal output to the satellite communication module to ensure that the clock requirements of the satellite communication module are met.

[0070] Optionally, the second end of the frequency deviation control unit 11 is also connected to a plurality of PLL units in the GPS module 100 .

[0071] In some embodiments, Figures 1 to 3 and Figure 5 As shown, the second end of the frequency deviation control unit 11 can also be connected to multiple PLL units in the GPS module 100, such as PLL1, PLL2...PLLn, to provide a clock signal to the GPS module 100 itself to achieve the GPS positioning function.

[0072] In addition, it should be noted that, for the above embodiment, when the satellite communication module can use a sine wave signal or a clock signal that does not require a strong drive, the design of the buffer circuit can be omitted. When the satellite communication module needs to use a square wave signal or has requirements for the clock signal drive strength, the buffer circuit is designed according to Figure 2 , Figure 3 or Figure 5 The logic of the described embodiment works.

[0073] In an embodiment of the present application, a clock output circuit is provided in the GPS module, and the clock output circuit includes: a frequency deviation control unit, wherein the first end of the frequency deviation control unit is used to access the clock signal, and the second end of the frequency deviation control unit is used to output the first clock signal of the frequency deviation adaptation GPS module and the satellite communication module; a clock adjustment unit, wherein the input end of the clock adjustment unit is connected to the second end of the frequency deviation control unit, the clock adjustment unit is used to enhance the driving current of the first clock signal output by the frequency deviation control unit, and the output end of the clock adjustment unit is used to output the first clock signal after the enhanced driving current to the satellite communication module. In this way, by adding a clock path to the GPS module, compensating the frequency deviation of the clock signal through the frequency deviation control unit, and then enhancing the driving current of the clock signal through the clock adjustment unit and outputting it to the satellite communication module, the cost of externally plugging a crystal oscillator in the satellite communication module can be saved.

[0074] The present application also provides an electronic device, including the GPS module and the satellite communication module described in the above embodiment. The specific implementation of this embodiment can refer to the relevant introduction of the above embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0075] See also Figure 8 , Figure 8 The flowchart of the clock signal output method provided in the embodiment of the present application is executed by the electronic device described in the above embodiment, such as Figure 8 As shown, the method comprises the following steps:

[0076] Step 801: When it is determined that the satellite communication module needs to work, the frequency deviation control unit outputs a first clock signal of the frequency deviation adaptation GPS module and the satellite communication module to the clock adjustment unit;

[0077] Step 802: Enhance the driving current of the first clock signal by the clock adjustment unit, and output the first clock signal with the enhanced driving current to the satellite communication.

[0078] Optionally, when the frequency deviation control unit is a frequency deviation compensation circuit and the clock adjustment unit includes a first MOS transistor and a clock buffer, step 801 includes:

[0079] When a clock request signal sent by the satellite communication module is received, the first MOS tube is controlled to be turned on, and the first clock signal is output to the clock buffer through the frequency deviation control unit.

[0080] Optionally, when the frequency deviation control unit is a path enabling control unit and the clock adjustment unit includes a clock buffer, step 801 includes:

[0081] When receiving a clock request signal sent by the satellite communication module, outputting the first clock signal to the clock buffer through the frequency deviation control unit;

[0082] And / or, when a SoC control signal is received, the first clock signal is output to the clock buffer through the frequency deviation control unit.

[0083] Optionally, in the case where the clock adjustment unit includes a MOS array, before outputting the enhanced first clock signal to the satellite communication, the method further includes:

[0084] According to the clock input requirement of the satellite communication module, the number of MOS tubes turned on in the MOS array is controlled so that the driving current of the clock signal output by the clock adjustment unit meets the clock input requirement of the satellite communication module;

[0085] After outputting the enhanced first clock signal to the satellite communication module, the method further includes:

[0086] In the case where the rising edge or the falling edge of the first clock signal output to the satellite communication module is too slow, the number of MOS transistors turned on in the MOS array is increased to enhance the driving current of the first clock signal output by the clock adjustment unit;

[0087] When the rising edge or falling edge of the first clock signal output to the satellite communication module is too fast, the number of MOS tubes turned on in the MOS array is reduced to reduce the driving current of the first clock signal output by the clock adjustment unit.

[0088] It should be noted that this embodiment is a method embodiment corresponding to the aforementioned clock output circuit embodiment. Its specific implementation method can refer to the relevant introduction of the aforementioned embodiment. To avoid repetition, it will not be described again here.

[0089] In the embodiment of the present application, when it is determined that the satellite communication module needs to work, the frequency deviation control unit outputs the first clock signal of the satellite communication module to the clock adjustment unit, and the driving current of the first clock signal is enhanced by the clock adjustment unit, and the first clock signal with enhanced driving current is output to the satellite communication. In this way, by adding a clock path to the GPS module, compensating the frequency deviation of the clock signal by the frequency deviation control unit, and then enhancing the driving current of the clock signal by the clock adjustment unit and outputting it to the satellite communication module, the cost of external crystal oscillator in the satellite communication module can be saved.

[0090] The clock signal output method provided in the embodiment of the present application can be executed by a clock signal output device. In the embodiment of the present application, the clock signal output device provided in the embodiment of the present application is illustrated by taking the clock signal output method executed by the clock signal output device as an example.

[0091] See also Fig. 9 , Fig. 9 The clock signal output device provided in the embodiment of the present application is a schematic diagram of the structure of the clock signal output device, which is arranged in the electronic device described in the above embodiment, such as Fig. 9 As shown, the clock signal output device 900 includes:

[0092] The frequency deviation control unit 901 is used to output the first clock signal of the frequency deviation adaptation GPS module and the satellite communication module to the clock adjustment unit when it is determined that the satellite communication module needs to work;

[0093] The clock adjustment unit 902 is used to enhance the driving current of the first clock signal and output the first clock signal with the enhanced driving current to the satellite communication.

[0094] Optionally, when the frequency deviation control unit 901 is a frequency deviation compensation circuit and the clock adjustment unit 902 includes a first MOS tube and a clock buffer, the first MOS tube is turned on when receiving a clock request signal sent by the satellite communication module, and the frequency deviation control unit 901 outputs the first clock signal to the clock buffer.

[0095] Optionally, when the frequency deviation control unit is a path enabling control unit and the clock adjustment unit includes a clock buffer, the frequency deviation control unit 902 outputs the first clock signal to the clock buffer when receiving a clock request signal sent by the satellite communication module;

[0096] And / or, the frequency deviation control unit 902 outputs the first clock signal to the clock buffer when receiving the SoC control signal.

[0097] Optionally, the clock signal output device 900 further includes:

[0098] A control module, used to control the number of MOS transistors turned on in the MOS array according to the clock input requirement of the satellite communication module, so that the driving current of the clock signal output by the clock adjustment unit 902 meets the clock input requirement of the satellite communication module;

[0099] The control module is further configured to increase the number of MOS transistors turned on in the MOS array to enhance the driving current of the first clock signal output by the clock adjustment unit 902 when the rising edge or the falling edge of the first clock signal output to the satellite communication module is too slow;

[0100] The control module is also used to reduce the number of MOS tubes turned on in the MOS array when the rising edge or falling edge of the first clock signal output to the satellite communication module is too fast, so as to reduce the driving current of the first clock signal output by the clock adjustment unit 902.

[0101] In the embodiment of the present application, when the clock signal output device 900 determines that the satellite communication module needs to work, the frequency deviation control unit outputs the first clock signal of the satellite communication module to the clock adjustment unit; the driving current of the first clock signal is enhanced by the clock adjustment unit, and the first clock signal with enhanced driving current is output to the satellite communication. In this way, by adding a clock path to the GPS module, compensating the frequency deviation of the clock signal by the frequency deviation control unit, and then enhancing the driving current of the clock signal by the clock adjustment unit and outputting it to the satellite communication module, the cost of external crystal oscillator in the satellite communication module can be saved.

[0102] The clock signal output device in the embodiment of the present application can be an electronic device, or a component in the electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal, or other devices other than a terminal. Exemplarily, the electronic device can be a mobile phone, a tablet computer, a laptop computer, a PDA, a vehicle-mounted electronic device, a mobile Internet device (Mobile Internet Device, MID), an augmented reality (augmented reality, AR) / virtual reality (virtual reality, VR) device, a robot, a wearable device, an ultra-mobile personal computer (ultra-mobile personal computer, UMPC), a netbook or a personal digital assistant (personal digital assistant, PDA), etc., and can also be a server, a network attached storage (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), a teller machine or a self-service machine, etc., which is not specifically limited in the embodiment of the present application.

[0103] The clock signal output device in the embodiment of the present application may be a device having an operating system. The operating system may be an Android operating system, an iOS operating system, or other possible operating systems, which are not specifically limited in the embodiment of the present application.

[0104] The clock signal output device provided in the embodiment of the present application can achieve Figure 7 The various processes implemented by the method embodiment can achieve the same technical effect, and to avoid repetition, they will not be described here.

[0105] Alternatively, if Fig.10 As shown, an embodiment of the present application also provides an electronic device 1000, including a processor 1001 and a memory 1002, wherein the memory 1002 stores programs or instructions that can be executed on the processor 1001, and when the program or instructions are executed by the processor 1001, the various steps of the above-mentioned clock signal output method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they are not repeated here.

[0106] It should be noted that the electronic devices in the embodiments of the present application include the mobile electronic devices and non-mobile electronic devices mentioned above.

[0107] Fig.11 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of the present application.

[0108] The electronic device 1100 includes but is not limited to: a radio frequency unit 1101, a network module 1102, an audio output unit 1103, an input unit 1104, a sensor 1105, a display unit 1106, a user input unit 1107, an interface unit 1108, a memory 1109, a processor 1110 and the GPS module 1111 described in the aforementioned embodiments and other components.

[0109] Those skilled in the art will appreciate that the electronic device 1100 may also include a power source (such as a battery) for supplying power to each component, and the power source may be logically connected to the processor 1110 through a power management system, thereby implementing functions such as managing charging, discharging, and power consumption management through the power management system. Fig.11 The electronic device structure shown in the figure does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently, which will not be described in detail here.

[0110] The processor 1110 is configured to:

[0111] When it is determined that the satellite communication module needs to work, the frequency deviation control unit outputs a first clock signal whose frequency deviation is adapted to the GPS module and the satellite communication module to the clock adjustment unit;

[0112] The driving current of the first clock signal is enhanced by the clock adjustment unit, and the first clock signal with the enhanced driving current is output to the satellite communication.

[0113] Optionally, when the frequency deviation control unit is a frequency deviation compensation circuit and the clock adjustment unit includes a first MOS tube and a clock buffer, the processor 1110 is further used to control the first MOS tube to be turned on when receiving a clock request signal sent by the satellite communication module, and output the first clock signal to the clock buffer through the frequency deviation control unit.

[0114] Optionally, when the frequency deviation control unit is a path enabling control unit and the clock adjustment unit includes a clock buffer, the processor 1110 is further configured to output the first clock signal to the clock buffer through the frequency deviation control unit when receiving a clock request signal sent by the satellite communication module;

[0115] And / or, when a SoC control signal is received, the first clock signal is output to the clock buffer through the frequency deviation control unit.

[0116] Optionally, the processor 1110 is further configured to:

[0117] According to the clock input requirement of the satellite communication module, the number of MOS tubes turned on in the MOS array is controlled so that the driving current of the clock signal output by the clock adjustment unit meets the clock input requirement of the satellite communication module;

[0118] In the case where the rising edge or the falling edge of the first clock signal output to the satellite communication module is too slow, the number of MOS transistors turned on in the MOS array is increased to enhance the driving current of the first clock signal output by the clock adjustment unit;

[0119] When the rising edge or falling edge of the first clock signal output to the satellite communication module is too fast, the number of MOS tubes turned on in the MOS array is reduced to reduce the driving current of the first clock signal output by the clock adjustment unit.

[0120] It should be understood that in the embodiment of the present application, the input unit 1104 may include a graphics processor (Graphics Processing Unit, GPU) 11041 and a microphone 11042, and the graphics processor 11041 processes the image data of the static picture or video obtained by the image capture device (such as a camera) in the video capture mode or the image capture mode. The display unit 1106 may include a display panel 11061, and the display panel 11061 may be configured in the form of a liquid crystal display, an organic light emitting diode, etc. The user input unit 1107 includes a touch panel 11071 and at least one of other input devices 11072. The touch panel 11071 is also called a touch screen. The touch panel 11071 may include two parts: a touch detection device and a touch controller. Other input devices 11072 may include, but are not limited to, a physical keyboard, function keys (such as volume control keys, switch keys, etc.), a trackball, a mouse, and a joystick, which will not be repeated here.

[0121] The memory 1109 can be used to store software programs and various data. The memory 1109 may mainly include a first storage area for storing programs or instructions and a second storage area for storing data, wherein the first storage area may store an operating system, an application program or instructions required for at least one function (such as a sound playback function, an image playback function, etc.), etc. In addition, the memory 1109 may include a volatile memory or a non-volatile memory, or the memory 1109 may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDRSDRAM), an enhanced synchronous dynamic random access memory (ESDRAM), a synchronous link dynamic random access memory (SLDRAM) and a direct memory bus random access memory (DRRAM). The memory 1109 in the embodiment of the present application includes but is not limited to these and any other suitable types of memory.

[0122] The processor 1110 may include one or more processing units; optionally, the processor 1110 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and application programs, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It is understandable that the modem processor may not be integrated into the processor 1110.

[0123] An embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, the various processes of the above-mentioned clock signal output method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0124] The processor is the processor in the electronic device described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a magnetic disk or an optical disk.

[0125] An embodiment of the present application further provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned clock signal output method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0126] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0127] An embodiment of the present application provides a computer program product, which is stored in a storage medium. The program product is executed by at least one processor to implement the various processes of the above-mentioned clock signal output method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0128] It should be noted that, in this article, the terms "comprise", "include" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, and may also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method may be performed in an order different from that described, and various steps may also be added, omitted, or combined. In addition, the features described with reference to certain examples may be combined in other examples.

[0129] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a computer software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present application.

[0130] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A global positioning system GPS module, characterized in that: The GPS module is provided with a clock output circuit, and the clock output circuit comprises: A frequency deviation control unit, wherein a first end of the frequency deviation control unit is used to access a clock signal, and a second end of the frequency deviation control unit is used to output a first clock signal whose frequency deviation is adapted to the GPS module and the satellite communication module; A clock adjustment unit, wherein the input end of the clock adjustment unit is connected to the second end of the frequency deviation control unit, the clock adjustment unit is used to enhance the driving current of the first clock signal output by the frequency deviation control unit, and the output end of the clock adjustment unit is used to output the first clock signal after the enhanced driving current to the satellite communication module.

2. The GPS module according to claim 1, characterized in that: The frequency deviation control unit is a frequency deviation compensation circuit, the clock adjustment unit includes a first switch and a clock buffer, the first end of the frequency deviation compensation circuit is used to access the clock signal provided by the clock chip, the third end of the frequency deviation compensation circuit is used to receive crystal temperature data, the frequency deviation compensation circuit is used to adjust the frequency deviation of the clock signal according to the received crystal temperature data to obtain a first clock signal whose frequency deviation is adapted to the GPS module and the satellite communication module, and the first switch is used to control the on-off between the frequency deviation compensation circuit and the clock buffer.

3. The GPS module according to claim 2, characterized in that: The first switch is a first field effect transistor MOS tube, the second end of the frequency deviation compensation circuit is connected to the drain of the first MOS tube, the gate of the first MOS tube is connected to the satellite communication module, and is used to receive the clock request signal sent by the satellite communication module, the source of the first MOS tube is connected to the input end of the clock buffer, and the power supply end of the clock buffer is connected to the power supply of the GPS module; Wherein, the first MOS transistor is in an on state when receiving a clock request signal sent by the satellite communication module; the first MOS transistor is in an off state when not receiving a clock request signal sent by the satellite communication module.

4. The GPS module according to claim 2 or 3, characterized in that: The clock output circuit further includes a phase-locked loop (PLL), the second end of the frequency offset compensation circuit is connected to the input end of the PLL, and the output end of the PLL is connected to the drain of the first switch.

5. The GPS module according to claim 1, characterized in that: The frequency deviation control unit is a path enabling control unit, the clock adjustment unit includes a clock buffer, the power supply end of the clock buffer is connected to the power supply of the GPS module; the first end of the path enabling control unit is connected to an external temperature compensated crystal oscillator TCXO; Among them, the third end of the path enable control unit is connected to the satellite communication module for receiving a clock request signal sent by the satellite communication module; and / or, the fourth end of the path enable control unit is used to access a chip-on-chip SoC control signal, and the SoC control signal is used to control whether the path enable control unit outputs a clock signal to the clock adjustment unit.

6. The GPS module according to any one of claims 2 to 5, characterized in that: The clock adjustment unit also includes a MOS array, a first end of the MOS array is connected to the power supply of the GPS module, a second end of the MOS array is connected to the power supply end of the clock buffer, and the MOS array is used to control the driving current of the clock signal output by the clock buffer.

7. The GPS module according to claim 6, characterized in that: The drain of each MOS tube in the MOS array is connected to the power supply of the GPS module, the source of each MOS tube is connected to the power supply terminal of the clock buffer, and the gate of each MOS tube is connected to the controller in the GPS module, and the controller is used to output a control signal to control the number of MOS tubes turned on in the MOS array.

8. The GPS module according to any one of claims 2 to 4, characterized in that: The first end of the frequency deviation compensation circuit is connected to the clock end of the clock chip, the clock chip is connected to a thermistor, the third end of the frequency deviation compensation circuit is connected to the output end of a digital-to-analog converter ADC in the clock chip, the input end of the ADC is connected to the thermistor, and the ADC is used to convert the NTC resistance value inside the thermistor into temperature data.

9. The GPS module according to any one of claims 1 to 5, characterized in that: The second end of the frequency deviation control unit is also connected to a plurality of PLLs in the GPS module.

10. An electronic device, characterized in that: The invention comprises a satellite communication module and the GPS module according to any one of claims 1 to 9.

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