Internal voltage generation circuit and electronic device including same

Abstract

The invention relates to an internal voltage generation circuit and an electronic device including the same. The electronic device includes an internal voltage generation circuit configured to detect a voltage level of an internal voltage generated by the internal voltage generation circuit. The internal voltage generation circuit is further configured to generate a drive code that determines a magnitude of the generated internal voltage together with the drive clock. The drive code may be reset in response to the internal voltage. The electronic device also includes a load circuit powered by the generated internal voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0132065, filed on October 4, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to electronic devices and more particularly to internal voltage generation circuits for memory devices and other electronic semiconductor devices. Background Art

[0004] Electronic devices such as cellular phones, laptops and computers are equipped with internal voltage generating circuits that provide power to the devices. As the name implies, an internal voltage generating circuit is an electronic circuit that is located within or is a part of an electronic device.

[0005] As used herein, an internal voltage generating circuit is composed of electronic components such as Figure 2 The internal voltage generating circuit is a circuit composed of electronic components (such as those depicted in FIG. 1 ) configured to provide a current that is transmitted or output from the internal voltage generating circuit at one or more voltage levels. The voltage level is usually a voltage level required by the electronic device in which the internal voltage generating circuit is located.

[0006] When the electrical load (load) on the internal voltage generating circuit increases, such as occurs when an electronic device such as a processor or storage device operates at an increased speed, or when its surrounding environment changes, a voltage loss, i.e., a voltage sag, may occur due to the inability of the internal voltage generating circuit to increase its output accordingly. Therefore, a voltage sag is considered in this article to be a significant magnitude reduction in the magnitude of the output voltage level that suffers or decreases the functional operation of the device. In other words, when the voltage level of the internal voltage drops, errors may occur in one or more operations performed by the electronic device receiving the internally generated voltage. Summary of the invention

[0007] According to an embodiment of the present disclosure, an electronic device may include an internal voltage generating circuit, which is configured to detect an internal voltage and generate a driving code in response to a driving clock. The internal voltage generating circuit is also configured to drive or generate an internal voltage in response to the driving code, and the driving code is reset in response to the generated internal voltage and in response to a load circuit, which is configured to receive the internally generated voltage required to perform an internal operation.

[0008] According to another embodiment of the present disclosure, an electronic device may include an internal voltage generating circuit configured to detect a voltage level of an internal voltage, generate a driving code in response to a driving clock, and generate an internal voltage in response to the driving code, the driving code being reset in response to the internal voltage and in response to an operation flag and a load circuit, the load circuit being configured to receive the internal voltage to perform an internal operation. The operation flag may be generated in relation to the internal operation of the load circuit.

[0009] According to another embodiment of the present disclosure, an internal voltage generating circuit may include: a drive control circuit configured to generate a drive control signal in response to a reference voltage and a feedback voltage generated from the internal voltage; a code generating circuit configured to generate a drive code in response to the drive control signal; and a drive circuit configured to drive the internal voltage in response to the drive code. The drive code may be reset when the feedback voltage is generated at a voltage level equal to or greater than a voltage level of the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0011] Figure 2 It shows that according to Figure 1 Schematic block diagram of a configuration of an example of an internal voltage generating circuit included in an electronic device shown.

[0012] Figure 3 It shows the operation Figure 2 A flow chart of the steps of a method for generating an internal voltage circuit is shown.

[0013] Figure 4 and Figure 5 It is shown Figure 2 A timing diagram of the operation of the internal voltage generating circuit is shown.

[0014] Figure 6 is a block diagram illustrating a configuration of an electronic device according to another embodiment of the present disclosure.

[0015] Figure 7 It shows that according to Figure 6 Schematic block diagram of a configuration of an example of an internal voltage generating circuit included in an electronic device shown.

[0016] Figure 8 It shows the operation Figure 7 A flow chart of another method of an internal voltage generating circuit is shown.

[0017] Fig. 9 It is shown Figure 7 A timing diagram of the operation of the internal voltage generating circuit is shown. DETAILED DESCRIPTION

[0018] In the description of the following embodiments, when a parameter is referred to as "predetermined", it may be intended to mean that when the parameter is used in a process or algorithm, the value of the parameter is predetermined. The value of the parameter may be set at the start of the process or algorithm, or may be set during an interval of execution of the process or algorithm.

[0019] It should be understood that although the terms "first", "second", "third", etc. are used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element and are not intended to imply the order or quantity of the elements. Therefore, without departing from the teachings of the present disclosure, the first element in some embodiments may be referred to as the second element in other embodiments.

[0020] In addition, it will be understood that when an element is referred to as being "connected" or "coupled" to another element, the element may be directly connected or coupled to the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0021] In various preferred embodiments, a logic "high" level and a logic "low" level may be used to describe the relative voltage levels of an electrical signal. A signal having a logic "high" level may be a positive voltage greater than a predetermined volt, while a signal having a logic "low" level may be a voltage less than or equal to a predetermined volt. In alternative embodiments, the logic "high" level may be set to a voltage level less than a predetermined volt, while the logic low level may be a predetermined volt. In other words, the actual voltage of the logic level is a design choice and may be set to be different or opposite as desired for a particular embodiment. For example, in an alternative embodiment using negative logic, a particular signal having a logic "high" voltage level in one embodiment may be set to have a logic "low" voltage level in another embodiment.

[0022] The term "logical bit group" may refer to a group of binary digits, i.e., bits, each of which has its own value. Therefore, a logical bit group is a group of bits; therefore, the group of bits has a combination of logic levels. When the logic level of each bit included in the signal changes, the logical bit group of the signal may be set differently. For example, when the signal includes two bits, when the logic level of each of the two bits included in the signal is "logic low level, logic low level", the logical bit group of the signal may be set to a first logical bit group, and when the logic level of each of the two bits included in the signal is "logic low level and logic high level", the logical bit group of the signal may be set to a second logical bit group.

[0023] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments described herein are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0024] Figure 1 is a block diagram showing the configuration of the electronic device 1 according to an embodiment of the present disclosure. Figure 1 The electronic device 1 shown in FIG. 1 may include an internal voltage generating circuit (VINT GEN) 11 and a load circuit 13 .

[0025] The internal voltage generating circuit 11 may be configured to detect the voltage level of its output voltage VINT (which is considered as the internally generated voltage in this document). VINT is output from the internal voltage generating circuit 11 and drives the load circuit 13. When the internal voltage VINT needs to be adjusted in response to the reference voltage VREF, the internal voltage generating circuit 11 may respond to the drive clock ( Figure 2 DCLK in) generates driver code ( Figure 2 DR_CD in ), and according to the driver code ( Figure 2 The internal voltage generating circuit 11 can adjust the amplitude of the internal voltage VINT by using the drive clock ( Figure 2 The driver code generated by DCLK in Figure 2 When the internal voltage VINT needs to be reset as determined by the reference voltage VREF, the internal voltage generating circuit 11 can stop driving the clock ( Figure 2 DCLK in the generation and reset of the driver code ( Figure 2 DR_CD in the MOSFET, thereby reducing current consumption.

[0026] The internal voltage generating circuit 11 can provide the internal voltage VINT to the load circuit 13. The load circuit 13 can receive the internal voltage VINT to perform various internal operations. When the load circuit 13 draws current from the internal voltage generating circuit, as occurs when the load circuit 13 is connected and operating, the voltage level of the internal voltage VINT will decrease. The magnitude of the reduction in the internal voltage VINT will generally correspond to the load current ( ) drawn by the load circuit 13 from the output node nd_OUT (through which the internal voltage VINT is output). Figure 2 The amplitude of 121).

[0027] Figure 2 It shows that according to Figure 1 1 is a block diagram of a configuration of an internal voltage generating circuit 11A of an example of the internal voltage generating circuit 11 shown.

[0028] like Figure 2As shown, the internal voltage generating circuit 11A may include a driving control circuit 111 , an oscillator (OSC) 113 , a code generating circuit (CD GEN) 115 , a driving circuit 117 , and a feedback voltage generating circuit (VFEED GEN) 119 .

[0029] The drive control circuit 111 may include a comparison circuit 125, preferably implemented as a comparator, whose output is a binary value comparison signal COM. The drive control circuit 111 may also include a drive control signal generation circuit 127, which may be implemented as a non-inverting unity gain operational amplifier.

[0030] The comparison circuit 125 may generate a comparison signal COM in response to the amplitude difference between the reference voltage VREF and the feedback voltage VFEED. The comparison circuit 125 may compare the reference voltage VREF and the feedback voltage VFEED, and generate a comparison signal COM having a high logic level or a low logic level in response to the comparison of the amplitudes of the two input signals with each other. As an example, when the feedback voltage VFEED is at a voltage level less than the voltage level of the reference voltage VREF, the comparison circuit 125 may generate a "high" logic level COM output signal. When the amplitude of the feedback voltage VFEED is equal to or greater than the amplitude of the reference voltage VREF, the comparison circuit 125 may generate a "low" logic level COM output signal. The drive control signal generation circuit 127 may receive the comparison signal COM from the electrically connected comparison circuit 125, and generate a drive control signal DR_CTR in response to the comparison signal COM.

[0031] The drive control signal generating circuit 127 may generate a drive control signal DR_CTR having the same logic level as the comparison signal COM. The drive control circuit 111 may compare the reference voltage VREF with the feedback voltage VFEED to detect whether the internal voltage VINT needs to be adjusted or whether the internal voltage VINT needs to be reset. The VREF voltage and the VFEED voltage are also compared to each other to generate a drive control signal DR_CTR having a logic level according to the detection result. As an example, the drive control circuit 111 may generate a drive control signal DR_CTR of a logic "high" level when the internal voltage VINT needs to be adjusted, and generate a drive control signal DR_CTR of a logic "low" level when the internal voltage VINT needs to be reset. The drive control signal generating circuit 127 may also generate a drive control signal DR_CTR so that the drive control signal DR_CTR has a voltage level different from the comparison signal COM voltage level. The drive control circuit 111 may be electrically connected to both the oscillator 113 and the code generating circuit 115 so as to provide the drive control signal DR_CTR to both the oscillator 113 and the code generating circuit 115.

[0032] The oscillator 113 may receive a drive control signal DR_CTR from the drive control circuit 111, and generate a drive clock DCLK in response to the drive control signal DR_CTR. The oscillator 113 may determine whether to generate the drive clock DCLK in response to the logic level of the drive control signal DR_CTR. As an example, when the drive control signal DR_CTR of a logic "high" level is generated, the oscillator 113 may activate the drive clock DCLK. As another example, when the drive control signal DR_CTR of a logic "low" level is generated, the oscillator 113 may deactivate the drive clock DCLK. The oscillator 113 may be electrically connected to the code generation circuit 115 to supply the drive clock DCLK to the code generation circuit 115.

[0033] The code generation circuit 115 may receive a drive control signal DR_CTR from the drive control circuit 111. It may also receive a drive clock DCLK from the oscillator 113. From these two signals, it may generate a drive code DR_CD. Thus, the code generation circuit generates a drive code DR_CD in response to both the drive control signal DR_CTR and the drive clock DCLK.

[0034] The code generation circuit 115 can generate the driving code DR_CD or reset the driving code DR_CD in response to the driving clock DCLK and in response to the logic level of the driving control signal DR_CTR. For example, when the driving control signal DR_CTR is logic 1, that is, at a "high" logic level, the code generation circuit 115 can count the driving clock DCLK pulses to generate the driving code DR_CD, and then set the logic bit of the driving code DR_CD group to increase the code value, that is, increase the driving code value. As another example, when the driving control signal DR_CTR is logic zero, that is, at a logic "low" level, the code generation circuit 115 can reset the driving code DR_CD.

[0035] As a design choice, each bit constituting a group of bits including the reset driving code DR_CD may be set in various ways, ie, logic 0 or logic 1. The code generation circuit 115 may be electrically connected to the driving circuit 117 to provide the driving code DR_CD to the driving circuit 117 .

[0036] Still refer to Figure 2 The driving circuit 117 may receive the driving code DR_CD from the code generating circuit 115, and generate the internal voltage VINT in response to the value of the driving code DR_CD. The driving circuit 117 may include a plurality of voltage drivers, the number of which corresponds to the number of bits included in the driving code DR_CD. Each driving element included in the driving circuit 117 may be implemented with a transistor.

[0037] The value of the drive code DR_CD provided to the driver circuit 117 determines (i.e. controls) the amplitude of the internally generated voltage VINT output from the driver circuit 117. The drive code DR_CD is therefore considered herein to be a “drive signal” or “drive force” of the driver circuit 117. The “drive force” should therefore be interpreted as a signal that determines or controls or specifies the amplitude of the “internal voltage” output from the driver circuit 117 or generated by the driver circuit 117.

[0038] As the value of the drive code DR_CD provided to the driver circuit 117 increases, the drive signal or "driving force" sent to the internal voltage VINT increases. As a result, the increase or decrease in the driving force (i.e., the value of DR_CD) will increase or decrease the amplitude of the internally generated voltage VINT provided to the load circuit 13. When the drive code DR_CD is reset (i.e., set to zero or some other predetermined reference value), the driver circuit 117 can output a predetermined static (inactive or static) internal voltage VINT, preferably zero volts or ground potential or other reference potential. As a design choice, the initial driving force can be set at a variety of levels.

[0039] like Figure 2 As shown, VINT output from the driving circuit 117 may be electrically connected to the feedback voltage generating circuit 119 , so that the generated internal voltage VINT is supplied to the feedback voltage generating circuit 119 .

[0040] The feedback voltage generating circuit 119 can therefore generate a feedback voltage VFEED in response to the amplitude of the internal voltage VINT. In different embodiments, the feedback voltage generating circuit 119 can divide the internal voltage VINT (or multiply in different embodiments) to generate the feedback voltage VFEED. In those embodiments, the feedback voltage VFEED can be generated to have a voltage level less than or greater than the internal voltage VINT. According to an embodiment, the feedback voltage generating circuit 119 can be implemented as a buffered internal voltage VINT to generate a feedback voltage VFEED set to have the same voltage level as the internal voltage VINT. When the voltage level of the internal voltage VINT is reset, the feedback voltage generating circuit 119 can generate a feedback voltage VFEED having a reset voltage level.

[0041] The load current source 121 and the filter capacitor 123 can be electrically connected to the output node nd_OUT, and the internally generated voltage VINT and the internal source power supply current are output from the output node nd_OUT. The amount of load current provided by the load current source 121 can be determined according to the degree or amount of the voltage level reduction of the internal voltage VINT when the load circuit 13 is working.

[0042] Figure 2The internal voltage generating circuit 11A shown in the figure can reduce current consumption by stopping the driving clock DCLK and resetting the driving code DR_CD when the internal voltage VINT needs to be reset. When the internal voltage VINT needs to be adjusted, the internal voltage generating circuit 11A can increment or set the count value of the driving clock DCLK and generate the driving code DR_CD, whose logic bit group is set to set or adjust the amplitude of the internal voltage VINT, thereby simply and quickly adjusting the voltage level of the generated internal voltage VINT so as to provide the operating voltage required by the load.

[0043] Figure 3 It is shown Figure 2 The flowchart of the steps of the method of operation of the internal voltage generating circuit 11A is shown. Figure 2 and Figure 3 The operation of the internal voltage generating circuit 11A is described as follows by dividing the operation of the internal voltage generating circuit 11A into a case where the feedback voltage VFEED is generated at a voltage level smaller than the voltage level of the reference voltage VREF and a case where the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF.

[0044] Comparison of the feedback voltage VFEED with the reference voltage VREF may be performed at step S101 (S101). When the feedback voltage VFEED is a voltage smaller than the reference voltage VREF (S103, "Yes"), at step S105, the drive control circuit 111 may generate a comparison signal COM at logic 1 (i.e., logic "high" level 'H') and output a drive control signal DR_CTR at logic 1 (i.e., logic "high" level 'H'). When the drive control signal DR_CTR provided to the oscillator 113 is at logic "high" level 'H', the oscillator 113 may activate (generate) the drive clock DCLK.

[0045] When the internal voltage VINT needs to be adjusted and when the drive control signal DR_CTR is a logic "high" level 'H', the code generation circuit 115 can count or increment the drive clock DCLK to generate a drive code DR_CD, including a bit whose logic value is set to increase the code value (S107). The drive circuit 117 can receive the drive code DR_CD with an increased code value, which causes the drive circuit 117 to output the internal voltage VINT with an increased voltage level. The feedback voltage generation circuit 119 that receives VINT can then generate a feedback voltage VFEED with an increased voltage level due to the increased level of the internal voltage VINT (S109).

[0046] As a result of the comparison between the feedback voltage VFFED and the reference voltage VREF (S101), when the feedback voltage VFEED is generated at a logic level equal to or greater than the logic level of the reference voltage VREF, the drive control circuit 111 may generate a comparison signal COM and a drive control signal DR_CTR both set to have a logic "low" level 'L' (S111). When the drive control signal DR_CTR is set to have a logic "low" level 'L', the oscillator 113 may deactivate the drive clock DCLK. When the internal voltage VINT needs to be reset and the drive control signal DR_CTR is a logic "low" level 'L', the code generation circuit 115 may reset (clear) the drive code DR_CD (S113). By resetting the driving code DR_CD, the driving force of the internal voltage VINT output from the driving circuit 117 (the value of the driving code DR_CD) can be set to have an initial amplitude, so that the voltage level of the internal voltage VINT can be reset (cleared), and the voltage level of the feedback voltage VFEED generated in the feedback voltage generating circuit 119 can also be reset (cleared) (S115).

[0047] Figure 4 and Figure 5 It is shown Figure 2 1A is a timing chart showing the operation of the internal voltage generating circuit 11A.

[0048] like Figure 4 As shown, during the interval from time T11 to time T13, when the load circuit (eg Figure 1 13) in the working state and the load current of the load current source 121 is generated, the code value of the driving code DR_CD can be adjusted upward or downward (increased or decreased) according to the comparison result of the feedback voltage VFEED and the reference voltage VREF. That is, when the feedback voltage VFEED is generated at a voltage level smaller than the voltage level of the reference voltage VREF, the code value of the driving code DR_CD can be gradually increased. Therefore, the voltage level of the feedback voltage VFEED can be increased. When the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF, the driving code DR_CD can be reset (cleared), and the voltage level of the feedback voltage VFEED can also be reset. When the load current is generated, because the reset feedback voltage VFEED is set to have a voltage level smaller than the voltage level of the reference voltage VREF, the operation of sequentially increasing the code value of the driving code DR_CD can be repeated until time T13. After time T13, when no load current is generated, the voltage level of the feedback voltage VFEED can be increased once according to the driving code DR_CD, and then maintained in a reset state.

[0049] like Figure 5As shown, during the time interval between time T21 and time T23, when the load circuit (eg Figure 1 13) in the embodiment works and the load current of the load current source 121 is generated, the value of the driving code DR_CD can be adjusted upward or downward according to the comparison of the feedback voltage VFEED and the reference voltage VREF. That is, when the feedback voltage VFEED is generated at a voltage level smaller than the voltage level of the reference voltage VREF, the code value of the driving code DR_CD can be increased, thereby the feedback voltage VFEED can be increased. When the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF, the driving code DR_CD can be reset, and the voltage level of the feedback voltage VFEED can also be reset.

[0050] Because the reset feedback voltage VFEED is set to have a voltage level smaller than that of the reference voltage VREF, the operation of sequentially or incrementally increasing the code value of the driving code DR_CD may be repeated until time T23, and then a load current is generated. After time T23, when no load current is generated, the feedback voltage VFEED may be maintained in a reset state after the voltage level increases twice according to the driving code DR_CD.

[0051] Figure 6 is a block diagram showing a configuration of an electronic device 3 according to another embodiment of the present disclosure.

[0052] like Figure 6 As shown, the electronic device 3 may include the Figure 2 An internal voltage generating circuit (VINTGEN) 31 and a load circuit (LOAD CIRCUIT) 33 are shown.

[0053] When the internal voltage VINT needs to be adjusted in response to the reference voltage VREF, the internal voltage generating circuit 31 can respond to the driving clock ( Figure 7 DCLK in) to generate the drive code ( Figure 7 The internal voltage generating circuit 31 can generate the internal voltage VINT by adjusting the driving force according to the driving code DR_CD. Figure 7 The driver code generated by DCLK in Figure 7 When the internal voltage VINT needs to be reset in response to the reference voltage VREF and the operation flag PFLAG, the internal voltage generating circuit 31 can stop generating the driving clock ( Figure 7 DCLK in) and reset the driver code ( Figure 7The operation flag PFLAG may be generated before the operation of the load circuit 33 stops and the generation of the load current stops.

[0054] In an embodiment, the operation flag PFLAG may be implemented to be generated when or after the operation of the load circuit 33 stops and the load current stops. The internal voltage generating circuit 31 may supply the internal voltage VINT to the load circuit 33 .

[0055] The load circuit 33 may receive the internal voltage VINT to perform various internal operations. When the operation of the load circuit 33 is performed, the voltage level of the internal voltage VINT may decrease, and the decrease in the voltage level of the internal voltage VINT may be regarded as a load current ( Figure 7 321 in the figure), and outputs the internal voltage VINT through the output node nd_OUT.

[0056] Figure 7 It shows that according to Figure 6 1 is a block diagram of a configuration of an internal voltage generating circuit 31A of an example of the internal voltage generating circuit 31 shown.

[0057] like Figure 7 As shown, the internal voltage generating circuit 31A may include a driving control circuit 311 , an oscillator (OSC) 313 , a code generating circuit (CD GEN) 315 , a driving circuit 317 , and a feedback voltage generating circuit (VFEED GEN) 319 .

[0058] The driving control circuit 311 may include a comparison circuit 325 and a driving control signal generating circuit 327. The comparison circuit 325 may generate a comparison signal COM in response to a reference voltage VREF and a feedback voltage VFEED. The comparison circuit 325 may compare the reference voltage VREF and the feedback voltage VFEED, and generate a comparison signal COM having a logic level according to the comparison result. As an example, when the feedback voltage VFEED is generated at a voltage level less than the voltage level of the reference voltage VREF, the comparison circuit 325 may generate a comparison signal COM of a logic "high" level, and when the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF, the comparison circuit 325 may generate a comparison signal COM of a logic "low" level. The driving control signal generating circuit 327 may receive the comparison signal COM from the electrically connected comparison circuit 325, and generate a driving control signal DR_CTR in response to the comparison signal COM. The driving control signal generating circuit 327 may generate a driving control signal DR_CTR set to have the same logic level as the comparison signal COM. The drive control circuit 311 may compare the reference voltage VREF and the feedback voltage VFEED, and generate a drive control signal DR_CTR having a logic level according to the comparison result. As an example, when the feedback voltage VFEED is generated at a voltage level less than the voltage level of the reference voltage VREF, the drive control circuit 311 may generate a drive control signal DR_CTR of a logic "high" level, and when the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF, the drive control circuit 311 may generate a drive control signal DR_CTR of a logic "low" level. The drive control signal generating circuit 327 may generate a drive control signal DR_CTR driven at a voltage level different from the comparison signal COM. The drive control circuit 311 may be electrically connected to the oscillator 313 and the code generating circuit 315 to supply the drive control signal DR_CTR to the oscillator 313 and the code generating circuit 315.

[0059] The oscillator 313 may receive a drive control signal DR_CTR from the drive control circuit 311, and generate a drive clock DCLK in response to the drive control signal DR_CTR and the operation flag PFLAG. The oscillator 313 may adjust whether to generate the drive clock DCLK according to the logic level of the drive control signal DR_CTR and whether the operation flag PFLAG is generated. As an example, when the drive control signal DR_CTR of the logic "high" level is generated, the oscillator 313 may activate the drive clock DCLK. As another example, when the drive control signal DR_CTR is generated at a logic "low" level and the operation flag PFLAG is generated at a logic "high" level, the oscillator 313 may deactivate the drive clock DCLK. As yet another example, when the drive control signal DR_CTR is generated at a logic "low" level and the operation flag PFLAG is not generated at a logic "high" level, the oscillator 313 may activate the drive clock DCLK. The oscillator 313 may be electrically connected to the code generation circuit 315 to supply the drive clock DCLK to the code generation circuit 315.

[0060] The code generation circuit 315 may receive a drive control signal DR_CTR from the drive control circuit 311, receive a drive clock DCLK from the oscillator 313, and generate a drive code DR_CD in response to the drive control signal DR_CTR, the drive clock DCLK, and the operation flag PFLAG. Depending on the logic level of the drive control signal DR_CTR and whether the operation flag PFLAG is generated, the code generation circuit 315 may generate the drive code DR_CD in response to the drive clock DCLK or reset the drive code DR_CD. As an example, when a drive control signal DR_CTR of a logic "high" level is generated, the code generation circuit 315 may count the drive clock DCLK to generate a drive code DR_CD, which includes a bit whose logic bit group is set to increase the code value. As another example, when a drive control signal DR_CTR of a logic "low" level is generated and the operation flag PFLAG is generated at a logic "high" level, the code generation circuit 315 may reset the drive code DR_CD. According to an embodiment, the logic bit group of the bit included in the reset driving code DR_CD can be set in a variety of ways. As another example, when the driving control signal DR_CTR of the logic "low" level is generated and the operation flag PFLAG is not generated, the code generation circuit 315 can count the driving clock DCLK to generate the driving code DR_CD, which includes a bit whose logic bit group is set to reduce the code value. The code generation circuit 315 can be electrically connected to the driving circuit 317 to supply the driving code DR_CD to the driving circuit 317.

[0061] The driving circuit 317 may receive the driving code DR_CD from the code generating circuit 315, and drive the internal voltage VINT in response to the driving code DR_CD. The driving circuit 317 may include a plurality of driving elements corresponding to the bits included in the driving code DR_CD, respectively. Each driving element included in the driving circuit 317 may be implemented with a PMOS transistor, but this is only an example, and the present disclosure is not limited thereto. As the code value of the driving code DR_CD increases, the driving force for driving the internal voltage VINT in the driving circuit 317 may be set larger, and as the code value of the driving code DR_CD decreases, the driving force for driving the internal voltage VINT in the driving circuit 317 may be set smaller. When the driving code DR_CD is reset, the driving circuit 317 may reset the voltage level of the internal voltage VINT by setting the driving force for driving the internal voltage VINT to a preset initial driving force. The driving circuit 317 may be electrically connected to the feedback voltage generating circuit 319 to supply the internal voltage VINT to the feedback voltage generating circuit 319.

[0062] The feedback voltage generating circuit 319 may receive the internal voltage VINT from the driving circuit 317, and generate a feedback voltage VFEED in response to the internal voltage VINT. The feedback voltage generating circuit 319 may divide the internal voltage VINT to generate the feedback voltage VFEED. In this case, the feedback voltage VFEED may be set to have a voltage level less than the voltage level of the internal voltage VINT. According to an embodiment, the feedback voltage generating circuit 319 may be implemented as a buffered internal voltage VINT to generate a feedback voltage VFEED set to have the same voltage level as the internal voltage VINT. When the voltage level of the internal voltage VINT is reset, the feedback voltage generating circuit 319 may generate a feedback voltage VFEED having a reset voltage level.

[0063] The load current source 321 and the capacitor 323 may be electrically connected to an output node nd_OUT through which the internal voltage VINT is output. The current amount of the load current source 321 may be determined according to the degree to which the voltage level of the internal voltage VINT is reduced when the operation of the load circuit 33 is performed.

[0064] When the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF and the operation flag PFLAG is generated at a logic "high" level, the internal voltage generation circuit 31A can stop the generation of the drive clock DCLK and reset the drive code DR_CD to reduce current consumption. In addition, when the feedback voltage VFEED is generated at a voltage level less than the voltage level of the reference voltage VREF, the internal voltage generation circuit 31A can count the drive clock DCLK and generate a drive code DR_CD, the logic bit group of which is set to adjust the driving force of the internal voltage VINT, thereby quickly adjusting the voltage level of the internal voltage VINT.

[0065] Figure 8 It is shown Figure 7 The operation flow chart of the internal voltage generating circuit 31A is shown in FIG. Figure 7 and Figure 8 The operation of the internal voltage generating circuit 31A is described as follows by dividing the operation of the internal voltage generating circuit 31A into when the feedback voltage VFEED is generated at a voltage level less than the voltage level of the reference voltage VREF, when the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF and the operation flag PFLAG is generated, and when the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF and the operation flag PFLAG is not generated.

[0066] First, the feedback voltage VFEED and the reference voltage VREF can be generally compared with each other through a voltage comparator (S301), and the structure and operation of the voltage comparator are well known to ordinary technicians in the electronic field. As a result of the comparison, when the feedback voltage VFEED is generated at a voltage level smaller than the voltage level of the reference voltage VREF (S303, "Yes"), the drive control circuit 311 can generate a comparison signal COM and a drive control signal DR_CTR, each of which is set to have a logic "high" level 'H' (S305). When the drive control signal DR_CTR set to have a logic "high" level 'H' is received, the oscillator 313 can activate the drive clock DCLK (S307). When the drive control signal DR_CTR of the logic "high" level 'H' is generated, the code generation circuit 315 can count the drive clock DCLK to generate a drive code DR_CD, which includes a bit whose logic bit group is set to increase the code value (S307). The driving circuit 317 may receive the driving code DR_CD having an increased code value to generate an internal voltage VINT driven with an increased voltage level, and the feedback voltage generating circuit 319 may also generate a feedback voltage VFEED having an increased voltage level according to the internal voltage VINT ( S309 ).

[0067] Next, as a result of the comparison of the feedback voltage VFEED with the reference voltage VREF (S301), when the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF and the operation flag PFLAG is generated at a logic "high" level 'H' (S303 'No', S311 'Yes'), the drive control circuit 311 may generate a comparison signal COM and a drive control signal DR_CTR both set to have a logic "low" level 'L' (S313). When the drive control signal DR_CTR set to have a logic "low" level 'L' is received and the operation flag PFLAG is generated at a logic "high" level 'H', the oscillator 313 may stop sending or deactivate the drive clock DCLK (S315). When the drive control signal DR_CTR is generated at a logic "low" level 'L' and the operation flag PFLAG is generated at a logic "high" level 'H', the code generation circuit 315 may reset the drive code DR_CD (S315). The driving force of the internal voltage VINT in the driving circuit 117 may be set to the initial driving force by the reset driving code DR_CD, the voltage level of the internal voltage VINT may be reset, and the feedback voltage VFEED generated in the feedback voltage generating circuit 319 may also be reset (S317).

[0068] Next, as a result of the comparison between the feedback voltage VFEED and the reference voltage VREF (S301), when the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF and the operation flag PFLAG is not generated at a logic "high" level 'H' (S303 'No', S311 'No'), the drive control circuit 311 may generate a comparison signal COM and a drive control signal DR_CTR both set to have a logic "low" level 'L' (S321). When receiving the drive control signal DR_CTR set to have a logic "low" level 'L' and the operation flag PFLAG is not generated at a logic "high" level 'H', the oscillator 313 may activate the drive clock DCLK (S323). When the driving control signal DR_CTR is generated at a logic "low" level 'L' and the operation flag PFLAG is not generated at a logic "high" level 'H', the code generation circuit 315 can count the driving clock DCLK to generate a driving code DR_CD, which includes a bit whose logic bit group is set to a reduced code value (S323). The driving circuit 317 can receive the driving code DR_CD with a reduced code value to generate an internal voltage VINT driven at a reduced voltage level, and the feedback voltage generation circuit 319 can also generate a feedback voltage VFEED with a reduced voltage level according to the internal voltage VINT (S325).

[0069] Fig. 9 It is shown Figure 7 2 is a timing chart showing the operation of the internal voltage generating circuit 31A.

[0070] like Fig. 9 As shown, during the interval from time T31 to time T33, when the load circuit (eg Figure 633) in the operation and the load current of the load current source 321 is generated, the code value of the driving code DR_CD can be adjusted according to the comparison result of the feedback voltage VFEED and the reference voltage VREF. That is, when the feedback voltage VFEED is generated at a voltage level smaller than the voltage level of the reference voltage VREF, the code value of the driving code DR_CD can be sequentially increased, and the voltage level of the feedback voltage VFEED can be increased. In addition, when the feedback voltage VFEED is generated at a voltage level equal to or greater than the voltage level of the reference voltage VREF and the operation flag PFLAG is not generated at a logic "high" level 'H', the code value of the driving code DR_CD can be sequentially reduced, and the voltage level of the feedback voltage VFEED can be reduced. The operation of sequentially increasing and decreasing the code value of the driving code DR_CD can be repeated until time T33, when the generation of the load current stops. At time T32, when the operation flag PFLAG is generated at a logic 'high' level 'H' and the feedback voltage VFEED is generated at a voltage level equal to or greater than that of the reference voltage VREF, the driving code DR_CD may be reset at time T34 and the voltage level of the feedback voltage VFEED may also be reset.

[0071] Concepts have been disclosed in conjunction with some of the embodiments described above. Those skilled in the art will appreciate that multiple modifications, additions, and substitutions are possible without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed in this specification should not be considered restrictive, but exemplary. The scope of the concept is not limited to the above description, but is defined by the appended claims, and all distinguishing features within the scope of equivalents should be interpreted as included in the concept.

Claims

1. An electronic device, comprising: Internal voltage generation circuitry that: Detecting the voltage level of the internal voltage; generating a driving code having a value determined by a driving clock; and generating an internal voltage as an output of the internal voltage generating circuit, the internal voltage having a magnitude corresponding to a driving code value, the driving code being reset in response to receiving the internal voltage of a predetermined magnitude; and A load circuit receives the internal voltage.

2. The electronic device according to claim 1, wherein: The internal voltage generating circuit changes the magnitude of the internal voltage in response to a change in a value of the driving code.

3. The electronic device according to claim 2, wherein: The internal voltage generating circuit enables or disables the driving clock in response to the internal voltage.

4. The electronic device according to claim 1, wherein: The internal voltage generating circuit deactivates the driving clock and resets the driving code when there is no need to reset the internal voltage.

5. The electronic device according to claim 1, wherein: The internal voltage generating circuit comprises: a drive control circuit that generates a drive control signal in response to a reference voltage and a feedback voltage generated from the internal voltage; a code generating circuit that generates the driving code in response to the driving control signal; and A driving circuit generates the internal voltage in response to a value of the driving code.

6. The electronic device according to claim 5, wherein: The drive control circuit generates the drive control signal having a logic level set according to a comparison of the feedback voltage and the reference voltage.

7. The electronic device according to claim 5, wherein: The code generation circuit counts the drive clock to generate the drive code, and a value of the drive code increases when the feedback voltage is generated at a voltage level smaller than a voltage level of the reference voltage.

8. The electronic device according to claim 5, wherein: The code generating circuit resets the driving code when the feedback voltage is generated at a voltage level equal to or greater than a voltage level of the reference voltage.

9. The electronic device according to claim 5, wherein: The driving circuit: causing the internal voltage to have a magnitude determined by the value of the driving code, and The internal voltage is reset when the value of the driving code is reset.

10. An electronic device comprising: Internal voltage generation circuitry that: Detecting the voltage level of the internal voltage; generating a driving code in response to a driving clock; generating an internal voltage, the voltage level of the internal voltage being determined by the driving code, the driving code being reset in response to a predetermined internal voltage and an operation flag; and a load circuit receiving the internal voltage; The operation flag is generated by the operation of the load circuit.

11. The electronic device according to claim 10, wherein: The operation flag is generated before the operation of the load circuit is stopped.

12. The electronic device according to claim 10, wherein: The internal voltage generating circuit deactivates the driving clock and resets the driving code when the operation flag is generated and the internal voltage needs to be reset.

13. The electronic device according to claim 10, wherein: The internal voltage generating circuit comprises: a drive control circuit that: generates a drive control signal in response to a reference voltage and a feedback voltage generated from the internal voltage; a code generating circuit that generates the driving code in response to the driving control signal and the operation flag; and A driving circuit generates the internal voltage in response to the driving code.

14. The electronic device according to claim 13, wherein: The code generating circuit counts the driving clock to generate the driving code; and when the feedback voltage is generated at a voltage level smaller than a voltage level of the reference voltage, increasing the code value.

15. The electronic device according to claim 13, wherein: The code generation circuit deactivates the driving clock and resets the driving code when the operation flag is generated and when the feedback voltage has a voltage level equal to or greater than the reference voltage.

16. The electronic device according to claim 13, wherein: The code generating circuit counts the driving clock pulses to generate the driving code, wherein the value of the driving code decreases when the operation flag is not generated and the feedback voltage is generated at a voltage level equal to or greater than the reference voltage.

17. The electronic device according to claim 13, wherein: The driving circuit: providing the internal voltage at a driving force set according to the driving code, and When the driving code is reset, the internal voltage is driven with an initial driving force to reset the internal voltage.

18. An internal voltage generating circuit, comprising: a drive control circuit that: generates a drive control signal in response to a reference voltage and a feedback voltage generated from an internal voltage; a code generating circuit that generates a driving code in response to the driving control signal; and a driving circuit that provides the internal voltage at an amplitude determined by the driving code, Wherein, the driving code is reset when the feedback voltage is generated at a voltage level equal to or greater than a voltage level of the reference voltage.

19. The internal voltage generating circuit according to claim 18, wherein: The code generating circuit counts the driving clock to generate the driving code, the value of the driving code increasing when the feedback voltage is generated at a voltage level lower than that of the reference voltage.

20. The internal voltage generating circuit according to claim 18, wherein: The driving circuit: generating an internal voltage determined by the value of the driving code; and An internal voltage is provided, the internal voltage having a magnitude that resets the internal voltage when the driving code is reset.

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