A BGR circuit compatible with a low voltage domain and an overvoltage domain

Abstract

The present invention discloses a BGR circuit compatible with a low voltage domain and an overvoltage domain, belonging to the field of microelectronic technology; the present invention includes voltage dividing resistors R1, R2 and R3 and voltage stabilizing capacitors C1-C4. The voltage dividing resistors R1, R2 and R3 are used to provide bias voltages for N1, N5, N6, P5, P6, P7 and P11, wherein N1, N5 and N6 are deep N-well MOS transistors, and P1, N1, N2, N3, N4 and R4 constitute a startup circuit; when the power supply voltage is 2.3V-5.5V, the present invention realizes the design of a low-power BGR with 3.3V devices, realizes that low-voltage devices will not be broken down and the life will not decay under the working conditions of overvoltage application, and the device performance will not decline in a low-voltage environment.

Description

Technical Field

[0001] The present invention relates to the field of microelectronics technology, and more specifically, it relates to a BGR circuit compatible with a low voltage domain and an overvoltage domain. Background Art

[0002] Currently, when designing a BGR circuit, devices are generally selected based on the maximum value of the power supply voltage domain; for example, if the power supply voltage is 5 volts, 5-volt devices will be selected; if the power supply voltage is 1.8 volts, 1.8-volt devices will be selected; this is not only to prevent the devices from being broken down and reduce the service life of the devices, but also for better performance. However, in some processes, the maximum value of the power supply voltage domain is 5 volts, but this process can only support 3.3-volt devices; in addition, it is also necessary to consider that the performance can still be maintained under low voltage conditions after the battery performance degrades, such as when the battery voltage drops to 2.3 volts, the device performance should not be affected, which requires a special design that can use low voltage devices to cope with overvoltage working conditions while ensuring that the device performance will not degrade in a low voltage environment. Summary of the Invention

[0003] Aiming at the deficiencies of the existing technology, the purpose of the present invention is to provide a BGR circuit compatible with a low voltage domain and an overvoltage domain, and solve the following technical problems: being able to use low voltage devices to cope with overvoltage working conditions while ensuring that the device performance will not degrade in a low voltage environment.

[0004] The purpose of the present invention can be achieved by the following technical solutions:

[0005] A BGR circuit compatible with a low voltage domain and an overvoltage domain includes voltage dividing resistors R1, R2, and R3 for providing bias voltages to N1, N5, N6, P5, P6, P7, and P11, where N1, N5, and N6 are deep N-well MOS transistors, and P1, N1, N2, N3, N4, and R4 constitute a startup circuit;

[0006] The gate of N2 is connected to the drain of N3, the gate of N4, and the negative pole of R4, and the source is connected to the positive pole of R4, so that when the BGR is not working properly, the gate voltage of N4 is quickly pulled up;

[0007] The source of N4 and the source of N10 are connected to the ground GND, and the drain of N4 is connected to the drain of N10, the source of N6, and the substrate for pulling the BGR out of the dead zone.

[0008] As a further solution of the present invention, the positive pole of R1 is connected to the power supply voltage AVDD, the negative pole of R1 is connected to the positive pole of R2, the gates of N1, N5, and N6, and the positive pole of C1, and the negative pole of R2 is connected to the positive pole of R3, the positive pole of C2, and the gates of P5, P6, P7, and P11.

[0009] As a further solution of the present invention, at a high voltage of 5.5V, N1, N5, N6, P5, P6, P7, and P11 operate in the saturation region and function as voltage-dividing resistors. At a low voltage of 2.3V, N1, N5, N6, P5, P6, P7, and P11 operate in the linear region and function as switching transistors, ensuring that N1 - N10 and P1 - P13 do not experience overvoltage at a high voltage of 5.5V. At a low voltage of 2.3V, P2, P3, P4, P8, P9, P10, P12, P13, and N7 - N10 all operate in the saturation region and do not enter the linear region, thereby reducing performance.

[0010] As a further solution of the present invention, N2 is used in this management pipe to provide high impedance.

[0011] As a further solution of the present invention, the substrates of all NMOS devices except for the self-trapped devices are grounded, and the substrates of all PMOS devices are connected to the power supply voltage.

[0012] Compared with the existing solutions, the beneficial effects of the present invention are as follows:

[0013] When the power supply voltage of the present invention is 2.3V - 5.5V, a low-power BGR design is achieved using 3.3V devices, enabling low-voltage devices to be applied under overvoltage working conditions without breakdown and life attenuation, and ensuring that the device performance does not degrade in a low-voltage environment. Brief Description of the Drawings

[0014] Figure 1 It is a circuit diagram of a BGR compatible with a low-voltage domain and an overvoltage domain according to the present invention. Detailed Embodiments

[0015] The present invention will be further described in detail below in conjunction with the drawings and specific embodiments. The embodiments of the present invention are given for purposes of illustration and description, and are not intended to be exhaustive or to limit the present invention to the disclosed form. Many modifications and variations are obvious to those of ordinary skill in the art. The embodiments are selected and described to better illustrate the principles and practical applications of the present invention, and to enable those of ordinary skill in the art to understand the present invention and design various embodiments with various modifications suitable for specific purposes.

[0016] Embodiment 1

[0017] Refer to Figure 1As shown in the figure, the present invention is a BGR circuit compatible with the low-voltage domain and the overvoltage domain, including voltage-dividing resistors R1, R2, and R3, and voltage-stabilizing capacitors C1 - C4. The voltage-dividing resistors R1, R2, and R3 are used to provide bias voltages for N1, N5, N6, P5, P6, P7, and P11. Among them, N1, N5, and N6 are deep N-well MOS transistors. P1, N1, N2, N3, N4, and R4 constitute a startup circuit. The voltage-stabilizing capacitors C1 - C4 are used to improve the stability of the voltages at VRES1, VRES2, VBAIS, and AIO_VBG_1P2 when the power supply is powered on, making the startup risk of the BGR circuit smaller;

[0018] This BGR is in voltage-mode form and has only one degeneracy point. Only when the currents flowing through Q1, Q2, and Q3 are zero, this BGR circuit is in the "dead zone". At this time, the feedback voltage VFB is at a low level, and N3 is turned off, so that the gate voltage of N4 is pulled up. When the gate voltage of N4 is greater than its threshold voltage V TH N4 will turn on, thus pulling down the voltage at the VBACK point. Therefore, the gate voltages VBAIS of P2, P3, P4, and P10 are also pulled down, increasing the currents flowing through P2, P3, P4, and P10, and raising the feedback voltage VFB. When the feedback voltage VFB is greater than the threshold voltage V of N3 TH N3 will turn on, the gate voltage of N4 drops to ground GND, and N4 is turned off. At this time, this BGR circuit has left the "dead zone".

[0019] N2 is a native transistor used to provide a high resistance. The threshold voltage V of this native transistor TH is very small. Therefore, when the gate is grounded to GND, it will also turn on and the equivalent resistance is also very large. The gate of N2 is not grounded to GND like a traditional native transistor, but is connected to the drain of N3, the gate of N4, and the negative pole of R4. Because if the gate of N2 is grounded to GND, under certain process corners, the V of the N2 transistor GS limits make the gate voltage of N4 unable to reach a high potential even when the BGR is in the dead zone, and even less than the threshold voltage V of N4 TH , which is not conducive to the establishment of soft start. The gate of N2 is connected to the drain of N3, the gate of N4, and the negative pole of R4, and the source is connected to the positive pole of R4, so that when the BGR is not working properly, the gate voltage of N4 is quickly pulled up.

[0020] P1 - P13 are PMOS transistors, N1 - N10 are NMOS transistors, R1 - R7 are resistors, C1 - C4 are voltage-stabilizing capacitors, and N1, N5, and N6 are deep N-well MOS transistors, which are 6-terminal devices;

[0021] The positive electrode of R1 is connected to the power supply voltage AVDD, and the negative electrode of R1 is connected to the positive electrode of R2, the gates of N1, N5, N6, and the positive electrode of C1; the negative electrode of R2 is connected to the positive electrode of R3, the positive electrode of C2, and the gates of P5, P6, P7, and P11; the negative electrode of R3 is grounded to GND.

[0022] The gate and drain of P1 are connected to the drain of N1 and the deep N-well, and the source is connected to the power supply voltage AVDD; the source and substrate of N1 are connected to the drain of N2; the gate of N2 is connected to the drain of N3, the gate of N4, and the negative electrode of R4, and the source is connected to the positive electrode of R4; the gate of N3 is connected to the negative electrode of R6 and the positive electrode of R7, and the source is grounded to GND; the source of N4 is grounded to GND, and the drain is connected to the drain of N10, the source and substrate of N6; the gates of P2, P3, P4, P9, P10, the negative electrode of C3, and the drain of N6 and the deep N-well are connected, the source is connected to the power supply voltage AVDD, and the drain is connected to the source of P5;

[0023] The source of P3 is connected to the power supply voltage AVDD, and the drain is connected to the source of P6; the source of P4 is connected to the power supply voltage AVDD, and the drain is connected to the source of P7; the drain of P5 is connected to the emitter of the bipolar junction pnp transistor Q1 and the gate of P12; the drain of P6 is connected to the positive electrode of R5 and the gate of P13; the drain of P7 is connected to the positive electrode of the capacitor C4 and the positive electrode of R6; the negative electrode of R5 is connected to the emitter of the bipolar junction pnp transistor Q2; the negative electrode of R7 is connected to the emitter of the bipolar junction pnp transistor Q3. The collectors and bases of Q1, the collectors and bases of Q2, and the collectors and bases of Q3 are all grounded to GND; the positive electrode of C3 is connected to the power supply AVDD; the negative electrodes of C1, C2, and C4 are all grounded to GND.

[0024] The gate and drain of P8 are connected to the gate of P10, the drain of N5, and the deep N-well, and the source is connected to the power supply AVDD; the source of P9 is connected to the power supply AVDD, and the drain is connected to the source of P11; the source of P10 is connected to the power supply AVDD; the drain of P11 is connected to the source and substrate of P12 and the source and substrate of P13; the drain of P12 is connected to the drain and gate of N8 and the gate of N7; the drain of P13 is connected to the drain and gate of N9 and the gate of N10; the source and substrate of N5 are connected to the drain of N7; the source and substrate of N6 are connected to the drain of N10; the sources of N7, N8, N9, and N10 are all grounded to GND.

[0025] The drain of N4 is connected to the drain of N10, the source and substrate of N6, used to pull BGR out of the dead zone, because N4 is a 3.3V device and cannot be connected to the gates of P2 and P3 in the traditional connection method. Otherwise, at a high voltage of 5.5V, the V of N4 DBThat is, the voltage difference between the leakage end and the substrate will overvoltage, greatly reducing the lifespan of the MOS transistor. At a high voltage of 5.5V, N1, N5, N6, P5, P6, P7, and P11 operate in the saturation region and function as voltage-dividing resistors. At a low voltage of 2.3V, N1, N5, N6, P5, P6, P7, and P11 operate in the linear region and function as switching transistors, ensuring that N1 - N10 and P1 - P13 do not overvoltage at a high voltage of 5.5V. At a low voltage of 2.3V, P2, P3, P4, P8, P9, P10, P12, P13, and N7 - N10 all operate in the saturation region and do not enter the linear region, thereby reducing performance.

[0026] The substrates of all NMOS devices, except for the self-trapped devices, are grounded, and the substrates of all PMOS devices are connected to the power supply voltage.

[0027] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, terms such as "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] The above has described a specific embodiment of the present invention in detail, but the content described is only a preferred embodiment of the present invention and cannot be considered as limiting the scope of implementation of the present invention. Any equivalent changes and improvements made within the scope of the application of the present invention should still fall within the scope covered by the patent of the present invention.

Claims

1. A BGR circuit compatible with a low voltage domain and an overvoltage domain, characterized in that: It includes voltage-dividing resistors R1, R2 and R3 and voltage-stabilizing capacitors C1-C4. The voltage-dividing resistors R1, R2 and R3 are used to provide bias voltages for N1, N5, N6, P5, P6, P7 and P11. Among them, N1, N5 and N6 are deep N-well MOS tubes, and P1, N1, N2, N3, N4 and R4 constitute a startup circuit. The positive electrode of R1 is connected to the power supply voltage AVDD, and the negative electrode of R1 is connected to the positive electrode of R2, the gates of N1, N5, N6 and the positive electrode of C1; the negative electrode of R2 is connected to the positive electrode of R3, the positive electrode of C2, the gates of P5, P6, P7 and P11; the negative electrode of R3 is connected to the ground GND; the positive electrode of C3 is connected to the power supply AVDD; the negative electrodes of C1, C2 and C4 are all connected to the ground GND; The gate and drain of P1 are connected to the drain and deep N-well of N1, and the source is connected to the power supply voltage AVDD; the source and substrate of N1 are connected to the drain of N2; the gate of N2 is connected to the drain of N3, the gate of N4, and the negative electrode of R4, and the source is connected to the positive electrode of R4; the gate of N3 is connected to the negative electrode of R6 and the positive electrode of R7, and the source is connected to the ground GND; the source of N4 is connected to the ground GND, and the drain is connected to the drain of N10, the source of N6, and the substrate; the gate of P2 is connected to the gate of P3, the gate of P4, the gate of P9, the drain of P10, the negative electrode of C3, the drain of N6, and the deep N-well, the source is connected to the power supply voltage AVDD, and the drain is connected to the source of P5; The source of P3 is connected to the power supply voltage AVDD, and the drain is connected to the source of P6; the source of P4 is connected to the power supply voltage AVDD, and the drain is connected to the source of P7; the drain of P5 is connected to the emitter of transistor Q1 and the gate of P12; the drain of P6 is connected to the positive electrode of R5 and the gate of P13; the drain of P7 is connected to the positive electrode of capacitor C4 and the positive electrode of R6; the negative electrode of R5 is connected to the emitter of transistor Q2; the negative electrode of R7 is connected to the emitter of transistor Q3; the collector and base of Q1, the collector and base of Q2, and the collector and base of Q3 are all connected to the ground GND; the gate and drain of P8 are connected to P10 The gate of P1 is connected to the drain of N5 and the deep N well, and the source is connected to the power supply AVDD; the source of P9 is connected to the power supply AVDD, and the drain is connected to the source of P11; the source of P10 is connected to the power supply AVDD; the drain of P11 is connected to the source and substrate of P12, and the source and substrate of P13; the drain of P12 is connected to the drain and gate of N8 and the gate of N7; the drain of P13 is connected to the drain and gate of N9 and the gate of N10; the source and substrate of N5 are connected to the drain of N7; the source and substrate of N6 are connected to the drain of N10; the sources of N7, N8, N9, and N10 are all connected to the ground GND; The gate of N2 is connected to the drain of N3, the gate of N4, and the negative electrode of R4, and the source of N2 is connected to the positive electrode of R4, so that when the BGR does not work normally, the gate voltage of N4 is quickly pulled up; The source of N4 is connected to the source of N10 and the ground GND, and the drain of N4 is connected to the drain of N10, the source of N6 and the substrate, which is used to pull BGR out of the dead zone; Among them, P1-P13 are PMOS tubes, N1-N10 are NMOS tubes, and R4-R7 are resistors.

2. A BGR circuit compatible with low voltage domain and super voltage domain according to claim 1, characterized in that: At a high voltage of 5.5V, N1, N5, N6, P5, P6, P7 and P11 work in the saturation region and function as voltage-dividing resistors. At a low voltage of 2.3V, N1, N5, N6, P5, P6, P7 and P11 work in the linear region and function as switching tubes, so that N1-N10 and P1-P13 will not be over-voltage at a high voltage of 5.5V. At a low voltage of 2.3V, P2, P3, P4, P8, P9, P10, P12, P13 and N7-N10 all work in the saturation region and will not enter the linear region, thereby reducing performance.

3. A BGR circuit compatible with low voltage domain and super voltage domain according to claim 1, characterized in that: N2 is an intrinsic tube used to provide high resistance.

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