A register indirect access circuit

Abstract

This invention relates to chip design, specifically to a register indirect access circuit, including a block enable generation device and multiple register block read / write devices. The block enable generation device and each register block read / write device share a register clock, write data, write enable, read enable, and read / write address. The block enable register read data output by the block enable generation device and the register block read data output by each register block read / write device are ORed together and then sent to the read data after being clocked once by a set of D flip-flops. The technical solution provided by this invention can effectively overcome the shortcomings of the prior art in that it is difficult to effectively expand the register addressing space without widening the address bus width.

Description

Technical Field

[0001] This invention relates to chip design, and more specifically to a register indirect access circuit. Background Technology

[0002] During chip development, a certain number of registers are typically used to meet design requirements, such as readable and writable configuration registers and readable-only status registers. These registers occupy a certain amount of address space, thus requiring a certain width of address bus for addressing. When there are many registers, a larger address space is needed. The general solution to this problem is to widen the address bus to ensure that all registers can be correctly addressed.

[0003] Widening the address bus can solve the problem of insufficient address space, but it also brings the disadvantage of increased chip area. When there are many registers, the required address space will be relatively large, and the required address bus width may become unacceptably large. Summary of the Invention

[0004] In view of the above-mentioned shortcomings of the prior art, the present invention provides a register indirect access circuit, which can effectively overcome the defect of the prior art that it is difficult to effectively expand the register addressing space without widening the address bus width.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A register indirect access circuit includes a block enable generation device and multiple register block read / write devices. The block enable generation device and each register block read / write device share a register clock, write data, write enable, read enable, and read / write address. The block enable register read data output by the block enable generation device and the register block read data output by each register block read / write device are ORed and then sent to the read data after being stepped on by a set of D flip-flops.

[0007] The block enable generation device includes a block enable register, a first register clock gate ICG1, a first equals comparator Q1, a first AND gate A1, a second AND gate A2, a first 2-to-1 selector M1, and a second equals comparator Q2. The first equals comparator Q1 is connected to a read / write address and a preset block enable register address. The first AND gate A1 is connected to the output of the first equals comparator Q1 and a write enable. The second AND gate A2 is connected to the output of the first equals comparator Q1 and a read enable. The first register clock gate ICG1 is connected to a register clock and the output of the first AND gate A1. The block enable register is connected to the output of the first register clock gate ICG1 and write data. The first 2-to-1 selector M1 is connected to the output of the second AND gate A2, the block enable register value output by the block enable register, and 0. The first 2-to-1 selector M1 outputs the block enable register read data. The second equals comparator Q2 is connected to the block enable register value output by the block enable register and a preset register block base address. The second equals comparator Q2 outputs the block enable corresponding to the register block.

[0008] The register block read / write device includes a register block, a third equals comparator Q3, a third AND gate A3, a second register clock gate ICG2, a first OR gate O1, and multiple sets of equals comparators, AND gates, and 2-to-1 selectors matching the number of registers stored inside the register block. The register block stores multiple registers. The third equals comparator Q3 is connected to the read / write address and a preset register address. The third AND gate A3 is connected to the output of the third equals comparator Q3, the block enable output of the second equals comparator Q2, and the write enable. The second register clock gate ICG2 is connected to the register clock and the output of the third AND gate A3. The register block is connected to the output of the second register clock gate ICG2, write data, the read / write address, and the preset register address. The register block outputs the register value.

[0009] The equal comparator q1 is connected to the read / write address and the preset register 1 address. The AND gate a1 is connected to the output, read enable, and block enable of the equal comparator q1. The 2-to-1 selector m1 is connected to the output of the AND gate a1, the register 1 value output by the register block, and 0. The first OR gate O1 is connected to the register 1 read data output by the 2-to-1 selector m1. The remaining equal comparators, AND gates, and 2-to-1 selectors have the same connection structure as the equal comparator q1, AND gate a1, and 2-to-1 selector m1. The first OR gate O1 outputs the register block read data.

[0010] Preferably, the register clock connected to the first register clock gate ICG1 is the working clock of the block enable generator. When the read / write address matches the preset block enable register address and the write enable is valid, the first register clock gate ICG1 is turned on; otherwise, the first register clock gate ICG1 is turned off, thereby updating the data of the block enable register.

[0011] When the read / write address matches the preset block enable register address and the read enable is valid, the read data of the block enable register will be assigned the value of the block enable register; otherwise, the read data of the block enable register will be assigned the value of 0.

[0012] After the first register clock gate ICG1 is turned on, the block enable register receives the register clock and starts working. When the value written to the block enable register matches the base address of a certain register block, the second equals comparator Q2 outputs the block enable corresponding to the register block, so as to enable the corresponding register block.

[0013] Preferably, the register block stores N registers, and a register is selected by reading or writing the address. Each register block and the block enable register share the read / write address bus, and the values ​​of the N registers are output to other circuits in the chip for use.

[0014] Each register block and the block enable register share the write data bus and the read data bus.

[0015] Preferably, the register clock accessed by the second register clock gate ICG2 is the working clock of the register block read / write device. When the read / write address matches a certain register address and the write enable and block enable are valid, the second register clock gate ICG2 is turned on; otherwise, the second register clock gate ICG2 is turned off.

[0016] After the second register clock gate ICG2 is turned on, the register block receives the register clock and starts working. The register block outputs the values ​​of register 1, 2, ..., N, realizing the data update of multiple registers inside the register block;

[0017] When the read / write address matches the preset address of register 1, 2, ..., N, and the read enable and block enable are valid, the read data of register 1, 2, ..., N will be assigned the value of register 1, 2, ..., N. Otherwise, the read data of register 1, 2, ..., N will be assigned the value of 0. Finally, the read data of register 1, 2, ..., N will be ORed and then assigned to the register block read data.

[0018] The register clock accessed by the second register clock gate ICG2 is the same as the register clock accessed by the first register clock gate ICG1.

[0019] Compared with the prior art, the register indirect access circuit provided by the present invention can effectively expand the register addressing space without widening the address bus width, avoid increasing the chip area, and has a simple circuit that is easy to implement while consuming fewer resources. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0021] Figure 1 This is a schematic diagram of the hardware structure of the present invention;

[0022] Figure 2 For the present invention Figure 1 Circuit diagram of the middle block enable generation device;

[0023] Figure 3 For the present invention Figure 1 Circuit diagram of a single register block read / write device. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0025] A register indirect access circuit, such as Figure 1 As shown, it includes a block enable generation device and multiple register block read / write devices. The block enable generation device and each register block read / write device share the register clock, write data, write enable, read enable, and read / write address. The block enable register read data output by the block enable generation device and the register block read data output by each register block read / write device are ORed and then sent to the read data after being passed through a set of D flip-flops for one clock cycle.

[0026] like Figure 2As shown, the block enable generation device includes a block enable register, a first register clock gate ICG1, a first equals comparator Q1, a first AND gate A1, a second AND gate A2, a first 2-to-1 selector M1, and a second equals comparator Q2. The first equals comparator Q1 is connected to the read / write address and a preset block enable register address. The first AND gate A1 is connected to the output of the first equals comparator Q1 and the write enable. The second AND gate A2 is connected to the output of the first equals comparator Q1 and the read enable. The first register clock gate ICG1 is connected to the register clock. The output of the clock and the first AND gate A1 is connected to the output of the first register clock gate ICG1 and write data. The first 2-to-1 selector M1 is connected to the output of the second AND gate A2, the block enable register value output by the block enable register and 0. The first 2-to-1 selector M1 outputs the block enable register read data. The second equal comparator Q2 is connected to the block enable register value output by the block enable register and the preset register block base address (1, 2, ..., M). The second equal comparator Q2 outputs the block enable corresponding to the register block.

[0027] The register clock connected to the first register clock gate ICG1 is the working clock of the block enable generator. When the read / write address matches the preset block enable register address and the write enable is valid, the first register clock gate ICG1 is turned on; otherwise, the first register clock gate ICG1 is turned off, thereby updating the data of the block enable register.

[0028] When the read / write address matches the preset block enable register address and the read enable is valid, the read data of the block enable register will be assigned the value of the block enable register; otherwise, the read data of the block enable register will be assigned the value of 0.

[0029] After the first register clock gate ICG1 is turned on, the block enable register receives the register clock and starts working. When the value written to the block enable register matches the base address of a certain register block, the second equals comparator Q2 outputs the block enable corresponding to the register block, so as to enable the corresponding register block.

[0030] Figure 2 In this context, write data refers to data written to the block enable register, and read data from the block enable register refers to data read from the block enable register.

[0031] like Figure 3As shown, the register block read / write device includes a register block, a third equals comparator Q3, a third AND gate A3, a second register clock gate ICG2, a first OR gate O1, and multiple sets of equals comparators, AND gates, and 2-to-1 selectors matching the number of registers stored inside the register block. The register block stores multiple registers. The third equals comparator Q3 is connected to the read / write address and a preset register address (1, 2, ..., N). The third AND gate A3 is connected to the output of the third equals comparator Q3, the block enable output of the second equals comparator Q2, and the write enable. The second register clock gate ICG2 is connected to the register clock and the output of the third AND gate A3. The register block is connected to the output of the second register clock gate ICG2, the write data, the read / write address, and the preset register address. The register block outputs the register value.

[0032] The equal comparator q1 is connected to the read / write address and the preset address of register 1. The AND gate a1 is connected to the output of equal comparator q1, the read enable, and the block enable. The 2-to-1 selector m1 is connected to the output of AND gate a1, the register 1 value output by the register block, and 0. The first OR gate O1 is connected to the register 1 read data output by the 2-to-1 selector m1. The remaining equal comparators, AND gates, and 2-to-1 selectors have the same connection structure as equal comparators q1, AND gate a1, and 2-to-1 selector m1. The first OR gate O1 outputs the register block read data.

[0033] The register block contains N registers. A register is selected by reading or writing the address. Each register block shares the read / write address bus with the block enable register. (Because of the shared read / write address bus, the address of the block enable register cannot be accessed, that is, the address of the block enable register is unique.) The values ​​of the N registers are output to other circuits in the chip.

[0034] Each register block and the block enable register share the write data bus and the read data bus.

[0035] The register clock accessed by the second register clock gate ICG2 is the working clock of the register block read / write device. When the read / write address matches a certain register address and write enable and block enable are valid, the second register clock gate ICG2 is turned on; otherwise, the second register clock gate ICG2 is turned off.

[0036] After the second register clock gate ICG2 is turned on, the register block receives the register clock and starts working. The register block outputs the values ​​of register 1, 2, ..., N, realizing the data update of multiple registers inside the register block;

[0037] When the read / write address matches the preset address of register 1, 2, ..., N, and the read enable and block enable are valid, the read data of register 1, 2, ..., N will be assigned the value of register 1, 2, ..., N. Otherwise, the read data of register 1, 2, ..., N will be assigned the value of 0. Finally, the read data of register 1, 2, ..., N will be ORed and then assigned to the register block read data.

[0038] The register clock accessed by the second register clock gate ICG2 is the same as the register clock accessed by the first register clock gate ICG1.

[0039] Figure 3 In this context, writing data refers to writing data into a register block, and reading data from a register block refers to reading data from a register block.

[0040] In the technical solution of this application, register access via register indirect access circuitry requires the following two steps:

[0041] 1) Configure the block enable register in the block enable generation device to be the base address of the register block where the target register is located, and enable the register block you want to access first;

[0042] 2) Perform data update or data read operations on the target register in the selected register block.

[0043] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions will not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A register indirect access circuit, characterized in that: It includes a block enable generation device and multiple register block read / write devices. The block enable generation device and each register block read / write device share the register clock, write data, write enable, read enable, and read / write address. The block enable register read data output by the block enable generation device and the register block read data output by each register block read / write device are ORed and then sent to the read data after being passed through a set of D flip-flops for one clock cycle. The block enable generation device includes a block enable register, a first register clock gate ICG1, a first equals comparator Q1, a first AND gate A1, a second AND gate A2, a first 2-to-1 selector M1, and a second equals comparator Q2. The first equals comparator Q1 is connected to a read / write address and a preset block enable register address. The first AND gate A1 is connected to the output of the first equals comparator Q1 and a write enable. The second AND gate A2 is connected to the output of the first equals comparator Q1 and a read enable. The first register clock gate ICG1 is connected to a register clock and the output of the first AND gate A1. The block enable register is connected to the output of the first register clock gate ICG1 and write data. The first 2-to-1 selector M1 is connected to the output of the second AND gate A2, the block enable register value output by the block enable register, and 0. The first 2-to-1 selector M1 outputs the block enable register read data. The second equals comparator Q2 is connected to the block enable register value output by the block enable register and a preset register block base address. The second equals comparator Q2 outputs the block enable corresponding to the register block. The register block read / write device includes a register block, a third equals comparator Q3, a third AND gate A3, a second register clock gate ICG2, a first OR gate O1, and multiple sets of equals comparators, AND gates, and 2-to-1 selectors matching the number of registers stored inside the register block. The register block stores multiple registers. The third equals comparator Q3 is connected to the read / write address and a preset register address. The third AND gate A3 is connected to the output of the third equals comparator Q3, the block enable output of the second equals comparator Q2, and the write enable. The second register clock gate ICG2 is connected to the register clock and the output of the third AND gate A3. The register block is connected to the output of the second register clock gate ICG2, write data, the read / write address, and the preset register address. The register block outputs the register value. The equal comparator q1 is connected to the read / write address and the preset register 1 address. The AND gate a1 is connected to the output, read enable, and block enable of the equal comparator q1. The 2-to-1 selector m1 is connected to the output of the AND gate a1, the register 1 value output by the register block, and 0. The first OR gate O1 is connected to the register 1 read data output by the 2-to-1 selector m1. The remaining equal comparators, AND gates, and 2-to-1 selectors have the same connection structure as the equal comparator q1, AND gate a1, and 2-to-1 selector m1. The first OR gate O1 outputs the register block read data.

2. The register indirect access circuit according to claim 1, characterized in that: The register clock connected to the first register clock gate ICG1 is the working clock of the block enable generator. When the read / write address matches the preset block enable register address and the write enable is valid, the first register clock gate ICG1 is turned on; otherwise, the first register clock gate ICG1 is turned off, thereby updating the data of the block enable register. When the read / write address matches the preset block enable register address and the read enable is valid, the read data of the block enable register will be assigned the value of the block enable register; otherwise, the read data of the block enable register will be assigned the value of 0. After the first register clock gate ICG1 is turned on, the block enable register receives the register clock and starts working. When the value written to the block enable register matches the base address of a certain register block, the second equals comparator Q2 outputs the block enable corresponding to the register block, so as to enable the corresponding register block.

3. The register indirect access circuit according to claim 1, characterized in that: The register block contains N registers. A register can be selected by reading or writing the address. Each register block and the block enable register share the read / write address bus. The values ​​of the N registers are output to other circuits in the chip. Each register block and the block enable register share the write data bus and the read data bus.

4. The register indirect access circuit according to claim 3, characterized in that: The register clock connected to the second register clock gate ICG2 is the working clock of the register block read / write device. When the read / write address matches a certain register address and the write enable and block enable are valid, the second register clock gate ICG2 is turned on; otherwise, the second register clock gate ICG2 is turned off. After the second register clock gate ICG2 is turned on, the register block receives the register clock and starts working. The register block outputs the values ​​of register 1, 2, ..., N, realizing the data update of multiple registers inside the register block; When the read / write address matches the preset address of register 1, 2, ..., N, and the read enable and block enable are valid, the read data of register 1, 2, ..., N will be assigned the value of register 1, 2, ..., N. Otherwise, the read data of register 1, 2, ..., N will be assigned the value of 0. Finally, the read data of register 1, 2, ..., N will be ORed and then assigned to the register block read data. The register clock accessed by the second register clock gate ICG2 is the same as the register clock accessed by the first register clock gate ICG1.

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