Interrupt detection method and device, electronic equipment and readable storage medium

Abstract

The invention discloses an interrupt detection method and device, electronic equipment and a readable storage medium, and the method comprises the steps: obtaining an instruction type of a first instruction when the instruction included in each basic block of a source program in a client is translated to the first instruction included in a preset position in the basic block; writing an interrupt detection instruction before a second instruction under the condition that the instruction type is a preset type; the second instruction is a translation result of the first instruction; the interrupt detection instruction is executed before the second instruction is executed, so that event response corresponding to the second instruction is carried out according to a detected interrupt signal. The overall code space occupation and dynamic execution time of the target program can be reduced, and the performance of the translator can be improved.

Description

Technical Field

[0001] The present application belongs to the field of computer technology, and specifically relates to an interruption detection method, device, electronic device and readable storage medium. Background Art

[0002] Binary translation can convert instructions of one instruction set architecture (ISA) into instructions of another ISA. During the binary translation process, if the system-level binary translator supports the operation of the client operating system, it needs to provide the required hardware device simulation for it. Usually, after the hardware device completes the operation requested by the processor, it will send an interrupt signal to the processor, and the processor will handle the interrupt according to the received interrupt signal. Therefore, the system-level binary translator also needs to respond to the client's interrupt mechanism through simulation.

[0003] In the related art, a system-level binary translator usually inserts a dynamic detection code with an interrupt flag bit into each basic block. However, this method will cause a significant increase in the amount of translated target program code, which not only generates more storage space and dynamic execution time, but also frequent interrupt detection will cause the translator performance to degrade. Summary of the invention

[0004] The present application aims to provide an interrupt detection method, device, electronic device and readable storage medium, which at least solves the problem in the prior art that the amount of target program code after translation increases significantly, occupies more storage space and dynamic execution time, and frequent interrupt detection also leads to a decrease in translator performance.

[0005] In order to solve the above technical problems, this application is implemented as follows: In a first aspect, an embodiment of the present application provides an interruption detection method, including: When translating instructions included in each basic block of the source program in the client, when translating to a first instruction included in a preset position in the basic block, obtaining an instruction type of the first instruction; When the instruction type is a preset type, an interrupt detection instruction is written before the second instruction; the second instruction is a translation result of the first instruction; The interrupt detection instruction is executed before executing the second instruction, so as to perform an event response corresponding to the second instruction according to the detected interrupt signal.

[0006] In a second aspect, an embodiment of the present application further provides an interruption detection device, including: A translation module, configured to, when translating instructions included in each basic block of a source program in a client, obtain an instruction type of a first instruction included in a preset position in the basic block when the first instruction is translated; A writing module, used for writing an interrupt detection instruction before a second instruction when the instruction type is a preset type; the second instruction is a translation result of the first instruction; The detection module is used to execute the interrupt detection instruction before executing the second instruction, so as to perform an event response corresponding to the second instruction according to the detected interrupt signal.

[0007] In a third aspect, an embodiment of the present application further provides an electronic device, comprising a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction, when executed by the processor, implements the method described in the first aspect.

[0008] In a fourth aspect, an embodiment of the present application further provides a readable storage medium, which, when instructions in the readable storage medium are executed by a processor of an electronic device, enables the electronic device to execute the method described in the first aspect.

[0009] In summary, in this embodiment, during the translation of the basic block, it can be decided whether to insert an interrupt detection instruction according to the instruction type of the first instruction in the basic block, and the interrupt detection instruction can be inserted before the instruction of a preset type. In this way, when a key change occurs in the program execution path, interrupt detection can be performed in time to ensure that the interrupt request is responded to at the appropriate time without interfering with the normal program execution process. This can prevent redundant code from being inserted into most basic blocks that do not require interrupt detection, thereby effectively reducing the storage space and dynamic execution time of the target program obtained after translation and improving the performance of the translator. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 It is a schematic diagram of a binary translation provided by the background technology of this application; Figure 2 is a flow chart of an interrupt detection method provided by an embodiment of the present application; Figure 3 is a flow chart of another interruption detection method provided by an embodiment of the present application; Figure 4 is a block diagram of an interruption detection device provided in an embodiment of the present application; Figure 5 is a block diagram of an electronic device according to an exemplary embodiment; Figure 6 is a block diagram of another electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0011] The method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0012] Before introducing the interrupt detection method, device, electronic device and readable storage medium provided by the present application, the application scenarios involved in each embodiment of the present application are first introduced. The present application can be applied to the scenario of performing interrupt detection when the source program of the source architecture platform is running on the target architecture platform.

[0013] At present, there are many differences in the instructions that can be supported by hardware designs of different instruction set architectures (ISA), which makes executable files compiled based on one ISA incompatible with other platforms. Binary translation technology can translate the program of the source architecture platform according to the different instruction set architecture platforms, so that the application of the source architecture platform can run on another target architecture platform.

[0014] In the embodiment of the present application, the binary translator can use the "translate while running" method to translate the instructions of the client architecture into host architecture instructions and run them during execution. After the translator can read the binary file, it usually translates and executes it according to the granularity of basic blocks (TB); Figure 1 As shown, an executable program developed based on a client architecture platform can be read from the executable program in a reading manner, and the basic block to be executed can be searched for the translation result corresponding to the basic block to be executed in the code cache area. If the basic block is not found, the basic block is translated, the translated translation result is stored in the code cache area, and the translated translation result is executed. If the translation result is found, the translation result of the basic block can be directly executed.

[0015] The system-level binary translator included in the binary translator needs to simulate the corresponding hardware devices in the client to adapt the client operating system (i.e., the simulated operating system) when it is running. For example, the simulated processor communicates with the hardware device through an interrupt mechanism. When the hardware device completes the operation requested by the processor, it sends an interrupt signal to the processor to inform the processor that there is an event to be processed. Therefore, the system-level binary translator needs to respond to the client's interrupt mechanism in a simulated manner.

[0016] However, due to the basic block linking technology in binary translation, a translated basic block can directly jump to another translated code block for execution, which will cause the execution logic of the program to execute the basic block code cached in the translator for a long time. In order to ensure the response to the interrupt signal in this case and avoid the untimely processing of the interrupt signal, in the related art, the system-level binary translator usually inserts a dynamic detection code for the interrupt flag bit in the instruction code corresponding to each basic block, but this interrupt detection code will take up additional code space and dynamic execution time, and frequent interrupt detection will also cause the translator performance to degrade.

[0017] In order to solve the above problems, the present application provides an interrupt detection method, device, electronic device and readable storage medium, which can determine whether to insert an interrupt detection instruction according to the instruction type of the first instruction in the basic block during the translation of the basic block, and can insert the interrupt detection instruction before the instruction of the preset type. In this way, when a key change occurs in the program execution path, interrupt detection can be performed in time to ensure that the interrupt request is responded to at the appropriate time without interfering with the normal program execution process. It can prevent redundant code from being inserted into most basic blocks that do not require interrupt detection, thereby effectively reducing the storage space and dynamic execution time of the target program obtained after translation, and improving the performance of the translator.

[0018] The method provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0019] Figure 2 It is a flowchart of an interrupt detection method provided in an embodiment of the present application, and the method includes the following steps.

[0020] Step 101 : when translating instructions included in each basic block of a source program in a client, when translating to a first instruction included in a preset position in the basic block, obtaining an instruction type of the first instruction.

[0021] In this step, each basic block included in the source program in the client may be translated first, and the instructions included in each basic block may be translated into instructions corresponding to the host architecture.

[0022] The source program may represent an application developed based on a source architecture platform (client architecture platform). That is, the source program is a program developed based on a first instruction set architecture, and the basic block refers to a sequence of instructions executed sequentially in the source program, and the source program may include multiple basic blocks.

[0023] First, when it is necessary to run a client program developed based on a source architecture platform (i.e., the source program in this application) on a host architecture platform, for each basic block included in the source program, the source architecture instructions in the basic block can be translated into host architecture instructions in real time according to the instructions actually executed on the basic block.

[0024] For example, the source architecture platform can be represented as an x86 architecture platform, the host architecture platform can be represented as another architecture platform, and the binary program can be represented as an x86 program. When an x86 program developed based on the x86 architecture platform is run on another architecture platform, a basic block in the x86 program can be translated for the instructions in the basic block.

[0025] For example, a basic block instruction sequence included in an x86 program can be expressed as follows.

[0026] MOV EAX,5; assign the immediate value 5 to the EAX register; MOV EBX,3; assign the immediate value 3 to the EBX register; ADD EAX,EBX; Add the values ​​of EAX and EBX and store the result in EAX; MOV DWORD PTR [0x1000],EAX; stores the value of EAX to the memory address [0x1000].

[0027] Since the register naming and instruction format in the instruction set of another architecture platform are different from those of x86, the general registers of another architecture platform can be set to a0, a1, etc. When the basic block instruction is translated into an instruction executable on another architecture platform, the translation result of the basic block can be expressed as follows.

[0028] li a0,5; load the immediate value 5 into the a0 register; li a1,3; load the immediate value 3 into the a1 register; add a0,a0,a1; add the values ​​of a0 and a1 and store the result in a0; sd a0,0x1000; stores the value of a0 to memory address 0x1000.

[0029] In this way, the instructions included in each basic block can be translated into instructions corresponding to the host machine architecture.

[0030] Then, when the first instruction included in the preset position in the basic block is translated, the instruction type of the first instruction may be obtained.

[0031] Among them, the first instruction is an instruction that can change the execution order of the program. When executing the program, it can jump to other locations in the program according to specific conditions or unconditionally to continue execution, rather than executing them sequentially according to the storage order of the instructions in the memory.

[0032] In this step, during the translation of the basic block, the instruction sequence corresponding to the basic block in the source program can be first obtained, and then the corresponding instruction sequence in the source program can be translated in sequence. When translating to the instructions included in the preset position, the corresponding instructions at the preset position can be detected to obtain the instruction type of the first instruction.

[0033] Among them, the basic block is a sequence of instructions executed sequentially in the program, with a single entry and a single exit. In this sequence, instructions are executed in order, and there will be no jumps in the middle (except for the jump at the end of the basic block). For example, in a simple program that calculates the sum of two numbers and outputs the result, the continuous instructions from the instruction that reads the two numbers to the instruction that completes the addition operation can constitute a basic block.

[0034] Optionally, for executable programs developed based on a specific architecture, a disassembly operation can be performed first. The disassembly tool converts the binary machine code of the program into an instruction sequence in the form of assembly language. For example, under the x86 architecture, the executable file can be disassembled into human-readable assembly instructions using tools such as the capstone disassembler (used to disassemble machine code into assembly instructions). Then, by analyzing the instruction sequence obtained by the disassembly, the specified instructions can be used to divide it to obtain the basic blocks of the source program, where the specified instructions can include jump instructions (such as JMP, CALL, RET, etc.) and conditional judgment instructions (such as JE, JNE, etc.).

[0035] When the specific position of each basic block in the source program and the corresponding instruction sequence are obtained, the corresponding instruction sequence in the source program can be translated in sequence. When translating to the instructions included in the preset position, the corresponding instructions at the preset position can be detected to obtain the instruction type of the first instruction.

[0036] For example, for an instruction sequence of a basic block of a source program containing multiple instructions, the instruction position with an offset of 5 can be set as the preset position. That is, counting from the start instruction of the instruction sequence, the position of the 6th instruction is the preset position to be detected. For example, the instruction sequence of a basic block corresponding to the source program can be as follows.

[0037] Offset Instructions 0LI R0,5; 1LI R2,3; 2ADD R0,R0,R2; 3LI R3,10; 4SUB R3,R3,R2; 5JMP target label; #preset position; 6MUL R0,R0,R3; 7SD R0,0x1000.

[0038] In a possible implementation, the first instruction is a jump instruction, and when obtaining the instruction type of the first instruction, the jump type of the jump instruction may be obtained.

[0039] Considering that there are specific jump instructions in different instruction set architectures, for example, in the x86 architecture, common jump instructions include unconditional jump (JMP), jump if equal (JE), jump if not equal (JNE), jump if greater than (JG), etc. By comparing the opcode of the instruction at the preset position with the opcodes included in the known jump instruction set in the x86 architecture, it can be determined whether the instruction is a jump instruction.

[0040] For example, from the instruction sequence of the source program corresponding to the above basic block, it can be seen that when the instruction with an offset of 5 is translated to the specified position, it is found that the instruction is JMP target label, which means that when the processor executes the JMP target_label instruction, it will immediately jump to other addresses identified by the target_label label to continue execution, and will no longer continue to execute subsequent instructions (such as MUL R0, R0, R3 and SD R0, 0x1000).

[0041] Then, since jump instructions can be mainly divided into unconditional jumps and conditional jumps. For example, unconditional jump instructions (such as JMP) will jump directly to the specified target address without satisfying any conditions; while conditional jump instructions (such as JE, JNE, etc.) can jump to a specified target address when the given conditions are met, and can jump to another specified target address when the given conditions are not met.

[0042] Therefore, the jump type of the first instruction can be determined according to the operation code of the first instruction. For example, if the operation code is JMP, it is an unconditional jump; if it is JE, JNE, etc., it is a conditional jump.

[0043] In some embodiments, the preset position may also be located at any position in the instruction sequence. In the present application, the position of the preset position in the instruction sequence is not limited. Optionally, the preset position may be set to the last instruction of the basic block at the end.

[0044] This is to ensure the integrity of the instructions during the program execution. Since a basic block is usually a set of sequentially executed instruction sequences with a single entry and exit, setting the preset position at the end of the basic block can ensure that the sequence is fully executed without interruption and achieve its intended function. For example, in a basic block that calculates matrix multiplication, the instructions cooperate with each other to complete part of the matrix multiplication calculation task. If the block is interrupted in the middle, the calculation result will be incomplete or wrong. Only by setting the preset position at the end of the basic block can the entire calculation step be completed as an atomic operation.

[0045] Setting the preset position as the end position of the basic block can comply with the sequential execution logic of the program. This is because the basic block is a sequence of instructions executed sequentially in the program. Usually, after completing a series of related operations internally, the next execution path will be determined based on conditional judgment or jump instructions. Setting the preset position at the end position of the basic block is consistent with the execution characteristics of the basic block. It can perform interrupt detection in time after the basic block completes its established task, and then decide whether to continue to execute the next basic block or perform interrupt processing based on the detection results, making the execution process of the program clearer and more orderly.

[0046] For example, in a program that calculates factorials, the operation of calculating factorials will be completed in a basic block. When the basic block is executed to the end position, it means that the factorial calculation is completed. At this time, an interrupt detection is performed, and then a decision is made whether to continue to perform other calculation tasks or handle the interrupt based on whether there is an interrupt signal. This is in line with the logical order of the program to complete the calculation first and then perform other operations.

[0047] Therefore, when translating to the first instruction included in the end position, the first instruction corresponding to the end position can be detected to obtain the instruction type of the first instruction.

[0048] For example, under the x86 architecture, the instruction sequence of a basic block of a source program containing multiple instructions can be expressed as follows.

[0049] MOV AX,10; assign 10 to register AX; ADD AX,20; add 20 to the value of AX; CMP AX,30; Compare the values ​​of AX and 30; JE equal_label; conditional jump instruction, if equal, jump to equal_label; JMP end_block; unconditional jump instruction, jump to end_block; equal_label: MOV AX,40; If they are equal, assign 40 to AX; end_block: MOV BX,AX; assign the value of AX to BX.

[0050] When it is detected that the last instruction is JE (Jump if Equa, conditional jump instruction), when the result of the previous comparison operation is equal (the zero flag ZF in the flag register = 1), the program will jump to the specified target address (such as equal_label); if it is not equal (ZF = 0), it will continue to execute the next instruction sequentially.

[0051] When the last instruction is detected as JMP (unconditional jump instruction), the program will jump directly to the specified target address (such as end_block) regardless of any conditions.

[0052] Step 102: When the instruction type is a preset type, write an interrupt detection instruction before the second instruction.

[0053] The second instruction is a translation result of the first instruction.

[0054] Considering that inserting a section of dynamic detection code for the interrupt flag bit in the instruction code corresponding to each basic block will cause additional code space and dynamic execution time, it is possible to judge based on the instruction type (i.e., jump type) of the first instruction of the basic block, and then determine whether to perform interrupt detection for different jump types. In addition to the preset types, the interrupt detection instruction can be stopped from being written, which can reduce unnecessary interrupt detection. In the case where the interrupt will not be detected in time due to the loop execution or the interrupt detection has been performed at other related instructions, the interrupt detection code is not inserted. For example, the not taken (condition not satisfied) branch of the conditional jump and the return-type indirect jump instruction can avoid unnecessary interrupt detection operations in these cases, thereby reducing the additional overhead of the system and improving the execution efficiency of the translated program.

[0055] Step 103: execute the interrupt detection instruction before executing the second instruction, so as to perform an event response corresponding to the second instruction according to the detected interrupt signal.

[0056] In this step, an interrupt detection operation is performed before executing the second instruction, which can ensure that the system can respond to various interrupt events in a timely manner, avoid ignoring interrupts due to jump operations, and ensure the stability, reliability and real-time performance of the system.

[0057] During operation, the operating system may encounter various external or internal events, such as interrupt signals generated by hardware devices (such as keyboards, mice, disks, etc.), or interrupts triggered by software exceptions (such as division by zero errors, illegal instructions, etc.). If the operating system does not respond to these interrupts in a timely manner, system errors may occur, such as data loss, program crashes, etc. By performing interrupt detection before the second instruction, these interrupts can be processed before the program control flow changes, thereby ensuring stable operation of the system.

[0058] By adopting the above technical scheme, during the translation of the basic block, it can be decided whether to insert the interrupt detection instruction according to the instruction type of the first instruction in the basic block, and the interrupt detection instruction can be inserted before the instruction of the preset type. In this way, when the program execution path undergoes a key change, the interrupt detection can be performed in time to ensure that the interrupt request is responded to at the appropriate time without interfering with the normal program execution process. It can prevent redundant code from being inserted into most basic blocks that do not require interrupt detection, thereby effectively reducing the storage space and dynamic execution time of the target program obtained after translation, and improving the performance of the translator.

[0059] Figure 3 It is a flowchart of another interruption detection method provided in an embodiment of the present application, and the method includes the following steps.

[0060] Step 201: Translate the instructions included in each basic block of the source program in the client.

[0061] Optionally, each basic block included in the source program in the client may be translated, and the instructions included in each basic block may be translated into instructions corresponding to the host architecture.

[0062] Specifically, this step may refer to the above step 101, which will not be described in detail here.

[0063] Step 202: When translating to a first instruction included in a preset position in the basic block, obtain an operation code of the first instruction.

[0064] The first instruction is an instruction that can change the execution order of the program, and can be used to jump to other locations in the program to continue execution according to specific conditions or unconditional jump instructions when executing the program, rather than executing them in the order in which the instructions are stored in the memory. The opcode is a binary code used to identify the jump type in the instruction set architecture corresponding to the client.

[0065] Furthermore, the opcode is a binary code used to identify the instruction type in the instruction set architecture corresponding to the client.

[0066] In this step, during the translation of the basic block, the instruction sequence corresponding to the basic block in the source program can be first obtained, and then the corresponding instruction sequence in the source program can be translated in sequence. When translating to the instructions included in the preset position, the corresponding instructions at the preset position can be detected to obtain the instruction type of the first instruction.

[0067] In a possible implementation, the first instruction is a jump instruction, and when obtaining the instruction type of the first instruction, the jump type of the jump instruction may be obtained.

[0068] For example, for an instruction sequence of a basic block of a source program containing multiple instructions, the instruction position with an offset of 5 can be set as the preset position. In other words, counting from the start instruction of the instruction sequence, the position of the 6th instruction is the preset position to be detected. For example, the instruction sequence of a basic block corresponding to the source program can be as follows: Offset Instructions 0LI R0,5; 1LI R2,3; 2ADD R0,R0,R2; 3LI R3,10; 4SUB R3,R3,R2; 5JMP target label; #preset position; 6MUL R0,R0,R3; 7SD R0,0x1000.

[0069] In a possible implementation, considering that there are specific jump instructions in different instruction set architectures, for example, in the x86 architecture, common jump instructions include JMP (unconditional jump), JE (jump if equal), JNE (jump if not equal), JG (jump if greater than), etc. By comparing the opcode of the instruction at the preset position with the known jump instruction set, it can be determined whether the instruction is a jump instruction.

[0070] For example, from the instruction sequence of the source program corresponding to the above basic block, it can be seen that when the instruction with offset 5 is translated, it is found that the instruction is JMP target label, which means that when the processor executes the JMP target_label instruction, it will immediately jump to the address identified by the target_label label to continue execution, and will no longer continue to execute subsequent instructions (such as MUL R0, R0, R3 and SD R0, 0x1000).

[0071] When it is determined that the instruction at the end position is a jump instruction, the corresponding jump type, ie, unconditional jump or conditional jump, can be determined by obtaining the operation code of the jump instruction.

[0072] The opcode is a part of the instruction machine code, which defines the specific operation to be performed by the instruction.

[0073] It should be noted that in different instruction set architectures, the encoding method and length of the opcode are different. Therefore, the method of obtaining the opcode is usually related to the specific implementation environment.

[0074] In a possible implementation, when translating the jump instruction, a disassembly operation may be performed on the jump instruction to convert the jump instruction into an instruction sequence in the form of assembly language.

[0075] For example, under the x86 architecture, tools such as the capstone disassembler (used to disassemble machine code into assembly instructions) can be used to disassemble the executable file into human-readable assembly instructions and then extract the opcode of the jump instruction.

[0076] When it is determined that it is a jump instruction, the instruction decoder will parse out the opcode part according to the instruction encoding rules. Instructions usually consist of opcodes and operands, and the opcode occupies a fixed position in the instruction encoding. For example, in some simple instruction sets, the opcode is located in the first few bits of the instruction, and the opcode is parsed from the binary encoding of the instruction through bit operations and mask operations.

[0077] For example, taking the instruction stored in a 32-bit register and the opcode in the first 6 bits as an example, the right shift operation can be performed first. Specifically, the instruction code in the 32-bit register can be shifted right by 26 bits as a whole. This is because the opcode is in the first 6 bits. After right shifting 26 bits, the opcode will be moved to the lowest 6 bits of the register, and the other high bits will be discarded. Then a mask operation can be performed. By performing an AND operation with 0x3F, all bits except the lowest 6 bits can be set to 0, leaving only the lowest 6 bits. Among them, 0x3F is represented in hexadecimal, and converted to binary is 00111111. This is because in the binary form of 0x3F, the lower 6 bits are all 1, and the upper 26 bits are all 0. The bitwise AND operation is performed with the instruction code after the right shift operation, and the opcode located in the lowest 6 bits can be accurately extracted through the AND operation.

[0078] Step 203: Search the preset corresponding relationship for the operation type corresponding to the operation code to obtain the instruction type of the first instruction.

[0079] The preset corresponding relationship includes the corresponding relationship between different operation codes and corresponding instruction types.

[0080] In this step, when the first instruction is a jump instruction, a preset corresponding relationship may be first constructed. The preset corresponding relationship may be expressed in the form of a mapping, which stores the corresponding information between the operation code and the jump type.

[0081] Since the operation codes and types of jump instructions are different in different computer architectures, a simple preset correspondence relationship taking the x86 architecture as an example can be expressed as follows.

[0082] Opcode jump type 0xE9 unconditional direct jump; 0xEB unconditional short jump; 0x74 conditional jump (equal jump, ZF=1); 0x75 Conditional jump (not equal jump, ZF=0).

[0083] In the code, you can also use a dictionary to represent the preset correspondence of opcodes, for example, opcode_to_jump_type (used to determine the corresponding jump type based on the opcode) is used to represent the preset correspondence, where the key is the opcode (in hexadecimal value expressed as an integer) and the value is the corresponding jump type description. Then you can use the if opcode inopcode_to_jump_type statement to determine whether the opcode exists in the dictionary. If it exists, use opcode_to_jump_type[opcode] to get the corresponding jump type; if it does not exist, output a prompt message similar to "not found".

[0084] In some embodiments, the jump type may include a conditional jump type, an indirect jump type, an unconditional jump type, and the like.

[0085] Specifically, the conditional jump type includes branches where the condition is met (taken branches) and branches where the condition is not met (not taken branches).

[0086] Since the jump target of the conditional jump instruction (such as JE, JNE, etc.) depends on whether the condition is met. In the loop structure, the conditional jump instruction is often used to control the execution of the loop. The taken branch will cause the program to jump back to the starting position of the loop to form a loop. If the interrupt is not detected in time during the loop, the interrupt will not be processed for a long time. Therefore, inserting the interrupt detection code before the instruction of the taken branch of the conditional jump instruction to jump to the link target can prevent the problem of long execution time caused by untimely detection caused by the loop structure. The not taken branch indicates that the condition is not met, and the program will continue to execute sequentially. Generally, the problem of untimely detection caused by the loop structure will not occur. Therefore, not inserting the interrupt detection code avoids unnecessary detection overhead and improves the execution efficiency of the target program.

[0087] For example, the following instructions represent a loop of instruction sequence A: MOV CX,5; Initialize loop counter to 5; loop_start:; ; Loop body code DEC CX; counter decreases by 1; CMP CX,0; Compare the counter to see if it is 0; JNE loop_start; If it is not 0 (that is, the condition is met and the taken branch is taken), jump back to loop_start.

[0088] From the above instruction sequence, we can see that JNEloop_start is a conditional jump instruction. When CX is not 0, it will jump back to loop_start through the taken branch to form a loop.

[0089] During the operation of the system, various external or internal events may generate interrupt signals, such as the user typing on the keyboard, the hard disk completing data reading and writing, etc. In order to ensure the responsiveness and stability of the system, these interrupts need to be handled in a timely manner. If interrupt detection is not performed during the execution of the loop, even if an interrupt signal is generated, the system will not be able to respond in time, which will cause data loss, no feedback on user operations, and other problems. Therefore, inserting detection code before the instruction to jump to the link target of the taken branch of the conditional jump instruction can ensure that there is an interrupt signal before each loop jump. Once an interrupt is detected, it means that the interrupt handler needs to be executed. The host machine's operating system will pause the current loop and switch to execute the interrupt handler. After processing, it will return to the loop to continue execution, thereby avoiding the problem of interrupts not being processed for a long time.

[0090] Indirect jump instructions usually include: return type instructions (such as ret instructions), and non-return type indirect jump instructions (such as MP[eax] instructions).

[0091] Since return instructions such as the ret instruction are used to indicate function return and restore the execution environment before the function call. Since the interrupt detection code has been inserted at the function call instruction, another detection at the ret instruction will cause repeated detection. Therefore, the interrupt detection of the ret instruction can be optimized to reduce unnecessary performance loss. For non-return indirect jump instructions (such as JMP[eax]), their jump behavior is relatively complex. In order to ensure that it can check whether there is an interrupt that needs to be processed before the indirect jump, the interrupt detection code is inserted before the instruction that jumps to the link target after the instruction is translated to detect whether there is an interrupt handler.

[0092] For example, for return-type instructions, an instruction sequence describing a function call and return process can be represented as follows.

[0093] MAIN: ;Insert interrupt detection code before function call CHECK_INTERRUPT CALL SUBROUTINE ; Subsequent code MOV AX,10 JMP END_PROGRAM ;Subroutines SUBROUTINE: ; Subroutine code MOV BX, 20 RET; Function returns, no interrupt detection is performed here; END_PROGRAM: HLT.

[0094] From the above instruction sequence, we can see that CALLSUBROUTINE is a function call instruction, and the interrupt detection code CHECK_INTERRUPT is inserted before the call. When the subroutine executes the RET instruction, since the interrupt detection has been performed at the function call, the interrupt detection is no longer performed here, avoiding repeated operations and reducing performance loss.

[0095] For another example, for a non-return indirect jump instruction, an instruction sequence for the non-return indirect jump instruction can be represented as follows.

[0096] MAIN: MOV EAX,[TARGET_ADDRESS]; Load the target address into the EAX register; ;Insert interrupt detection code before indirect jump CHECK_INTERRUPT JMP [EAX]; indirect jump; ; Subsequent code MOV AX,10 JMP END_PROGRAM ;Code at the target address TARGET_CODE: MOV BX,20 JMP END_PROGRAM END_PROGRAM: HLT.

[0097] From the above instruction sequence, we know that JMP[EAX] is a non-return indirect jump instruction. Before executing this instruction, insert the interrupt detection code "CHECK_INTERRUPT". This ensures that before the program jumps to the address pointed to by the non-return indirect jump instruction, it can detect whether there is an interrupt handler to be processed, ensuring the stability of the target program obtained after translation and the response time of execution.

[0098] In this way, by optimizing the interrupt detection of return-type indirect jump instructions and inserting interrupt detection code before non-return-type indirect jump instructions, we can avoid unnecessary repeated detection and reduce performance loss, and ensure timely response to the interrupt handler before complex jump operations, thereby improving the overall performance and reliability of the target program obtained after translation.

[0099] Also, unconditional jump instructions (such as JMP) will jump to the specified target address regardless of any conditions, and the jump behavior is determined. Inserting interrupt detection code before the instruction to jump to the link target after the instruction is translated can ensure that whether an interrupt occurs before the program jumps, avoid skipping the interrupt handler during the jump process, and ensure the system's interrupt response timeliness.

[0100] When the preset type includes a conditional jump type, execute step 204, step 207-step 209; when the preset type includes an indirect jump type, execute step 205-step 209; when the preset type includes an unconditional jump type, execute step 207 and step 209.

[0101] Step 204: in the process of translating the first instruction, obtaining the instruction to be jumped in the first instruction.

[0102] The instruction to be jumped to includes the next instruction to be executed adjacent to the first instruction.

[0103] For example, taking the x86 architecture as an example, the JE instruction in the x86 architecture means jumping if "equal to" a given condition (that is, jumping if the condition is met), and the JNE instruction means jumping if "not equal to" a given condition (that is, jumping if the condition is not met). Therefore, when the first instruction is read, the meaning of the instruction representing the specific operation included in the first instruction can be identified. For example, when it is identified that the instruction representing the specific operation included in the first instruction is the JE instruction, the first instruction indicates that if the condition is met, it will jump to the instruction to be jumped included in the first instruction to execute the instruction to be jumped; and when it is identified that the instruction representing the specific operation included in the first instruction is the JNE instruction, the first instruction indicates that if the condition is not met, it will jump to the instruction to be jumped included in the first instruction to execute the instruction to be jumped. Among them, the instruction to be jumped refers to the next instruction to be executed after the execution of the first instruction.

[0104] If the condition is satisfied as indicated in the first instruction, step 207 is executed; if the condition is not satisfied as indicated in the first instruction, step 208 is executed.

[0105] Step 205: Obtain the operand included in the first instruction.

[0106] The operand is the data address involved in the operation in the first instruction.

[0107] In this step, the indirect jump instruction is first identified by identifying the operation code of the instruction, wherein the indirect jump instruction determines the instruction to be executed through the parameter value included in the second instruction.

[0108] There are specific indirect jump instructions in different instruction set architectures. For example, in the x86 architecture, common indirect jump instruction forms include JMP[reg] instruction, JMP[mem+reg*scale+disp] instruction, and RET instruction series (essentially a special indirect jump), etc. By comparing the opcode of the instruction at the preset position with the opcode included in the known jump instruction set in the x86 architecture, it is determined whether the instruction is an indirect jump instruction.

[0109] For example, the JMP [EAX] instruction, the JMP [0x1000 + EBX * 4 + 8] instruction and the RET instruction are all indirect jump instructions.

[0110] Then, when an indirect jump instruction is identified, the data address included in the indirect jump instruction can be checked to determine the register involved in the jump address calculation.

[0111] For example, for the JMP[reg] instruction form: the operand is a register, such as the EAX register in the JMP[EAX] instruction; for the JMP[mem+reg*scale+disp] instruction form: the operand involves multiple fields, and the registers need to be parsed out, such as the EBX register in the JMP[0x1000+EBX*4+8] instruction; and for the RET instruction: although there is no explicit operand on the surface, it is closely related to the stack pointer register (ESP or RSP, depending on 32-bit or 64-bit mode).

[0112] Step 206, determining the register type corresponding to the operand.

[0113] In the case where the register involved in the jump address calculation is determined using step 205, step 206 may determine the corresponding register type according to the determined specific register.

[0114] The register type includes a first register type and a second register type, and the first register type includes a general register, and the second register type includes a stack pointer register.

[0115] In one possible implementation, non-return indirect jump instructions are usually related to general registers (such as EAX, EBX, etc.) because general registers can be flexibly assigned and modified during program execution, and non-return indirect jump instructions are often used to implement dynamic program flow control, such as determining the jump target address based on different conditions, runtime calculation results, or external inputs. By storing the calculated target address in a general register and then using an indirect jump instruction to jump to the address pointed to by the register, highly flexible jump logic can be implemented.

[0116] Typically, a non-return indirect jump instruction, for example, the JMP [EAX] instruction will jump to the memory address pointed to by the EAX register to execute code. Therefore, when it is determined that the register is a general register (such as EAX, EBX, etc.), it can be determined that the corresponding register type is the first register type.

[0117] In another possible implementation, since the indirect jump instruction of the return type is usually closely related to the stack operation, this is because the return address is pushed into the stack when the function is called, and the return address popped from the stack can be used to jump when the function returns.

[0118] Typically, an indirect jump instruction of the return type, such as the ret instruction, implicitly uses the stack pointer register (ESP). For example, when the ret instruction is executed, it usually pops a value (i.e., the return address) from the top of the stack and loads it into the instruction pointer register (EIP) to implement the return of the function. Therefore, when it is determined that the register is the stack pointer register (ESP), it can be determined that the corresponding register type is the second register type.

[0119] When the register type is the first register type, step 207 is executed; when the register type is the second register type, step 208 is executed.

[0120] Step 207, write an interrupt detection instruction before the second instruction.

[0121] In this step, if the preset type is a conditional jump type, then when the condition indicated in the first instruction is satisfied, an interrupt detection instruction may be written before the to-be-jumped instruction included in the second instruction.

[0122] For example, in the case of inserting an interrupt detection code, the above instruction sequence A can be expressed as follows.

[0123] MOV CX,5; Initialize loop counter to 5; loop_start: DEC CX; loop body code; counter decrements by 1; CMP CX,0; Compare the counter to see if it is 0; CHECK_INTERRUPT; insert interrupt detection code; JNE loop_start; If it is not 0 (that is, the condition is met and the taken branch is taken), jump back to loop_start.

[0124] From the above instruction sequence, we can know that CHECK_INTERRUPT is the interrupt detection code inserted. Every time the loop executes to this step, the system will check whether there is an interrupt signal. If there is, it will process it accordingly. If not, it will continue to execute the loop process until the comparison counter is 0 and jump out of the loop process.

[0125] Step 208, stop before the second instruction and write an interrupt detection instruction.

[0126] In this step, if the preset type is a conditional jump type, when the condition indicated in the first instruction is not satisfied, the interrupt detection instruction can be written before the to-be-jumped instruction included in the second instruction.

[0127] Step 209, in the process of running the translation result, an interrupt detection operation is performed before executing the second instruction, so as to respond to the event that triggers the interrupt signal according to the detected interrupt signal.

[0128] In this step, the interrupt identification value stored in the interrupt register may be firstly obtained.

[0129] The interrupt identification value is an interrupt identification value stored in the interrupt register when an interrupt signal is detected; the interrupt identification value includes a first target value, such as 1, and a second target value, such as 0.

[0130] When the interrupt flag value is the first target value, the second instruction is executed. Alternatively, when the interrupt flag value is the second target value, an exit instruction is executed, wherein the exit instruction is used to indicate stopping the execution of the instruction sequence corresponding to the basic block.

[0131] By adopting the above technical scheme, during the translation of the basic block, it can be decided whether to insert the interrupt detection instruction according to the instruction type of the first instruction, and the interrupt detection instruction can be inserted before the instruction of a specific type. In this way, when the program execution path undergoes a critical change, the interrupt detection can be performed in time to ensure that the interrupt is responded to at the appropriate time without interfering with the normal program execution process. It can prevent the basic blocks that do not require interrupt detection from being inserted with redundant code, thereby effectively reducing the overall code space occupied by the target program, and can reduce the dynamic execution time of the code, which can improve the performance of the translator.

[0132] Figure 4 is a block diagram of an interrupt detection device provided in an embodiment of the present application, such as Figure 4 As shown, the device 300 includes: The translation module 301 is used for translating the instructions included in each basic block of the source program in the client, and when translating to the first instruction included in the preset position in the basic block, obtaining the instruction type of the first instruction; A writing module 302, used for writing an interrupt detection instruction before a second instruction when the instruction type is a preset type; the second instruction is a translation result of the first instruction; The detection module 303 is used to execute the interrupt detection instruction before executing the second instruction, so as to perform an event response corresponding to the second instruction according to the detected interrupt signal.

[0133] Optionally, the translation module 301 is used to obtain the opcode of the first instruction; the opcode is a binary code used to identify the instruction type in the instruction set architecture corresponding to the client; the operation type corresponding to the opcode is searched in the preset correspondence relationship to obtain the instruction type of the first instruction; the preset correspondence relationship includes the correspondence between different opcodes and corresponding instruction types.

[0134] Optionally, the preset type includes a conditional jump type; the conditional jump type is an instruction type that determines the instruction to be executed by determining whether the condition included in the second instruction is satisfied; the write module 302 is used to obtain the instruction to be jumped in the first instruction during the translation of the first instruction, and the instruction to be jumped is included in the next instruction to be executed adjacent to the first instruction; when the condition is satisfied as indicated in the first instruction, start writing the interrupt detection instruction before the instruction to be jumped included in the second instruction; otherwise, stop writing the interrupt detection instruction before the instruction to be jumped included in the second instruction.

[0135] Optionally, the preset type includes an indirect jump type; the indirect jump type is an instruction type for determining the instruction to be executed through a parameter value included in the second instruction; the write module 302 is used to obtain an operand included in the first instruction; the operand is the address of the data involved in the operation in the first instruction; determine the register type corresponding to the operand; and according to the register type, execute the write operation corresponding to the interrupt detection instruction.

[0136] Optionally, the writing module 302 is used to start writing the interrupt detection instruction before the second instruction when the register type is the first register type; and stop writing the interrupt detection instruction before the second instruction when the register type is the second register type.

[0137] Optionally, the preset type includes an unconditional jump type; the writing module 302 is used to insert an interrupt detection instruction between a previous instruction adjacent to the second instruction and the second instruction.

[0138] Optionally, the detection module 303 is used to obtain the interrupt identification value stored in the interrupt register; the interrupt identification value is the marking information sent to the interrupt register by the interrupt detection instruction when the interrupt signal is detected; when the interrupt identification value is the first target value, the second instruction is executed; when the interrupt identification value is the second target value, an exit instruction is executed to stop executing the instruction sequence corresponding to the basic block.

[0139] In summary, this embodiment can determine whether to insert an interrupt detection instruction according to the instruction type of the first instruction in the basic block during the translation of the basic block, and can insert the interrupt detection instruction before the instruction of the preset type. In this way, when a key change occurs in the program execution path, interrupt detection can be performed in time to ensure that the interrupt request is responded to at the appropriate time without interfering with the normal program execution process. This can prevent unnecessary code from being inserted into most basic blocks that do not require interrupt detection, thereby effectively reducing the storage space and dynamic execution time of the target program obtained after translation and improving the performance of the translator.

[0140] Figure 5 1 is a block diagram of an electronic device 500 according to an exemplary embodiment. For example, the electronic device 500 may be a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0141] Reference Figure 5 , the electronic device 500 may include one or more of the following components: a processing component 502 , a memory 504 , a power component 506 , a multimedia component 508 , an audio component 510 , an input / output interface 512 , a sensor component 514 , and a communication component 516 .

[0142] The processing component 502 generally controls the overall operation of the electronic device 500, such as operations associated with display, phone calls, data communications, camera operations, and recording operations. The processing component 502 may include one or more processors 520 to execute instructions to complete all or part of the steps of the above-mentioned method. In addition, the processing component 502 may include one or more modules to facilitate the interaction between the processing component 502 and other components. For example, the processing component 502 may include a multimedia module to facilitate the interaction between the multimedia component 508 and the processing component 502.

[0143] The memory 504 is used to store various types of data to support the operation of the electronic device 500. Examples of such data include instructions for any application or method operating on the electronic device 500, contact data, phone book data, messages, pictures, multimedia, etc. The memory 504 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk.

[0144] The power supply component 506 provides power to the various components of the electronic device 500. The power supply component 506 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 500.

[0145] The multimedia component 508 includes a screen that provides an output interface between the electronic device 500 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touch, slide, and gestures on the touch panel. The touch sensor may not only sense the demarcation of the touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 508 includes a front camera and / or a rear camera. When the electronic device 500 is in an operating mode, such as a shooting mode or a multimedia mode, the front camera and / or the rear camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have a focal length and optical zoom capability.

[0146] The audio component 510 is used to output and / or input audio signals. For example, the audio component 510 includes a microphone (MIC), and when the electronic device 500 is in an operation mode, such as a call mode, a recording mode, and a voice recognition mode, the microphone is used to receive an external audio signal. The received audio signal can be further stored in the memory 504 or sent via the communication component 516. In some embodiments, the audio component 510 also includes a speaker for outputting audio signals.

[0147] The input / output interface 512 provides an interface between the processing component 502 and the peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include but are not limited to: a home button, a volume button, a start button, and a lock button.

[0148] The sensor assembly 514 includes one or more sensors for providing various aspects of status assessment for the electronic device 500. For example, the sensor assembly 514 can detect the open / closed state of the electronic device 500, the relative positioning of components, such as the display and keypad of the electronic device 500, and the sensor assembly 514 can also detect the position change of the electronic device 500 or a component of the electronic device 500, the presence or absence of user contact with the electronic device 500, the orientation or acceleration / deceleration of the electronic device 500, and the temperature change of the electronic device 500. The sensor assembly 514 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 514 may also include an optical sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 514 may also include an accelerometer, a gyroscope sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

[0149] The communication component 516 is used to facilitate wired or wireless communication between the electronic device 500 and other devices. The electronic device 500 can access a wireless network based on a communication standard, such as WiFi, a carrier network (such as 2G, 3G, 4G or 5G), or a combination thereof. In an exemplary embodiment, the communication component 516 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 516 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0150] In an exemplary embodiment, the electronic device 500 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement an interrupt detection method provided in an embodiment of the present application.

[0151] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 504 including instructions, and the instructions can be executed by a processor 520 of an electronic device 500 to perform the above method. For example, the non-transitory storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, etc.

[0152] Figure 66 is a block diagram of another electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be provided as a server. Figure 6 The electronic device 600 includes a processing component 622, which further includes one or more processors, and a memory resource represented by a memory 632 for storing instructions executable by the processing component 622, such as an application. The application stored in the memory 632 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 622 is configured to execute instructions to perform an interrupt detection method provided in an embodiment of the present application.

[0153] The electronic device 600 may further include a power supply component 626 configured to perform power management of the electronic device 600, a wired or wireless network interface 650 configured to connect the electronic device 600 to a network, and an input / output interface 658. The electronic device 600 may operate based on an operating system stored in the memory 632.

[0154] An embodiment of the present application also provides a computer program product, including a computer program, and an interrupt detection method implemented when the computer program is executed by a processor.

[0155] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0156] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. An interruption detection method, characterized in that: The method comprises: When translating instructions included in each basic block of the source program in the client, when translating to a first instruction included in a preset position in the basic block, obtaining an instruction type of the first instruction; When the instruction type is a preset type, an interrupt detection instruction is written before the second instruction; the second instruction is a translation result of the first instruction; The interrupt detection instruction is executed before executing the second instruction, so as to perform an event response corresponding to the second instruction according to the detected interrupt signal.

2. The method according to claim 1, characterized in that: The instruction type for obtaining the first instruction includes: Obtaining an operation code of the first instruction; the operation code is a binary code for identifying an instruction type in an instruction set architecture corresponding to the client; The operation type corresponding to the operation code is searched in a preset corresponding relationship to obtain the instruction type of the first instruction; the preset corresponding relationship includes a corresponding relationship between different operation codes and corresponding instruction types.

3. The method according to claim 1, characterized in that The preset type includes a conditional jump type; the conditional jump type is an instruction type that determines the instruction to be executed by determining whether a condition included in the second instruction is satisfied; Then, writing the interrupt detection instruction before the second instruction includes: In the process of translating the first instruction, obtaining the to-be-jumped instruction in the first instruction; The instruction to be jumped to includes a next instruction to be executed adjacent to the first instruction; When the condition indicated in the first instruction is satisfied, start writing the interrupt detection instruction before the instruction to be jumped included in the second instruction; otherwise, stop writing the interrupt detection instruction before the instruction to be jumped included in the second instruction.

4. The method according to claim 1, characterized in that The preset type includes an indirect jump type; the indirect jump type is an instruction type of an instruction to be executed determined by a parameter value included in the second instruction; Then, writing the interrupt detection instruction before the second instruction includes: Acquire an operand included in the first instruction; the operand is an address of data involved in operation in the first instruction; Determine the register type corresponding to the operand; According to the register type, a write operation corresponding to the interrupt detection instruction is executed.

5. The method according to claim 4, characterized in that The execution of the write operation corresponding to the interrupt detection instruction includes: When the register type is the first register type, starting to write the interrupt detection instruction before the second instruction; When the register type is the second register type, the interrupt detection instruction is written before the second instruction.

6. The method according to claim 1, characterized in that The preset type includes an unconditional jump type; Then, writing the interrupt detection instruction before the second instruction includes: An interrupt detection instruction is inserted between a previous instruction adjacent to the second instruction and the second instruction.

7. The method according to any one of claims 1 to 6, characterized in that Executing the interrupt detection instruction before executing the second instruction includes: Obtaining an interrupt identification value stored in an interrupt register; the interrupt identification value is marking information sent to the interrupt register by the interrupt detection instruction when the interrupt signal is detected; When the interrupt flag value is the first target value, executing the second instruction; When the interrupt flag value is the second target value, an exit instruction is executed to stop executing the instruction sequence corresponding to the basic block.

8. An interruption detection device, characterized in that: The device comprises: A translation module, configured to, when translating instructions included in each basic block of a source program in a client, obtain an instruction type of a first instruction included in a preset position in the basic block when the first instruction is translated; A writing module, used for writing an interrupt detection instruction before a second instruction when the instruction type is a preset type; the second instruction is a translation result of the first instruction; The detection module is used to execute the interrupt detection instruction before executing the second instruction, so as to perform an event response corresponding to the second instruction according to the detected interrupt signal.

9. An electronic device, characterized in that: The method comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, wherein the program or instruction implements the steps of the method according to any one of claims 1 to 7 when executed by the processor.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the method as claimed in any one of claims 1 to 7.

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