Storage and calculation integrated architecture simulator acceleration method based on dynamic domain decomposition

Abstract

The invention discloses a storage and calculation integrated architecture simulator acceleration method based on dynamic domain decomposition, and the method is based on a dynamic domain decomposition technology, and is especially suitable for a discrete event driven type simulation environment. An existing system structure simulator can utilize the advantages of a modern multi-core CPU to divide a simulation task into a plurality of relatively independent parts through a domain decomposition strategy so as to achieve parallel processing. However, in a storage and calculation integrated framework, due to the fact that the number of calculation cores is large and complex connection topology exists between the cores, a traditional domain decomposition method is difficult to effectively apply, and the simulation efficiency is greatly limited. According to the method provided by the invention, the problem is solved, and dynamic domain decomposition is carried out on the simulation model through a specially designed algorithm by utilizing a mapping file provided by a compiler. According to the method, domain division can be adjusted and optimized in real time according to specific requirements of the simulation architecture during execution of different tasks, and the working efficiency and the simulation speed of the storage and calculation integrated architecture simulator are remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the field of intelligent computing, and in particular relates to a storage-computation integrated architecture simulator acceleration method based on dynamic domain decomposition. Background Art

[0002] In recent years, as the scale of DNN model parameters has increased, CMOS-based devices following the von Neumann architecture are now facing the challenge of the memory wall and encountering bottlenecks in the improvement of storage, bandwidth, and energy consumption. Storage-computing integration is considered to be a promising technology to avoid the memory wall and has become a hot research direction in the field of deep neural network accelerators.

[0003] At the same time, storage-computing simulators are playing an increasingly important role in storage-computing hardware-software co-design and architecture search. In order to improve simulation efficiency, the traditional simulation field widely uses decomposition methods to accelerate the simulation process, that is, to divide the entire simulation task into multiple relatively independent subtasks, which run in parallel on different processor cores. This method is effective for conventional computer architectures. However, for the storage-computing architecture, its complexity lies in the fact that it contains a large number of closely connected computing cores and forms a specific topological structure, which makes it difficult to directly apply the traditional domain decomposition strategy. Therefore, in actual operation, many simulators of storage-computing architecture still rely on polling each computing core or using less efficient methods such as serial discrete event simulation, which leads to efficiency bottlenecks in the simulation process.

[0004] In response to the above problems, the present invention proposes a new method based on dynamic domain decomposition, which aims to solve the efficiency problem of the storage-computing integrated architecture simulator. This method makes full use of the mapping file information provided by the compiler corresponding to the simulation architecture. The mapping file records in detail the task allocation of each computing core during the program execution process. Through the designed algorithm, the simulation model can be dynamically decomposed according to specific task requirements. This means that when faced with different types of computing tasks, the simulator can automatically adjust its internal structure and optimize parallel processing capabilities, thereby significantly improving the simulation speed.

[0005] In addition, this method of dynamic domain decomposition not only improves simulation efficiency, but also enhances the flexibility and adaptability of the simulator. It allows the simulator to adjust its configuration in real time according to changes in specific application scenarios to ensure optimal performance. At the same time, since this method can better tap the inherent parallelism of the storage-computing integrated architecture, it also provides new ideas and technical support for future high-performance computing research. This invention further optimizes the storage-computing integrated architecture simulation technology and is expected to promote the rapid development of related fields. Summary of the invention

[0006] The purpose of the present invention is to provide a storage-computing integrated architecture simulator acceleration method based on dynamic domain decomposition to address the deficiencies of the prior art. The purpose of the present invention is achieved through the following technical solutions: A storage-computing integrated architecture simulator acceleration method based on dynamic domain decomposition, comprising:

[0007] Based on the compiler, the target network is converted into a form suitable for execution of the storage-computing integrated architecture, that is, a binary instruction program for simulation, and an additional mapping file is created; the mapping file includes weight replication information, weight and storage-computing integrated device array mapping information, and the number of inputs corresponding to each weight block;

[0008] The simulator obtains a configuration file, initializes and instantiates a simulation model based on the configuration file, and then domain decomposes the simulation model based on the mapping file; the simulator allocates a computing thread to each decomposed part, loads the binary instruction program, and the simulator starts the simulation task. The storage-computing integrated architecture includes a storage-computing integrated device array; the storage-computing integrated device array includes a number of storage-computing integrated computing cores.

[0009] Furthermore, it also includes: measuring the performance of the simulation process based on evaluation indicators, wherein the evaluation indicators include delay, energy consumption, power consumption and accuracy.

[0010] Furthermore, the target network includes a deep neural network model.

[0011] Furthermore, the target network is converted into a form suitable for execution of the storage-computing integrated architecture based on the compiler, that is, a binary instruction program for simulation, and an additional mapping file is created, including:

[0012] First, the compiler performs operator fusion; then the weight mapping process distributes the weights of the target network to the storage and computing integrated device array; the subsequent data flow scheduling focuses on optimizing the design data flow path between different computing units; finally, the compiler generates a binary instruction program for simulation and creates an additional mapping file.

[0013] Furthermore, the simulator allocates computing threads to each decomposed part, including:

[0014] Weight replication is used to balance the execution time between different network layers. When allocating computing threads, the number of inputs corresponding to each weight block is combined to keep the workload of each thread balanced. Alternatively, computing cores that map the same network layer are allocated to the same thread. Among them, each input of each weight block is equivalent to the unit workload of the simulator.

[0015] Furthermore, the computing cores assigned to the same thread share a time queue for simulation.

[0016] Furthermore, the computing cores mapped with the same network layer are assigned to the same thread. Specifically, n network layers are assigned to n threads respectively. To ensure the execution order of instructions, the simulation process is as follows:

[0017] Thread 1, which contains the first-layer weight calculation core, starts simulation from time 0; when reaching time a, the number of generated results reaches the threshold, and the event queue of thread 1 sends these data to thread 2, which contains the second-layer weight calculation core, through inter-thread events; thread 2 will start simulation from time 0 after receiving these data, and will synchronize with the data sent by thread 1 after its own simulation time reaches time a, and load these data into its own calculation core. This ensures that thread 2 receives data at the correct time; after that, thread 2 will pause at time a until thread 1 sends data next time and then simulates again, and synchronizes at the time of receiving new data; the interaction process between thread n-1 and thread n is the same as the interaction process between thread 1 and thread 2.

[0018] The beneficial effects of the present invention are as follows: 1. The method of the present invention is specially designed for a storage-computing integrated architecture simulator, and is particularly optimized for discrete event-driven simulators. The method improves simulation efficiency and performance by modifying the existing compiler-simulator interaction process, especially when processing complex computing tasks.

[0019] 2. The mapping file is generated by the compiler corresponding to the simulation architecture. It is different from the storage-computing integrated program generated by the compilation. It is mainly used to describe the mapping of the corresponding network weights on the storage-computing integrated device array. It must include but not be limited to the following information: weight replication information, weight and storage-computing integrated device array mapping information, the number of inputs corresponding to each weight block and other key data. This information is crucial to ensure the accuracy and consistency of the simulation process, so that the simulator can accurately reproduce the behavior of the original DNN model at runtime. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0021] Figure 1 A simulation flow chart provided for an embodiment of the present invention.

[0022] Figure 2 A high throughput based domain decomposition flow chart.

[0023] Figure 3 A low-latency based domain decomposition flow chart. DETAILED DESCRIPTION

[0024] The present invention is described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the features of the following embodiments and implementations can be combined with each other.

[0025] A storage-computing integrated architecture simulator acceleration method based on dynamic domain decomposition of the present invention comprises:

[0026] Based on the compiler, the target network is converted into a form suitable for execution of the storage-computing integrated architecture, that is, a binary instruction program for simulation, and an additional mapping file is created; the mapping file includes weight replication information, weight and storage-computing integrated device array mapping information, and the number of inputs corresponding to each weight block;

[0027] Get the configuration file. The simulator initializes and instantiates the simulation model based on the configuration file. Then, the simulation model is domain decomposed based on the mapping file. The smallest unit of domain decomposition is a storage-computing integrated computing core, that is, a functional unit that can execute instructions independently or have a complete control flow. This means that each storage-computing integrated computing core can participate in the simulation as an independent working unit. Each decomposed part can be composed of one or more storage-computing integrated computing cores, depending on the specific computing task requirements and hardware configuration. This method ensures flexibility and scalability, and the allocation of computing resources can be adjusted according to actual needs; then, the simulator allocates computing threads to each decomposed part, loads the binary instruction program, and the simulator starts the simulation task.

[0028] Specifically, for a specific computing task, before the simulation starts, the simulator receives a network mapping file compiled by the corresponding compiler. The mapping file not only contains information about the network structure, but also describes in detail the specific location of the weight data in the storage and computing device array. Through a specific algorithm, the simulation model is dynamically decomposed according to the mapping file to ensure that the model can be reasonably divided according to the task characteristics to meet different computing needs. The domain decomposition algorithm follows the principle of load balancing and strives to make the workload of each divided part in the simulator similar, so as to more effectively utilize multi-threading to increase the simulation speed. Through the load distribution strategy, it is ensured that the task distribution between each computing unit is as even as possible to avoid some units being overloaded while other units are idle, thereby maximizing the overall performance. This dynamic domain decomposition technology can effectively reduce the communication overhead between different decomposed parts and maximize the use of hardware resources.

[0029] During the simulation process, a parallel discrete event simulation mechanism is used. Each part generated by domain decomposition shares a global event queue for that part, and each event queue is assigned a computing thread to support efficient parallel processing while ensuring the consistency and correctness of the event sequence. This mechanism allows multiple computing threads to execute in parallel without conflict, thereby improving the speed and efficiency of the simulation.

[0030] The applicable architecture of this application should be a complex architecture with multiple integrated computing cores and a complete interconnection network, which is particularly suitable for high-performance computing tasks in a multi-core or multi-node environment, and does not include a simple single-core architecture. In a single-core architecture, due to the lack of parallel processing capabilities, the simulator degenerates into a serial execution mode and loses the acceleration effect. Therefore, this application emphasizes the parallel acceleration advantage achieved in a multi-core environment.

[0031] This application is applicable to scenarios where the performance of the simulation host is limited. When the performance of the simulation host is unlimited, the simulation architecture will perform domain decomposition based on the number of available storage-computing integrated computing cores, that is, the simulation model domain will be decomposed into several parts according to the number of storage-computing integrated computing cores, and a time queue and execution thread will be allocated to each part. In this case, ignoring the synchronization overhead, the highest speedup ratio can be achieved in theory.

[0032] Figure 1 The workflow of the storage-computing integrated architecture simulator acceleration method based on dynamic domain decomposition is presented in detail. The whole process is divided into two main stages: compilation and simulation. The compilation stage is the starting point of the whole process, where a deep neural network (DNN) model is shown on the left as input data. The core task of this stage is to convert the original DNN model into a form suitable for efficient execution of the storage-computing integrated architecture through a series of optimization steps. First, the compiler performs operator fusion to reduce the computational complexity by merging multiple operators. This step helps to simplify the subsequent processing logic and improve the operation efficiency. Next, the weight mapping process efficiently distributes the weights in the DNN model to the storage-computing integrated device array to ensure the locality and efficiency of data access. The subsequent data flow scheduling focuses on optimizing the design data flow path between different computing units to minimize data transmission delay and power consumption, thereby providing the optimal data flow planning for subsequent simulations. Finally, the compiler generates a binary instruction program for simulation and creates an additional mapping file, which will guide the simulator to perform intelligent domain decomposition in the subsequent simulation process to ensure that the simulation task can effectively utilize multi-core CPU resources.

[0033] After entering the simulation phase, the focus of work shifted to the preparation of configuration files and the execution of simulation tasks. The left side of the lower half shows the configuration files required by the simulator. These files cover four key aspects: architecture resources, array parameters, device characteristics, and simulator configuration. See Table 1 for details. They provide the necessary settings for initializing the simulation environment. The simulator initializes and instantiates the simulation model based on these configuration files, and then intelligently divides the simulation model according to the mapping file, that is, domain decomposition. This process ensures that the dependencies between the parts are minimized, which facilitates parallel processing and improves simulation efficiency. Next, the simulator allocates computing threads to each decomposed part to ensure that each computing unit can make full use of available resources. After loading the binary instruction program generated by the compiler, the simulator officially starts the simulation task. During this process, a series of evaluation indicators are listed on the right, including latency, energy consumption, power consumption, and accuracy. These indicators are used to comprehensively measure the performance of the simulation process and help researchers analyze and optimize the model.

[0034] Table 1. Configuration file contents

[0035] This method introduces a new interaction mechanism between the compiler and the simulator - generating a mapping file through weight mapping to guide dynamic domain decomposition, and also significantly improves simulation efficiency and flexibility. Traditionally, the compiler is only responsible for generating binary instruction programs for the simulator to load, and the newly added mapping file enables the simulator to perform domain decomposition more accurately before simulation, further enhancing the simulator's ability to adapt to complex computing tasks. This enhanced interaction mechanism allows the simulator to more effectively utilize multi-core CPU resources, thereby improving the overall simulation speed and efficiency. This method not only achieves an improvement in simulation speed, but also provides a new idea for storage-computing integrated parallel simulation, which is particularly important when exploring the application scenarios of new storage-computing integrated architectures.

[0036] Before starting to introduce the dynamic domain decomposition algorithm and process of this application in detail, some basic concepts need to be explained in advance for better understanding. The simulation principle based on discrete event simulator is to model and analyze the dynamic behavior of the system by processing a series of discrete events at a specific time point. This method is suitable for systems where state changes are mainly triggered by discrete events, such as computer architecture, computer network and other fields. First, it is necessary to abstract and model the target system, define the components of the system, state variables and the interaction rules between these components. Each component can be an entity or resource, such as CPU, memory, on-chip network, etc.; state variables describe the status of these components, such as busy / idle, empty / full, etc. Next, define various events that may occur in the system, such as arrival events, service completion events, transfer events and fault events, and set an associated timestamp for each event to indicate the specific time when the event occurs. Create an event queue to store all future events to be processed and arrange them in chronological order. The time in the simulation process does not advance continuously, but jumps to the time point of the next event to occur. After processing all events at the current time point each time, the simulator will update the system state and generate subsequent events that may occur based on the new state, and then add these new events to the event queue. For each event taken out of the event queue, the corresponding processing logic is executed, including updating the system state, triggering new events, and recording data about performance indicators. Set the conditions for the end of the simulation, such as reaching the preset simulation time, processing a certain number of tasks, or meeting a certain state condition. When the termination condition is met, the simulation ends and the results are output for analysis. In this way, simulation based on discrete event simulators can efficiently simulate the dynamic behavior of complex systems and is widely used in many fields such as computer architecture and computer networks to help decision makers understand the behavior patterns of the system, predict future trends, and formulate effective strategies.

[0037] The event queue is the carrier of the simulation process based on the discrete event simulator. It can be considered that the events in the parts that share an event queue in the simulation process are strictly executed in chronological order. However, a single event queue can only perform serial simulation, and it is impossible to utilize the multi-core parallel characteristics in modern computers, resulting in low simulation efficiency. The basic idea of ​​domain decomposition is to divide the simulation object into multiple parts, configure an event queue for each part, and arrange these event queues on different threads for parallel simulation. However, this will bring new problems: the simulation speed of different event queues may be very different due to different loads, which will cause the simulation time of each queue to be inconsistent at the same time. Event interaction will occur between the parts. If the faster queue sends an event to the slower queue, the event needs to be cached first, and the slower queue needs to execute until the interaction time before the event is sent synchronously; if the slower queue sends an event to the faster queue, the future event will affect the past state on the faster queue, which may cause serious simulation errors, generally called causal errors. Therefore, the purpose of the dynamic domain decomposition algorithm designed in this application is to improve the efficiency of parallel simulation while avoiding causal errors.

[0038] Figure 2 The process of domain decomposition of the target integrated storage and computing architecture in high-throughput compilation mode is shown in detail. The characteristics of high-throughput compilation include the reasoning granularity of inter-layer pipeline, and different batches of data are executed between layers. Each dotted line in the figure represents a tile, and each geometric figure in each tile represents an integrated storage and computing core. In this example, the architecture has a total of 4 tiles, and each tile has 8 integrated storage and computing cores. The target network is mapped to the integrated storage and computing architecture through the compiler. For ease of understanding, the mapping results contained in the mapping file are represented here with a diagram. The different graphics represent the computing cores of different network layers: the circle is the first layer (convolutional layer), the square is the second layer (convolutional layer), the diamond is the third layer (fully connected layer), and the hexagon is the fourth layer (fully connected layer). Different letters in the same graphic represent the number of copies of the network weights of the same layer. For example, the first layer is copied twice in the figure, so there are two blocks A and B; the second layer is copied three times, so there are three blocks A, B, and C. The purpose of weight replication is to balance the execution time between different layers. By replicating multiple weights and executing them in parallel, the execution time of longer time-consuming layers can be reduced. The structure of the lower half of the figure corresponds to that of the upper half, except that the letters representing the number of replications are replaced by numbers representing the number of inputs. During the simulation, each input of each weight block can be approximately equivalent to the unit workload of the simulator. Assuming that the simulation host is limited to 10 threads, these computing cores need to be allocated to 10 threads and the sum of the workload of each thread needs to be minimized. The bottom of the figure shows an optimal allocation result, and the computing cores assigned to the same thread will then share a time queue for simulation.

[0039] Figure 3 The process of domain decomposition of the target storage-computing integrated architecture in low-latency compilation mode is shown in detail. The characteristic of low-latency compilation mode is that for the same network inference process, the data of the previous layer will be passed to the next layer when it accumulates to an appropriate amount, without waiting for the data of the previous layer to be processed completely. This mode is particularly suitable for application scenarios that require fast response. Although the target network and architecture are exactly the same as those in the high-throughput compilation example, so the weight mapping results are the same, but the data scheduling method is different. In low-latency mode, the result of the previous layer is the input of the next layer, and there is a dependency on the data. If something like Figure 2 As in the previous example, freely allocating computing cores will cause the order of instruction execution to be disordered. Therefore, the domain decomposition method adopted here is to allocate computing cores that map the same layer to the same thread.

[0040] As can be seen from the lower half of the figure, the four-layer network is assigned to four threads respectively. In order to ensure the execution order of instructions, the simulation process is as follows: Thread 1, which contains the first-layer weight calculation core, starts simulation from time 0. When time a is reached, the number of generated results reaches the threshold, and the event queue of thread 1 sends these data (the output of the first-layer network) to thread 2, which contains the second-layer weight calculation core, through inter-thread events. Thread 2 will start simulating from time 0 after receiving these data, and will synchronize with the data sent by thread 1 after its own simulation time reaches time a, and load these data into its own calculation core. This ensures that thread 2 receives data at the correct time. After that, thread 2 will pause at time a until thread 1 sends data next time and then simulates again, and synchronizes at the time of receiving new data.

[0041] The interaction process between thread 2 and thread 3 is similar to that between thread 1 and thread 2. Thread 2, which contains the second-layer weight calculation core, starts simulation at time 0. When it reaches time b, the number of generated results reaches the threshold, and the event queue of thread 2 sends these data (part of the output of the second-layer network) to thread 3, which contains the third-layer weight calculation core, through inter-thread events. Thread 3 will start simulating from time 0 after receiving these data, and will synchronize with the data sent by thread 2 after its own simulation time reaches time b, and load these data into its own calculation core. The subsequent interactions between threads follow the same principle. Although the synchronization operation will generate additional overhead for the simulator and consume some of the advantages brought by parallel simulation, in low-latency mode, this method can strictly guarantee the execution order of instructions in a parallel environment, thereby ensuring the stability and accuracy of the entire system.

[0042] The method proposed in the present invention solves the above-mentioned problem by utilizing the mapping file provided by the compiler supporting the simulation architecture and combining it with a specially designed algorithm to implement dynamic domain decomposition on the simulation model. This method can adjust and optimize the division of domains in real time according to the specific needs of the simulation architecture when performing different tasks, thereby maximizing the parallel potential of the system and significantly improving the work efficiency and simulation speed of the storage-computing integrated architecture simulator. By introducing dynamic domain decomposition technology, the present invention overcomes the bottleneck in the storage-computing integrated architecture simulation, realizes a more efficient parallel simulation process, and thus improves the overall performance of the simulator.

[0043] An embodiment of the present invention also provides a storage-computing integrated architecture simulator acceleration device based on dynamic domain decomposition, including one or more processors for implementing the above-mentioned storage-computing integrated architecture simulator acceleration method based on dynamic domain decomposition.

[0044] An embodiment of the present invention also provides a computer-readable storage medium on which a program is stored. When the program is executed by a processor, it is used to implement the above-mentioned storage and computing integrated architecture simulator acceleration method based on dynamic domain decomposition.

[0045] An embodiment of the present invention also provides a computer program product, including a computer program, which, when executed by a processor, implements the above-mentioned storage-computing integrated architecture simulator acceleration method based on dynamic domain decomposition.

[0046] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0047] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0048] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0049] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0050] The above embodiments are only used to illustrate the design ideas and features of the present invention, and their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. The protection scope of the present invention is not limited to the above embodiments. Therefore, any equivalent changes or modifications made based on the principles and design ideas disclosed by the present invention are within the protection scope of the present invention.

Claims

1. A storage-computing integrated architecture simulator acceleration method based on dynamic domain decomposition, characterized in that: include: Based on the compiler, the target network is converted into a form suitable for execution of the storage-computing integrated architecture, that is, a binary instruction program for simulation, and an additional mapping file is created; the mapping file includes weight replication information, weight and storage-computing integrated device array mapping information, and the number of inputs corresponding to each weight block; The configuration file is obtained, the simulator initializes and instantiates the simulation model based on the configuration file, and then domain decomposes the simulation model based on the mapping file; the simulator allocates a computing thread to each decomposed part, loads the binary instruction program, and the simulator starts the simulation task.

2. The method for accelerating a storage-computing integrated architecture simulator based on dynamic domain decomposition according to claim 1, characterized in that: Also includes: The performance of the simulation process is measured based on evaluation metrics, including latency, energy consumption, power consumption, and accuracy.

3. The method for accelerating a storage-computing integrated architecture simulator based on dynamic domain decomposition according to claim 1, characterized in that: The target network includes a deep neural network model.

4. The method for accelerating a storage-computing integrated architecture simulator based on dynamic domain decomposition according to claim 1, characterized in that: The compiler converts the target network into a form suitable for execution in the storage-computing architecture, that is, a binary instruction program for simulation, and creates an additional mapping file, including: First, the compiler performs operator fusion; then the weight mapping process distributes the weights of the target network to the storage and computing integrated device array; the subsequent data flow scheduling focuses on optimizing the design data flow path between different computing units; finally, the compiler generates a binary instruction program for simulation and creates an additional mapping file.

5. The method for accelerating a storage-computing integrated architecture simulator based on dynamic domain decomposition according to claim 1, characterized in that: The simulator allocates computing threads to each of the decomposed parts, including: Weight replication is used to balance the execution time between different network layers. When allocating computing threads, the number of inputs corresponding to each weight block is combined to keep the workload of each thread balanced. Alternatively, computing cores that map the same network layer are allocated to the same thread. Among them, each input of each weight block is equivalent to the unit workload of the simulator.

6. The method for accelerating a storage-computing integrated architecture simulator based on dynamic domain decomposition according to claim 5, characterized in that: The computing cores assigned to the same thread share a time queue for simulation.

7. The method for accelerating a storage-computation integrated architecture simulator based on dynamic domain decomposition according to claim 5, characterized in that: The computing cores mapped with the same network layer are assigned to the same thread. Specifically, n network layers are assigned to n threads respectively. To ensure the execution order of instructions, the simulation process is as follows: Thread 1, which contains the first-layer weight calculation core, starts simulation from time 0; when reaching time a, the number of generated results reaches the threshold, and the event queue of thread 1 sends these data to thread 2, which contains the second-layer weight calculation core, through inter-thread events; thread 2 will start simulation from time 0 after receiving these data, and will not synchronize with the data sent by thread 1 until its own simulation time reaches time a, and load these data into its own calculation core; this ensures that thread 2 receives data at the correct time; after that, thread 2 will pause at time a until thread 1 sends data next time and then simulates again, and synchronizes at the time of receiving new data; The interaction process between thread n-1 and thread n is the same as the interaction process between thread 1 and thread 2.

8. A storage-computing integrated architecture simulator acceleration device based on dynamic domain decomposition, characterized in that: It includes one or more processors for implementing a storage-computation integrated architecture simulator acceleration method based on dynamic domain decomposition as described in any one of claims 1-7.

9. A computer-readable storage medium having a program stored thereon, characterized in that: When the program is executed by a processor, it is used to implement a storage-computing integrated architecture simulator acceleration method based on dynamic domain decomposition as described in any one of claims 1-7.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, it implements a storage-computing integrated architecture simulator acceleration method based on dynamic domain decomposition as described in any one of claims 1-7.

Images