Method, apparatus, device, and storage medium for preventing bus deadlock on a chip system
By providing configuration registers for each address space on the bus of the chip system to describe its properties, the bus deadlock problem caused by hollow addresses is solved, and the stable operation of the system is achieved.
Patent Information
- Application Number
- CN202510293466.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-12
- Publication Date
- 2025-06-24
- Estimated Expiration
- 2045-03-12
AI Technical Summary
Bus deadlock problems caused by hollow addresses in chip systems, especially when the processor performs speculative execution or access, may cause system deadlock.
By providing at least one set of configuration registers for each address space on the bus, address space attributes are described, including cacheable attribute bit domains, non-eased attribute bit domains, device attribute bit domains, and address space start address bit domains. Determine the attributes of the current address space based on these attributes, and decide whether to allow access to the current address space based on attributes and address requests.
It effectively avoids the bus deadlock problem caused by hollow addresses. By dynamically adjusting the properties of the address space, it ensures that the system can run normally when the processor performs speculative execution or access.
Smart Images
Figure CN119781998B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of chip systems. Specifically, it relates to a method, device, equipment, and storage medium for preventing bus deadlocks on a chip system. Background Technique
[0002] In modern chip systems, a large number of peripherals are often integrated. The functional scenarios of these peripherals are diverse. For example, Figure 1 As shown is a typical chip system block diagram. Here, the peripherals are all connected to the bus. For example, Figure 1 DEVICE below represents all external devices. These external devices generally occupy a part of the bus space. MEM represents the system storage module. The space occupied by DEVICE can be the Device space. In addition, the two paths of space coming out of the CORE kernel can be roughly divided into cacheable and non-cacheable spaces.
[0003] Now, in the processor, both the instruction fetch unit and the memory access unit have speculative access or speculative execution mechanisms to ensure faster and more efficient execution of the processor. Then, for these speculative address accesses, there is a probability of failure. When the predicted address appears in a hole in the address space, unknown problems such as system deadlocks will occur. For example, if the prefetch address space exactly belongs to an unknown hole address, then the predicted address will not receive any response, which will lead to system deadlocks.
[0004] When there is a fixed hole address in the chip system, this hole address may be due to a space that was not considered during bus design, resulting in a blank in the bus space. At this time, if speculative execution or speculative access occurs and the hole address is accessed, it will lead to system deadlocks. This requires a mechanism to adjust the response when the hole address space is speculatively executed or accessed to prevent system deadlocks.
[0005] In the chip system, for some devices, they may need to sleep or power off in certain application scenarios. Then, the space where the device is located will be called a hole address at a specific time and can be normally accessed at a specific time. When a speculative access is performed and the device happens to be in a sleeping or powered-off state, it will lead to system deadlocks. And if the space attribute is changed to make the space unable to be speculatively executed or accessed, then when the device is in a normal working state, normal access cannot be performed. This requires dynamically adjusting the access attribute of the space where the device is located.
[0006] In the chip system, when the system is just starting up, perhaps only a very small part of the device space is in an accessible state, and other spaces are black hole spaces. Then, when accessing these small parts of space, many descriptions of space attributes may need to be set for these accessible spaces, consuming a lot of resources. Summary of the Invention
[0007] An embodiment of the present application provides a method, apparatus, device, and storage medium for preventing bus deadlock on a chip system.
[0008] In the first aspect of the embodiments of the present application, a method for preventing bus deadlock on a chip system is provided, including:
[0009] For each address space on the bus, at least one set of configuration registers for describing the attributes of the address space is provided, where each set of configuration registers includes a first register and a second register;
[0010] In the first register, configure the cacheable attribute bit field, non-cacheable attribute bit field, device attribute bit field, and the starting address bit field of the address space. In the second register, configure the bit field used to calculate the size of the address space to be described;
[0011] Determine the attribute of the current address space according to the values of the cacheable attribute bit field, non-cacheable attribute bit field, and device attribute bit field;
[0012] Determine whether to allow access to the current address space according to the attribute of the current address space and the address request of the current address space.
[0013] In an optional embodiment of the present application, determining the attribute of the current address space according to the values of the cacheable attribute bit field, non-cacheable attribute bit field, and device attribute bit field includes:
[0014] When the value of the cacheable attribute bit field is 1 and the values of the non-cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the cacheable attribute;
[0015] When the value of the non-cacheable attribute bit field is 1 and the values of the cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the non-cacheable attribute;
[0016] When the value of the device attribute bit field is 1 and the values of the non-cacheable attribute bit field and the cacheable attribute bit field are both 0, the attribute of the current address space is the device attribute;
[0017] When the values of the cacheable attribute bit field, non-cacheable attribute bit field, and device attribute bit field are all 0, the attribute of the current address space is the general attribute.
[0018] In an optional embodiment of the present application, determining whether to allow access to the current address space according to the attribute of the current address space and the address request of the current address space includes:
[0019] When the attribute of the current address space is a device attribute and the address request is a predictive address request, access to the current address space is not allowed.
[0020] When the attribute of the current address space is any one of a non-cacheable attribute, a cacheable attribute, and a normal attribute and the address request is a predictive address request, access to the current address space is allowed.
[0021] In an optional embodiment of the present application, the method further includes:
[0022] For the case where multiple sets of configuration registers describe the attributes of the same address space, determine the attribute of the current address space according to the priority of the address space attributes, where the sorting of the address space attributes from high to low priority is: cacheable attribute, non-cacheable attribute, device attribute, and normal attribute.
[0023] In an optional embodiment of the present application, the method further includes:
[0024] For each fixed hole address space on the bus, describe the attribute of the current fixed hole address space as a device attribute through a set of configuration registers.
[0025] In an optional embodiment of the present application, the method further includes:
[0026] For each variable hole address space on the bus, during the period when the variable hole address space is a hole address, describe the attribute of the current variable hole address space as a device attribute through a set of configuration registers, and during the period when the variable hole address space is a non-hole address, describe the attribute of the current variable hole address space as any one of a non-cacheable attribute, a cacheable attribute, and a normal attribute by modifying the configuration of the current set of configuration registers.
[0027] In an optional embodiment of the present application, the method further includes:
[0028] For each mixed address space on the bus, describe the attribute of the current mixed address space as a device attribute through a set of configuration registers, and describe the attribute of the hole address space in the current mixed address space as any one of a non-cacheable attribute, a cacheable attribute, and a normal attribute through another set of configuration registers, where the mixed address space includes a hole address space and a non-hole address space and the proportion of the non-hole address space in the mixed address space is less than a preset value.
[0029] The second aspect of the embodiments of the present application provides a device for preventing bus deadlock on a chip system, including:
[0030] A providing module is used to provide, for each address space on the bus, at least one set of configuration registers for describing the attributes of the address space, where each set of configuration registers includes a first register and a second register;
[0031] A configuration module is used to configure, in the first register, a cacheable attribute bit field, a non-cacheable attribute bit field, a device attribute bit field, and an address space start address bit field, and to configure, in the second register, a bit field for calculating the size of the address space to be described;
[0032] A first determination module is used to determine the attribute of the current address space according to the values of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field;
[0033] A second determination module is used to determine whether to allow access to the current address space according to the attribute of the current address space and the address request of the current address space.
[0034] In a third aspect of the embodiments of the present application, a computer device is provided, including: a memory and a processor, where the memory stores a computer program, and when the processor executes the computer program, the steps of the method for preventing bus deadlock on a chip system as described in any one of the above are implemented.
[0035] In a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored, and characterized in that when the computer program is executed by a processor, the steps of the method for preventing bus deadlock on a chip system as described in any one of the above are implemented.
[0036] The above technical solutions provided by the embodiments of the present application compared with the prior art have at least some or all of the following advantages:
[0037] For the method for preventing bus deadlock on a chip system described in the embodiments of the present application, for each address space on the bus, at least one set of configuration registers for describing the attributes of the address space is provided, where each set of configuration registers includes a first register and a second register; in the first register, a cacheable attribute bit field, a non-cacheable attribute bit field, a device attribute bit field, and an address space start address bit field are configured, and in the second register, a bit field for calculating the size of the address space to be described is configured; the attribute of the current address space is determined according to the values of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field; whether to allow access to the current address space is determined according to the attribute of the current address space and the address request of the current address space, and by using the configuration registers to perform a combined description of at least one attribute on the addresses where address holes may occur, the problem of bus deadlock caused by address holes is avoided. Description of the Drawings
[0038] The accompanying drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation of the present application. In the drawings:
[0039] Figure 1 Schematic diagram of chip system integration provided for the prior art;
[0040] Figure 2 Flowchart of a method for preventing bus deadlock on a chip system provided by an embodiment of the present application;
[0041] Figure 3 Schematic diagram of the first register bit field provided by an embodiment of the present application;
[0042] Figure 4 Schematic diagram of a fixed hole address deadlock scenario provided by an embodiment of the present application;
[0043] Figure 5 Schematic diagram of a variable hole address deadlock scenario provided by an embodiment of the present application;
[0044] Figure 6 Schematic diagram of a deadlock scenario where a small number of addresses among a large number of hole addresses can be normally accessed provided by an embodiment of the present application;
[0045] Figure 7 Schematic diagram of the device structure for preventing bus deadlock on a chip system provided by an embodiment of the present application;
[0046] Figure 8 Schematic diagram of the computer device structure provided by an embodiment of the present application. Detailed implementation manners
[0047] In the process of implementing the present application, the inventors found that there is a problem of bus deadlock caused by hole addresses on the current chip system.
[0048] In view of the above problems, embodiments of the present application provide a method, device, equipment, and storage medium for preventing bus deadlock on a chip system to avoid the problem of bus deadlock caused by hole addresses on the chip system.
[0049] The solutions in the embodiments of the present application can be implemented in various computer languages. For example, object-oriented programming languages such as Java and interpreted scripting languages such as JavaScript.
[0050] In order to make the technical solutions and advantages in the embodiments of the present application clearer and more understandable, the exemplary embodiments of the present application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.
[0051] Please refer to Figure 2 , the method for preventing bus deadlock on a chip system provided by the embodiments of the present application includes the following S100 to S400:
[0052] S100. For each address space on the bus, provide at least one set of configuration registers for describing the attributes of the address space, where each set of configuration registers includes a first register and a second register;
[0053] S200. In the first register, configure the cacheable attribute bit field, non-cacheable attribute bit field, device attribute bit field, and address space start address bit field. In the second register, configure the bit field for calculating the size of the address space to be described;
[0054] S300. Determine the attributes of the current address space according to the values of the cacheable attribute bit field, non-cacheable attribute bit field, and device attribute bit field;
[0055] S400. Determine whether to allow access to the current address space according to the attributes of the current address space and the address request of the current address space.
[0056] In an optional embodiment of the present application, the device attribute space is the space provided for device peripherals. It is only allowed when it is confirmed that the instruction really needs to access the address of this attribute space. When a predictive address request access occurs, an error is reported to the processor. The cacheable attribute space is the attribute provided for the cache memory. In order to accelerate the access of data explicitly, this space can be accessed by predictive address requests. The non-cacheable attribute space can also be accessed by predictive address requests.
[0057] In an optional embodiment of the present application, in S100, refer to Figure 3 , taking a 32-bit address as an example, the bit fields of the first register include 0, 1, 2, and 31:3. Table 1 and Table 2 below are the description tables of the first register and the second register respectively.
[0058] Table 1
[0059]
[0060] In Table 1, a first register can only be one of the above three attributes, that is, the above three attributes must be mutually exclusive. If all of the above three attributes are 0, it is called a general attribute, which is a hidden attribute and can be accessed by a predictive address request. The occupation of the lower 3 bits does not affect the description of the address space because the minimum described address space is 4k, so it does not affect the setting of BASE_ADDR.
[0061] Table 2
[0062]
[0063] In an optional embodiment of the present application, when it is necessary to configure the interval [0x80000000, 0x90000000) as the device attribute, the following two register groups of the configuration register entry0 can be configured:
[0064] The first register entry_base_address_cfg0 = 0x80000004;
[0065] The second register entry_range_mask_cfg0 = 0xf0000000.
[0066] In an optional embodiment of the present application, in S300, determining the attribute of the current address space according to the values of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field includes:
[0067] When the value of the cacheable attribute bit field is 1 and the values of the non-cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the cacheable attribute;
[0068] When the value of the non-cacheable attribute bit field is 1 and the values of the cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the non-cacheable attribute;
[0069] When the value of the device attribute bit field is 1 and the values of the non-cacheable attribute bit field and the cacheable attribute bit field are both 0, the attribute of the current address space is the device attribute;
[0070] When the values of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field are all 0, the attribute of the current address space is the general attribute.
[0071] In an optional embodiment of the present application, in S400, determining whether to allow access to the current address space according to the attribute of the current address space and the address request of the current address space includes:
[0072] Access to the current address space is not allowed when the attribute of the current address space is a device attribute and the address request is a predictive address request.
[0073] Access to the current address space is allowed when the attribute of the current address space is any one of a non-cacheable attribute, a cacheable attribute, and a normal attribute and the address request is a predictive address request.
[0074] In an optional embodiment of the present application, the method further includes:
[0075] For the case where multiple sets of configuration registers describe the attributes of the same address space, determine the attribute of the current address space according to the priority of the address space attributes, where the sorting of the address space attributes from high to low priority is: cacheable attribute, non-cacheable attribute, device attribute, and normal attribute.
[0076] In an optional embodiment of the present application, there can be many sets of configuration register entries. The number of sets of configuration register entries required can be selected in the hardware according to specific application requirements. Each set of configuration register entries can describe the attributes of the same or different addresses. That is, multiple sets of configuration register entries can be used to describe the attributes of the same address. In the case where there are multiple attributes for the same address, different priorities are assigned to the address attributes, and the attribute with the highest priority is used as the attribute of the address.
[0077] In an optional embodiment of the present application, the method further includes:
[0078] For each fixed hole address space on the bus, describe the attribute of the current fixed hole address space as a device attribute through a set of configuration registers.
[0079] As Figure 4 shown, assume that there is now an address space [0x80000000, 0x90000000), and this address space is a hole address space. The attribute of this address space is defaulted to a non-cacheable attribute. Therefore, when the processor initiates a predictive address request that falls into the region space [0x80000000, 0x90000000), a deadlock will occur. This region space can be described through a set of configuration register entries. Assume that a set of configuration register entry0 describes the space as a non-cacheable attribute, then the attribute of the space described by this configuration register entry0 can be changed to a device attribute space. The configuration is as follows:
[0080] entry_base_address_cfg0 = 0x80000004;
[0081] entry_range_mask_cfg0 = 0xf0000000;
[0082] Therefore, when the processor initiates a predictive address request, an error will be reported to prevent the deadlock problem caused by the hole address.
[0083] As Figure 5 shown, assume there is a bus system now. A part of the address space [0x80000000, 0x800f000) may be a hole address at a certain time and can be normally accessed by a predictive address request at a certain time. The rest is all hole address space. It can be seen that a very small part of the address space can be predictively and normally accessed in a specific place, and a specific scenario may be a hole address. When the address space [0x80000000, 0x800f000) becomes a hole address at a certain moment, it only needs to be configured with the following process, and the configuration is as follows:
[0084] entry_base_address_cfg0 = 0x80000004;
[0085] entry_range_mask_cfg0 = 0xfffff000;
[0086] At this time, when a predictive address request initiated by the processor falls within this area, an error will be reported to prevent system deadlock. However, if the predictive address request initiated by the processor falls within [0x80000000, 0x800f000), and exactly in the current scenario, the space [0x80000000, 0x800f000) can be normally accessed. At this time, if it is still regarded as the device attribute space, it will cause the situation that the interval [0x80000000, 0x800f000) cannot be accessed. Therefore, entry0 can be continued to be configured to describe the area [0x80000000, 0x800f000) again, and use entry0 to set [0x80000000, 0x800f000) as the cacheable attribute space;
[0087] entry_base_address_cfg0 = 0x80000001;
[0088] entry_range_mask_cfg0 = 0xfffff000;
[0089] In this way, the space from 0x80000000 to 0x800f000 changes from the device attribute to the cacheable attribute, so it can be normally accessed at this time.
[0090] As Figure 6As shown, assume there is a bus system now. Most of the address space is empty, and only a small part of the space [0x80000000, 0x800f000) can be accessed. In this scenario, the entire space can be described as a device attribute space. The entire space can be configured as device attributes using entry0. The configuration is as follows:
[0091] entry_base_address_cfg0 = 0x00000004;
[0092] entry_range_mask_cfg0 = 0x00000000;
[0093] At this time, when the processor initiates a predictive address request that falls within this region, an error will occur, thus preventing system deadlocks. However, if the predictive address request initiated by the processor falls within [0x80000000, 0x800f000), and the space [0x80000000, 0x800f000) can be normally accessed, if it is still regarded as a device attribute space at this time, it will result in the situation where the interval [0x80000000, 0x800f000) cannot be accessed. Therefore, another entry1 can be used to describe the region [0x80000000, 0x800f000) again. Use entry1 to set [0x80000000, 0x800f000) as a cacheable attribute space. The configuration is as follows:
[0094] entry_base_address_cfg1 = 0x80000001;
[0095] entry_range_mask_cfg1 = 0xfffff000;
[0096] In this way, the space from 0x80000000 to 0x800f000 has two attributes, cacheable attribute and device attribute. Due to the existence of attribute priorities, the device attribute will be overwritten, so it can be normally accessed at this time.
[0097] In an optional embodiment of the present application, the method further includes:
[0098] For each variable empty address space on the bus, during the period when the variable empty address space is an empty address, the attributes of the current variable empty address space are described as device attributes through a group of configuration registers. During the period when the variable empty address space is a non-empty address, the attributes of the current variable empty address space are described as any one of non-cacheable attribute, cacheable attribute, and ordinary attribute by modifying the configuration of the current group of configuration registers.
[0099] In an optional embodiment of the present application, the method further includes:
[0100] For each hybrid address space on the bus, the attributes of the current hybrid address space are described as device attributes through a set of configuration registers, and the attributes of the hole address space in the current hybrid address space are described as any one of non-cacheable attributes, cacheable attributes, and ordinary attributes, where the hybrid address space includes a hole address space and a non-hole address space, and the proportion of the non-hole address space in the hybrid address space is less than a preset value.
[0101] The method for preventing bus deadlocks on the chip system of the present application can flexibly change the attributes of the current address space through multiple address attribute descriptions, thereby solving the problems of deadlocks caused by accessing hole addresses or inaccessible addresses caused by dynamically changing attributes of the accessed addresses when the processor in the chip system performs predictive address access.
[0102] It should be understood that although the steps in the flowchart are sequentially shown according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, the execution of these steps has no strict order limit, and these steps can be executed in other orders. Moreover, at least a part of the steps in the figure may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.
[0103] Please refer to Figure 7 , an embodiment of the present application provides an apparatus 700 for preventing bus deadlocks on a chip system, including:
[0104] A providing module 710, configured to provide at least one set of configuration registers for describing the attributes of the address space for each address space on the bus, where each set of configuration registers includes a first register and a second register;
[0105] A configuration module 720, configured to configure a cacheable attribute bit field, a non-cacheable attribute bit field, a device attribute bit field, and an address space start address bit field in the first register, and configure a bit field for calculating the size of the address space to be described in the second register;
[0106] A first determining module 730, configured to determine the attributes of the current address space according to the values of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field;
[0107] A second determination module 740, configured to determine whether to allow access to the current address space according to the attributes of the current address space and the address request of the current address space.
[0108] The device for preventing bus deadlock on the chip system of the present application flexibly changes the attributes of the current address space through multiple address attribute descriptions, so as to solve the problems that when a processor in the chip system performs predictive address access, accessing a hole address causes deadlock, or the accessed address space can be accessed sometimes and becomes a hole address sometimes, resulting in the inability to execute the access request normally.
[0109] For the specific limitations of the above device 700, reference can be made to the limitations of the method for preventing bus deadlock on the chip system in the above text, which will not be elaborated here. Each module in the above device 700 can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or independent of the processor, or stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.
[0110] In one embodiment, a computer device is provided, and the internal structure diagram of the computer device can be as Figure 8 shown. The computer device includes a processor, a memory, a network interface, and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a method for preventing bus deadlock on a chip system as described above. It includes: including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it implements any step in the method for preventing bus deadlock on the chip system as described above.
[0111] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, it can implement any step in the method for preventing bus deadlock on a chip system as described above.
[0112] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.
[0113] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or blocks.
[0114] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in Figure 1 one or more of the flows Figure 1 or blocks.
[0115] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or blocks.
[0116] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications that fall within the scope of the present application.
[0117] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to cover these changes and modifications.
Claims
1. A method for preventing bus deadlock on a chip system, characterized in that: include: For each address space on the bus, at least one group of configuration registers for describing attributes of the address space is provided, wherein each group of configuration registers includes a first register and a second register; In the first register, configure the cacheable attribute bit field, the non-cacheable attribute bit field, the device attribute bit field and the address space start address bit field, and in the second register, configure the bit field used to calculate the size of the address space to be described; Determine the attributes of the current address space according to the values of the cacheable attribute bit field, the non-cacheable attribute bit field and the device attribute bit field; Determine whether to allow access to the current address space according to the attributes of the current address space and the address request of the current address space; The attributes of the current address space are determined based on the values of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field, including: When the value of the cacheable attribute bit field is 1, and the values of the non-cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the cacheable attribute; When the value of the non-cacheable attribute bit field is 1, and the values of the cacheable attribute bit field and the device attribute bit field are both 0, the attribute of the current address space is the non-cacheable attribute; When the value of the device attribute bit field is 1, and the values of the non-cacheable attribute bit field and the cacheable attribute bit field are both 0, the attribute of the current address space is the device attribute; When the values of the cacheable attribute bit field, the non-cacheable attribute bit field, and the device attribute bit field are all 0, the attributes of the current address space are normal attributes; Determine whether to allow access to the current address space based on the attributes of the current address space and the address request of the current address space, including: In the case where the attribute of the current address space is a device attribute and the address request is a predictive address request, access to the current address space is not allowed; In a case where the attribute of the current address space is any one of a non-cacheable attribute, a cacheable attribute, and a normal attribute and the address request is a predictive address request, access to the current address space is permitted.
2. The method according to claim 1, characterized in that The method further comprises: In the case where multiple groups of configuration registers describe the attributes of the same address space, the attributes of the current address space are determined according to the priority of the address space attributes, where the address space attributes are sorted from high to low priority as follows: cacheable attributes, non-cacheable attributes, device attributes, and common attributes.
3. The method according to claim 1, characterized in that The method further comprises: For each fixed hole address space on the bus, the attributes of the current fixed hole address space are described as device attributes through a group of configuration registers.
4. The method according to claim 1, characterized in that: The method further comprises: For each variable hole address space on the bus, during the period when the variable hole address space is a hole address, the attributes of the current variable hole address space are described as device attributes through a group of configuration registers. During the period when the variable hole address space is a non-hole address, the attributes of the current variable hole address space are described as any one of non-cacheable attributes, cacheable attributes and ordinary attributes by modifying the configuration of the current group of configuration registers.
5. The method according to claim 1, characterized in that The method further comprises: For each hybrid address space on the bus, the attributes of the current hybrid address space are described as device attributes through a set of configuration registers, and the attributes of the hole address space in the current hybrid address space are described as any one of uncacheable attributes, cacheable attributes and ordinary attributes through another set of configuration registers, wherein the hybrid address space includes hole address space and non-hole address space and the proportion of non-hole address space in the hybrid address space is less than a preset value.
6. A computer device comprising: It comprises a memory and a processor, wherein the memory stores a computer program, and is characterized in that when the processor executes the computer program, the steps of the method for preventing bus deadlock on a chip system as described in any one of claims 1 to 5 are implemented.
7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for preventing bus deadlock on a chip system as described in any one of claims 1 to 5 are implemented.
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