A command generation method, device and medium for NAND controller testing

Abstract

The present invention relates to the field of NAND testing, and specifically to a command generation method, device and medium for NAND controller testing. The present invention divides the random command generation process into two stages: the pre-generation stage first determines the command type and quantity, and applies for memory space according to the total number of commands, and then writes the main difference information between the current command and other commands into the memory unit space. The immediate generation stage first generates a framework test command that contains the common parts of each command and other commands, reads the main difference information stored in the pre-generation stage and generates secondary difference information, fills the main difference information and secondary difference information into the framework test command, generates a complete test command and transmits it to the NAND controller. The present invention can improve the command generation efficiency of the test software by balancing the memory and CPU resources of the test system to meet the stress testing requirements of the NAND controller.

Description

Technical Field

[0001] The present invention relates to the field of NAND testing, and in particular to a command generation method, device and medium for NAND controller testing. Background Art

[0002] In traditional random testing methods, random commands are typically generated just before they are sent. Because each configuration element in the command must be randomized individually, the interval between command transmissions is significantly increased, leading to the risk of insufficient test pressure. Furthermore, if commands are generated randomly from the outset to ensure sufficient test pressure, a large amount of memory is required to store these commands, placing high demands on the test system's hardware environment. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a command generation method, device and medium for NAND controller testing. By balancing the memory and CPU resources of the test system, the command generation efficiency of the test software can be improved to meet the stress testing requirements of the NAND controller.

[0004] In order to solve the technical problem, the technical solution adopted by the present invention is: a command generation method for NAND controller testing, which divides the random command generation process into two stages: a pre-generation stage and an immediate generation stage;

[0005] The pre-generation phase first determines the command type and quantity based on the configuration information sent by the tester, and allocates a space in the memory according to the total number of commands. Then, the order in which each command should be sent is determined. According to the order in which the commands are sent, the main differences between the current command and other commands are written into the allocated memory unit space.

[0006] The immediate generation phase first generates a framework test command in accordance with the test command format required for NAND controller testing. The framework test command contains the common parts of each command with other commands and can be used repeatedly. Then the test program reads the primary difference information stored in the pre-generation phase and generates secondary difference information at the same time. The primary difference information and secondary difference information are filled into the framework test command to generate a complete test command and transmit it to the NAND controller. Test commands are generated sequentially in this way until the predetermined number of commands is reached. There is an adjustable proportional relationship between the primary difference information and the secondary difference information.

[0007] Furthermore, the ratio of the primary difference information to the secondary difference information is adjusted according to the memory size and CPU computing power.

[0008] Furthermore, for a test machine whose memory is greater than the set requirement but whose CPPU computing power is less than the set requirement, all difference information is written into the memory as primary difference information in the pre-generation stage, and there is no need to generate secondary difference information in the immediate generation stage.

[0009] Furthermore, for a test set where the memory is less than the set requirement but the CPU computing power is greater than the set requirement, the amount of secondary difference information is greater than the amount of primary difference information.

[0010] Furthermore, the main difference information includes command type, whether the scrambling function is enabled, whether the additional data function is enabled, whether the data check code function is enabled, and the data unit length.

[0011] Furthermore, the secondary difference information includes the specific storage address of the user data in the DDR, the specific storage address of the additional data in the DDR, the specific storage address of the data in the NAND, the command ID number, and the scrambling sequence to be used.

[0012] Furthermore, the configuration information includes the test command type, the number of each type of test command, and the NAND address operated by the test command.

[0013] Furthermore, the sending order of each command is randomly determined and the secondary difference information is generated through a random function.

[0014] The present invention also discloses a command generation device for NAND controller testing, comprising a processor and a memory storing program instructions, wherein the processor is configured to execute the command generation method for NAND controller testing as described above when running the program instructions.

[0015] A storage medium stores program instructions, which, when run, execute the command generation method for NAND controller testing as described above.

[0016] The present invention provides the following beneficial effects: The method provided by the present invention is simple to operate and adaptable to a variety of hardware environments with varying CPU power and memory space combinations. It effectively reduces the interval between command transmissions while simultaneously ensuring test pressure and randomness, meeting the requirements for testing the stable operation of NAND controllers under a large number of random command scenarios. Compared to traditional methods, while maintaining the same testing capabilities, this method offers greater flexibility and environmental adaptability, fully leveraging the advantages and characteristics of different hardware platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 Schematic diagram of this method;

[0018] Figure 2 Schematic diagram of the device described in Example 2. DETAILED DESCRIPTION

[0019] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0020] Example 1

[0021] This embodiment discloses a command generation method for NAND controller testing, such as Figure 1 As shown, this method divides command generation into two stages: pre-generation and immediate generation.

[0022] Pre-generation phase: The main task of the test program is to randomly sort the commands sent according to the configuration information and write the main difference information of each command into the memory

[0023] The main difference information includes: command type, whether the scrambling function is enabled, whether the additional data (Meta data) function is enabled, whether the data check code function is enabled, data unit length and other basic control information

[0024] Instant generation phase: The main task of the test program is to read the primary difference information in the memory, combine it with the secondary difference information and framework commands generated in real time into a test command, and issue it.

[0025] Secondary difference information includes: the specific storage address of user data in DDR, the specific storage address of additional data (Meta data) in DDR, the specific storage address of data in NAND, command ID number, scrambling sequence to be used, and other detailed operation information required by the current command.

[0026] Specifically, this method is completed by the following steps:

[0027] 1. The test program obtains basic information configured by the tester through the interactive interface, including test command type, quantity of each type, NAND address operated by the test command, and other control information;

[0028] 2. The test program enters the test command pre-generation phase. Based on the total number of commands M, a sufficiently large memory space is requested and divided into M units of equal size.

[0029] 3. Call the random function to randomly sort the commands, determine the sending order of each command, and write the main differences between the current command and other commands into the divided memory unit space in sequence according to the sending order;

[0030] 4. The test program enters the command generation phase and generates a framework test command according to the command format required for NAND controller testing. The framework test command contains the common parts of each command with other commands and can be used repeatedly.

[0031] 5. The test program reads the main difference information prepared in the memory and fills it into the framework test command;

[0032] 6. The test program uses a random function to instantly generate minor difference information, fills it into the framework test command, and then combines it into a complete test command and transmits it to the NAND controller;

[0033] 7. Repeat steps 5 and 6 until the number of test commands sent reaches the predetermined number, and the process ends.

[0034] In the above steps, the ratio of primary difference information to secondary difference information can be adjusted according to the memory size and CPU computing power to adapt to a variety of hardware environments including different CPU computing power and memory space sizes. For example, for a test machine whose memory is greater than the set requirements but whose CPU computing power is less than the set requirements, all difference information is written into the memory as primary difference information in the pre-generation stage, and there is no need to generate secondary difference information in the immediate generation stage, which minimizes the time interval for the test program to issue commands and ensures the test pressure. For a test set whose memory is less than the set requirements but whose CPU computing power is greater than the set requirements, the amount of secondary difference information is greater than the amount of primary difference information, and more difference information is generated in the immediate generation stage to reduce the memory usage in the pre-generation stage.

[0035] Example 2

[0036] The embodiment of the present disclosure provides a command generating device 300 for NAND controller testing, such as Figure 2 As shown, the device includes a processor 304 and a memory 301. Optionally, the device may also include a communication interface 302 and a bus 303. The processor 304, communication interface 302, and memory 301 may communicate with each other via bus 303. Communication interface 302 may be used for information transmission. Processor 304 may invoke logic instructions in memory 301 to execute the command generation method for NAND controller testing described in the above embodiment.

[0037] In addition, the logic instructions in the memory 301 can be implemented in the form of software functional units and can be stored in a computer-readable storage medium when sold or used as an independent product.

[0038] Memory 301, as a computer-readable storage medium, can be used to store software programs and computer-executable programs, such as the program instructions / modules corresponding to the methods in the embodiments of the present disclosure. Processor 304 executes the program instructions / modules stored in memory 301 to perform functional applications and data processing, thereby implementing the command generation device method for NAND controller testing in the above-mentioned embodiments.

[0039] The memory 301 may include a program storage area and a data storage area. The program storage area may store an operating system and at least one application required for a function; the data storage area may store data generated based on the use of the terminal device. Furthermore, the memory 301 may include high-speed random access memory and non-volatile memory.

[0040] Example 3

[0041] This embodiment provides a computer-readable storage medium storing computer-executable instructions, wherein the computer-executable instructions are configured to execute the above-mentioned command generation method for NAND controller testing.

[0042] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0043] The technical solutions of the embodiments of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes one or more instructions for causing a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in the embodiments of the present disclosure. The aforementioned storage medium may be a non-transitory storage medium, including: a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, an optical disk, and other media that can store program code, or a transient storage medium.

[0044] The above description and the accompanying drawings sufficiently illustrate the embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent only possible variations. Unless expressly required, individual components and functions are optional, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terms used in this application are only used to describe the embodiments and are not used to limit the scope of protection. As used in the description herein, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to also include the plural forms. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of one or more associated listings. In addition, when used in this application, the term "comprise" and its variations "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, an element defined by the sentence "comprising a..." does not exclude the presence of other identical elements in the process, method or device that includes the element. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments can be referenced to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can be referred to the description of the method part.

[0045] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software may depend on the specific application and design constraints of the technical solution. The technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. The technicians will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

Claims

1. A command generation method for NAND controller testing, characterized by: This method divides the random command generation process into two stages: pre-generation stage and immediate generation stage; The pre-generation phase first determines the command type and quantity based on the configuration information sent by the tester, and allocates a space in the memory according to the total number of commands. Then, the order in which each command should be sent is determined. According to the order in which the commands are sent, the main differences between the current command and other commands are written into the allocated memory unit space. The immediate generation phase first generates a framework test command in the test command format required for NAND controller testing. This framework test command contains the common parts of each command with other commands and can be used repeatedly. Then, the test program reads the primary difference information stored in the pre-generation phase and generates secondary difference information. The primary and secondary difference information are filled into the framework test command to generate a complete test command and transmit it to the NAND controller. Test commands are generated in this way until the predetermined number of commands is reached. There is an adjustable proportional relationship between the main difference information and the secondary difference information.

2. The command generation method for NAND controller testing according to claim 1, wherein: Adjust the ratio of primary difference information to secondary difference information based on memory size and CPU computing power.

3. The command generation method for NAND controller testing according to claim 2, wherein: For a test machine with a memory larger than the set requirement but a CPU computing power smaller than the set requirement, all difference information is written into the memory as primary difference information in the pre-generation stage, and there is no need to generate secondary difference information in the immediate generation stage.

4. The command generation method for NAND controller testing according to claim 2, wherein: For a test set with less memory than the set requirement but more CPU power than the set requirement, the number of secondary difference information is greater than the number of primary difference information.

5. The command generation method for NAND controller testing according to claim 1, wherein: The main difference information includes command type, whether the scrambling function is enabled, whether the additional data function is enabled, whether the data check code function is enabled, and the data unit length.

6. The command generation method for NAND controller testing according to claim 1, wherein: The secondary difference information includes the specific storage address of user data in DDR, the specific storage address of additional data in DDR, the specific storage address of data in NAND, the command ID number, and the scrambling sequence to be used.

7. The command generation method for NAND controller testing according to claim 1, wherein: The configuration information includes the test command type, the number of test commands of each type, and the NAND address operated by the test command.

8. The command generation method for NAND controller testing according to claim 1, wherein: The sending order of each command is randomly determined by a random function and secondary difference information is generated.

9. A command generation device for NAND controller testing, comprising a processor and a memory storing program instructions, characterized in that: The processor is configured to execute the command generation method for NAND controller testing according to any one of claims 1 to 8 when running the program instructions.

10. A storage medium storing program instructions, characterized in that: When the program instructions are executed, the command generation method for NAND controller testing according to any one of claims 1 to 8 is executed.

Images