Configuration method and system for starting slave device based on SPI Slave

Abstract

According to the configuration method and system for starting the slave device based on the SPI Slave, the limitation of an existing method for loading an FPGA program can be solved, and use of a user is simplified; the flexibility of configuration can be improved through externally controllable pause and interrupt methods. The method comprises the following steps that: (1) external master equipment is connected with slave equipment through an SPI (Serial Peripheral Interface) communication protocol; (2) generating a configuration file of the slave device through EDA software; (3) the external master device transmits the configuration file to the slave device through the spislave interface; setting a spiclk frequency and a data volume of one-time transmission; the external master device interactively queries the idle state of the slave device with the slave device; if a configuration pause command is received, configuration is stopped, and configuration continues from a pause position after a configuration continuing command is received; if a configuration interruption name is received, stopping configuration and restarting configuration of other configuration files; and (4) judging whether the slave equipment is successfully configured.

Description

Technical Field

[0001] The present invention relates to the technical field of chips, and in particular to a configuration method for starting a slave device based on SPI Slave, and a configuration system for starting a slave device based on SPI Slave. Background Art

[0002] Field Programmable Gate Array (FPGA) is a large-scale programmable device that solves the problem of customized circuits. Users can use hardware description language to compile the required functional design into a code stream file to configure the FPGA and realize the circuit functions required by users. The advantages of programmability, reconfigurability and ease of use make FPGA widely used in various fields.

[0003] However, the existing methods for loading chip programs such as FPGA and CPLD have the following defects: 1. SPI Master configuration method (such as Figure 1 As shown in the figure): Through external flash, after power-on or Prog_b reset, FPGA actively reads a certain length of data from the external flash to configure FPGA. The configuration process cannot be interrupted or paused, and it is necessary to wait until the configuration is completed.

[0004] 2. Slave Serial / slave select map configuration method (such as Figure 2 The interface has many control signals and is not a universal communication protocol. There is no back pressure solution mechanism and the configuration clock cannot be too fast. If it is too fast, the FPGA will not be able to process the data and will lose the data. Summary of the invention

[0005] In order to overcome the defects of the prior art, the technical problem to be solved by the present invention is to provide a configuration method based on SPI Slave startup slave device, which can solve the limitations of the existing method of loading FPGA program, and transmit the configuration file in a serial manner with fewer communication signals with FPGA and standard SPI communication protocol, which will simplify user use; and the flexibility of configuration can be improved through the externally controllable pause and interrupt method, which has extremely high practical value.

[0006] The technical solution of the present invention is: the configuration method based on SPI Slave startup slave device comprises the following steps: (1) The external master device is connected to the slave device through the SPI communication protocol. The SPI mode is mode 0 or mode 3. The SPI clock frequency is set by the external master device. (2) Generate a configuration file from the device using EDA software; (3) The external master device transmits the configuration file to the slave device through the spi_slave interface; sets the clock frequency spi_clk of the SPI interface data transmission and the amount of data transmitted at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, the configuration is stopped, and the configuration is continued from the pause position after receiving a configuration resume command; if a configuration interrupt name is received, the configuration is stopped and the configuration of other configuration files is restarted; (4) Determine whether the slave device configuration is successful and output the result of whether the configuration is successful or not.

[0007] The beneficial technical effects of the present invention are: 1. The external SPI master device directly transfers the configuration file to the FPGA through the SPI interface, and no flash dedicated to storing the configuration file is required.

[0008] 2. Through the standard SPI communication protocol, the serial interface has fewer signals and is easy to use. In Slave mode, the frequency of the configuration clock and the amount of data transmitted at one time can be flexibly changed externally to meet the FPGA configuration requirements of various configuration time requirements without the need to change the configuration file content.

[0009] 3. By interacting with the FPGA, the external device can query the status of the FPGA to adaptively solve the problem of data loss caused by the FPGA being unable to receive the data due to the reverse pressure caused by the external data being transmitted too quickly when the FPGA is configured with different SPI clocks.

[0010] 4. Configure the FPGA in passive mode through SPI slave. During the configuration process, you can pause the configuration at any time according to the upper computer, and continue the configuration after a period of time, or interrupt the current configuration and start a new configuration.

[0011] A configuration system based on SPI Slave startup of a slave device is also provided. The external master device is connected to the slave device through the SPI communication protocol. The SPI mode is mode 0 or mode 3. The SPI clock frequency is set by the external master device. The configuration system based on SPI Slave startup of a slave device includes: A configuration file generation module, which generates a configuration file from a device through EDA software; The configuration file transmission module is configured as an external master device transmitting the configuration file to the slave device through the spi_slave interface; setting the clock frequency spi_clk of the SPI interface data transmission and the amount of data transmitted at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, the configuration is stopped, and the configuration is continued from the pause position after receiving a configuration resume command; if a configuration interrupt name is received, the configuration is stopped and the configuration of other configuration files is restarted; The judgment module judges whether the slave device configuration is successful and outputs the result of whether the configuration is successful or not. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is the SPI_Master configuration method of the prior art.

[0013] Figure 2 It is a Slave Serial / slave select map configuration method in the prior art.

[0014] Figure 3 A schematic diagram of the SPI_Slave configuration method of the present invention is shown.

[0015] Figure 4 The figure is a flow chart of a configuration method of a slave device based on SPI Slave startup according to the present invention. DETAILED DESCRIPTION

[0016] like Figure 3 , Figure 4 As shown, this configuration method based on SPI Slave startup slave device includes the following steps: (1) The external master device is connected to the slave device through the SPI communication protocol. The SPI mode is mode 0 or mode 3. The SPI clock frequency is set by the external master device. (2) Generate a configuration file from the device using EDA software; (3) The external master device transmits the configuration file to the slave device through the spi_slave interface; sets the clock frequency spi_clk of the SPI interface data transmission and the amount of data transmitted at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, the configuration is stopped, and the configuration is continued from the pause position after receiving a configuration resume command; if a configuration interrupt name is received, the configuration is stopped and the configuration of other configuration files is restarted; (4) Determine whether the slave device configuration is successful and output the result of whether the configuration is successful or not.

[0017] The beneficial technical effects of the present invention are: 1. The external SPI master device directly transfers the configuration file to the FPGA through the SPI interface, and no flash dedicated to storing the configuration file is required.

[0018] 2. Through the standard SPI communication protocol, the serial interface has fewer signals and is easy to use. In Slave mode, the frequency of the configuration clock and the amount of data transmitted at one time can be flexibly changed externally to meet the FPGA configuration requirements of various configuration time requirements without the need to change the configuration file content.

[0019] 3. By interacting with the FPGA, the external device can query the status of the FPGA to adaptively solve the problem of data loss caused by the FPGA being unable to receive the data due to the reverse pressure caused by the external data being transmitted too quickly when the FPGA is configured with different SPI clocks.

[0020] 4. Configure the FPGA in passive mode through SPI slave. During the configuration process, you can pause the configuration at any time according to the upper computer, and continue the configuration after a period of time, or interrupt the current configuration and start a new configuration.

[0021] Preferably, in step (1), the external master device is a host computer and the slave device is an FPGA.

[0022] Preferably, in step (2), the EDA software performs synthesis, layout and routing, and generates a configuration file in sequence according to the functional program to be implemented by the FPGA written by the user.

[0023] Preferably, the step (3) comprises the following sub-steps: (3.1) Set the FPGA configuration mode to spi_slave mode; (3.2) The host computer sets the SPI mode to mode 0 or mode 3; sets the SPI clock frequency spi_clk; and starts sending prog_b reset to the FPGA; (3.3) The host computer sends the corresponding control status register address and writes the send start bit value: sets the amount of data to be transmitted at one time, N, marking the start of FPGA configuration loading; (3.4) The host computer sends the corresponding control status register address to the FPGA and reads the value of the register. If the value of the 20th bit is 1, it means that the FPGA is busy; if it is 0, it means that the FPGA is idle. The host computer interacts with the FPGA to inquire about the status of the FPGA by repeatedly reading the control status register until the FPGA is idle. (3.5) When the FPGA is in idle state, the host computer writes N (N is set in step (3.2)) 8-bit (bit0~bit7) data outputs in the configuration file to the corresponding data register address of the FPGA in turn; (3.6) Repeat steps (3.4) and (3.5) until the configuration file data transmission is completed; if the data end of the configuration file is less than the amount of data to be transmitted once, the remaining bits are filled with zeros; (3.7) Repeat step (3.4); (3.8) When the FPGA is in idle state, the host computer writes the send end bit to the corresponding control status register address of the FPGA, indicating that the host computer has completed the transmission of the configuration file.

[0024] Preferably, in step (4), if the FPGA configuration is successful, done=1; if the configuration fails, done=0; if the host computer chooses to reconfigure, step (3.1) is executed, otherwise the process ends.

[0025] Preferably, in step (1), the external master device is a host computer, and the slave device is a CPLD (which can be used in product designs configured using the SPI slave mode).

[0026] Those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps of the above-mentioned embodiment method, and the storage medium can be: ROM / RAM, disk, CD, memory card, etc. Therefore, corresponding to the method of the present invention, the present invention also includes a configuration system based on SPI Slave startup slave device, and the system is usually represented in the form of functional modules corresponding to the steps of the method. The external master device is connected to the slave device through the SPI communication protocol, the SPI mode is mode 0 or mode 3, and the SPI clock frequency is set by the external master device. The configuration system based on SPI Slave startup slave device includes: A configuration file generation module, which generates a configuration file from a device through EDA software; The configuration file transmission module is configured as an external master device transmitting the configuration file to the slave device through the spi_slave interface; setting the clock frequency spi_clk of the SPI interface data transmission and the amount of data transmitted at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, the configuration is stopped, and the configuration is continued from the pause position after receiving a configuration resume command; if a configuration interrupt name is received, the configuration is stopped and the configuration of other configuration files is restarted; The judgment module judges whether the slave device configuration is successful and outputs the result of whether the configuration is successful or not.

[0027] Preferably, the external master device is a host computer, and the slave device is an FPGA.

[0028] Preferably, in the configuration file generation module, the EDA software sequentially performs synthesis, layout and routing, and generates a configuration file according to the functional program to be implemented by the FPGA written by the user.

[0029] Preferably, the configuration file transmission module performs the following steps: (3.1) Set the FPGA configuration mode to spi_slave mode; (3.2) The host computer sets the SPI mode to mode 0 or mode 3; sets the SPI clock frequency spi_clk; and starts sending prog_b reset to the FPGA; (3.3) The host computer sends the corresponding control status register address and writes the send start bit value: sets the amount of data to be transmitted at one time, N, marking the start of FPGA configuration loading; (3.4) The host computer sends the corresponding control status register address to the FPGA and reads the value of the register. If the value of the 20th bit is 1, it means that the FPGA is busy; if it is 0, it means that the FPGA is idle. The host computer interacts with the FPGA to inquire about the status of the FPGA by repeatedly reading the control status register until the FPGA is idle. (3.5) When the FPGA is in idle state, the host computer writes the N 8-bit data outputs in the configuration file to the corresponding data register address of the FPGA in sequence; (3.6) Repeat steps (3.4) and (3.5) until the configuration file data transmission is completed; if the data end of the configuration file is less than the amount of data to be transmitted once, the remaining bits are filled with zeros; (3.7) Repeat step (3.4); (3.8) When the FPGA is in idle state, the host computer writes the send end bit to the corresponding control status register address of the FPGA, indicating that the host computer has completed the transmission of the configuration file.

[0030] The above description is only a preferred embodiment of the present invention and does not limit the present invention in any form. Any simple modification, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention are still within the protection scope of the technical solution of the present invention.

Claims

1. A configuration method for starting a slave device based on SPI Slave, characterized in that: It includes the following steps: (1) The external master device is connected to the slave device through the SPI communication protocol. The SPI mode is mode 0 or mode 3. The SPI clock frequency is set by the external master device. (2) Generate a configuration file from the device using EDA software; (3) The external master device transmits the configuration file to the slave device through the spi_slave interface; sets the clock frequency spi_clk of the SPI interface data transmission and the amount of data transmitted at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, the configuration is stopped, and the configuration is continued from the pause position after receiving a configuration resume command; if a configuration interrupt name is received, the configuration is stopped and the configuration of other configuration files is restarted; (4) Determine whether the slave device configuration is successful and output the result of whether the configuration is successful or not.

2. The configuration method based on SPI Slave startup slave device according to claim 1, characterized in that: In the step (1), the external master device is a host computer and the slave device is an FPGA.

3. The configuration method based on SPI Slave startup slave device according to claim 2, characterized in that: In the step (2), the EDA software performs synthesis, layout and routing, and generates a configuration file in sequence according to the functional program to be implemented by the FPGA written by the user.

4. The configuration method based on SPI Slave startup slave device according to claim 3, characterized in that: The step (3) comprises the following sub-steps: (3.1) Set the FPGA configuration mode to spi_slave mode; (3.2) The host computer sets the SPI mode to mode 0 or mode 3; sets the SPI clock frequency spi_clk; and starts sending prog_b reset to the FPGA; (3.3) The host computer sends the corresponding control status register address and writes the send start bit value: sets the amount of data to be transmitted at one time, N, marking the start of FPGA configuration loading; (3.4) The host computer sends the corresponding control status register address to the FPGA and reads the value of the register. If the value of the 20th bit is 1, it means that the FPGA is in a busy state. If it is 0, it means that the FPGA is in an idle state. The host computer interacts with the FPGA to inquire about the status of the FPGA by repeatedly reading the control status register until the FPGA is in an idle state. (3.5) When the FPGA is in idle state, the host computer writes the N 8-bit data outputs in the configuration file to the corresponding data register address of the FPGA in sequence; (3.6) Repeat steps (3.4) and (3.5) until the configuration file data transmission is completed; if the data end of the configuration file is less than the amount of data to be transmitted once, the remaining bits are filled with zeros; (3.7) Repeat step (3.4); (3.8) When the FPGA is in idle state, the host computer writes the send end bit to the corresponding control status register address of the FPGA, indicating that the host computer has completed the transmission of the configuration file.

5. The configuration method based on SPI Slave startup slave device according to claim 4, characterized in that: In step (4), if the FPGA configuration is successful, done=1; if the configuration fails, done=0; if the host computer chooses to reconfigure, execute step (3.1), otherwise end.

6. The configuration method based on SPI Slave startup slave device according to claim 1, characterized in that: In the step (1), the external master device is a host computer and the slave device is a CPLD.

7. Based on SPI Slave startup slave device configuration system, the characteristics are: The external master device is connected to the slave device through the SPI communication protocol. The SPI mode is mode 0 or mode 3. The SPI clock frequency is set by the external master device. The configuration system based on SPISlave startup slave device includes: A configuration file generation module, which generates a configuration file from a device through EDA software; The configuration file transmission module is configured as an external master device transmitting the configuration file to the slave device through the spi_slave interface; setting the clock frequency spi_clk of the SPI interface data transmission and the amount of data transmitted at one time; the external master device interacts with the slave device to query the idle state of the slave device; if a configuration pause command is received, the configuration is stopped, and the configuration is continued from the pause position after receiving a configuration resume command; if a configuration interrupt name is received, the configuration is stopped and the configuration of other configuration files is restarted; The judgment module judges whether the slave device configuration is successful and outputs the result of whether the configuration is successful or not.

8. The configuration system based on SPI Slave booting slave device according to claim 7, characterized in that: The external master device is the host computer and the slave device is the FPGA.

9. The configuration system based on SPI Slave booting slave device according to claim 8, characterized in that: In the configuration file generation module, the EDA software performs synthesis, layout and routing, and generates configuration files in sequence according to the functional program to be implemented by the FPGA written by the user.

10. The configuration system based on SPI Slave booting slave device according to claim 9, characterized in that: The configuration file transmission module performs the following steps: (3.1) Set the FPGA configuration mode to spi_slave mode; (3.2) The host computer sets the SPI mode to mode 0 or mode 3; sets the SPI clock frequency spi_clk; and starts sending prog_b reset to the FPGA; (3.3) The host computer sends the corresponding control status register address and writes the send start bit value: sets the amount of data to be transmitted at one time, N, marking the start of FPGA configuration loading; (3.4) The host computer sends the corresponding control status register address to the FPGA and reads the value of the register. If the value of the 20th bit is 1, it means that the FPGA is in a busy state. If it is 0, it means that the FPGA is in an idle state. The host computer interacts with the FPGA to inquire about the status of the FPGA by repeatedly reading the control status register until the FPGA is in an idle state. (3.5) When the FPGA is in idle state, the host computer writes the N 8-bit data outputs in the configuration file to the corresponding data register address of the FPGA in sequence; (3.6) Repeat steps (3.4) and (3.5) until the configuration file data transmission is completed; if the data end of the configuration file is less than the amount of data to be transmitted once, the remaining bits are filled with zeros; (3.7) Repeat step (3.4); (3.8) When the FPGA is in idle state, the host computer writes the send end bit to the corresponding control status register address of the FPGA, indicating that the host computer has completed the transmission of the configuration file.

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