Data synchronization method and device, processor, display card and computer equipment

Abstract

The invention discloses a data synchronization method and device, a processor, a display card and computer equipment, and belongs to the technical field of data synchronization. The method comprises the steps that under the condition that hardware of a first processor completes data processing, the first processor writes a target address into an address register through firmware and triggers interruption, and the target address is a storage address of a data processing result in a storage unit; under the condition that the second processor receives the interrupt, the second processor reads a target address written by firmware from an address register through driving; and the second processor reads the data processing result from the storage unit based on the target address by driving. By adopting the scheme provided by the embodiment of the invention, the data synchronization efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of data synchronization, and in particular to a data synchronization method, device, processor, graphics card and computer equipment. Background Art

[0002] In a computer system, the processor usually needs to use external hardware to perform some data processing. For example, the processor uses the multimedia codec in the graphics card to encode and decode multimedia data. After the hardware completes the data processing, the data processing results need to be synchronized to the processor. This process is called data synchronization.

[0003] In the related art, after the hardware completes data processing, the firmware reports an interrupt. After the driver receives the interrupt, it further obtains intermediate information from the firmware, and determines the storage address of the data processing result by analyzing the intermediate information, thereby reading the data processing result based on the storage address. Taking multimedia codec data synchronization as an example, after the hardware completes the encoding and decoding of a frame of image, the firmware reports an interrupt; after the driver receives the interrupt, it obtains the frame information of the frame from the firmware, and analyzes the frame information to determine the storage address of the codec data in the video memory, and then reads the codec data from the video memory.

[0004] During the above data synchronization process, each time the driver receives an interrupt, it needs to interact with the firmware to obtain intermediate information, and the frequent interaction between the driver and the firmware will affect the data synchronization efficiency. Summary of the invention

[0005] The present application provides a data synchronization method, device, processor, graphics card and computer equipment, and the technical solution is as follows:

[0006] On the one hand, an embodiment of the present application provides a data synchronization method, the method comprising:

[0007] When the hardware of the first processor completes data processing, the first processor writes a target address into an address register through firmware and triggers an interrupt, wherein the target address is a storage address of the data processing result in the storage unit;

[0008] When the second processor receives the interrupt, the second processor reads the target address written by the firmware from the address register through a driver;

[0009] The second processor reads the data processing result from the storage unit based on the target address through the driver.

[0010] On the other hand, an embodiment of the present application provides a data synchronization method, the method being executed by a second processor running a driver, the method comprising:

[0011] In case of receiving an interrupt triggered by the firmware, reading a target address written by the firmware from an address register;

[0012] A data processing result is read from a storage unit based on the target address, wherein the data processing result is obtained by hardware executing data processing.

[0013] Optionally, the method further includes:

[0014] When the data processing result is read, updating the synchronization status corresponding to the target address in the synchronization list, the synchronization list including each synchronization address and the synchronization status corresponding to the synchronization address, the synchronization status including not synchronized, synchronizing and synchronized;

[0015] Among them, "unsynchronized" is the initial synchronization state of each synchronization address in the synchronization list, "synchronizing" indicates that the data corresponding to the synchronization address is waiting for synchronization, and "synchronized" indicates that the data corresponding to the synchronization address has completed synchronization.

[0016] Optionally, when the data processing result is read, updating the synchronization state corresponding to the target address in the synchronization list includes:

[0017] In case the data processing result is read, determining a target synchronization address in the synchronization list that is consistent with the target address;

[0018] The synchronization state corresponding to the target synchronization address is updated from being synchronized to synchronized.

[0019] Optionally, the synchronization addresses in the synchronization list are used cyclically;

[0020] The method further comprises:

[0021] Determine a target synchronization address in the synchronization list that is consistent with the target address;

[0022] Based on the synchronization state corresponding to the target synchronization address, sending a data processing instruction to the firmware, the data processing instruction is used to instruct to perform data processing, and write the data processing result into the storage unit based on the target address;

[0023] After sending the data processing instruction to the firmware, the synchronization state corresponding to the target synchronization address is updated from being synchronized.

[0024] Optionally, the sending a data processing instruction to the firmware based on the synchronization state corresponding to the target synchronization address includes:

[0025] When the synchronization state corresponding to the target synchronization address is unsynchronized, sending the data processing instruction to the firmware;

[0026] or,

[0027] When the synchronization state corresponding to the target synchronization address is synchronized, the data processing instruction is sent to the firmware.

[0028] Optionally, the sending a data processing instruction to the firmware based on the synchronization state corresponding to the target synchronization address further includes:

[0029] When the synchronization state corresponding to the target synchronization address is in synchronization, waiting for the synchronization state to be updated;

[0030] When the synchronization state corresponding to the target synchronization address is updated from being synchronized to synchronized, the data processing instruction is sent to the firmware.

[0031] Optionally, the synchronization addresses in the synchronization list are used cyclically;

[0032] The method further comprises:

[0033] Receiving a list configuration instruction sent by the firmware, wherein the list configuration instruction includes the synchronization address used cyclically;

[0034] The synchronization list is configured based on the list configuration instruction, and the synchronization state corresponding to each synchronization address in the synchronization list is initialized.

[0035] Optionally, the method further includes:

[0036] receiving a register configuration instruction sent by the firmware, wherein the register configuration instruction is used to configure a register index of the address register;

[0037] storing the register index in the register configuration instruction;

[0038] The step of reading the target address written by the firmware from the address register comprises:

[0039] The target address written by the firmware is read from the address register indicated by the register index.

[0040] Optionally, the hardware is a multimedia codec, the data processing result is multimedia codec data, and the target address is a storage address of the multimedia codec data in a video memory.

[0041] On the other hand, an embodiment of the present application provides a data synchronization method, the method being executed by a first processor running firmware, the method comprising:

[0042] When the data processing is completed, the target address is written into the address register and an interrupt is triggered. The target address is the storage address of the data processing result in the storage unit. The interrupt is used to trigger an interrupt to read the data processing result.

[0043] Optionally, the method further includes:

[0044] A data processing instruction sent by the driver is received, wherein the data processing instruction is used to instruct execution of data processing, and the data processing result is written into the storage unit based on the target address.

[0045] Optionally, the driver maintains a synchronization list, the synchronization list includes each synchronization address and a synchronization state corresponding to the synchronization address, the synchronization state includes unsynchronized, synchronizing, and synchronized; the synchronization addresses in the synchronization list are used cyclically;

[0046] The method further comprises:

[0047] A list configuration instruction is sent to the driver, wherein the list configuration instruction includes the synchronization address used cyclically.

[0048] Optionally, the method further includes:

[0049] Sending a register configuration instruction to the driver, wherein the register configuration instruction is used to configure a register index of the address register;

[0050] When the data processing is completed, writing the target address into the address register comprises:

[0051] When data processing is completed, the target address is written into the address register indicated by the register index.

[0052] Optionally, the hardware is a multimedia codec, the data processing result is multimedia codec data, and the target address is a storage address of the multimedia codec data in a video memory.

[0053] On the other hand, an embodiment of the present application provides a data synchronization device, the device comprising:

[0054] A first reading module, configured to read a target address written by the firmware from an address register when receiving an interrupt triggered by the firmware;

[0055] The second reading module is used to read the data processing result from the storage unit based on the target address, and the data processing result is obtained by executing data processing by hardware.

[0056] On the other hand, an embodiment of the present application provides a data synchronization device, the device comprising:

[0057] A writing module, used to write a target address into the address register when the data processing is completed, wherein the target address is a storage address of the data processing result in the storage unit;

[0058] An interrupt module is used to trigger an interrupt, and the interrupt is used to trigger an interrupt to read the data processing result.

[0059] On the other hand, an embodiment of the present application provides a processor, which is used to execute the data synchronization method described in the above aspects.

[0060] On the other hand, an embodiment of the present application provides a graphics card, which is used to execute the data synchronization method described in the above aspects.

[0061] On the other hand, an embodiment of the present application provides a computer-readable storage medium, in which at least one computer instruction is stored. The at least one computer instruction is loaded and executed to implement the data synchronization method as described in the above aspects.

[0062] On the other hand, an embodiment of the present application provides a computer program product, which includes computer instructions, the computer instructions are stored in a computer-readable storage medium, a processor obtains the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to implement the data synchronization method as described in the above aspects.

[0063] The beneficial effects of the technical solution provided by this application include at least:

[0064] In an embodiment of the present application, an address register is newly added to record the storage address of the data processing result in the storage unit. When the hardware completes the data processing, the first processor writes the storage address of the data processing result in the storage unit to the address register and triggers an interrupt through the firmware. Since the driver also has the right to access the address register, after receiving the interrupt, the second processor can read the storage address directly from the address register through the driver without additional interaction with the firmware, which simplifies the interaction process between the driver and the firmware, improves the efficiency of the driver in obtaining the data processing result from the storage unit, and thus improves the data synchronization efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0066] Figure 1 It is a schematic diagram of implementing data synchronization between firmware and driver in the related art;

[0067] Figure 2 is a flow chart of a data synchronization method provided by an exemplary embodiment of the present application;

[0068] Figure 3 It is a schematic diagram of an implementation of a target address writing and reading process shown in an exemplary embodiment of the present application;

[0069] Figure 4 It is a schematic diagram of an implementation of a multimedia encoding and decoding data synchronization process shown in an exemplary embodiment of the present application;

[0070] Figure 5 is a schematic diagram of a synchronization list shown in an exemplary embodiment of the present application;

[0071] Figure 6 is a schematic diagram of a state transition relationship between different synchronization states shown in an exemplary embodiment of the present application;

[0072] Figure 7 is a schematic diagram of an implementation of a synchronization status update process shown in an exemplary embodiment of the present application;

[0073] Figure 8 is a schematic diagram of an implementation of a synchronization status update process shown in another exemplary embodiment of the present application;

[0074] Fig. 9 is a schematic diagram of an implementation of a synchronization status update process shown in another exemplary embodiment of the present application;

[0075] Fig.10 is a schematic diagram of an implementation of a synchronization status update process shown in another exemplary embodiment of the present application;

[0076] Fig.11 is a schematic diagram of an implementation of a synchronization list configuration process shown in an exemplary embodiment of the present application;

[0077] Fig.12 is a flow chart of a data synchronization method provided by another exemplary embodiment of the present application;

[0078] Fig.13is a flow chart of a data synchronization method provided by another exemplary embodiment of the present application;

[0079] Fig.14 is a structural block diagram of a data synchronization device provided by an exemplary embodiment of the present application;

[0080] Fig.15 It is a structural block diagram of a data synchronization device provided by another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0081] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0082] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0083] The terms used in this disclosure are for the purpose of describing specific embodiments only and are not intended to limit the disclosure. The singular forms of "a", "said" and "the" used in this disclosure and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0084] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the information such as setting operations involved in this application is obtained with full authorization.

[0085] It should be understood that although the terms first, second, etc. may be used in the present disclosure to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present disclosure, the first parameter may also be referred to as the second parameter, and similarly, the second parameter may also be referred to as the first parameter. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0086] First, the relevant terms involved in this application are introduced:

[0087] Firmware: Firmware is software stored in a hardware device, usually in read-only memory (ROM), flash memory, or other types of non-volatile storage media. The main function of firmware is to control the operation and behavior of the hardware device.

[0088] Driver: Also known as a driver, it is a piece of software in a computer operating system that is used to enable the operating system to communicate with hardware devices. The driver acts as an interface between the hardware device and the operating system, allowing the operating system to identify and use the hardware device. The communication between the operating system and the hardware device is achieved through the driver and firmware.

[0089] Interrupt: refers to the process in which the computer automatically stops the running program and switches to the program that handles the new situation when some unexpected situation occurs during the operation of the computer and requires the intervention of the host. After the processing is completed, the program that was originally suspended returns to continue running. The interrupt in the embodiment of the present application is triggered by the firmware and is used to inform the driver that the hardware has completed data processing. After the driver receives the interrupt, it synchronizes the data processing results of the hardware.

[0090] Register: The operation of temporarily storing binary data or code is called registration, and the circuit that implements the registration function is called a register. As the most basic sequential logic circuit, the register is the basic module in the digital logic circuit. Commonly used registers are named according to the number of bits that can store data, and can include 4-bit registers, 8-bit registers, 16-bit registers, etc. The address register (AR) involved in the embodiments of the present application is used to store address information.

[0091] Instruction: It is a command that instructs a computer to perform a certain operation. It is the smallest functional unit of a computer. An instruction is a statement in machine language, and an instruction is a group of meaningful binary codes. The collection of all instructions of a computer constitutes the instruction system of the computer, also known as the instruction set.

[0092] like Figure 1 As shown, in the related art, the process of data synchronization between firmware and driver includes the following steps:

[0093] Step 1, the firmware triggers an interrupt;

[0094] In the multimedia codec scenario, after the multimedia codec in the graphics card completes the encoding and decoding of a frame of image, the firmware triggers an interrupt to inform the driver to synchronize the encoding and decoding data.

[0095] Step 2: The driver receives the interrupt and requests the firmware to provide intermediate information;

[0096] In the multimedia codec scene, the driver requests the firmware to provide frame information corresponding to the codec data to be synchronized.

[0097] Step 3, the firmware provides intermediate information to the driver;

[0098] In the multimedia codec scene, the firmware provides the driver with frame information corresponding to the codec data to be synchronized.

[0099] Step 4: The driver receives the intermediate information and parses the intermediate information to determine the storage address.

[0100] In the multimedia codec scene, the driver determines the memory address of the codec data in the graphics card by parsing the intermediate information, and then reads the codec data from the graphics card based on the memory address to complete data synchronization.

[0101] From the above process, it can be seen that after the driver receives the interrupt, it cannot directly read the data to be synchronized from the hardware, but needs to further interact and analyze with the firmware to determine the storage address of the data to be synchronized. In the multimedia codec scenario, the firmware and the driver need to synchronize data after each frame of the image is encoded and decoded, and the frequent interaction between the firmware and the driver will affect the data synchronization efficiency, and then affect the codec efficiency in the multimedia codec scenario.

[0102] Figure 2 A flowchart of a data synchronization method provided by an exemplary embodiment of the present application is shown. This implementation is illustrated by taking the method used for a first processor (used for processing data through hardware and running firmware) and a second processor (used for running a driver) as an example. The method may include the following steps.

[0103] Step 201, when the hardware of the first processor completes data processing, the first processor writes a target address into an address register through firmware, where the target address is a storage address of the data processing result in a storage unit.

[0104] In a possible implementation, after the hardware of the first processor completes data processing and stores the data processing result in the storage unit, it reports an interrupt indicating completion of data processing to the firmware. Based on the interrupt reported by the hardware, the firmware writes the target address of the data processing result in the storage unit into the address register.

[0105] In some embodiments, the data processing instruction sent by the driver to the firmware includes a target address, that is, when the driver sends the data processing instruction, it instructs the hardware to write the data processing result to a specified address in the storage unit after completing the data processing. After receiving the interrupt reported by the hardware, the firmware writes the target address in the data processing instruction into the address register.

[0106] Optionally, the address register is a newly added register in a register group that provides interrupt status, and the firmware and the driver are configured to have access rights to the address register, wherein the firmware has write permission to write an address to the address register, and the driver has read permission to read an address from the address register.

[0107] In some embodiments, the newly written address in the address register will overwrite the historically written address, that is, the target address stored in the address register is the storage address of the latest data processing result in the storage unit.

[0108] Optionally, the storage unit may be an internal storage unit of the hardware. For example, in a multimedia codec scenario, when the hardware is a multimedia codec in a graphics card (first processor), the data processing result is multimedia codec data, the storage unit is a video memory of the graphics card, and the target address is a storage address in the video memory (video memory address).

[0109] Of course, in other possible designs or application scenarios, the storage unit may also be an external storage unit of the hardware, and both the processor and the hardware support access to the storage unit. For example, the storage unit is a memory. The embodiments of the present application do not limit the specific location and type of the storage unit.

[0110] Indicatively, Figure 3 As shown, when the hardware completes the data processing, the firmware 31 writes the target address into the address register 32 in the register group.

[0111] Step 202: The firmware triggers an interrupt.

[0112] When the target address is written, the firmware triggers an interrupt.

[0113] Indicatively, Figure 3 As shown, after the target address is written, the firmware 31 triggers an interrupt.

[0114] Step 203: When the second processor receives an interrupt, the second processor reads the target address written by the firmware from the address register through a driver.

[0115] In the related art, the driver is configured to interact with the firmware after receiving an interrupt triggered by the firmware to obtain the intermediate information provided by the firmware, and parse the intermediate information to determine the storage address of the data processing result. In the embodiment of the present application, the driver is configured to directly read the target address in the address register after receiving an interrupt triggered by the firmware. In order to ensure that the address can be read correctly, the driver is configured to have access rights to the address register.

[0116] It can be seen that compared with the data synchronization scheme in the related art, in the embodiment of the present application, the driver does not need to further interact with the firmware after receiving the interrupt, but directly reads the storage address of the data processing result. On the one hand, it simplifies the processing logic of the driver after receiving the interrupt (simplified to reading the data in the register), and on the other hand, it simplifies the interaction process between the driver and the firmware during the data synchronization process (simplified to only triggering the interrupt).

[0117] Indicatively, Figure 3 As shown, after receiving the interrupt triggered by the firmware 31 , the driver 33 reads the target address written by the firmware 31 from the address register 32 .

[0118] Step 204: The second processor reads the data processing result from the storage unit based on the target address by driving.

[0119] Furthermore, based on the read target address, the second processor completes data synchronization by driving to read the data processing result written by the hardware from the storage unit.

[0120] Since the interaction logic between the driver and the firmware is simplified after the interrupt, the interval between the driver receiving the interrupt and finally obtaining the data processing results is shortened. In scenarios where frequent data synchronization is required (such as multimedia encoding and decoding scenarios), the data synchronization efficiency can be significantly improved.

[0121] like Figure 4 As shown, it shows a schematic diagram of the implementation of the data synchronization process in a multimedia codec scenario provided by an exemplary embodiment of the present application. After the multimedia codec 41 in the graphics card completes the multimedia data encoding and decoding, it writes the multimedia encoding and decoding data into the target address of the video memory 42 and reports an interrupt to the firmware 43.

[0122] According to the interrupt, the firmware 43 writes the target address into the address register 44 in the register group and triggers an interrupt.

[0123] After receiving the interruption triggered by the firmware 43 , the driver 45 reads the target address from the address register 44 , and reads the multimedia codec data from the video memory 42 according to the target address.

[0124] In summary, in an embodiment of the present application, an address register is newly added for recording the storage address of the data processing result in the storage unit. When the hardware completes the data processing, the first processor writes the storage address of the data processing result in the storage unit to the address register and triggers an interrupt through the firmware. Since the driver also has the right to access the address register, after receiving the interrupt, the second processor can read the storage address directly from the address register through the driver without additional interaction with the firmware, which simplifies the interaction process between the driver and the firmware, improves the efficiency of the driver in obtaining the data processing result from the storage unit, and thus improves the data synchronization efficiency.

[0125] In order to ensure that the data processing results are correctly synchronized and avoid the data processing results being overwritten by other data processing results before synchronization, in a possible implementation, the driver maintains a synchronization list, which includes a synchronization address and a synchronization state corresponding to the synchronization address. The synchronization address is the address of the storage unit storing the data processing results.

[0126] Optionally, the synchronization list is in the form of a linked list or an array, etc. The embodiment of the present application does not limit the specific form of the synchronization list.

[0127] Indicatively, Figure 5 As shown, when the synchronization class table adopts a linked list form, each node in the synchronization list has two variables, namely a synchronization address and a synchronization state corresponding to the synchronization address.

[0128] In some embodiments, the synchronization address in the synchronization list has three synchronization states, namely, Unsync, Syncing, and Synced.

[0129] Unsynchronized: the initial synchronization state of each synchronization address in the synchronization list. If no data processing instruction is received to instruct writing the data processing result to the synchronization address, the synchronization state of the synchronization address is Unsynchronized.

[0130] Synchronizing: Indicates that the data corresponding to the synchronization address is waiting for synchronization, that is, the data processing instruction to write the data processing result to the synchronization address has been received, but the driver has not completed the operation of reading the data processing result from the synchronization address. Optionally, when in the synchronization state, the synchronization address has not written the data processing result (the hardware is still processing the data), or the synchronization address has written the data processing result, but the driver has not started to read the data processing result from the synchronization address, or the synchronization address has written the data processing result, and the driver is reading the data processing result from the synchronization address, but has not completed the reading.

[0131] Synchronized: Indicates that the data corresponding to the synchronization address has been synchronized, that is, the driver has read the data processing result from the synchronization address.

[0132] In a possible design, the state transition relationship between synchronization states is as follows: Figure 6 As shown. Among them, for a synchronization address that is not synchronized, if a data processing instruction is received that indicates that the data processing result is to be written to the synchronization address, the synchronization address is updated from not synchronized to synchronized. For a synchronization address that is synchronized, if the driver completes reading the data processing result from the synchronization address, the synchronization address is updated from synchronized to synchronized. For a synchronization address that is synchronized, if a data processing instruction is received again that indicates that the data processing result is to be written to the synchronization address, the synchronization address is updated from synchronized to synchronized. For a synchronization address that is synchronized, if data synchronization ends, the synchronization address is restored from synchronized to the initial unsynchronized state.

[0133] In a possible implementation, when the data processing result is read, the second processor updates the synchronization state corresponding to the target address in the synchronization list through the driver. That is, each time after completing data synchronization, the driver needs to update the synchronization state of the synchronization address that completed data synchronization.

[0134] Regarding the specific method of updating the synchronization status, in some embodiments, after the second processor sends a data processing instruction to the firmware through the driver, the synchronization status corresponding to the synchronization address indicated by the data processing instruction in the synchronization list is updated to synchronizing. Therefore, when data synchronization is completed, the second processor determines the target synchronization address in the synchronization list that is consistent with the target address through the driver, and updates the synchronization status corresponding to the target synchronization address from synchronizing to synchronized.

[0135] Optionally, the driver compares the target address read from the address register with each synchronization address in the synchronization list to determine a target synchronization address that is consistent with the target address.

[0136] Indicatively, Figure 7 As shown, after the driver receives the interrupt, the target address read from the address register is Address2, and after reading the data processing result from the storage unit based on Address2, the synchronization state of Address2 in node 2 is updated from synchronizing to synchronized.

[0137] In some embodiments, in order to save storage space of the storage unit, the synchronization addresses in the synchronization list are used cyclically, that is, the data processing results obtained by the hardware in different rounds are cyclically written into multiple specified addresses in the storage unit. In other words, after the data processing results stored under a certain synchronization address in the storage unit are synchronized, the hardware can write the new data processing results into the synchronization address.

[0138] In this scenario, in order to avoid the occupation of the synchronization address that has not completed synchronization, resulting in the failure of synchronization of some data, in a possible implementation, before the second processor sends the data processing instruction to the firmware through the driver, it is necessary to perform a synchronization status detection on the synchronization address indicated by the data processing instruction, and send the data processing instruction to the firmware when the synchronization status of the synchronization address meets the conditions.

[0139] In some embodiments, when the driver needs to instruct the hardware to write the data processing results to the target address, the second processor determines the target synchronization address in the synchronization list that is consistent with the target address through the driver, and based on the synchronization state corresponding to the target synchronization address, sends a data processing instruction to the firmware, wherein the data processing instruction is used to instruct the execution of data processing and write the data processing results to the storage unit based on the target address.

[0140] In some embodiments, the data processing instruction includes a target address. The data processing instruction may also include data to be processed, or a read address of the data to be processed, wherein the data to be processed is submitted to the driver by an application with data processing requirements. For example, an application with multimedia data encoding and decoding requirements submits the multimedia data to be encoded and decoded to the multimedia encoding and decoding driver. The embodiments of the present application do not limit the specific content contained in the data processing instruction.

[0141] According to different synchronization states of the target synchronization address, the above-mentioned sending of data processing instructions to the firmware may include the following situations:

[0142] Case 1: When the synchronization state corresponding to the target synchronization address is unsynchronized, the second processor sends a data processing instruction to the firmware through the driver.

[0143] When the synchronization state corresponding to the target synchronization address is not synchronized, it indicates that the driver has not previously sent a historical data processing instruction to the firmware to instruct the data processing result to be written to the target synchronization address. In this case, since the data processing result is not written to the target synchronization address, the driver sending the data processing instruction to the firmware will not affect the synchronization of the historical data processing result under the target synchronization address.

[0144] In some embodiments, after sending the data processing instruction to the firmware, the second processor updates the synchronization state corresponding to the target synchronization address in the synchronization list from unsynchronized to synchronized through a driver.

[0145] Indicatively, Figure 8As shown, when it is necessary to instruct the hardware to perform data processing and write the data processing results to Address3 of the storage unit, since the synchronization status corresponding to Address3 in the synchronization list is not synchronized, the driver sends a data processing instruction containing Address3 to the firmware, and updates the synchronization status corresponding to Address3 in node 3 to synchronized.

[0146] Case 2: When the synchronization state corresponding to the target synchronization address is synchronized, the second processor sends a data processing instruction to the firmware through the driver.

[0147] When the synchronization state corresponding to the target synchronization address is synchronized, it indicates that the driver has previously sent a historical data processing instruction to the firmware to instruct the data processing result to be written to the target synchronization address, and the driver has synchronized the data processing result from the target synchronization address. In this case, since the historical data processing result written under the target synchronization address has been synchronized, the driver sends a data processing instruction to the firmware, and the subsequent data processing result newly written to the target synchronization address will not affect the synchronization of the historical data processing result.

[0148] In some embodiments, after sending the data processing instruction to the firmware, the second processor updates the synchronization state corresponding to the target synchronization address in the synchronization list from synchronized to synchronizing through a driver.

[0149] Indicatively, Fig. 9 As shown, when it is necessary to instruct the hardware to perform data processing and write the data processing result to Address2 of the storage unit, since the synchronization status corresponding to Address2 in the synchronization list is synchronized, the driver sends a data processing instruction containing Address2 to the firmware and updates the synchronization status corresponding to Address2 to synchronizing.

[0150] Case 3: When the synchronization state corresponding to the target synchronization address is in sync, the second processor waits for the synchronization state to be updated through the driver; when the synchronization state corresponding to the target synchronization address is updated from in sync to synchronized, the driver sends a data processing instruction to the firmware.

[0151] When the synchronization state corresponding to the target synchronization address is in sync, it indicates that the driver has previously sent a historical data processing instruction to the firmware to instruct the data processing result to be written to the target synchronization address, and the driver has not yet synchronized the data processing result from the target synchronization address. In this case, since the historical data processing result that has not been synchronized is written to the target synchronization address, if the driver sends a data processing instruction to the firmware, it will affect the synchronization of the historical data processing result under the target synchronization address. For example, the new data processing result may overwrite the historical data processing result, resulting in the driver being unable to synchronize the historical data processing result.

[0152] Therefore, in this scenario, the driver does not directly send data processing instructions to the firmware, but waits for the synchronization status of the target synchronization address to be updated. When the synchronization status is updated to synchronized, it indicates that the historical data results under the target synchronization address have been synchronized, and the driver can now send data processing instructions to the firmware.

[0153] In some embodiments, after sending the data processing instruction to the firmware, the second processor updates the synchronization state corresponding to the target synchronization address in the synchronization list from synchronized to synchronizing through a driver.

[0154] Indicatively, Fig.10 As shown, when it is necessary to instruct the hardware to process data and write the data processing results to Address1 of the storage unit, since the synchronization status corresponding to Address1 in the synchronization list is synchronizing, the driver cannot send the data processing instruction immediately and needs to wait for the synchronization status of Address1 to be updated. When the synchronization status of Address1 is updated to synchronized, the driver sends the data processing instruction containing Address1 to the firmware and updates the synchronization status corresponding to Address1 in Node 1 to synchronizing.

[0155] In the above-mentioned various cases, in some embodiments, after receiving the data processing instruction sent by the driver, the firmware further controls the hardware to perform the data processing operation indicated by the data processing instruction. The firmware indicates the read address of the data to be processed to the hardware based on the data processing instruction, so that the hardware reads the data to be processed from the read address; the firmware also indicates what operation to perform on the data to be processed based on the data processing instruction; the firmware also indicates the storage address (i.e., the target address) of the data processing result to the hardware based on the data processing instruction, so that the hardware writes the data processing result into the storage unit based on the target address.

[0156] In this embodiment, the driver introduces a synchronization status detection mechanism by maintaining a synchronization list and when the synchronization address in the synchronization list is used cyclically. Under this mechanism, before sending a data processing instruction containing a target synchronization address to the firmware, the driver determines whether the historical data processing result under the target synchronization address has completed synchronization based on the synchronization status of the target synchronization address in the synchronization list, and waits for the historical data processing result under the target synchronization address to complete synchronization if the historical data processing result has not completed synchronization, thereby avoiding the historical data processing result being overwritten by the new data processing result due to the direct sending of the data processing instruction, and improving the accuracy of data synchronization.

[0157] In one possible design, when the hardware cyclically uses the specified address in the storage unit to achieve data synchronization, that is, the synchronization address in the synchronization list is cyclically used, in order to make the driver aware of the synchronization address, in one possible implementation, the firmware sends a list configuration instruction to the driver, which includes the cyclically used synchronization address.

[0158] Optionally, the synchronization address used cyclically in the list configuration instruction may be a fixed address or an address dynamically allocated by the firmware.

[0159] Optionally, upon receiving a data processing request from an application, the second processor sends a list configuration request to the firmware through the driver. The firmware determines a synchronization address for cyclic use based on the list configuration request and sends a list configuration instruction to the driver.

[0160] Optionally, the number of synchronization addresses configured by the firmware is a fixed value, or the firmware dynamically configures the number of synchronization addresses.

[0161] In a possible implementation, the firmware may dynamically determine the number of cyclically used synchronization addresses according to the occupancy of the storage unit.

[0162] For example, when the occupancy rate of the storage unit is lower than a threshold, the firmware can allocate a first number of synchronization addresses; when the occupancy rate of the storage unit is higher than the threshold, the firmware can allocate a second number of synchronization addresses, wherein the first number is greater than the second number. In this way, the data synchronization speed in low-load (low storage occupancy) scenarios can be improved, and excessive storage space occupation in high-load (high storage occupancy) scenarios can be avoided.

[0163] The firmware can also dynamically configure the number of synchronization addresses based on other factors, such as dynamically allocating the number of synchronization addresses based on the data synchronization speed requirements of the application. For example, more synchronization addresses are allocated to applications with high data synchronization speed requirements (as shown by the fact that the data synchronization speed has a greater impact on the running quality of the application), and fewer synchronization addresses are allocated to applications with low data synchronization requirements. The embodiments of the present application do not limit the basis for the firmware to configure the number of synchronization addresses.

[0164] After receiving the list configuration instruction, the second processor configures the synchronization list based on the list configuration instruction through a driver, and initializes the synchronization state corresponding to each synchronization address in the synchronization list.

[0165] Optionally, the driver configures the physical address contained in each node in the linked list based on the synchronization address in the list configuration instruction, and initializes the synchronization state of each synchronization address to unsynchronized.

[0166] In an illustrative example, Fig.11As shown, when an application with multimedia codec requirements sends a codec request to the driver 111, the driver 111 sends a list configuration request to the firmware 112. According to the request, the firmware 112 determines the synchronization addresses for multimedia codec data synchronization from the video memory 113 as Address 1, 2, and 3, respectively, and sends a list configuration instruction containing the above synchronization addresses to the driver 111. After receiving the list configuration instruction, the driver 111 configures the synchronization list 114 and initializes the synchronization state corresponding to each synchronization address to unsynchronized.

[0167] In this embodiment, the synchronization addresses that are used cyclically in the synchronization list are configured by the firmware through list configuration instructions. On the one hand, this ensures the consistency of the synchronization addresses at the firmware and the driver, and ensures the correctness of data synchronization; on the other hand, the firmware can dynamically configure the synchronization addresses used for data synchronization, such as dynamically configuring the number of synchronization addresses, thereby improving the flexibility of the data synchronization process.

[0168] In a possible implementation, the address register is a fixed register, that is, a register index of the address register is pre-configured in the firmware and the driver.

[0169] In another possible implementation, the address register is a register dynamically allocated by the firmware. In this case, in order to ensure that the driver can correctly read the target address in the address register, in some embodiments, the second processor sends a register configuration instruction to the driver through the firmware, and the register configuration instruction is used to configure the register index of the address register; the driver receives and stores the register index in the register configuration instruction.

[0170] Optionally, upon receiving a data processing request from an application, the second processor sends a register configuration request to the firmware through the driver. Based on the register configuration request, the firmware configures an address register for storing an address and sends a register configuration instruction to the driver. The firmware may configure a register in an idle state in the register group as an address register.

[0171] It should be noted that if the register configuration request sent by the driver is not received, the firmware does not need to configure the address register in the register group. In other words, the address register can be reused to store other types of data when there is no data synchronization requirement.

[0172] During the subsequent data synchronization process, the firmware writes the target address into the address register indicated by the register index, and the driver reads the target address written by the firmware from the address register indicated by the register index.

[0173] In an illustrative example, when an application with multimedia codec requirements sends a codec request to the driver, the second processor sends a register configuration request to the firmware through the driver. Based on the request, the firmware determines the address register used to store the address in the multimedia codec data synchronization process from the register group, and sends a register configuration instruction containing a register index to the driver. After receiving the register configuration instruction, the driver saves the register index contained in the instruction.

[0174] During the subsequent data synchronization process, the driver reads the target address written by the firmware from the address register indicated by the register index based on the saved register index.

[0175] In this embodiment, the address register configured by the firmware for address synchronization ensures the consistency of the addresses written by the firmware and read by the driver, thereby ensuring the correctness of subsequent data synchronization; on the other hand, in the absence of data synchronization requirements, the address register can be reused to store other types of data, thereby avoiding resource waste caused by idle registers.

[0176] Fig.12 A flow chart of a data synchronization method provided by another exemplary embodiment of the present application is shown. The method is executed by a second processor running a driver, and the method includes the following steps.

[0177] Step 1201, when receiving an interrupt triggered by the firmware, read the target address written by the firmware from the address register.

[0178] Step 1202, reading a data processing result from a storage unit based on a target address, the data processing result being obtained by hardware executing data processing.

[0179] In some embodiments, when the data processing result is read, the driver updates the synchronization status corresponding to the target address in the synchronization list, the synchronization list includes each synchronization address and the synchronization status corresponding to the synchronization address, the synchronization status includes not synchronized, synchronizing and synchronized; wherein, not synchronized is the initial synchronization status of each synchronization address in the synchronization list, synchronizing indicates that the data corresponding to the synchronization address is waiting for synchronization, and synchronized indicates that the data corresponding to the synchronization address has completed synchronization.

[0180] In some embodiments, during the process of updating the synchronization state corresponding to the target address in the synchronization list, when the data processing result is read, the driver determines the target synchronization address in the synchronization list that is consistent with the target address; and updates the synchronization state corresponding to the target synchronization address from being synchronized to synchronized.

[0181] In some embodiments, when the synchronization addresses in the synchronization list are used cyclically, the driver determines a target synchronization address in the synchronization list that is consistent with the target address; based on the synchronization state corresponding to the target synchronization address, a data processing instruction is sent to the firmware, the data processing instruction is used to instruct the execution of data processing, and the data processing result is written to the storage unit based on the target address; after sending the data processing instruction to the firmware, the synchronization state corresponding to the target synchronization address is updated from being synchronized.

[0182] In some embodiments, based on the synchronization state corresponding to the target synchronization address, in the process of sending the data processing instruction to the firmware, if the synchronization state corresponding to the target synchronization address is not synchronized, the driver sends the data processing instruction to the firmware; or,

[0183] When the synchronization state corresponding to the target synchronization address is synchronized, the driver sends a data processing instruction to the firmware.

[0184] In some embodiments, in the process of sending data processing instructions to the firmware based on the synchronization status corresponding to the target synchronization address, when the synchronization status corresponding to the target synchronization address is synchronized, the driver waits for the synchronization status to be updated, and sends the data processing instructions to the firmware when the synchronization status corresponding to the target synchronization address is updated from synchronized to synchronized.

[0185] In some embodiments, when the synchronization addresses in the synchronization list are recycled, before data synchronization, the driver receives a list configuration instruction sent by the firmware, and the list configuration instruction includes the recycled synchronization addresses; configures the synchronization list based on the list configuration instruction, and initializes the synchronization status corresponding to each synchronization address in the synchronization list.

[0186] In some embodiments, before data synchronization, the driver receives a register configuration instruction sent by the firmware and stores a register index in the register configuration instruction, where the register configuration instruction is used to configure the register index of the address register. During data synchronization, the driver reads the target address written by the firmware from the address register indicated by the register index.

[0187] In some embodiments, the hardware is a multimedia codec, the data processing result is multimedia codec data, and the target address is a storage address of the multimedia codec data in a video memory.

[0188] The specific process of driving data synchronization can refer to the description of the driving side in the above embodiment, and will not be described in detail in this embodiment.

[0189] Fig.13 A flow chart of a data synchronization method provided by another exemplary embodiment of the present application is shown. The method is executed by a first processor running firmware, and the method includes the following steps.

[0190] Step 1301, when data processing is completed, write the target address into the address register, the target address is the storage address of the data processing result in the storage unit.

[0191] Step 1302, triggering an interrupt, where the interrupt is used to trigger an interrupt to read the data processing result.

[0192] In some embodiments, before performing data processing, the firmware receives a data processing instruction sent by the driver, where the data processing instruction is used to instruct the execution of data processing and write the data processing result into a storage unit based on a target address.

[0193] In some embodiments, the driver maintains a synchronization list, which includes each synchronization address and the synchronization status corresponding to the synchronization address, and the synchronization status includes unsynchronized, synchronizing, and synchronized; the synchronization addresses in the synchronization list are recycled, and before performing data synchronization, the firmware sends a list configuration instruction to the driver, and the list configuration instruction includes the cyclically used synchronization addresses.

[0194] In some embodiments, before performing data synchronization, the firmware sends a register configuration instruction to the driver, where the register configuration instruction is used to configure a register index of an address register; when data processing is completed, the firmware writes the target address into the address register indicated by the register index.

[0195] In some embodiments, the hardware is a multimedia codec, the data processing result is multimedia codec data, and the target address is a storage address of the multimedia codec data in a video memory.

[0196] The specific process of firmware implementing data synchronization can refer to the description of the firmware side in the above embodiment, and this embodiment will not be repeated here.

[0197] Fig.14 A structural block diagram of a data synchronization device provided by an exemplary embodiment of the present application is shown, the device comprising:

[0198] A first reading module 1401 is used to read the target address written by the firmware from the address register when receiving an interrupt triggered by the firmware;

[0199] The second reading module 1402 is used to read the data processing result from the storage unit based on the target address, and the data processing result is obtained by executing data processing by hardware.

[0200] Optionally, the device further comprises:

[0201] An updating module, configured to update the synchronization status corresponding to the target address in the synchronization list when the data processing result is read, wherein the synchronization list includes each synchronization address and the synchronization status corresponding to the synchronization address, and the synchronization status includes unsynchronized, synchronizing, and synchronized;

[0202] Among them, "unsynchronized" is the initial synchronization state of each synchronization address in the synchronization list, "synchronizing" indicates that the data corresponding to the synchronization address is waiting for synchronization, and "synchronized" indicates that the data corresponding to the synchronization address has completed synchronization.

[0203] Optionally, update the module to:

[0204] In case the data processing result is read, determining a target synchronization address in the synchronization list that is consistent with the target address;

[0205] The synchronization state corresponding to the target synchronization address is updated from being synchronized to synchronized.

[0206] Optionally, the synchronization addresses in the synchronization list are used cyclically;

[0207] The device further comprises:

[0208] Sending module, used for:

[0209] A target synchronization address in the synchronization list that is consistent with the target address;

[0210] Based on the synchronization state corresponding to the target synchronization address, sending a data processing instruction to the firmware, the data processing instruction is used to instruct to perform data processing, and write the data processing result into the storage unit based on the target address;

[0211] An update module is used to update the synchronization state corresponding to the target synchronization address from "synchronizing" after sending a data processing instruction to the firmware.

[0212] Optionally, the sending module is used to:

[0213] When the synchronization state corresponding to the target synchronization address is unsynchronized, sending the data processing instruction to the firmware;

[0214] or,

[0215] When the synchronization state corresponding to the target synchronization address is synchronized, the data processing instruction is sent to the firmware.

[0216] Optionally, the sending module is further used to:

[0217] When the synchronization state corresponding to the target synchronization address is in synchronization, waiting for the synchronization state to be updated;

[0218] When the synchronization state corresponding to the target synchronization address is updated from being synchronized to synchronized, the data processing instruction is sent to the firmware.

[0219] Optionally, the synchronization addresses in the synchronization list are used cyclically;

[0220] The device also includes:

[0221] A receiving module, used for receiving a list configuration instruction sent by the firmware, wherein the list configuration instruction includes the synchronization address used cyclically;

[0222] An initialization module is used to configure the synchronization list based on the list configuration instruction, and initialize the synchronization state corresponding to each synchronization address in the synchronization list.

[0223] Optionally, the device further comprises:

[0224] A receiving module, used for receiving a register configuration instruction sent by the firmware, wherein the register configuration instruction is used for configuring a register index of the address register;

[0225] A storage module, used for storing the register index in the register configuration instruction;

[0226] The first reading module 1401 is used to read the target address written by the firmware from the address register indicated by the register index.

[0227] Optionally, the hardware is a multimedia codec, the data processing result is multimedia codec data, and the target address is a storage address of the multimedia codec data in a video memory.

[0228] The process of implementing data synchronization by the above-mentioned data synchronization device may refer to the data synchronization method on the driving side, which will not be described in detail in this embodiment.

[0229] Fig.15 A structural block diagram of a data synchronization device provided by another exemplary embodiment of the present application is shown, the device comprising:

[0230] A writing module 1501 is used to write a target address into an address register when data processing is completed, wherein the target address is a storage address of the data processing result in a storage unit;

[0231] The interrupt module 1502 is used to trigger an interrupt, and the interrupt is used to trigger an interrupt to read the data processing result.

[0232] Optionally, the device further comprises:

[0233] The receiving module is used to receive a data processing instruction sent by the driver, wherein the data processing instruction is used to instruct the execution of data processing, and write the data processing result into the storage unit based on the target address.

[0234] Optionally, the driver maintains a synchronization list, the synchronization list includes each synchronization address and a synchronization state corresponding to the synchronization address, the synchronization state includes unsynchronized, synchronizing, and synchronized; the synchronization addresses in the synchronization list are used cyclically;

[0235] The device also includes:

[0236] The sending module is used to send a list configuration instruction to the driver, wherein the list configuration instruction includes the cyclically used synchronization address.

[0237] Optionally, the device further comprises:

[0238] A sending module, used for sending a register configuration instruction to the driver, wherein the register configuration instruction is used for configuring a register index of the address register;

[0239] The writing module 1501 is used to write the target address into the address register indicated by the register index when data processing is completed.

[0240] Optionally, the hardware is a multimedia codec, the data processing result is multimedia codec data, and the target address is a storage address of the multimedia codec data in a video memory.

[0241] The process of implementing data synchronization by the above-mentioned data synchronization device may refer to the data synchronization method on the firmware side, which will not be described in detail in this embodiment.

[0242] On the other hand, an embodiment of the present application provides a processor, which is used to implement the data synchronization method on the processor (driver) side in the above embodiment. Optionally, the processor is a CPU (Central Processing Unit), NPU (Neural Processing Unit), etc.

[0243] On the other hand, an embodiment of the present application provides a graphics card, which is used to implement the data synchronization method on the hardware (firmware) side of the above embodiment. Optionally, the hardware can be a hardware multimedia codec in the graphics card.

[0244] On the other hand, an embodiment of the present application provides a computer device, which includes the processor and the graphics card as described above. The computer device can be at least one of a portable computer, a desktop computer, a server, a server cluster, an artificial intelligence (AI) computing cluster, and a cloud computing cluster. When the processor and the graphics card synchronize multimedia codec data, the data synchronization method provided in the above embodiment can be sampled.

[0245] On the other hand, an embodiment of the present application provides a computer-readable storage medium, in which at least one computer instruction is stored. The at least one computer instruction is loaded and executed to implement the data synchronization method described in the above embodiment.

[0246] On the other hand, an embodiment of the present application provides a computer program product, which includes computer instructions, the computer instructions are stored in a computer-readable storage medium, a processor obtains the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to implement the data synchronization method described in the above embodiment.

[0247] It should be understood that the "multiple" mentioned in this article refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In addition, the step numbers described in this article only illustrate a possible execution sequence between the steps. In some other embodiments, the above steps may not be executed in the order of the numbers, such as two steps with different numbers are executed at the same time, or two steps with different numbers are executed in the opposite order to the diagram. The embodiments of the present application are not limited to this.

[0248] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A data synchronization method, characterized in that: The method comprises: When the hardware of the first processor completes data processing, the first processor writes a target address into an address register through firmware and triggers an interrupt, wherein the target address is a storage address of the data processing result in the storage unit; When the second processor receives the interrupt, the second processor reads the target address written by the firmware from the address register through a driver; The second processor reads the data processing result from the storage unit based on the target address through the driver.

2. The method according to claim 1, characterized in that The method further comprises: When the data processing result is read, the second processor updates the synchronization state corresponding to the target address in the synchronization list through the driver, wherein the synchronization list includes each synchronization address and the synchronization state corresponding to the synchronization address, and the synchronization state includes not synchronized, synchronizing, and synchronized; Among them, "unsynchronized" is the initial synchronization state of each synchronization address in the synchronization list, "synchronizing" indicates that the data corresponding to the synchronization address is waiting for synchronization, and "synchronized" indicates that the data corresponding to the synchronization address has completed synchronization.

3. The method according to claim 2, characterized in that When the data processing result is read, the second processor updates the synchronization state corresponding to the target address in the synchronization list through the driver, including: When the data processing result is read, the second processor determines, through the driver, a target synchronization address in the synchronization list that is consistent with the target address; The second processor updates the synchronization state corresponding to the target synchronization address from being synchronized to synchronized through the driver.

4. The method according to claim 2, characterized in that: The synchronization addresses in the synchronization list are used cyclically; The method further comprises: The second processor determines, through the driver, a target synchronization address in the synchronization list that is consistent with the target address; The second processor sends a data processing instruction to the firmware through the driver based on the synchronization state corresponding to the target synchronization address, wherein the data processing instruction is used to instruct to perform data processing, and write the data processing result into the storage unit based on the target address; After sending the data processing instruction to the firmware, the second processor updates the synchronization state corresponding to the target synchronization address from "synchronizing" through the driver.

5. The method according to claim 4, characterized in that The second processor sends a data processing instruction to the firmware through the driver based on the synchronization state corresponding to the target synchronization address, including: When the synchronization state corresponding to the target synchronization address is unsynchronized, the second processor sends the data processing instruction to the firmware through the driver; or, When the synchronization state corresponding to the target synchronization address is synchronized, the second processor sends the data processing instruction to the firmware through the driver.

6. The method according to claim 4, characterized in that The second processor sends a data processing instruction to the firmware based on the synchronization state corresponding to the target synchronization address through the driver, and further includes: When the synchronization state corresponding to the target synchronization address is in synchronization, the second processor waits for synchronization state update through the driver; When the synchronization state corresponding to the target synchronization address is updated from being synchronized to synchronized, the second processor sends the data processing instruction to the firmware through the driver.

7. The method according to claim 2, characterized in that The synchronization addresses in the synchronization list are used cyclically; The method further comprises: The first processor sends a list configuration instruction to the driver through the firmware, wherein the list configuration instruction includes the synchronization address used cyclically; The second processor configures the synchronization list based on the list configuration instruction through the driver, and initializes the synchronization state corresponding to each synchronization address in the synchronization list.

8. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: The first processor sends a register configuration instruction to the driver through the firmware, where the register configuration instruction is used to configure a register index of the address register; The second processor receives and stores the register index in the register configuration instruction through the driver; The first processor writes the target address into the address register through the firmware, including: The first processor writes the target address into the address register indicated by the register index through the firmware; The second processor reads the target address written by the firmware from the address register through the driver, including: The second processor reads the target address written by the firmware from the address register indicated by the register index through the driver.

9. The method according to any one of claims 1 to 7, characterized in that: The hardware is a multimedia codec, the data processing result is multimedia codec data, and the target address is a storage address of the multimedia codec data in a video memory.

10. A data synchronization method, characterized in that: The method is executed by a second processor running a driver, and the method includes: In case of receiving an interrupt triggered by the firmware, reading a target address written by the firmware from an address register; A data processing result is read from a storage unit based on the target address, wherein the data processing result is obtained by hardware executing data processing.

11. A data synchronization method, characterized in that: The method is performed by a first processor running firmware, and the method includes: When the data processing is completed, the target address is written into the address register, and the target address is the storage address of the data processing result in the storage unit. Trigger an interrupt, where the interrupt is used to trigger an interrupt to read the data processing result.

12. A data synchronization device, characterized in that: The device comprises: A first reading module, configured to read a target address written by the firmware from an address register when receiving an interrupt triggered by the firmware; The second reading module is used to read the data processing result from the storage unit based on the target address, and the data processing result is obtained by executing data processing by hardware.

13. A data synchronization device, characterized in that: The device comprises: A writing module, used to write a target address into the address register when the data processing is completed, wherein the target address is a storage address of the data processing result in the storage unit; An interrupt module is used to trigger an interrupt, and the interrupt is used to trigger an interrupt to read the data processing result.

14. A processor, characterized in that: The processor is configured to execute the data synchronization method as claimed in claim 10.

15. A graphics card, characterized in that: The graphics card is used to execute the data synchronization method as claimed in claim 11.

16. A computer device, characterized in that: The computer device comprises the processor as claimed in claim 14 and the graphics card as claimed in claim 15 .

17. A computer-readable storage medium, characterized in that: At least one computer instruction is stored in the computer-readable storage medium, and the at least one computer instruction is loaded and executed to implement the data synchronization method as claimed in claim 10 or 11.

18. A computer program product, characterized in that The computer program product includes computer instructions, which are stored in a computer-readable storage medium. The processor obtains the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions to implement the data synchronization method as described in claim 10 or 11.

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