RTL automatic testing method, system and medium for RISC-V DSP chip

Abstract

The embodiment of the present application provides an RTL automatic testing method, system and medium for a RISC‑V DSP chip, the method comprising: establishing an RTL test framework, generating multiple test modes based on the RTL test framework; generating a matching test program according to the multiple test modes, and forming corresponding test steps based on the test program; obtaining a test item, analyzing the test requirement information of the test item, matching the test mode based on the test requirement information, and generating a test matching degree; judging whether the test matching degree is greater than or equal to a set matching degree threshold; if greater than or equal to, selecting a test program based on the matching test mode to test the test item; if less than, adjusting the test mode based on correction information; establishing multiple test programs according to the RTL test framework to meet the requirements of different test items, matching different test programs according to the requirements of different test items, thereby accurately testing the chip and improving the test effect.

Description

Technical Field

[0001] The present application relates to the field of chip testing technology, and in particular to an RTL automatic testing method, system and medium for a RISC-V DSP chip. Background Art

[0002] The RTL batch automatic testing framework is used to perform batch automatic testing in the scenario of multiple projects / multiple test case sets at the RTL (Register-Transfer Level) level during VERILOG design.

[0003] The RTL batch automatic testing framework includes general configuration and independent configuration information for each project, a set of input stimuli (test cases) for each project, and RTL design code for each project. It conforms to the test stimulus-test environment-test output architecture design and can be used to test the RTL code of each project itself, as well as the key data used by the RTL code. It can also test various input stimuli, which may have specific functions in subsequent applications. Existing chip testing methods cannot select different test modes according to the requirements of different test projects, making it difficult to test the chip efficiently and accurately, affecting the test effect. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide an RTL automatic testing method, system and medium for a RISC-V DSP chip, establish multiple test programs through an RTL test framework to meet the needs of different test projects, match different test programs according to the needs of different test projects, thereby accurately testing the chip and improving the test effect.

[0005] The embodiment of the present application also provides an RTL automatic testing method for a RISC-V DSP chip, including:

[0006] Establish an RTL test framework and generate multiple test modes based on the RTL test framework;

[0007] Generate a matching test program according to multiple test patterns, and form corresponding test steps based on the test program;

[0008] Acquire test items, analyze test requirement information of the test items, match test modes based on the test requirement information, and generate test matching degrees;

[0009] Determine whether the test matching degree is greater than or equal to a set matching degree threshold;

[0010] If it is greater than or equal to, then a test program is selected based on the matching test mode to test the test item and generate test data in real time;

[0011] If it is less than, correction information is generated and the test mode is adjusted based on the correction information.

[0012] Optionally, in the RTL automatic testing method of the RISC-V DSP chip described in the embodiment of the present application, an RTL test framework is established, and multiple test modes are generated based on the RTL test framework, specifically including:

[0013] Construct an RTL test framework, wherein the RTL test framework includes interaction logic, test process control logic, data processing logic, and result aggregation logic;

[0014] Generate multiple interaction modes based on interaction logic, and generate multiple control modes based on test process control logic;

[0015] Generate multiple processing modes based on data processing logic, and generate multiple aggregation modes based on result aggregation logic;

[0016] The interactive mode, the control mode, the processing mode and the summary mode are randomly paired to obtain multiple paired combinations;

[0017] A test logic corresponding to each pairing combination is formed based on the plurality of pairing combinations, and a corresponding test mode is generated based on the test logic.

[0018] Optionally, in the RTL automatic testing method of the RISC-V DSP chip described in the embodiment of the present application, a matching test program is generated according to multiple test modes, and corresponding test steps are formed based on the test program, specifically including:

[0019] Obtain the test logic corresponding to each test mode, establish a test program based on the test logic, and analyze the deviation rate between the test program and the test logic;

[0020] Determining whether the deviation rate is greater than or equal to a set deviation rate threshold;

[0021] If the deviation rate is greater than or equal to the set threshold, feedback information is generated, and the test program is adjusted based on the feedback information;

[0022] If it is less than the set deviation rate threshold, the test steps are established according to the current test procedure.

[0023] Optionally, in the RTL automatic testing method of the RISC-V DSP chip described in the embodiment of the present application, obtaining a test item, analyzing the test requirement information of the test item, matching a test mode based on the test requirement information, and generating a test matching degree specifically include:

[0024] Get the test project, analyze the project's dependency path, required special variables, data processing or transfer details configuration, and post-compilation processing logic;

[0025] Analyze the test project's requirements based on the project's dependency paths, required special variables, data processing or transfer details, configuration, and post-compilation processing logic;

[0026] Compare the requirement information of the test item with the set requirement information to obtain the test difference information;

[0027] Comparing the test difference information with the test information of the test mode to obtain a test difference rate;

[0028] Determining whether the test difference rate is greater than or equal to a set test difference rate threshold;

[0029] If it is greater than or equal to, a first test matching degree is generated;

[0030] If it is less than, a second test match is generated.

[0031] Optionally, in the RTL automatic testing method of the RISC-V DSP chip described in the embodiment of the present application, a test program is selected based on a matching test mode to test the test item, and test data is generated in real time, specifically including:

[0032] Obtain a test mode, select a test program according to the test mode, and generate test steps based on the test program;

[0033] Test each test step of the test items according to the test steps;

[0034] Generate test data corresponding to each test step according to the test steps;

[0035] Integrate the test data corresponding to each test step to obtain the final test data.

[0036] Optionally, in the RTL automatic testing method of the RISC-V DSP chip described in the embodiment of the present application, adjusting the test mode based on the correction information specifically includes:

[0037] Acquire a test match degree, and compare the test match degree with a set match degree threshold, wherein the set match degree threshold includes a first match degree threshold and a second match degree threshold, and the first match degree threshold is less than the second match degree threshold;

[0038] If the test matching degree is greater than the first matching degree threshold and less than the second matching degree threshold, generating first correction information;

[0039] generating a first correction parameter based on the first correction information, and adjusting the test mode in a first manner based on the first correction parameter;

[0040] If the test matching degree threshold is greater than or equal to the second matching degree threshold, generating second correction information;

[0041] A second correction parameter is generated based on the second correction information, and the test pattern is adjusted in a second manner based on the second correction parameter.

[0042] In a second aspect, an embodiment of the present application provides an RTL automatic testing system for a RISC-V DSP chip, the system comprising: a memory and a processor, the memory comprising a program of an RTL automatic testing method for a RISC-V DSP chip, and the program of the RTL automatic testing method for a RISC-V DSP chip is executed by the processor to implement the following steps:

[0043] Establish an RTL test framework and generate multiple test modes based on the RTL test framework;

[0044] Generate a matching test program according to multiple test patterns, and form corresponding test steps based on the test program;

[0045] Acquire test items, analyze test requirement information of the test items, match test modes based on the test requirement information, and generate test matching degrees;

[0046] Determine whether the test matching degree is greater than or equal to a set matching degree threshold;

[0047] If it is greater than or equal to, then a test program is selected based on the matching test mode to test the test item and generate test data in real time;

[0048] If it is less than, correction information is generated and the test mode is adjusted based on the correction information.

[0049] Optionally, in the RTL automatic test system of the RISC-V DSP chip described in the embodiment of the present application, an RTL test framework is established, and multiple test modes are generated based on the RTL test framework, specifically including:

[0050] Construct an RTL test framework, wherein the RTL test framework includes interaction logic, test process control logic, data processing logic, and result aggregation logic;

[0051] Generate multiple interaction modes based on interaction logic, and generate multiple control modes based on test process control logic;

[0052] Generate multiple processing modes based on data processing logic, and generate multiple aggregation modes based on result aggregation logic;

[0053] The interactive mode, the control mode, the processing mode and the summary mode are randomly paired to obtain multiple paired combinations;

[0054] A test logic corresponding to each pairing combination is formed based on the plurality of pairing combinations, and a corresponding test mode is generated based on the test logic.

[0055] Optionally, in the RTL automatic test system of the RISC-V DSP chip described in the embodiment of the present application, a matching test program is generated according to multiple test modes, and corresponding test steps are formed based on the test program, specifically including:

[0056] Obtain the test logic corresponding to each test mode, establish a test program based on the test logic, and analyze the deviation rate between the test program and the test logic;

[0057] Determining whether the deviation rate is greater than or equal to a set deviation rate threshold;

[0058] If the deviation rate is greater than or equal to the set threshold, feedback information is generated, and the test program is adjusted based on the feedback information;

[0059] If it is less than the set deviation rate threshold, the test steps are established according to the current test procedure.

[0060] In a third aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium includes an RTL automatic testing method program for a RISC-V DSP chip. When the RTL automatic testing method program for a RISC-V DSP chip is executed by a processor, the steps of the RTL automatic testing method for a RISC-V DSP chip as described in any one of the above items are implemented.

[0061] As can be seen from the above, an RTL automatic testing method, system and medium for a RISC-V DSP chip provided in an embodiment of the present application establish an RTL test framework, generate multiple test modes based on the RTL test framework; generate matching test programs according to the multiple test modes, and form corresponding test steps based on the test programs; obtain test items, analyze the test requirement information of the test items, match the test modes based on the test requirement information, and generate a test matching degree; determine whether the test matching degree is greater than or equal to a set matching degree threshold; if greater than or equal to, select a test program based on the matching test mode to test the test item, and generate test data in real time; if less than, generate correction information, and adjust the test mode based on the correction information; establish multiple test programs according to the RTL test framework to meet the needs of different test items, match different test programs according to the needs of different test items, so as to accurately test the chip and improve the test effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0063] Figure 1 A flowchart of the RTL automatic testing method of the RISC-V DSP chip provided in the embodiment of the present application;

[0064] Figure 2 A flow chart of a test pattern generation method of an RTL automatic test method for a RISC-V DSP chip provided in an embodiment of the present application;

[0065] Figure 3 A flow chart of a method for obtaining test steps of an RTL automatic test method for a RISC-V DSP chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0066] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0067] It should be noted that similar reference numerals and letters represent similar items in the following drawings, so once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of this application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0068] Please refer to Figure 1 , Figure 1 The flowchart of the RTL automatic testing method of a RISC-V DSP chip in some embodiments of the present application. The RTL automatic testing method of the RISC-V DSP chip is used in a terminal device, and the RTL automatic testing method of the RISC-V DSP chip includes the following steps:

[0069] S101, establishing an RTL test framework, and generating multiple test patterns based on the RTL test framework;

[0070] S102, generating a matching test program according to a plurality of test patterns, and forming corresponding test steps based on the test program;

[0071] S103, acquiring a test item, analyzing test requirement information of the test item, matching a test mode based on the test requirement information, and generating a test matching degree;

[0072] S104, determining whether the test matching degree is greater than or equal to a set matching degree threshold;

[0073] S105, if it is greater than or equal to, select a test program based on the matching test mode to test the test item and generate test data in real time; if it is less than, generate correction information and adjust the test mode based on the correction information.

[0074] It should be noted that by analyzing the demand information of the test items and matching the corresponding test procedures, the test items can be accurately tested and the test effect can be improved.

[0075] Please refer to Figure 2 , Figure 2 This is a flow chart of a test pattern generation method of an RTL automatic test method for a RISC-V DSP chip in some embodiments of the present application. According to an embodiment of the present invention, an RTL test framework is established, and multiple test patterns are generated based on the RTL test framework, specifically including:

[0076] S201, constructing an RTL test framework, which includes interaction logic, test process control logic, data processing logic, and result aggregation logic;

[0077] S202, generating multiple interaction modes based on the interaction logic, and generating multiple control modes based on the test process control logic;

[0078] S203, generating multiple processing modes based on the data processing logic, and generating multiple aggregation modes based on the result aggregation logic;

[0079] S204, randomly pairing the interaction mode, the control mode, the processing mode, and the summary mode to obtain a plurality of pairing combinations;

[0080] S205 , forming a one-to-one corresponding test logic for the pairing combinations based on the multiple pairing combinations, and generating a corresponding test mode based on the test logic.

[0081] It should be noted that by establishing an RTL test framework and randomly combining the protection mode, control mode, processing mode and summary mode within the test framework, a variety of pairing combinations are formed. Different pairing combinations form different test logics, thereby obtaining different test modes.

[0082] Please refer to Figure 3 , Figure 3 This is a flow chart of a test step acquisition method of an RTL automatic test method for a RISC-V DSP chip in some embodiments of the present application. According to an embodiment of the present invention, a matching test program is generated according to multiple test modes, and corresponding test steps are formed based on the test program, specifically including:

[0083] S301, obtaining the test logic corresponding to each test mode, establishing a test program based on the test logic, and analyzing the deviation rate between the test program and the test logic;

[0084] S302, determining whether the deviation rate is greater than or equal to a set deviation rate threshold;

[0085] S303, if the deviation rate is greater than or equal to the set deviation rate threshold, generating feedback information, and adjusting the test program based on the feedback information;

[0086] S304: If the deviation rate is less than the set threshold, a test step is established according to the current test procedure.

[0087] It should be noted that by analyzing the deviation rate between the test logic and the test program, the test program is adjusted according to different deviation rates, thereby ensuring the accuracy of the test program.

[0088] According to an embodiment of the present invention, acquiring a test item, analyzing test requirement information of the test item, matching a test mode based on the test requirement information, and generating a test matching degree specifically include:

[0089] Get the test project, analyze the project's dependency path, required special variables, data processing or transfer details configuration, and post-compilation processing logic;

[0090] Analyze the test project's requirements based on the project's dependency paths, required special variables, data processing or transfer details, configuration, and post-compilation processing logic;

[0091] Compare the requirement information of the test item with the set requirement information to obtain the test difference information;

[0092] Compare the test difference information with the test information of the test pattern to obtain a test difference rate;

[0093] Determine whether the test difference rate is greater than or equal to a set test difference rate threshold;

[0094] If it is greater than or equal to, a first test matching degree is generated;

[0095] If it is less than, a second test match is generated.

[0096] It should be noted that, by analyzing the test items, different test items have different requirements, so the matching degree of the test program is analyzed according to different test items.

[0097] According to an embodiment of the present invention, a test program is selected based on a matching test mode to test a test item, and test data is generated in real time, specifically including:

[0098] Obtain a test mode, select a test program according to the test mode, and generate test steps based on the test program;

[0099] Test each test step of the test items according to the test steps;

[0100] Generate test data corresponding to each test step according to the test steps;

[0101] Integrate the test data corresponding to each test step to obtain the final test data.

[0102] It should be noted that by analyzing the test patterns, different test patterns match corresponding test programs, and different test programs perform different steps of testing on the test items, thereby generating test data corresponding to each test step, and analyzing the test data of each test step separately to obtain complete test data.

[0103] According to an embodiment of the present invention, adjusting the test mode based on the correction information specifically includes:

[0104] Acquire a test match degree, and compare the test match degree with a set match degree threshold, where the set match degree threshold includes a first match degree threshold and a second match degree threshold, and the first match degree threshold is less than the second match degree threshold;

[0105] If the test matching degree is greater than the first matching degree threshold and less than the second matching degree threshold, generating first correction information;

[0106] generating a first correction parameter based on the first correction information, and adjusting the test mode in a first manner based on the first correction parameter;

[0107] If the test matching degree threshold is greater than or equal to the second matching degree threshold, generating second correction information;

[0108] A second correction parameter is generated based on the second correction information, and the test pattern is adjusted in a second manner based on the second correction parameter.

[0109] It should be noted that by analyzing the test matching degree, different test matching degrees correspond to different correction parameters, so that the test mode is adjusted in different ways, thereby ensuring that the test mode meets the requirements of the test project and improving the test accuracy.

[0110] In a second aspect, an embodiment of the present application provides an RTL automatic testing system for a RISC-V DSP chip, the system comprising: a memory and a processor, the memory comprising a program of an RTL automatic testing method for a RISC-V DSP chip, and the program of the RTL automatic testing method for a RISC-V DSP chip is executed by the processor to implement the following steps:

[0111] Establish an RTL test framework and generate multiple test modes based on the RTL test framework;

[0112] Generate a matching test program according to multiple test patterns, and form corresponding test steps based on the test program;

[0113] Acquire test items, analyze test requirement information of the test items, match test modes based on the test requirement information, and generate test matching degrees;

[0114] Determine whether the test matching degree is greater than or equal to the set matching degree threshold;

[0115] If it is greater than or equal to, then a test program is selected based on the matching test mode to test the test item and generate test data in real time;

[0116] If it is less than, correction information is generated and the test mode is adjusted based on the correction information.

[0117] It should be noted that by analyzing the demand information of the test items and matching the corresponding test procedures, the test items can be accurately tested and the test effect can be improved.

[0118] According to an embodiment of the present invention, an RTL test framework is established, and multiple test modes are generated based on the RTL test framework, specifically including:

[0119] Build the RTL test framework, which includes interaction logic, test process control logic, data processing logic, and result summary logic;

[0120] Generate multiple interaction modes based on interaction logic, and generate multiple control modes based on test process control logic;

[0121] Generate multiple processing modes based on data processing logic, and generate multiple aggregation modes based on result aggregation logic;

[0122] The interactive mode, the control mode, the processing mode and the summary mode are randomly paired to obtain multiple paired combinations;

[0123] A test logic corresponding to each pairing combination is formed based on the plurality of pairing combinations, and a corresponding test mode is generated based on the test logic.

[0124] It should be noted that by establishing an RTL test framework and randomly combining the protection mode, control mode, processing mode and summary mode within the test framework, a variety of pairing combinations are formed. Different pairing combinations form different test logics, thereby obtaining different test modes.

[0125] According to an embodiment of the present invention, a matching test program is generated according to a plurality of test modes, and corresponding test steps are formed based on the test program, specifically including:

[0126] Obtain the test logic corresponding to each test mode, establish a test program based on the test logic, and analyze the deviation rate between the test program and the test logic;

[0127] Determine whether the deviation rate is greater than or equal to the set deviation rate threshold;

[0128] If the deviation rate is greater than or equal to the set threshold, feedback information is generated, and the test program is adjusted based on the feedback information;

[0129] If it is less than the set deviation rate threshold, the test steps are established according to the current test procedure.

[0130] It should be noted that by analyzing the deviation rate between the test logic and the test program, the test program is adjusted according to different deviation rates, thereby ensuring the accuracy of the test program.

[0131] According to an embodiment of the present invention, acquiring a test item, analyzing test requirement information of the test item, matching a test mode based on the test requirement information, and generating a test matching degree specifically include:

[0132] Get the test project, analyze the project's dependency path, required special variables, data processing or transfer details configuration, and post-compilation processing logic;

[0133] Analyze the test project's requirements based on the project's dependency paths, required special variables, data processing or transfer details, configuration, and post-compilation processing logic;

[0134] Compare the requirement information of the test item with the set requirement information to obtain the test difference information;

[0135] Compare the test difference information with the test information of the test pattern to obtain a test difference rate;

[0136] Determine whether the test difference rate is greater than or equal to a set test difference rate threshold;

[0137] If it is greater than or equal to, a first test matching degree is generated;

[0138] If it is less than, a second test match is generated.

[0139] It should be noted that, by analyzing the test items, different test items have different requirements, so the matching degree of the test program is analyzed according to different test items.

[0140] According to an embodiment of the present invention, a test program is selected based on a matching test mode to test a test item, and test data is generated in real time, specifically including:

[0141] Obtain a test mode, select a test program according to the test mode, and generate test steps based on the test program;

[0142] Test each test step of the test items according to the test steps;

[0143] Generate test data corresponding to each test step according to the test steps;

[0144] Integrate the test data corresponding to each test step to obtain the final test data.

[0145] It should be noted that by analyzing the test patterns, different test patterns match corresponding test programs, and different test programs perform different steps of testing on the test items, thereby generating test data corresponding to each test step, and analyzing the test data of each test step separately to obtain complete test data.

[0146] According to an embodiment of the present invention, adjusting the test mode based on the correction information specifically includes:

[0147] Acquire a test match degree, and compare the test match degree with a set match degree threshold, where the set match degree threshold includes a first match degree threshold and a second match degree threshold, and the first match degree threshold is less than the second match degree threshold;

[0148] If the test matching degree is greater than the first matching degree threshold and less than the second matching degree threshold, generating first correction information;

[0149] generating a first correction parameter based on the first correction information, and adjusting the test mode in a first manner based on the first correction parameter;

[0150] If the test matching degree threshold is greater than or equal to the second matching degree threshold, generating second correction information;

[0151] A second correction parameter is generated based on the second correction information, and the test pattern is adjusted in a second manner based on the second correction parameter.

[0152] It should be noted that by analyzing the test matching degree, different test matching degrees correspond to different correction parameters, so that the test mode is adjusted in different ways, thereby ensuring that the test mode meets the requirements of the test project and improving the test accuracy.

[0153] A third aspect of the present invention provides a computer-readable storage medium, which includes an RTL automatic testing method program for a RISC-V DSP chip. When the RTL automatic testing method program for a RISC-V DSP chip is executed by a processor, the steps of the RTL automatic testing method for a RISC-V DSP chip as described in any of the above items are implemented.

[0154] The present invention discloses an RTL automatic testing method, system and medium for a RISC-V DSP chip. The method includes establishing an RTL testing framework, generating multiple test modes based on the RTL testing framework; generating a matching test program according to the multiple test modes, and forming corresponding test steps based on the test program; acquiring a test item, analyzing test requirement information of the test item, matching the test mode based on the test requirement information, and generating a test matching degree; judging whether the test matching degree is greater than or equal to a set matching degree threshold; if greater than or equal to, selecting a test program based on the matching test mode to test the test item, and generating test data in real time; if less than, generating correction information, and adjusting the test mode based on the correction information; establishing multiple test programs according to the RTL testing framework to meet the requirements of different test items, matching different test programs according to the requirements of different test items, thereby accurately testing the chip and improving the test effect.

[0155] In the several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical, mechanical or other forms.

[0156] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed on multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0157] In addition, all functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0158] Those skilled in the art can understand that: all or part of the steps of implementing the above method embodiments can be completed by hardware related to program instructions, the aforementioned program can be stored in a readable storage medium, and when the program is executed, it executes the steps of the above method embodiments; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), disks or optical disks, and other media that can store program codes.

[0159] Or, if the above-mentioned integrated unit of the present invention is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a readable storage medium. Based on this understanding, the technical solution of the embodiment of the present invention can be essentially or partly reflected in the form of a software product that contributes to the prior art. The software product is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROM, RAM, magnetic disks or optical disks.

Claims

1. An RTL automatic testing method for a RISC-V DSP chip, characterized in that: include: Establish an RTL test framework and generate multiple test modes based on the RTL test framework; Generate a matching test program according to multiple test patterns, and form corresponding test steps based on the test program; Acquire test items, analyze test requirement information of the test items, match test modes based on the test requirement information, and generate test matching degrees; Determine whether the test matching degree is greater than or equal to a set matching degree threshold; If it is greater than or equal to, then a test program is selected based on the matching test mode to test the test item and generate test data in real time; If it is less than, correction information is generated and the test mode is adjusted based on the correction information.

2. The RTL automatic testing method of the RISC-V DSP chip according to claim 1, characterized in that: Establish an RTL test framework and generate multiple test modes based on the RTL test framework, including: Construct an RTL test framework, wherein the RTL test framework includes interaction logic, test process control logic, data processing logic, and result aggregation logic; Generate multiple interaction modes based on interaction logic, and generate multiple control modes based on test process control logic; Generate multiple processing modes based on data processing logic, and generate multiple aggregation modes based on result aggregation logic; The interactive mode, the control mode, the processing mode and the summary mode are randomly paired to obtain multiple paired combinations; A test logic corresponding to each pairing combination is formed based on the plurality of pairing combinations, and a corresponding test mode is generated based on the test logic.

3. The RTL automatic testing method of the RISC-V DSP chip according to claim 2, characterized in that: Generate a matching test program according to multiple test patterns, and form corresponding test steps based on the test program, specifically including: Obtain the test logic corresponding to each test mode, establish a test program based on the test logic, and analyze the deviation rate between the test program and the test logic; Determining whether the deviation rate is greater than or equal to a set deviation rate threshold; If the deviation rate is greater than or equal to the set threshold, feedback information is generated, and the test program is adjusted based on the feedback information; If it is less than the set deviation rate threshold, the test steps are established according to the current test procedure.

4. The RTL automatic testing method of the RISC-V DSP chip according to claim 3, characterized in that: Obtain test items, analyze test requirement information of test items, match test modes based on test requirement information, and generate test matching degree, including: Get the test project, analyze the project's dependency path, required special variables, data processing or transfer details configuration, and post-compilation processing logic; Analyze the test project's requirements based on the project's dependency paths, required special variables, data processing or transfer details, configuration, and post-compilation processing logic; Compare the requirement information of the test item with the set requirement information to obtain the test difference information; Comparing the test difference information with the test information of the test mode to obtain a test difference rate; Determining whether the test difference rate is greater than or equal to a set test difference rate threshold; If it is greater than or equal to, a first test matching degree is generated; If it is less than, a second test match is generated.

5. The RTL automatic testing method of the RISC-V DSP chip according to claim 1, characterized in that: Select the test program based on the matching test mode to test the test items and generate test data in real time, including: Obtain a test mode, select a test program according to the test mode, and generate test steps based on the test program; Test each test step of the test items according to the test steps; Generate test data corresponding to each test step according to the test steps; Integrate the test data corresponding to each test step to obtain the final test data.

6. The RTL automatic testing method of the RISC-V DSP chip according to claim 5, characterized in that: Adjust the test mode based on the correction information, including: Acquire a test match degree, and compare the test match degree with a set match degree threshold, wherein the set match degree threshold includes a first match degree threshold and a second match degree threshold, and the first match degree threshold is less than the second match degree threshold; If the test matching degree is greater than the first matching degree threshold and less than the second matching degree threshold, generating first correction information; generating a first correction parameter based on the first correction information, and adjusting the test mode in a first manner based on the first correction parameter; If the test matching degree threshold is greater than or equal to the second matching degree threshold, generating second correction information; A second correction parameter is generated based on the second correction information, and the test pattern is adjusted in a second manner based on the second correction parameter.

7. An RTL automatic test system for a RISC-V DSP chip, characterized in that: The system includes: a memory and a processor, wherein the memory includes a program of an RTL automatic test method for a RISC-V DSP chip, and when the program of the RTL automatic test method for a RISC-V DSP chip is executed by the processor, the following steps are implemented: Establish an RTL test framework and generate multiple test modes based on the RTL test framework; Generate a matching test program according to multiple test patterns, and form corresponding test steps based on the test program; Acquire test items, analyze test requirement information of the test items, match test modes based on the test requirement information, and generate test matching degrees; Determine whether the test matching degree is greater than or equal to a set matching degree threshold; If it is greater than or equal to, then a test program is selected based on the matching test mode to test the test item and generate test data in real time; If it is less than, correction information is generated and the test mode is adjusted based on the correction information.

8. The RTL automatic test system of the RISC-V DSP chip according to claim 7, characterized in that: Establish an RTL test framework and generate multiple test modes based on the RTL test framework, including: Construct an RTL test framework, wherein the RTL test framework includes interaction logic, test process control logic, data processing logic, and result aggregation logic; Generate multiple interaction modes based on interaction logic, and generate multiple control modes based on test process control logic; Generate multiple processing modes based on data processing logic, and generate multiple aggregation modes based on result aggregation logic; The interactive mode, the control mode, the processing mode and the summary mode are randomly paired to obtain multiple paired combinations; A test logic corresponding to each pairing combination is formed based on the plurality of pairing combinations, and a corresponding test mode is generated based on the test logic.

9. The RTL automatic test system of the RISC-V DSP chip according to claim 8, characterized in that: Generate a matching test program according to multiple test patterns, and form corresponding test steps based on the test program, specifically including: Obtain the test logic corresponding to each test mode, establish a test program based on the test logic, and analyze the deviation rate between the test program and the test logic; Determining whether the deviation rate is greater than or equal to a set deviation rate threshold; If the deviation rate is greater than or equal to the set threshold, feedback information is generated, and the test program is adjusted based on the feedback information; If it is less than the set deviation rate threshold, the test steps are established according to the current test procedure.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium includes an RTL automatic testing method program for a RISC-V DSP chip. When the RTL automatic testing method program for a RISC-V DSP chip is executed by a processor, the steps of the RTL automatic testing method for a RISC-V DSP chip as described in any one of claims 1 to 6 are implemented.

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