A method and system for generating circuit board design drawings

Abstract

This invention relates to the field of circuit board design data processing technology, and more particularly to a method and system for generating circuit board design diagrams. The method includes the following steps: acquiring circuit board design requirement information; performing semantic analysis on the circuit board design requirement information to generate design requirement semantic data; extracting circuit board design features from the design requirement semantic data to obtain circuit board design feature information; and identifying circuit board performance requirements from the circuit board design feature information to generate circuit board performance requirement data. This invention utilizes data processing technology, pattern recognition technology, 3D mapping technology, and deep learning technology to solve the problems of interlayer alignment and interlayer interconnection in multilayer board design; and optimizes and adjusts the impedance discontinuity characteristics caused by vias, thereby ensuring the stability and reliability of the generated circuit board design diagram.

Description

Technical Field

[0001] This invention relates to the field of circuit board design data processing technology, and in particular to a method and system for generating circuit board design diagrams. Background Technology

[0002] Early circuit board design technology utilized metal foil cut into conductors and achieved electrical interconnection between different layers by setting vias at the intersections of the lines. The development of circuit board design software has progressed from manual drawing to automated wiring techniques, then to split-type design, and finally to 3D design. Modern circuit board design software possesses comprehensive tools for design, source code control, simulation, and output, greatly improving design efficiency and accuracy. The generation of modern circuit board designs typically involves first drawing a circuit diagram and then converting it into a circuit board design. However, with the increasing number of components and the complexity of signal lines, existing technologies in multilayer board design face technical challenges related to interlayer alignment and interconnection. Vias are used for interlayer connections in multilayer circuit boards, but improper design can lead to parasitic capacitance and inductance problems in signal transmission, affecting signal integrity and speed. Furthermore, the presence of vias can cause impedance discontinuities, resulting in signal reflection and delay. Summary of the Invention

[0003] Therefore, it is necessary to provide a method and system for generating circuit board design diagrams to solve at least one of the above-mentioned technical problems.

[0004] To achieve the above objective, a method for generating circuit board design diagrams is provided, the method comprising the following steps:

[0005] Step S1: Obtain circuit board design requirement information; perform semantic analysis on the circuit board design requirement information to generate design requirement semantic data; extract circuit board design features from the design requirement semantic data to obtain circuit board design feature information; identify circuit board performance requirements from the circuit board design feature information to generate circuit board performance requirement data.

[0006] Step S2: Identify circuit board components based on circuit board design feature information to obtain circuit board component data; perform component correlation analysis on circuit board component data to obtain component correlation data; and perform circuit board interlayer structure detection based on component correlation data to obtain circuit board interlayer structure information.

[0007] Step S3: Analyze the interlayer interconnection requirements of the circuit board based on the circuit board performance requirements data, and generate interlayer interconnection requirement data; generate circuit board hole positions based on the circuit board design feature information based on the interlayer interconnection requirement data, and obtain circuit board hole position data; perform preliminary simulation of interlayer interconnection based on the circuit board hole position data, and obtain preliminary simulation data of interlayer interconnection.

[0008] Step S4: Perform impedance continuity detection on the circuit board via location area of ​​the preliminary interlayer interconnection simulation data to obtain circuit board impedance continuity data; adjust the circuit board via location data based on the circuit board impedance continuity data to generate circuit board via location adjustment data; identify the degree of interlayer alignment on the circuit board based on the preliminary interlayer interconnection simulation data to obtain the degree of interlayer registration; optimize the interlayer registration of the preliminary interlayer interconnection simulation data based on the degree of interlayer registration to generate optimized interlayer registration data.

[0009] Step S5: Based on the circuit board hole position adjustment data and interlayer registration optimization data, optimize the interlayer interconnection of the preliminary simulation data to generate circuit board interlayer interconnection information; perform 3D image mapping of circuit board design on the interlayer interconnection information according to the circuit board design feature information to obtain the circuit board design drawing.

[0010] This invention acquires circuit board design requirement information and performs semantic analysis to accurately generate semantic data of design requirements, providing accurate foundational information for subsequent design. Feature extraction is performed on the semantic data of design requirements to clarify specific parameters and requirements of the design. Furthermore, circuit board performance requirements are identified to ensure the design meets expected performance standards. Component identification is performed on the circuit board design feature information, providing specific component information for the design. Component correlation analysis is performed on the circuit board component data to clarify the relationships between various components. Interlayer structure detection is performed based on the component correlation data, providing details of physical connections between layers. Interlayer interconnection requirements are analyzed based on the circuit board performance requirement data to clarify the electrical connection design of the circuit board. Circuit board via locations are generated based on the interlayer interconnection requirements data, providing precise location information for interlayer connections. Preliminary simulation of circuit board interlayer interconnections is performed, providing a preliminary preview of the interlayer connection effect for the design. Impedance continuity detection is performed on the via location area of ​​the preliminary interlayer interconnection simulation data to ensure signal transmission stability. By adjusting via location data using impedance continuity data, the signal transmission path is optimized. Interlayer alignment is identified in the preliminary simulation data of interlayer interconnections, providing a basis for precise interlayer alignment. The accuracy of interlayer connections is improved by optimizing the preliminary simulation data based on interlayer registration. Optimizing the preliminary simulation data based on PCB via adjustment data and interlayer registration optimization data optimizes the PCB interlayer interconnection information. Three-dimensional image mapping of the interlayer interconnection information based on PCB design features visually displays the PCB's three-dimensional structure, providing detailed visual references for subsequent PCB manufacturing and inspection. Therefore, this invention, through data processing technology, pattern recognition technology, 3D mapping technology, and deep learning technology, solves the interlayer alignment and interconnection problems in multilayer board design and optimizes the impedance discontinuity characteristics caused by vias, thereby ensuring the stability and reliability of the generated PCB design.

[0011] Preferably, step S2 includes the following steps:

[0012] Step S21: Identify the circuit board component types from the circuit board design feature information to obtain circuit board component type information; extract component parameter features from the circuit board component type information to obtain component parameter feature information; integrate the circuit board component type information and component parameter feature information to obtain circuit board component data.

[0013] Step S22: Locate the component connection nodes in the circuit board component data to obtain component connection node information; identify the connection paths between components based on the component connection node information to generate connection path information between components;

[0014] Step S23: Based on the component connection node information and the connection path information between components, identify the connection relationship between components in the circuit board component data to obtain component association data;

[0015] Step S24: Identify the inter-layer connection features of the circuit board based on the component association data to obtain the inter-layer connection information of the circuit board; divide the inter-layer connection information of the circuit board into functional module layers to generate functional module layer data of the circuit board; detect the inter-layer structure of the circuit board based on the functional module layer data of the circuit board to obtain the inter-layer structure information of the circuit board.

[0016] This invention identifies component types from circuit board design feature information, providing specific component classifications for design; extracts component parameter features, enabling detailed descriptions of component technical specifications; integrates circuit board component data, including component types and parameter features, providing data support for subsequent component layout and connection; locates component connection nodes, clarifying physical connection points between components; identifies connection paths between components, detailing electrical connection routes between components; identifies connection relationships between components based on component connection node information and connection path information, revealing the interconnection relationships between components and providing key information for understanding the entire circuit board's electrical network structure and optimizing design; identifies circuit board layer connection features based on component association data, clarifying the electrical connection methods between different layers; divides circuit board functional modules into modules with specific functions, facilitating management and optimization; and detects circuit board layer structure, providing detailed information on the physical connections between layers, which is crucial for ensuring the manufacturing quality and performance of the circuit board.

[0017] Preferably, step S3 includes the following steps:

[0018] Step S31: Extract the interlayer signal transmission rate requirements from the interlayer structure information of the circuit board based on the circuit board performance requirement data to obtain the interlayer signal transmission requirement parameters;

[0019] Step S32: Based on the circuit board performance requirement data, identify the power distribution efficiency requirements of the interlayer structure information of the circuit board to obtain the interlayer power distribution requirement parameters;

[0020] Step S33: Determine the interconnection density requirements of the interlayer structure information of the circuit board based on the circuit board performance requirement data, and obtain the interlayer interconnection density requirement parameters;

[0021] Step S34: Merge the inter-layer signal transmission requirement parameters, inter-layer power distribution requirement parameters, and inter-layer interconnection density requirement parameters into inter-layer interconnection requirement parameters to generate inter-layer interconnection requirement data;

[0022] Step S35: Based on the inter-layer interconnection requirement data, identify the circuit board hole distribution area using the circuit board design feature information to obtain circuit board hole distribution area data; perform hole coordinate positioning on the circuit board hole distribution area data to generate hole coordinate positioning data;

[0023] Step S36: Extract the hole size parameters of the circuit board based on the interlayer interconnection requirement data to obtain the hole size parameters; match the hole coordinate positioning data and the hole size parameters to obtain the circuit board hole position data.

[0024] Step S37: Perform preliminary simulation of interlayer interconnection of the circuit board based on the circuit board hole location data and circuit board design feature information to obtain preliminary simulation data of interlayer interconnection.

[0025] This invention extracts signal transmission rate requirements from interlayer structure information based on PCB performance requirement data, ensuring that the PCB design meets specific data transmission speed requirements. It also identifies power distribution efficiency requirements based on PCB performance requirement data, achieving efficient power distribution on the PCB and ensuring stable circuit operation and optimized power management. Furthermore, it determines interconnection density requirements from interlayer structure information using PCB performance requirement data, providing a clear design guide for PCB wiring density, ensuring more connections within limited space while maintaining design reliability. Finally, it integrates interlayer signal transmission requirements, interlayer power distribution requirements, and interlayer interconnection density requirements. By merging the parameters, a comprehensive requirement framework is provided for the interlayer interconnection design of the circuit board, ensuring the comprehensiveness and coordination of the design. Based on the interlayer interconnection requirement data, the hole distribution area is identified by the circuit board design feature information, providing the necessary position information for precise hole drilling. Based on the interlayer interconnection requirement data, the hole size parameters are extracted, providing accurate size and position information for the hole design on the circuit board, which is crucial for ensuring the accuracy of interlayer interconnection. The preliminary simulation of interlayer interconnection based on the circuit board hole location data and circuit board design feature information provides a preliminary simulation effect for the interlayer interconnection of the circuit board, enabling the verification of the feasibility and performance of the design before actual manufacturing.

[0026] Preferably, step S37 includes the following steps:

[0027] Step S371: Extract circuit board design parameters from circuit board design feature information to obtain circuit board design parameters; arrange circuit board components according to circuit board design parameters to generate circuit board component layout data; perform single-layer circuit board routing on circuit board component layout data to generate single-layer circuit board routing data.

[0028] Step S372: Based on the circuit board via location data, perform interlayer via connectivity simulation on the single-layer circuit board wiring data to obtain via connectivity simulation results; perform interlayer signal transmission path simulation on the via connectivity simulation results to obtain interlayer signal path simulation data.

[0029] Step S373: Perform interlayer interconnect density simulation based on interlayer signal path simulation data to generate interlayer interconnect density simulation data; evaluate the interlayer bonding degree of the interlayer interconnect density simulation data to obtain the interlayer bonding degree value;

[0030] Step S374: Perform preliminary simulation of interlayer interconnection of the circuit board based on the interlayer bonding degree value and the circuit board design feature information to obtain preliminary simulation data of interlayer interconnection.

[0031] This invention extracts design parameters from circuit board design feature information, providing precise guidance for component placement. Component placement based on these parameters ensures the rationality and functionality of the component layout. Single-layer circuit board routing based on component placement data provides detailed path planning for single-layer circuit connections. Inter-layer via connectivity simulation based on via location data verifies the accuracy of the via design. Inter-layer signal transmission path simulation based on the via connectivity simulation results provides a path for signal transmission between different layers. Path analysis ensures the continuity and reliability of signal transmission; interlayer interconnect density simulation based on interlayer signal path simulation data provides quantitative data for evaluating the wiring density of the circuit board; interlayer bonding degree evaluation based on interlayer interconnect density simulation data provides an evaluation standard for the tightness and integrity of interlayer connections, enabling optimization of interlayer connection design; preliminary simulation of interlayer interconnection of the circuit board based on interlayer bonding degree values ​​and circuit board design feature information provides a comprehensive simulation result for interlayer connections of the circuit board, enabling prediction and adjustment of the effects of interlayer connections before actual manufacturing, ensuring the quality and performance of the final product.

[0032] Preferably, step S4 includes the following steps:

[0033] Step S41: Identify the impedance characteristics of the preliminary simulation data of interlayer interconnection to obtain the circuit board impedance characteristic data; perform impedance continuity detection of the circuit board via area based on the circuit board impedance characteristic data to obtain the circuit board impedance continuity data.

[0034] Step S42: Adjust the circuit board hole position data based on the circuit board impedance continuity data to generate circuit board hole position adjustment data;

[0035] Step S43: Perform interlayer feature identification on the preliminary simulation data of interlayer interconnection to obtain interlayer interconnection feature data; perform interlayer alignment calculation on the interlayer interconnection feature data to generate interlayer alignment calculation values; perform interlayer bonding measurement on the interlayer interconnection feature data to generate interlayer bonding measurement values.

[0036] Step S44: Evaluate the interlayer alignment degree of the circuit board by combining the interlayer alignment measurement value and the interlayer bonding degree measurement value to obtain the interlayer registration degree of the circuit board.

[0037] Step S45: Optimize the interlayer registration of the preliminary simulation data of interlayer interconnection based on the interlayer registration degree of the circuit board, and generate optimized interlayer registration data.

[0038] This invention identifies the impedance characteristics of preliminary simulation data for interlayer interconnects, providing key parameters for signal integrity of the circuit board. Impedance continuity detection of the via locations based on this data ensures stable signal transmission in these areas, avoiding signal distortion and reflection. Adjusting via location data using the circuit board impedance continuity data optimizes the via design to meet impedance continuity requirements, improving signal transmission quality and overall circuit board performance. Interlayer feature identification of preliminary simulation data provides a detailed description of the accuracy of interlayer connections. Interlayer alignment and bonding measurements are also performed. The generation of values ​​provides a quantitative indicator for the precise alignment and bonding of interlayer connections, which is crucial to ensuring the reliability and stability of interlayer connections. Evaluating the interlayer alignment and bonding measurements provides a comprehensive assessment of the accuracy of interlayer connections. This helps identify and correct potential problems in interlayer connections, thereby improving the overall quality of the circuit board. Optimizing the preliminary simulation data of interlayer interconnects through the degree of interlayer registration improves the alignment accuracy of interlayer connections. This helps reduce errors in interlayer connections, improves the manufacturing precision and performance of the circuit board, and ensures that the final product meets design specifications and performance requirements.

[0039] Preferably, step S41 includes the following steps:

[0040] Step S411: Perform high-frequency signal path identification on the preliminary simulation data of interlayer interconnection to obtain high-frequency signal path data; extract impedance parameters from the high-frequency signal path data to obtain impedance parameter information;

[0041] Step S412: Identify the impedance characteristics of the circuit board by analyzing the impedance parameter information to obtain the impedance characteristic data of the circuit board; perform path impedance consistency verification on the impedance characteristic data of the circuit board to obtain the path impedance consistency verification result.

[0042] Step S413: Locate the impedance anomaly area based on the path impedance consistency verification result to obtain impedance anomaly area location data; compare the impedance anomaly area location data with the preset impedance value to obtain the impedance value comparison result.

[0043] Step S414: Measure the impedance continuity deviation of the impedance value comparison results to obtain continuity deviation measurement data; evaluate the impedance continuity of the continuity deviation measurement data to obtain circuit board impedance continuity data.

[0044] This invention identifies high-frequency signal paths from preliminary simulation data of inter-layer interconnects, providing precise path information for analyzing signal transmission characteristics; extracts impedance parameters from these path data, providing key parameters for evaluating the electrical characteristics of the signal paths; identifies circuit board impedance characteristics from the impedance parameter information, providing a detailed description of electrical performance for the design; verifies path impedance consistency, ensuring that the impedance design of the signal paths meets expected standards and guaranteeing signal integrity; locates impedance anomaly areas from the path impedance consistency verification results, accurately identifying problem areas in the design; compares these data with preset impedance values, providing a basis for identifying and correcting impedance deviations in the design; measures impedance continuity deviation from the impedance value comparison results, quantifying impedance inconsistencies; and evaluates impedance continuity from these data, providing an important reference for ensuring stable signal transmission on the circuit board, improving the performance and reliability of the circuit board.

[0045] Preferably, step S42 includes the following steps:

[0046] Step S421: Detect impedance continuity changes in the circuit board impedance continuity data to obtain impedance continuity change data; measure the abnormal change amount in the impedance continuity change data to generate the impedance abnormal change amount measurement value.

[0047] Step S422: Based on the measured value of impedance anomaly, map the hole position data of the circuit board to generate abnormal hole position mapping information; extract the hole position size parameters from the abnormal hole position mapping information to obtain the abnormal hole position size parameters; identify the hole position routing layout from the abnormal hole position mapping information to obtain the abnormal hole position routing data.

[0048] Step S423: Perform circuit board hole position dispersion adjustment on the abnormal hole position mapping information to obtain circuit board hole position adjustment data; reduce the size of the abnormal hole position size parameters to obtain hole size reduction parameters; re-layout the hole position routing pins on the abnormal hole position routing data to generate hole position routing pin layout data.

[0049] Step S424: Integrate the circuit board hole position adjustment data, hole size reduction parameters, and hole routing pin layout data into circuit board hole position adjustment data to obtain circuit board hole position adjustment data.

[0050] This invention detects changes in the impedance continuity data of circuit boards, revealing the impedance distribution on the circuit board; it measures abnormal changes in this data to accurately identify areas where impedance changes exceed expectations, which is crucial for maintaining signal integrity and circuit performance; and it maps the hole position data based on the measured values ​​of abnormal impedance changes, providing a basis for precise hole position adjustment. Extracting dimensional parameters from these mapping information optimizes the physical dimensions of the holes. Simultaneously, identifying the routing layout of the mapping information provides necessary information for adjusting the routing, ensuring smooth signal transmission. Dispersing and adjusting the hole positions of abnormally changed mapping information optimizes the hole layout and reduces impedance anomalies. Reducing the size parameters of abnormally changed holes reduces impedance discontinuities in the signal path. Rearranging the pins of abnormally changed hole routing data improves the signal transmission path and enhances the overall performance of the circuit board. Integrating the circuit board hole position adjustment data, hole size reduction parameters, and hole routing pin layout data provides a comprehensive adjustment scheme for the final hole design of the circuit board, ensuring that the circuit board achieves the expected electrical performance and mechanical precision during manufacturing, thereby improving product reliability and performance.

[0051] Preferably, step S45 includes the following steps:

[0052] Step S451: Quantify the registration deviation of the interlayer registration degree of the circuit board to generate registration deviation quantification data; identify the interlayer registration deviation distribution of the registration deviation quantification data to obtain interlayer registration deviation distribution data.

[0053] Step S452: Detect the correction region of the interlayer registration deviation distribution data to generate interlayer registration correction region information; calculate the registration correction parameters of the interlayer registration correction region information to obtain the registration correction parameter values;

[0054] Step S453: Perform inter-layer interconnection angle correction on the inter-layer interconnection feature data using the registration correction parameter values ​​to obtain interconnection angle correction data; adjust the inter-layer interconnection displacement based on the interconnection angle correction data to obtain interconnection displacement adjustment data;

[0055] Step S454: Adjust the inter-layer interconnection structure of the preliminary simulation data using the interconnection displacement adjustment data to obtain interconnection structure adjustment data; optimize the inter-layer registration of the preliminary simulation data using the interconnection structure adjustment data to generate optimized inter-layer registration data.

[0056] This invention quantifies the registration deviation of interlayer registration on circuit boards, providing a numerical measure of the accuracy of interlayer alignment; identifies the distribution of interlayer registration deviation, revealing the specific distribution of registration deviation between layers; detects correction areas based on the interlayer registration deviation distribution data, clarifying the specific areas requiring correction; calculates registration correction parameters, providing precise correction guidance for these areas, ensuring the accuracy of interlayer alignment; corrects the angle of interlayer interconnect feature data using registration correction parameter values, ensuring that the angle of interlayer connections meets design requirements; adjusts the interlayer interconnect displacement based on interconnect angle correction data, optimizing the position of interlayer connections and improving connection accuracy; adjusts the structure of preliminary interlayer interconnect simulation data using interconnect displacement adjustment data, improving the physical connection structure between layers; and optimizes interlayer registration based on interconnect structure adjustment data, further improving the accuracy of interlayer alignment and ensuring the high performance and reliability of the circuit board.

[0057] Preferably, step S5 includes the following steps:

[0058] Step S51: Verify the hole position adjustment of the preliminary simulation data of interlayer interconnection using the circuit board hole position adjustment data to obtain hole position adjustment verification data; verify the interlayer registration optimization of the preliminary simulation data of interlayer interconnection using the interlayer registration optimization data to obtain interlayer registration optimization verification data.

[0059] Step S52: Evaluate the interlayer adjustment verification results of the circuit board based on the hole position adjustment verification data and the interlayer registration optimization verification data, and generate the interlayer adjustment verification results of the circuit board; optimize the interlayer interconnection of the circuit board based on the preliminary simulation data of the interlayer interconnection based on the interlayer adjustment verification results, and generate the interlayer interconnection information of the circuit board.

[0060] Step S53: Based on the circuit board design feature information, perform inter-layer design parameter spatial coordinate matching on the inter-layer interconnection information of the circuit board to generate inter-layer design coordinate matching data; map the inter-layer design coordinate matching data to the three-dimensional data of the circuit board design to obtain the three-dimensional spatial mapping data of the circuit board.

[0061] Step S54: Perform 3D image synthesis on the 3D spatial mapping data of the circuit board to obtain a 3D design image of the circuit board; enhance the image details of the 3D design image of the circuit board to generate a circuit board design drawing.

[0062] This invention verifies the accuracy of hole position adjustments in preliminary simulation data of interlayer interconnects using circuit board hole position adjustment data; it also verifies the accuracy of interlayer registration by using interlayer registration optimization data. These two verification steps provide data support for subsequent interlayer interconnect optimization. The evaluation of the circuit board interlayer adjustment verification results based on the hole position adjustment verification data and the interlayer registration optimization verification data provides a comprehensive assessment for interlayer interconnect optimization. Based on this verification result, the optimization of circuit board interlayer interconnects using preliminary simulation data further improves the interlayer interconnection performance. The system ensures the performance and reliability of inter-layer interconnections; it matches the spatial coordinates of inter-layer interconnection information based on the circuit board design features, providing a coordinate basis for accurate 3D design; it maps these matched data to 3D data of the circuit board design, providing detailed spatial information for subsequent 3D image synthesis; it synthesizes 3D images from the 3D spatial mapping data of the circuit board, which can intuitively display the 3D structure of the circuit board; it enhances the image details of the 3D design image of the circuit board, and the generated circuit board design drawing provides clear and detailed visual data for design review, manufacturing and quality control, ensuring the accurate communication and implementation of the design.

[0063] This specification provides a system for generating circuit board design diagrams, used to execute the above-described method for generating circuit board design diagrams. The system for generating circuit board design diagrams includes:

[0064] The circuit board design data acquisition module is used to acquire circuit board design requirement information; perform semantic analysis on the circuit board design requirement information to generate design requirement semantic data; extract circuit board design features from the design requirement semantic data to obtain circuit board design feature information; and identify circuit board performance requirements from the circuit board design feature information to generate circuit board performance requirement data.

[0065] The PCB interlayer structure analysis module is used to identify PCB components based on PCB design feature information to obtain PCB component data; perform component correlation analysis on PCB component data to obtain component correlation data; and perform PCB interlayer structure detection based on component correlation data to obtain PCB interlayer structure information.

[0066] The circuit board interlayer interconnection simulation module is used to perform interlayer interconnection requirement analysis on the interlayer structure information of the circuit board based on the circuit board performance requirement data, and generate interlayer interconnection requirement data; based on the interlayer interconnection requirement data, generate circuit board hole positions based on the circuit board design feature information, and obtain circuit board hole position data; and perform preliminary simulation of interlayer interconnection of the circuit board based on the circuit board hole position data, and obtain preliminary simulation data of interlayer interconnection.

[0067] The circuit board interlayer interconnection optimization and adjustment module is used to detect the impedance continuity of the circuit board via locations in the preliminary simulation data of interlayer interconnection, thereby obtaining circuit board impedance continuity data; adjust the circuit board via locations using the circuit board impedance continuity data, thereby generating circuit board via location adjustment data; identify the degree of interlayer alignment of the circuit board in the preliminary simulation data of interlayer interconnection, thereby obtaining the degree of interlayer registration; and optimize the interlayer registration of the preliminary simulation data of interlayer interconnection based on the degree of interlayer registration, thereby generating optimized interlayer registration data.

[0068] The circuit board design drawing generation module is used to optimize the interlayer interconnection of the circuit board based on the circuit board hole position adjustment data and interlayer registration optimization data, and generate the interlayer interconnection information of the circuit board; and to perform three-dimensional image mapping of the interlayer interconnection information of the circuit board based on the circuit board design feature information to obtain the circuit board design drawing.

[0069] This invention utilizes a PCB design data acquisition module to obtain PCB design requirement information and perform semantic analysis, accurately generating semantic data for design requirements. This provides accurate foundational information for subsequent design. Feature extraction is performed on the semantic data to clarify specific parameters and requirements of the design. Furthermore, PCB performance requirements are identified to ensure the design meets expected performance standards. A PCB interlayer structure analysis module identifies components based on PCB design features, providing specific component information for the design. Component correlation analysis is performed on the component data to clarify the relationships between various components. Interlayer structure detection is conducted based on the component correlation data, providing details of physical connections between layers. A PCB interlayer interconnection simulation module analyzes interlayer interconnection requirements based on PCB performance requirement data, clarifying the electrical connection design of the PCB. Through-hole generation is performed based on the interlayer interconnection requirements data, providing precise location information for interlayer connections. Preliminary simulation of PCB interlayer interconnections provides a preliminary preview of the interlayer connection effect for the design. The circuit board interlayer interconnection optimization and adjustment module performs impedance continuity detection on the via locations in the preliminary simulation data of interlayer interconnections, ensuring the stability of signal transmission. By adjusting the via location data based on impedance continuity data, the signal transmission path is optimized. The interlayer alignment degree is identified in the preliminary simulation data of interlayer interconnections, providing a basis for precise interlayer alignment. The accuracy of interlayer connections is improved by optimizing the preliminary simulation data based on the interlayer registration degree. The circuit board design drawing generation module optimizes the preliminary simulation data based on the circuit board via location adjustment data and interlayer registration optimization data, thus optimizing the circuit board interlayer interconnection information. Three-dimensional image mapping of the interlayer interconnection information based on circuit board design feature information provides a visual representation of the circuit board's three-dimensional structure, offering detailed visual references for subsequent circuit board manufacturing and inspection. Therefore, this invention, through data processing technology, pattern recognition technology, three-dimensional mapping technology, and deep learning technology, solves the problems of interlayer alignment and interlayer interconnection in multilayer board design; and optimizes and adjusts the impedance discontinuity characteristics caused by vias, thereby ensuring the stability and reliability of the generated circuit board design drawing. Attached Figure Description

[0070] Figure 1 This is a flowchart illustrating the steps of a method for generating circuit board design drawings.

[0071] Figure 2 for Figure 1 A detailed flowchart illustrating the implementation steps of step S2.

[0072] Figure 3 for Figure 1 A detailed flowchart illustrating the implementation steps of step S5.

[0073] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0074] The technical method of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0075] Furthermore, the accompanying drawings are merely illustrative of the invention and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor methods and / or microcontroller methods.

[0076] It should be understood that although the terms "first," "second," etc., may be used herein to describe various units, these units should not be limited by these terms. These terms are used merely to distinguish one unit from another. For example, without departing from the scope of the exemplary embodiments, a first unit may be referred to as a second unit, and similarly, a second unit may be referred to as a first unit. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0077] To achieve the above objectives, please refer to Figures 1 to 3 A method for generating circuit board design drawings, the method comprising the following steps:

[0078] Step S1: Obtain circuit board design requirement information; perform semantic analysis on the circuit board design requirement information to generate design requirement semantic data; extract circuit board design features from the design requirement semantic data to obtain circuit board design feature information; identify circuit board performance requirements from the circuit board design feature information to generate circuit board performance requirement data.

[0079] Step S2: Identify circuit board components based on circuit board design feature information to obtain circuit board component data; perform component correlation analysis on circuit board component data to obtain component correlation data; and perform circuit board interlayer structure detection based on component correlation data to obtain circuit board interlayer structure information.

[0080] Step S3: Analyze the interlayer interconnection requirements of the circuit board based on the circuit board performance requirements data, and generate interlayer interconnection requirement data; generate circuit board hole positions based on the circuit board design feature information based on the interlayer interconnection requirement data, and obtain circuit board hole position data; perform preliminary simulation of interlayer interconnection based on the circuit board hole position data, and obtain preliminary simulation data of interlayer interconnection.

[0081] Step S4: Perform impedance continuity detection on the circuit board via location area of ​​the preliminary interlayer interconnection simulation data to obtain circuit board impedance continuity data; adjust the circuit board via location data based on the circuit board impedance continuity data to generate circuit board via location adjustment data; identify the degree of interlayer alignment on the circuit board based on the preliminary interlayer interconnection simulation data to obtain the degree of interlayer registration; optimize the interlayer registration of the preliminary interlayer interconnection simulation data based on the degree of interlayer registration to generate optimized interlayer registration data.

[0082] Step S5: Based on the circuit board hole position adjustment data and interlayer registration optimization data, optimize the interlayer interconnection of the preliminary simulation data to generate circuit board interlayer interconnection information; perform 3D image mapping of circuit board design on the interlayer interconnection information according to the circuit board design feature information to obtain the circuit board design drawing.

[0083] This invention acquires circuit board design requirement information and performs semantic analysis to accurately generate semantic data of design requirements, providing accurate foundational information for subsequent design. Feature extraction is performed on the semantic data of design requirements to clarify specific parameters and requirements of the design. Furthermore, circuit board performance requirements are identified to ensure the design meets expected performance standards. Component identification is performed on the circuit board design feature information, providing specific component information for the design. Component correlation analysis is performed on the circuit board component data to clarify the relationships between various components. Interlayer structure detection is performed based on the component correlation data, providing details of physical connections between layers. Interlayer interconnection requirements are analyzed based on the circuit board performance requirement data to clarify the electrical connection design of the circuit board. Circuit board via locations are generated based on the interlayer interconnection requirements data, providing precise location information for interlayer connections. Preliminary simulation of circuit board interlayer interconnections is performed, providing a preliminary preview of the interlayer connection effect for the design. Impedance continuity detection is performed on the via location area of ​​the preliminary interlayer interconnection simulation data to ensure signal transmission stability. By adjusting via location data using impedance continuity data, the signal transmission path is optimized. Interlayer alignment is identified in the preliminary simulation data of interlayer interconnections, providing a basis for precise interlayer alignment. The accuracy of interlayer connections is improved by optimizing the preliminary simulation data based on interlayer registration. Optimizing the preliminary simulation data based on PCB via adjustment data and interlayer registration optimization data optimizes the PCB interlayer interconnection information. Three-dimensional image mapping of the interlayer interconnection information based on PCB design features visually displays the PCB's three-dimensional structure, providing detailed visual references for subsequent PCB manufacturing and inspection. Therefore, this invention, through data processing technology, pattern recognition technology, 3D mapping technology, and deep learning technology, solves the interlayer alignment and interconnection problems in multilayer board design and optimizes the impedance discontinuity characteristics caused by vias, thereby ensuring the stability and reliability of the generated PCB design.

[0084] In this embodiment of the invention, reference is made to Figure 1 The diagram shown is a flowchart illustrating the steps of a method for generating circuit board design diagrams according to the present invention. In this example, the method for generating circuit board design diagrams includes the following steps:

[0085] Step S1: Obtain circuit board design requirement information; perform semantic analysis on the circuit board design requirement information to generate design requirement semantic data; extract circuit board design features from the design requirement semantic data to obtain circuit board design feature information; identify circuit board performance requirements from the circuit board design feature information to generate circuit board performance requirement data.

[0086] In this embodiment of the invention, basic parameters and performance requirements of the circuit board design are extracted from design documents and specifications. Specifically, key information such as board thickness, number of layers, wiring layer layout, and characteristic impedance values ​​are extracted. Natural language processing techniques, such as semantic role labeling and dependency parsing, are used to perform semantic analysis on the design requirements, generating semantic data of the design requirements. Specifically, a semantic model is constructed by identifying key terms and parameters in the design documents, converting textual information into structured data. Deep learning techniques, such as convolutional neural networks (CNNs), are used to analyze the circuit board design features. Specifically, by analyzing the circuit board's stack-up structure and signal line layout, performance requirements for signal integrity and electromagnetic compatibility (EMC) are identified. A CNN model is constructed, including convolutional layers, activation layers, pooling layers, and fully connected layers, to extract circuit board design features and identify performance requirements. Specifically, the CNN model is constructed using Python and Keras libraries, and model parameters are optimized through forward and backward propagation. The identified performance requirements are converted into specific performance parameters and test standards, and the impedance matching parameters of the signal lines are determined according to the circuit board's signal integrity requirements. According to EMC requirements, the shielding design and grounding strategy of the circuit board are determined, ultimately generating circuit board performance requirement data.

[0087] Step S2: Identify circuit board components based on circuit board design feature information to obtain circuit board component data; perform component correlation analysis on circuit board component data to obtain component correlation data; and perform circuit board interlayer structure detection based on component correlation data to obtain circuit board interlayer structure information.

[0088] In this embodiment of the invention, image recognition technology, such as YOLOv8, is used to process circuit board images and identify components in the images. Specifically, the circuit board design image is input into a trained YOLOv8 model. The model extracts features through convolutional layers and performs classification and recognition through subsequent fully connected layers, outputting the location and category information of the components. Taking a specific circuit board image as an example, the input image size is 1920x1080 pixels. The model identifies components such as resistors and capacitors in the image and outputs the bounding box coordinates and category label of each component. The recognition result includes 10 resistors, with bounding box coordinates of [x1, y1, x2, y2] and a category label of "Resistor". Association rule learning algorithms, such as the Apriori algorithm, are used to perform association analysis on component data. This algorithm mines association rules between components by analyzing the co-occurrence relationships between them. Based on the identified component data, association rules between components are constructed. Specifically, the power management module where resistors and capacitors are located is analyzed, thereby generating the association rule "if there is a resistor in the circuit, then there will be a capacitor in the circuit." Interlayer misalignment detection technology, such as X-ray inspection, is used to inspect the interlayer structure of the circuit board. Specifically, X-ray imaging technology is used to observe the interlayer misalignment inside the circuit board. Taking a multilayer circuit board as an example, X-ray equipment is used to inspect the circuit board and obtain image data of the interlayer misalignment state. Through image analysis, the size, direction, and state of the interlayer misalignment are determined, and this information is recorded as interlayer structure information to obtain the interlayer structure information of the circuit board.

[0089] Step S3: Analyze the interlayer interconnection requirements of the circuit board based on the circuit board performance requirements data, and generate interlayer interconnection requirement data; generate circuit board hole positions based on the circuit board design feature information based on the interlayer interconnection requirement data, and obtain circuit board hole position data; perform preliminary simulation of interlayer interconnection based on the circuit board hole position data, and obtain preliminary simulation data of interlayer interconnection.

[0090] In this embodiment of the invention, circuit simulation software is used to analyze interlayer interconnection requirements. Specifically, the HFSS module in ANSYS software is used. Based on the circuit board performance requirements data, such as signal transmission rate and power distribution, electromagnetic field simulation is performed on the interlayer structure to generate interlayer interconnection requirement data. Taking a four-layer circuit board as an example, the performance requirements data specifies a particular signal transmission rate and power distribution. Through simulation analysis, it is determined that a blind via needs to be added between the second and third layers to meet signal integrity requirements, thereby generating interlayer interconnection requirement data containing the location and size of the blind via. The via locations are generated using CAD software, specifically based on the interlayer interconnection requirement data, in Altium... In the Designer, the precise location and size of the blind vias are determined, generating via location data; for example, the blind via location is (X: 50mil, Y: 00mil), the diameter is 10mil, and the depth is 40mil. Interlayer interconnection simulation is then performed using 3D modeling software, such as SolidWorks. Based on the via location data, 3D modeling and preliminary simulation of the PCB interlayer interconnection are conducted. Specifically, in SolidWorks, a 3D model of a four-layer PCB is constructed based on the via location data, and interlayer interconnection is simulated. The simulation results show that the blind via location and size meet the design requirements, and there are no short circuits or open circuits in the interlayer connections. Finally, preliminary simulation data for interlayer interconnection is generated.

[0091] Step S4: Perform impedance continuity detection on the circuit board via location area of ​​the preliminary interlayer interconnection simulation data to obtain circuit board impedance continuity data; adjust the circuit board via location data based on the circuit board impedance continuity data to generate circuit board via location adjustment data; identify the degree of interlayer alignment on the circuit board based on the preliminary interlayer interconnection simulation data to obtain the degree of interlayer registration; optimize the interlayer registration of the preliminary interlayer interconnection simulation data based on the degree of interlayer registration to generate optimized interlayer registration data.

[0092] In this embodiment of the invention, the impedance continuity of the via region on a circuit board is detected using the Time Domain Reflectometry (TDR) method. Specifically, a step signal is sent and the reflected signal is detected to assess the degree of impedance change in the link. On the TDR device, the via region of the circuit board under test is connected to the test equipment, and a 50-ohm step signal is sent. The reflected signal is recorded and compared with the reflection generated by a standard impedance to obtain the impedance change. For example, if the test results show an impedance discontinuity at via region X1 with a change of 10 ohms, the via location data is adjusted using CAD software based on the impedance continuity data obtained from the TDR. For example, in Altium Designer, the size or position of the via is adjusted according to the location of the impedance discontinuity to eliminate it. For instance, based on the impedance discontinuity data, the diameter of via X1 is increased from 10 mil to 12 mil, thereby generating new via adjustment data, specifically including the adjusted via size and position. Interlayer alignment testing equipment, such as through-hole testing equipment, is used to determine the degree of interlayer alignment by detecting the continuity between the starting hole and each measuring hole. Multiple alignment testing devices are set up on the circuit board under test, each including inner and outer layer structures. The continuity between the starting hole and each measuring hole is detected through the through-hole to determine the interlayer offset. If the measured interlayer offset is 2 mils, it indicates a slight alignment deviation between layers. Based on the degree of interlayer alignment, the initial simulation data of the interlayer interconnection is optimized using 3D modeling software such as SolidWorks. Specifically, the position and angle of the layers are adjusted to improve the interlayer alignment. In SolidWorks, the interlayer interconnection simulation data is adjusted based on the interlayer offset data. For example, adjusting the position of the fourth layer relative to the third layer by 0.1 mm generates optimized interlayer registration data, which includes the adjusted interlayer position and angle information.

[0093] Step S5: Based on the circuit board hole position adjustment data and interlayer registration optimization data, optimize the interlayer interconnection of the preliminary simulation data to generate circuit board interlayer interconnection information; perform 3D image mapping of circuit board design on the interlayer interconnection information according to the circuit board design feature information to obtain the circuit board design drawing.

[0094] In this embodiment of the invention, Cadence Allegro software is used for interlayer interconnect optimization. Based on via position adjustment data and interlayer registration optimization data, the interlayer connections and via layout of the circuit board are adjusted. For example, the position of the vias is adjusted to ensure the integrity of signal transmission and reduce crosstalk. Specifically, in Cadence Allegro, for a four-layer PCB design, the position of via Hole1 is adjusted from (X:100mil, Y:200mil) to (X:105mil, Y:205mil) based on the via position adjustment data, and the alignment between layer 2 and layer 3 is adjusted based on the interlayer registration optimization data to ensure the accuracy of the interlayer connections. Through these adjustments, optimized interlayer interconnect information is generated, including updated via positions and interlayer connection details. Using SolidWorks software, 3D image mapping of circuit board designs is performed. Based on the circuit board design features and interlayer interconnection information, a 3D model of the circuit board is constructed. Specifically, in SolidWorks, the 2D design data of the circuit board is imported, and a 3D model is constructed based on the interlayer interconnection information. For example, for a four-layer PCB design, after importing the interlayer interconnection information, a 3D model containing all layers and vias is constructed. Through 3D image mapping technology, the internal structure and interlayer connections of the circuit board are intuitively displayed, and the final circuit board design drawing is generated. This includes showing the blind via connections between layer 1 and layer 4, and the buried via connections between layer 2 and layer 3.

[0095] As an example of the present invention, reference is made to Figure 2 As shown, in this example, step S2 includes:

[0096] Step S21: Identify the circuit board component types from the circuit board design feature information to obtain circuit board component type information; extract component parameter features from the circuit board component type information to obtain component parameter feature information; integrate the circuit board component type information and component parameter feature information to obtain circuit board component data.

[0097] Step S22: Locate the component connection nodes in the circuit board component data to obtain component connection node information; identify the connection paths between components based on the component connection node information to generate connection path information between components;

[0098] Step S23: Based on the component connection node information and the connection path information between components, identify the connection relationship between components in the circuit board component data to obtain component association data;

[0099] Step S24: Identify the inter-layer connection features of the circuit board based on the component association data to obtain the inter-layer connection information of the circuit board; divide the inter-layer connection information of the circuit board into functional module layers to generate functional module layer data of the circuit board; detect the inter-layer structure of the circuit board based on the functional module layer data of the circuit board to obtain the inter-layer structure information of the circuit board.

[0100] In this embodiment of the invention, a deep learning model, such as YOLOv8, is used for circuit board component type identification. Specifically, the model learns to identify different component shapes and features through training, achieving automatic classification and identification of circuit board design feature information. A two-dimensional convolutional neural network (2D-CNN) is used to automatically extract component parameter features, where the model's convolutional layers are used to automatically extract fault features, and the batch normalization layer is used to adjust the data distribution to reduce the impact of data distribution deviation. Component type information and parameter feature information are integrated to form complete circuit board component data. Specifically, image processing and natural language understanding technologies are used to automatically extract packaging parameters from electronic component data sheets and integrate component type and parameter feature information. Node positioning technology in wireless sensor networks is used to accurately locate component connection nodes. Specifically, algorithms are used to determine the accurate location of component connection nodes. Automatic identification technology, such as an electronic tag-based (RFID) identification system, is used to identify component connection node information and generate inter-component connection path information. The identifier identifies the electronic tags at the wire ends and sends the identification results to the acquisition device. The acquisition device is responsible for analyzing and processing the data and outputting the connection relationships, thereby obtaining the inter-component connection path information. By analyzing component connection node information and inter-component connection path information, the connection relationships between components are identified. Specifically, the identification results are analyzed and processed using acquisition equipment, and the connection relationships between each terminal and wire are output. A multi-layer circuit board (PCB) layer offset detection method is used to identify the connection characteristics between PCB layers, and corresponding detection loops are set up for each layer offset. Functional module layers are divided based on the PCB layer connection information. Specifically, by analyzing the inter-layer connection characteristics of the PCB, the PCB is divided into different functional module layers. PCB inter-layer structure detection technology is used to detect the PCB functional module layer data. Specifically, an automatic detection device is used to detect the PCB inter-layer alignment capability, thereby obtaining the PCB inter-layer structure information.

[0101] Preferably, step S3 includes the following steps:

[0102] Step S31: Extract the interlayer signal transmission rate requirements from the interlayer structure information of the circuit board based on the circuit board performance requirement data to obtain the interlayer signal transmission requirement parameters;

[0103] Step S32: Based on the circuit board performance requirement data, identify the power distribution efficiency requirements of the interlayer structure information of the circuit board to obtain the interlayer power distribution requirement parameters;

[0104] Step S33: Determine the interconnection density requirements of the interlayer structure information of the circuit board based on the circuit board performance requirement data, and obtain the interlayer interconnection density requirement parameters;

[0105] Step S34: Merge the inter-layer signal transmission requirement parameters, inter-layer power distribution requirement parameters, and inter-layer interconnection density requirement parameters into inter-layer interconnection requirement parameters to generate inter-layer interconnection requirement data;

[0106] Step S35: Based on the inter-layer interconnection requirement data, identify the circuit board hole distribution area using the circuit board design feature information to obtain circuit board hole distribution area data; perform hole coordinate positioning on the circuit board hole distribution area data to generate hole coordinate positioning data;

[0107] Step S36: Extract the hole size parameters of the circuit board based on the interlayer interconnection requirement data to obtain the hole size parameters; match the hole coordinate positioning data and the hole size parameters to obtain the circuit board hole position data.

[0108] Step S37: Perform preliminary simulation of interlayer interconnection of the circuit board based on the circuit board hole location data and circuit board design feature information to obtain preliminary simulation data of interlayer interconnection.

[0109] In this embodiment of the invention, electromagnetic field simulation software (such as ANSYS HFSS) is used to simulate the interlayer structure of the circuit board. Based on the dielectric constant and board material characteristics, the signal propagation delay in the circuit board traces is calculated. The calculation formula is as follows:

[0110]

[0111] Where t d L represents the signal transmission delay (in seconds); L represents the length of the trace (in meters).

[0112] v p The speed of signal propagation in a medium (unit: meters per second) is expressed by the following formula:

[0113]

[0114] Where c is the speed of light in a vacuum (approximately 3 × 10⁻⁶). 8 meters per second); ∈ r It is the relative permittivity of the dielectric material; the permittivity is a physical quantity that describes the material’s ability to store electrical energy. For FR4 material commonly used in circuit boards, its permittivity is between 4.2 and 4.4. This parameter can be obtained from the datasheet provided by the material supplier or through experimental measurement.

[0115] This study employs HDI (High-Density Interconnect) PCB technology to analyze the performance of the power distribution network and identify power distribution efficiency requirements. Specifically, HDI PCBs offer lower current density and more uniform power distribution, reducing power loss and improving overall energy efficiency. For a mobile device PCB, HDI technology is used to improve the uniformity and efficiency of the power distribution network and identify required power distribution efficiency parameters. Based on High-Density Interconnect (HDI) printed circuit technology, the wiring density and number of layers on the PCB are analyzed to determine interconnect density requirements. HDI boards offer advantages such as high-density wiring, high-frequency and high-speed operation, high conductivity, high insulation reliability, and low cost. For a high-performance computing device PCB, interconnect density requirements are determined to meet the demands of high-density wiring and high-frequency and high-speed operation. By comprehensively analyzing the signal transmission rate, power distribution efficiency, and interconnect density requirements, an inter-layer interconnection requirement dataset is generated. Using PCB design software (such as Cadence Allegro), the via distribution area is identified, and the optimal distribution area of ​​the vias is determined based on the interlayer interconnection requirements. Within the identified via distribution area, the via coordinates are precisely located. Based on the interlayer interconnection requirements, the via distribution area is identified in Cadence Allegro software, and the via coordinates are located to obtain the via coordinate positioning data. The via size parameters are extracted according to PCB via size standards (such as IPC-2221). The via coordinate positioning data is matched with the via size parameters to ensure that the position and size of each via meet the design requirements. A preliminary simulation of the PCB interlayer interconnection is performed using 3D electromagnetic field simulation software (such as ANSYS SIwave), and the performance of the interlayer interconnection is evaluated based on the via location data and design feature information. In ANSYS SIwave, a preliminary simulation of the interlayer interconnection is performed based on the via location data and PCB design feature information to obtain preliminary interlayer interconnection simulation data.

[0116] Preferably, step S37 includes the following steps:

[0117] Step S371: Extract circuit board design parameters from circuit board design feature information to obtain circuit board design parameters; arrange circuit board components according to circuit board design parameters to generate circuit board component layout data; perform single-layer circuit board routing on circuit board component layout data to generate single-layer circuit board routing data.

[0118] Step S372: Based on the circuit board via location data, perform interlayer via connectivity simulation on the single-layer circuit board wiring data to obtain via connectivity simulation results; perform interlayer signal transmission path simulation on the via connectivity simulation results to obtain interlayer signal path simulation data.

[0119] Step S373: Perform interlayer interconnect density simulation based on interlayer signal path simulation data to generate interlayer interconnect density simulation data; evaluate the interlayer bonding degree of the interlayer interconnect density simulation data to obtain the interlayer bonding degree value;

[0120] Step S374: Perform preliminary simulation of interlayer interconnection of the circuit board based on the interlayer bonding degree value and the circuit board design feature information to obtain preliminary simulation data of interlayer interconnection.

[0121] In this embodiment of the invention, CAD software (such as Altium Designer) is used to analyze the design features of the circuit board and extract design parameters, including board thickness, number of layers, trace width, and spacing. Based on the extracted design parameters, an algorithm (such as a genetic algorithm) is used to optimize the arrangement of components to reduce trace length and avoid signal interference. After the component arrangement is completed, a routing algorithm (such as a maze routing algorithm) is used to route the single-layer circuit board and generate routing data. Electromagnetic field simulation software (such as ANSYS HFSS) is used to simulate the connectivity of vias to ensure that the connection between vias meets the design requirements. Based on the simulation results of the via connectivity, the signal transmission path between layers is further simulated to evaluate signal integrity. Based on the simulation data of the interlayer signal path, simulation software is used to simulate the interlayer interconnect density to evaluate the rationality and feasibility of the routing. The analysis of the interlayer interconnect density simulation data evaluates the degree of bonding between layers to ensure the reliability of the interlayer connection. Using the interlayer bonding value and the circuit board design features, a preliminary simulation of the interlayer interconnect is performed to generate simulation data, providing a reference for subsequent circuit board manufacturing.

[0122] Preferably, step S4 includes the following steps:

[0123] Step S41: Identify the impedance characteristics of the preliminary simulation data of interlayer interconnection to obtain the circuit board impedance characteristic data; perform impedance continuity detection of the circuit board via area based on the circuit board impedance characteristic data to obtain the circuit board impedance continuity data.

[0124] Step S42: Adjust the circuit board hole position data based on the circuit board impedance continuity data to generate circuit board hole position adjustment data;

[0125] Step S43: Perform interlayer feature identification on the preliminary simulation data of interlayer interconnection to obtain interlayer interconnection feature data; perform interlayer alignment calculation on the interlayer interconnection feature data to generate interlayer alignment calculation values; perform interlayer bonding measurement on the interlayer interconnection feature data to generate interlayer bonding measurement values.

[0126] Step S44: Evaluate the interlayer alignment degree of the circuit board by combining the interlayer alignment measurement value and the interlayer bonding degree measurement value to obtain the interlayer registration degree of the circuit board.

[0127] Step S45: Optimize the interlayer registration of the preliminary simulation data of interlayer interconnection based on the interlayer registration degree of the circuit board, and generate optimized interlayer registration data.

[0128] In this embodiment of the invention, ANSYS HFSS software is used to perform three-dimensional full-wave electromagnetic field simulation to identify the impedance characteristics of the circuit board. Specifically, the characteristic impedance of the circuit board is calculated by simulating the propagation of electromagnetic waves in the circuit board structure. Based on the impedance characteristic data, the impedance continuity of the via region is further detected. Specifically, the electromagnetic field distribution in the via region is analyzed to ensure the stability and continuity of signal transmission. The via location data is adjusted according to the impedance continuity data to optimize impedance matching. Specifically, the precise positioning and size adjustment of the vias ensure the signal integrity of the circuit board. High-resolution X-ray imaging technology is used to identify interlayer interconnect features. Specifically, X-ray images are analyzed to extract... The geometric and alignment features of interlayer connections are analyzed. Alignment accuracy is evaluated by calculating the deviation values ​​of interlayer features based on interlayer feature data. An interlayer bonding integrity detection method is used to determine the bonding degree between layers, specifically by analyzing the change sequence of interlayer bonding features to evaluate bonding quality. The interlayer alignment degree of the circuit board is evaluated by combining the calculated values ​​of interlayer alignment degree and bonding degree. The interlayer alignment quality is determined by comprehensively analyzing the deviations of interlayer features and the changes in bonding features. Based on the evaluation results of the interlayer alignment degree, the preliminary simulation data of interlayer interconnects is optimized, specifically adjusting the geometric parameters of interlayer connections to improve interlayer alignment accuracy and bonding quality.

[0129] Preferably, step S41 includes the following steps:

[0130] Step S411: Perform high-frequency signal path identification on the preliminary simulation data of interlayer interconnection to obtain high-frequency signal path data; extract impedance parameters from the high-frequency signal path data to obtain impedance parameter information;

[0131] Step S412: Identify the impedance characteristics of the circuit board by analyzing the impedance parameter information to obtain the impedance characteristic data of the circuit board; perform path impedance consistency verification on the impedance characteristic data of the circuit board to obtain the path impedance consistency verification result.

[0132] Step S413: Locate the impedance anomaly area based on the path impedance consistency verification result to obtain impedance anomaly area location data; compare the impedance anomaly area location data with the preset impedance value to obtain the impedance value comparison result.

[0133] Step S414: Measure the impedance continuity deviation of the impedance value comparison results to obtain continuity deviation measurement data; evaluate the impedance continuity of the continuity deviation measurement data to obtain circuit board impedance continuity data.

[0134] In this embodiment of the invention, electromagnetic field simulation software (such as ANSYS HFSS) is used to analyze the preliminary simulation data of interlayer interconnection and identify high-frequency signal paths; high-frequency signal path data is extracted by simulating the propagation of electromagnetic waves in the circuit board structure. The specific steps include: building a circuit board model in HFSS, setting an appropriate simulation frequency, running the simulation, and extracting the signal path; using an impedance extraction tool (such as Polar SI9000) to extract impedance parameters on the identified high-frequency signal path; simulating the impedance parameter information of the signal path by setting ports and excitation signals, including characteristic impedance and transmission line impedance; using the impedance parameter information and circuit board design rules to identify the impedance characteristics of the circuit board; specifically comparing the actual impedance parameters with the design target impedance to ensure impedance matching; analyzing the circuit board impedance characteristic data to verify whether the impedance on the path is consistent; ensuring the impedance continuity on the signal path by comparing the impedance parameters of different segments; using a signal integrity analysis tool (such as Cadence Sigrity) to locate impedance anomaly areas based on the path impedance consistency verification results; specifically determining the specific location of the anomaly area by analyzing impedance discontinuities; comparing the impedance anomaly area location data with the preset impedance value, and determining the degree of impedance anomaly by comparing the actual impedance value with the design value. Before measuring impedance continuity deviation, a preset impedance continuity deviation value is set. This value is usually determined based on PCB design specifications and signal integrity requirements. For example, for a high-speed digital circuit, the preset impedance continuity deviation is set to ±5%. Impedance measurement is performed using the time-domain reflectometry (TDR) method. TDR assesses the degree of impedance variation in the link by sending a step signal with a fast rising edge to the circuit board under test and detecting the reflected signal. The impedance data obtained from the TDR measurement is compared with the preset impedance value to calculate the deviation between the actual impedance value and the preset value. The impedance value at each measurement point is recorded, and the percentage deviation from the preset value is calculated.

[0135] Preferably, step S42 includes the following steps:

[0136] Step S421: Detect impedance continuity changes in the circuit board impedance continuity data to obtain impedance continuity change data; measure the abnormal change amount in the impedance continuity change data to generate the impedance abnormal change amount measurement value.

[0137] Step S422: Based on the measured value of impedance anomaly, map the hole position data of the circuit board to generate abnormal hole position mapping information; extract the hole position size parameters from the abnormal hole position mapping information to obtain the abnormal hole position size parameters; identify the hole position routing layout from the abnormal hole position mapping information to obtain the abnormal hole position routing data.

[0138] Step S423: Perform circuit board hole position dispersion adjustment on the abnormal hole position mapping information to obtain circuit board hole position adjustment data; reduce the size of the abnormal hole position size parameters to obtain hole size reduction parameters; re-layout the hole position routing pins on the abnormal hole position routing data to generate hole position routing pin layout data.

[0139] Step S424: Integrate the circuit board hole position adjustment data, hole size reduction parameters, and hole routing pin layout data into circuit board hole position adjustment data to obtain circuit board hole position adjustment data.

[0140] In this embodiment of the invention, time-domain reflectometry (TDR) is used to detect the impedance continuity data of the circuit board. Specifically, TDR sends a step signal with a fast rising edge to the circuit board under test and detects the reflected signal to assess the degree of impedance change in the link. Based on the TDR detection results, the impedance continuity change data is analyzed, and an abnormal change is measured using an automatic balancing bridge method. By comparing the impedance values ​​at different test points, the impedance change is calculated, generating an abnormal impedance change measurement value. Image processing techniques, such as the Canny-Zernike time-subpixel edge detection method, are used to accurately map the hole positions, generating abnormal hole position mapping information. The least squares method is used to fit the hole positions. The process begins with obtaining hole size parameters from the edges. Image processing and pattern recognition techniques are used to identify the hole routing layout, resulting in data on abnormally changing hole routing. Based on this abnormal hole mapping information, computer-aided design (CAD) software is used to adjust the hole positions, generating circuit board hole position adjustment data. Then, based on the abnormally changing hole size parameters, CAD software is used to adjust the hole dimensions, achieving size reduction and generating hole size reduction parameters. Finally, based on the abnormally changing hole routing data, the hole routing pins are rearranged, generating hole routing pin layout data. Finally, by integrating the hole position adjustment data, hole size reduction parameters, and hole routing pin layout data using CAD software, circuit board hole adjustment data is obtained.

[0141] Preferably, step S45 includes the following steps:

[0142] Step S451: Quantify the registration deviation of the interlayer registration degree of the circuit board to generate registration deviation quantification data; identify the interlayer registration deviation distribution of the registration deviation quantification data to obtain interlayer registration deviation distribution data.

[0143] Step S452: Detect the correction region of the interlayer registration deviation distribution data to generate interlayer registration correction region information; calculate the registration correction parameters of the interlayer registration correction region information to obtain the registration correction parameter values;

[0144] Step S453: Perform inter-layer interconnection angle correction on the inter-layer interconnection feature data using the registration correction parameter values ​​to obtain interconnection angle correction data; adjust the inter-layer interconnection displacement based on the interconnection angle correction data to obtain interconnection displacement adjustment data;

[0145] Step S454: Adjust the inter-layer interconnection structure of the preliminary simulation data using the interconnection displacement adjustment data to obtain interconnection structure adjustment data; optimize the inter-layer registration of the preliminary simulation data using the interconnection structure adjustment data to generate optimized inter-layer registration data.

[0146] In this embodiment of the invention, image processing techniques, such as image registration methods, are used to quantitatively analyze the degree of interlayer registration on the circuit board. By comparing the differences between actual interlayer alignment and standard alignment, quantitative registration deviation data is generated. The interlayer alignment detection equipment and methods are used to analyze the quantitative registration deviation data, identify the distribution of interlayer registration deviations, and obtain interlayer registration deviation distribution data. Based on the interlayer registration deviation distribution data, the interlayer alignment detection equipment is used to detect correction areas, generating interlayer registration correction area information. A mathematical model, such as an affine transformation model, is used to process the interlayer registration correction area information. The process involves analyzing and calculating registration correction parameters. Using these parameters, image processing techniques are employed to correct the angles of the interlayer interconnection feature data, yielding interconnection angle correction data. Based on this angle correction data, image registration methods are used to adjust the displacement of the interlayer interconnection feature data, resulting in interconnection displacement adjustment data. Furthermore, image processing techniques are used to structurally adjust the preliminary interlayer interconnection simulation data, generating interconnection structure adjustment data. Finally, based on this structure adjustment data, image registration methods are used to optimize the interlayer interconnection registration of the preliminary simulation data, generating optimized interlayer registration data.

[0147] As an example of the present invention, reference is made to Figure 3 As shown, step S5 in this example includes:

[0148] Step S51: Verify the hole position adjustment of the preliminary simulation data of interlayer interconnection using the circuit board hole position adjustment data to obtain hole position adjustment verification data; verify the interlayer registration optimization of the preliminary simulation data of interlayer interconnection using the interlayer registration optimization data to obtain interlayer registration optimization verification data.

[0149] Step S52: Evaluate the interlayer adjustment verification results of the circuit board based on the hole position adjustment verification data and the interlayer registration optimization verification data, and generate the interlayer adjustment verification results of the circuit board; optimize the interlayer interconnection of the circuit board based on the preliminary simulation data of the interlayer interconnection based on the interlayer adjustment verification results, and generate the interlayer interconnection information of the circuit board.

[0150] Step S53: Based on the circuit board design feature information, perform inter-layer design parameter spatial coordinate matching on the inter-layer interconnection information of the circuit board to generate inter-layer design coordinate matching data; map the inter-layer design coordinate matching data to the three-dimensional data of the circuit board design to obtain the three-dimensional spatial mapping data of the circuit board.

[0151] Step S54: Perform 3D image synthesis on the 3D spatial mapping data of the circuit board to obtain a 3D design image of the circuit board; enhance the image details of the 3D design image of the circuit board to generate a circuit board design drawing.

[0152] In this embodiment of the invention, a circuit board via detection device is used to verify the preliminary simulation data of interlayer interconnection based on via adjustment data. Specifically, the operation includes inputting the via adjustment data into the detection device, which automatically calibrates the vias, and generating via adjustment verification data by comparing the via positions before and after adjustment. The interlayer registration optimization data is then verified using a method for implementing an interlayer vertical interconnection structure. The steps include applying a registration optimization algorithm to the preliminary simulation data of interlayer interconnection, generating interlayer registration optimization verification data by measuring the interlayer alignment before and after registration, and combining the via adjustment verification data and the interlayer registration optimization verification data to evaluate the verification results of circuit board interlayer adjustment using statistical analysis methods. Specifically, the deviation values ​​between via adjustment and interlayer registration are calculated to generate circuit board interlayer adjustment verification results. Based on the interlayer adjustment verification results, the preliminary simulation data of interlayer interconnection is optimized using a microwave multilayer board interlayer interconnection matching method. Specifically, interlayer connection parameters, such as trace width and spacing, are adjusted to meet the performance requirements of interlayer interconnection, generating circuit board interlayer... Interconnection information; utilizing arbitrary layer interconnection (HDI) technology, spatial coordinate matching of interlayer interconnection information is performed based on circuit board design feature information; specifically, the design feature information is input into the HDI software, which automatically matches interlayer design parameters with spatial coordinates to generate interlayer design coordinate matching data; 3D image synthesis technology is used to map the interlayer design coordinate matching data into 3D space; specifically, image processing software is used to load the interlayer design data, and 3D coordinate system drawing and image synthesis operations are performed to obtain the circuit board 3D spatial mapping data; using agricultural flexible pH chip performance optimization technology based on MSER affine transformation registration, 3D image synthesis is performed on the circuit board 3D spatial mapping data; specifically, the MSER algorithm is used to extract key feature points, and image registration is achieved through affine transformation to synthesize 3D images; image enhancement technology is used to enhance the details of the circuit board 3D design image; specifically, histogram equalization, Gaussian noise addition, non-mean filtering, contrast adjustment, and sharpening techniques are used to enhance image details and finally generate the circuit board design diagram.

[0153] This specification provides a system for generating circuit board design diagrams, used to execute the above-described method for generating circuit board design diagrams. The system for generating circuit board design diagrams includes:

[0154] The circuit board design data acquisition module is used to acquire circuit board design requirement information; perform semantic analysis on the circuit board design requirement information to generate design requirement semantic data; extract circuit board design features from the design requirement semantic data to obtain circuit board design feature information; and identify circuit board performance requirements from the circuit board design feature information to generate circuit board performance requirement data.

[0155] The PCB interlayer structure analysis module is used to identify PCB components based on PCB design feature information to obtain PCB component data; perform component correlation analysis on PCB component data to obtain component correlation data; and perform PCB interlayer structure detection based on component correlation data to obtain PCB interlayer structure information.

[0156] The circuit board interlayer interconnection simulation module is used to perform interlayer interconnection requirement analysis on the interlayer structure information of the circuit board based on the circuit board performance requirement data, and generate interlayer interconnection requirement data; based on the interlayer interconnection requirement data, generate circuit board hole positions based on the circuit board design feature information, and obtain circuit board hole position data; and perform preliminary simulation of interlayer interconnection of the circuit board based on the circuit board hole position data, and obtain preliminary simulation data of interlayer interconnection.

[0157] The circuit board interlayer interconnection optimization and adjustment module is used to detect the impedance continuity of the circuit board via locations in the preliminary simulation data of interlayer interconnection, thereby obtaining circuit board impedance continuity data; adjust the circuit board via locations using the circuit board impedance continuity data, thereby generating circuit board via location adjustment data; identify the degree of interlayer alignment of the circuit board in the preliminary simulation data of interlayer interconnection, thereby obtaining the degree of interlayer registration; and optimize the interlayer registration of the preliminary simulation data of interlayer interconnection based on the degree of interlayer registration, thereby generating optimized interlayer registration data.

[0158] The circuit board design drawing generation module is used to optimize the interlayer interconnection of the circuit board based on the circuit board hole position adjustment data and interlayer registration optimization data, and generate the interlayer interconnection information of the circuit board; and to perform three-dimensional image mapping of the interlayer interconnection information of the circuit board based on the circuit board design feature information to obtain the circuit board design drawing.

[0159] This invention utilizes a PCB design data acquisition module to obtain PCB design requirement information and perform semantic analysis, accurately generating semantic data for design requirements. This provides accurate foundational information for subsequent design. Feature extraction is performed on the semantic data to clarify specific parameters and requirements of the design. Furthermore, PCB performance requirements are identified to ensure the design meets expected performance standards. A PCB interlayer structure analysis module identifies components based on PCB design features, providing specific component information for the design. Component correlation analysis is performed on the component data to clarify the relationships between various components. Interlayer structure detection is conducted based on the component correlation data, providing details of physical connections between layers. A PCB interlayer interconnection simulation module analyzes interlayer interconnection requirements based on PCB performance requirement data, clarifying the electrical connection design of the PCB. Through-hole generation is performed based on the interlayer interconnection requirements data, providing precise location information for interlayer connections. Preliminary simulation of PCB interlayer interconnections provides a preliminary preview of the interlayer connection effect for the design. The circuit board interlayer interconnection optimization and adjustment module performs impedance continuity detection on the via locations in the preliminary simulation data of interlayer interconnections, ensuring the stability of signal transmission. By adjusting the via location data based on impedance continuity data, the signal transmission path is optimized. The interlayer alignment degree is identified in the preliminary simulation data of interlayer interconnections, providing a basis for precise interlayer alignment. The accuracy of interlayer connections is improved by optimizing the preliminary simulation data based on the interlayer registration degree. The circuit board design drawing generation module optimizes the preliminary simulation data based on the circuit board via location adjustment data and interlayer registration optimization data, thus optimizing the circuit board interlayer interconnection information. Three-dimensional image mapping of the interlayer interconnection information based on circuit board design feature information provides a visual representation of the circuit board's three-dimensional structure, offering detailed visual references for subsequent circuit board manufacturing and inspection. Therefore, this invention, through data processing technology, pattern recognition technology, three-dimensional mapping technology, and deep learning technology, solves the problems of interlayer alignment and interlayer interconnection in multilayer board design; and optimizes and adjusts the impedance discontinuity characteristics caused by vias, thereby ensuring the stability and reliability of the generated circuit board design drawing.

[0160] Therefore, the embodiments should be considered as exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of the equivalents of the application are intended to be included within the invention.

[0161] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. A method for generating circuit board design drawings, characterized in that, Includes the following steps: Step S1: Obtain circuit board design requirements information; Semantic analysis is performed on the circuit board design requirements information to generate design requirement semantic data; circuit board design features are extracted from the design requirement semantic data to obtain circuit board design feature information. Identify circuit board performance requirements from circuit board design feature information and generate circuit board performance requirement data. Step S2: Identify circuit board components based on circuit board design feature information to obtain circuit board component data; perform component correlation analysis on circuit board component data to obtain component correlation data; and perform circuit board interlayer structure detection based on component correlation data to obtain circuit board interlayer structure information. Step S3: Analyze the interlayer interconnection requirements of the circuit board based on the circuit board performance requirements data, and generate interlayer interconnection requirement data; Based on the interlayer interconnection requirement data, the circuit board design feature information is used to generate circuit board hole positions, thus obtaining circuit board hole position data. Preliminary simulation of interlayer interconnection of circuit board is performed based on the hole location data of circuit board to obtain preliminary simulation data of interlayer interconnection; Step S411: Perform high-frequency signal path identification on the preliminary simulation data of interlayer interconnection to obtain high-frequency signal path data; extract impedance parameters from the high-frequency signal path data to obtain impedance parameter information; Step S412: Identify the impedance characteristics of the circuit board by analyzing the impedance parameter information to obtain the impedance characteristic data of the circuit board; perform path impedance consistency verification on the impedance characteristic data of the circuit board to obtain the path impedance consistency verification result. Step S413: Locate the impedance anomaly area based on the path impedance consistency verification result to obtain impedance anomaly area location data; compare the impedance anomaly area location data with the preset impedance value to obtain the impedance value comparison result. Step S414: Measure the impedance continuity deviation of the impedance value comparison results to obtain continuity deviation measurement data; Impedance continuity is assessed by analyzing the continuity deviation measurement data to obtain the circuit board impedance continuity data. Step S42: Adjust the circuit board hole position data based on the circuit board impedance continuity data to generate circuit board hole position adjustment data; Step S43: Perform inter-layer feature identification on the preliminary simulation data of inter-layer interconnection to obtain inter-layer interconnection feature data; Inter-layer alignment is calculated on the inter-layer interconnection feature data, and inter-layer alignment calculation values ​​are generated; Interlayer bonding degree is measured on the interlayer interconnection feature data, and interlayer bonding degree is generated; Step S44: Evaluate the interlayer alignment degree of the circuit board by combining the interlayer alignment measurement value and the interlayer bonding degree measurement value to obtain the interlayer registration degree of the circuit board. Step S45: Optimize the interlayer registration of the preliminary simulation data of interlayer interconnection based on the interlayer registration degree of the circuit board, and generate optimized interlayer registration data; Step S5: Based on the circuit board hole position adjustment data and interlayer registration optimization data, optimize the interlayer interconnection of the preliminary simulation data to generate circuit board interlayer interconnection information; perform 3D image mapping of circuit board design on the interlayer interconnection information according to the circuit board design feature information to obtain the circuit board design drawing.

2. The method for generating circuit board design drawings according to claim 1, characterized in that, Step S2 includes the following steps: Step S21: Identify the circuit board component types from the circuit board design feature information to obtain circuit board component type information; extract component parameter features from the circuit board component type information to obtain component parameter feature information; integrate the circuit board component type information and component parameter feature information to obtain circuit board component data. Step S22: Locate the component connection nodes in the circuit board component data to obtain component connection node information; identify the connection paths between components based on the component connection node information to generate connection path information between components; Step S23: Based on the component connection node information and the connection path information between components, identify the connection relationship between components in the circuit board component data to obtain component association data; Step S24: Identify the inter-layer connection features of the circuit board based on the component association data to obtain the inter-layer connection information of the circuit board; divide the inter-layer connection information of the circuit board into functional module layers to generate functional module layer data of the circuit board; detect the inter-layer structure of the circuit board based on the functional module layer data of the circuit board to obtain the inter-layer structure information of the circuit board.

3. The method for generating circuit board design drawings according to claim 1, characterized in that, Step S3 includes the following steps: Step S31: Extract the interlayer signal transmission rate requirements from the interlayer structure information of the circuit board based on the circuit board performance requirement data to obtain the interlayer signal transmission requirement parameters; Step S32: Based on the circuit board performance requirement data, identify the power distribution efficiency requirements of the interlayer structure information of the circuit board to obtain the interlayer power distribution requirement parameters; Step S33: Determine the interconnection density requirements of the interlayer structure information of the circuit board based on the circuit board performance requirement data, and obtain the interlayer interconnection density requirement parameters; Step S34: Merge the inter-layer signal transmission requirement parameters, inter-layer power distribution requirement parameters, and inter-layer interconnection density requirement parameters into inter-layer interconnection requirement parameters to generate inter-layer interconnection requirement data; Step S35: Based on the inter-layer interconnection requirement data, identify the circuit board hole distribution area using the circuit board design feature information to obtain circuit board hole distribution area data; perform hole coordinate positioning on the circuit board hole distribution area data to generate hole coordinate positioning data; Step S36: Extract the hole size parameters of the circuit board based on the interlayer interconnection requirement data to obtain the hole size parameters; match the hole coordinate positioning data and the hole size parameters to obtain the circuit board hole position data. Step S37: Perform preliminary simulation of interlayer interconnection of the circuit board based on the circuit board hole location data and circuit board design feature information to obtain preliminary simulation data of interlayer interconnection.

4. The method for generating circuit board design drawings according to claim 3, characterized in that, Step S37 includes the following steps: Step S371: Extract circuit board design parameters from circuit board design feature information to obtain circuit board design parameters; arrange circuit board components according to circuit board design parameters to generate circuit board component layout data; perform single-layer circuit board routing on circuit board component layout data to generate single-layer circuit board routing data. Step S372: Based on the circuit board via location data, perform interlayer via connectivity simulation on the single-layer circuit board wiring data to obtain via connectivity simulation results; perform interlayer signal transmission path simulation on the via connectivity simulation results to obtain interlayer signal path simulation data. Step S373: Perform interlayer interconnect density simulation based on interlayer signal path simulation data to generate interlayer interconnect density simulation data; evaluate the interlayer bonding degree of the interlayer interconnect density simulation data to obtain the interlayer bonding degree value; Step S374: Perform preliminary simulation of interlayer interconnection of the circuit board based on the interlayer bonding degree value and the circuit board design feature information to obtain preliminary simulation data of interlayer interconnection.

5. The method for generating circuit board design drawings according to claim 1, characterized in that, Step S42 includes the following steps: Step S421: Detect impedance continuity changes in the circuit board impedance continuity data to obtain impedance continuity change data; measure the abnormal change amount in the impedance continuity change data to generate the impedance abnormal change amount measurement value. Step S422: Based on the measured value of impedance anomaly, map the hole position data of the circuit board to generate abnormal hole position mapping information; extract the hole position size parameters from the abnormal hole position mapping information to obtain the abnormal hole position size parameters; identify the hole position routing layout from the abnormal hole position mapping information to obtain the abnormal hole position routing data. Step S423: Perform circuit board hole position dispersion adjustment on the abnormal hole position mapping information to obtain circuit board hole position adjustment data; reduce the size of the abnormal hole position size parameters to obtain hole size reduction parameters; re-layout the hole position routing pins on the abnormal hole position routing data to generate hole position routing pin layout data. Step S424: Integrate the circuit board hole position adjustment data, hole size reduction parameters, and hole routing pin layout data into circuit board hole position adjustment data to obtain circuit board hole position adjustment data.

6. The method for generating circuit board design drawings according to claim 1, characterized in that, Step S45 includes the following steps: Step S451: Quantify the registration deviation of the interlayer registration degree of the circuit board to generate registration deviation quantification data; identify the interlayer registration deviation distribution of the registration deviation quantification data to obtain interlayer registration deviation distribution data. Step S452: Detect the correction region of the interlayer registration deviation distribution data to generate interlayer registration correction region information; calculate the registration correction parameters of the interlayer registration correction region information to obtain the registration correction parameter values; Step S453: Perform inter-layer interconnection angle correction on the inter-layer interconnection feature data using the registration correction parameter values ​​to obtain interconnection angle correction data; adjust the inter-layer interconnection displacement based on the interconnection angle correction data to obtain interconnection displacement adjustment data; Step S454: Adjust the inter-layer interconnection structure of the preliminary simulation data using the interconnection displacement adjustment data to obtain interconnection structure adjustment data; optimize the inter-layer registration of the preliminary simulation data using the interconnection structure adjustment data to generate optimized inter-layer registration data.

7. The method for generating circuit board design drawings according to claim 1, characterized in that, Step S5 includes the following steps: Step S51: Verify the hole position adjustment of the preliminary simulation data of interlayer interconnection using the circuit board hole position adjustment data to obtain hole position adjustment verification data; verify the interlayer registration optimization of the preliminary simulation data of interlayer interconnection using the interlayer registration optimization data to obtain interlayer registration optimization verification data. Step S52: Evaluate the interlayer adjustment verification results of the circuit board based on the hole position adjustment verification data and the interlayer registration optimization verification data, and generate the interlayer adjustment verification results of the circuit board; optimize the interlayer interconnection of the circuit board based on the preliminary simulation data of the interlayer interconnection based on the interlayer adjustment verification results, and generate the interlayer interconnection information of the circuit board. Step S53: Based on the circuit board design feature information, perform inter-layer design parameter spatial coordinate matching on the inter-layer interconnection information of the circuit board to generate inter-layer design coordinate matching data; map the inter-layer design coordinate matching data to the three-dimensional data of the circuit board design to obtain the three-dimensional spatial mapping data of the circuit board. Step S54: Perform 3D image synthesis on the 3D spatial mapping data of the circuit board to obtain a 3D design image of the circuit board; enhance the image details of the 3D design image of the circuit board to generate a circuit board design drawing.

8. A system for generating circuit board design drawings, characterized in that, The system for generating circuit board design diagrams as described in claim 1, for performing the method of generating circuit board design diagrams as described in claim 1, comprises: The circuit board design data acquisition module is used to acquire circuit board design requirement information; perform semantic analysis on the circuit board design requirement information to generate design requirement semantic data; extract circuit board design features from the design requirement semantic data to obtain circuit board design feature information; and identify circuit board performance requirements from the circuit board design feature information to generate circuit board performance requirement data. The PCB interlayer structure analysis module is used to identify PCB components based on PCB design feature information to obtain PCB component data; perform component correlation analysis on PCB component data to obtain component correlation data; and perform PCB interlayer structure detection based on component correlation data to obtain PCB interlayer structure information. The circuit board interlayer interconnection simulation module is used to perform interlayer interconnection requirement analysis on the interlayer structure information of the circuit board based on the circuit board performance requirement data, and generate interlayer interconnection requirement data; based on the interlayer interconnection requirement data, generate circuit board hole positions based on the circuit board design feature information, and obtain circuit board hole position data; and perform preliminary simulation of interlayer interconnection of the circuit board based on the circuit board hole position data, and obtain preliminary simulation data of interlayer interconnection. The circuit board interlayer interconnection optimization and adjustment module is used to detect the impedance continuity of the circuit board via locations in the preliminary simulation data of interlayer interconnection, thereby obtaining circuit board impedance continuity data; adjust the circuit board via locations using the circuit board impedance continuity data, thereby generating circuit board via location adjustment data; identify the degree of interlayer alignment of the circuit board in the preliminary simulation data of interlayer interconnection, thereby obtaining the degree of interlayer registration; and optimize the interlayer registration of the preliminary simulation data of interlayer interconnection based on the degree of interlayer registration, thereby generating optimized interlayer registration data. The circuit board design drawing generation module is used to optimize the interlayer interconnection of the circuit board based on the circuit board hole position adjustment data and interlayer registration optimization data, and generate the interlayer interconnection information of the circuit board; and to perform three-dimensional image mapping of the interlayer interconnection information of the circuit board based on the circuit board design feature information to obtain the circuit board design drawing.

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