Quantum circuit optimization design method and device, storage medium and computer equipment

Abstract

According to the quantum circuit optimization design method and device, the storage medium and the computer equipment provided by the invention, when a quantum circuit is designed, an initial quantum circuit structure pool formed by a plurality of initial quantum circuits and a first candidate queue formed by blank circuits can be firstly obtained; expanding circuits in the first candidate queue according to each initial quantum circuit, and adjusting the scale of the expanded first candidate queue according to the performance index value of each circuit in the expanded first candidate queue; the method comprises the following steps: adjusting a first candidate queue, selecting a circuit with a performance index value meeting a preset score from the adjusted first candidate queue as a to-be-optimized circuit, randomly selecting a plurality of quantum gates from the to-be-optimized circuit to form a second candidate queue, and optimizing the to-be-optimized circuit according to each quantum gate in the second candidate queue. And a final target circuit is obtained. According to the process, the to-be-optimized circuit capable of meeting the specific QNN training requirements can be quickly found.

Description

Technical Field

[0001] The present application relates to the technical field of quantum circuit optimization design, and in particular to a quantum circuit optimization design method, device, storage medium and computer equipment. Background Art

[0002] Quantum machine learning, as an intersection of quantum computing and artificial intelligence, has received widespread attention from academia and industry in recent years. By utilizing the unique properties of quantum mechanics, such as quantum superposition and entanglement, quantum machine learning algorithms are expected to break through the limitations of classical machine learning algorithms and achieve significant performance improvements in tasks such as high-dimensional data processing and complex pattern recognition.

[0003] As an important type of quantum machine learning model, quantum neural networks (QNN) have demonstrated advantages over classical neural networks in quantum many-body physics research, such as quantum phase recognition, ground state preparation and energy solution, and Gibbs state preparation, by constructing parameterized quantum circuits and using classical optimization algorithms to train parameters. Most of them have been initially experimentally verified in noisy intermediate-scale quantum (NISQ) devices.

[0004] At present, although NISQ devices can provide hundreds of physical qubits, the current quantum neural network scale is still limited to more than ten qubits due to the training capacity, far from realizing the potential of NISQ. In addition, since QNN often faces multiple challenges in training, such as insufficient expressiveness, barren plateaus, local minima, etc., these problems seriously affect the training efficiency and model performance of quantum neural networks. When the number of qubits and circuit depth increase, the performance of QNN will decrease significantly.

[0005] Therefore, how to accurately design quantum circuits suitable for specific QNN training requirements has become a technical problem that needs to be solved urgently. Summary of the invention

[0006] The purpose of this application is to solve at least one of the above-mentioned technical deficiencies, especially the technical defect in the prior art that quantum circuits suitable for specific QNN training requirements cannot be accurately designed.

[0007] The present application provides a quantum circuit optimization design method, the method comprising:

[0008] Acquire an initial quantum circuit structure pool consisting of a plurality of initial quantum circuits and a first candidate queue consisting of blank circuits;

[0009] Expanding the circuits in the first candidate queue according to each initial quantum circuit, and adjusting the size of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue;

[0010] Selecting a circuit whose performance index value meets a preset score from the adjusted first candidate queue as a circuit to be optimized, and randomly selecting a plurality of quantum gates from the circuit to be optimized to form a second candidate queue;

[0011] The circuit to be optimized is optimized according to each quantum gate in the second candidate queue to obtain a final target circuit.

[0012] Optionally, the step of expanding the circuits in the first candidate queue according to the initial quantum circuits to obtain an expanded first candidate queue includes:

[0013] Ranking each circuit in the first candidate queue, selecting the circuit ranked first, and randomly selecting other circuits from the remaining circuits;

[0014] Expanding the first-ranked circuit and the other circuits respectively according to the initial quantum circuits to obtain a third candidate queue consisting of a plurality of expanded circuits;

[0015] The first candidate queue is expanded according to the performance indicator value of each expansion circuit in the third candidate queue to obtain an expanded first candidate queue.

[0016] Optionally, the expanding the first candidate queue according to the performance indicator value of each expansion circuit in the third candidate queue to obtain the expanded first candidate queue includes:

[0017] Calculating the performance index value of each expansion circuit in the third candidate queue;

[0018] According to the performance indicator value of each expansion circuit, several expansion circuits are selected from the third candidate queue and added to the first candidate queue to obtain an expanded first candidate queue.

[0019] Optionally, calculating the performance indicator value of each expansion circuit in the third candidate queue includes:

[0020] Determining a performance indicator value to be calculated, and a Hamiltonian and a sampling number corresponding to the performance indicator value;

[0021] By combining Clifford gates, the continuous time evolution described by the Hamiltonian is discretized to obtain a discretized parameter value combination;

[0022] For each revolving door in each extension circuit in the third candidate queue, at each sampling, randomly select any one parameter value in the parameter value combination as the parameter value of the revolving door, and after modifying the extension circuit according to the selected parameter value, calculate the performance indicator value of the modified extension circuit until the sampling number is reached;

[0023] The performance index value calculated after each sampling in each expansion circuit is obtained, and the performance index value of each expansion circuit is calculated according to the variance corresponding to each performance index value.

[0024] Optionally, adjusting the size of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue includes:

[0025] Calculate the performance index value of each circuit in the expanded first candidate queue to obtain a calculation result;

[0026] The circuits in the expanded first candidate queue are sorted in descending order according to the calculation result, and the size of the expanded first candidate queue is adjusted according to the sorting result and a preset size threshold.

[0027] Optionally, the selecting a circuit whose performance indicator value satisfies a preset score from the adjusted first candidate queue as a circuit to be optimized, and randomly selecting a plurality of quantum gates from the circuit to be optimized to form a second candidate queue, comprises:

[0028] Determine whether the circuit with the highest performance indicator value in the adjusted first candidate queue meets a preset score;

[0029] If the conditions are met, the circuit that meets the preset score is used as the circuit to be optimized, and a plurality of quantum gates are randomly selected from the circuit to be optimized to form a second candidate queue;

[0030] If not satisfied, after updating the first candidate queue according to the adjusted first candidate queue, return to execute the step of expanding the circuits in the first candidate queue according to each initial quantum circuit, and adjusting the scale of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue.

[0031] Optionally, optimizing the circuit to be optimized according to each quantum gate in the second candidate queue to obtain a final target circuit includes:

[0032] Selecting any one quantum gate from the second candidate queue as the current quantum gate;

[0033] After removing the current quantum gate from the circuit to be optimized, determining whether the performance index value of the circuit to be optimized after the quantum gate is removed is greater than a preset index threshold;

[0034] If yes, the circuit to be optimized after removing the quantum gate is used as the final target circuit;

[0035] Otherwise, after deleting the current quantum gate from the second candidate queue, continue to perform the steps of selecting any quantum gate from the second candidate queue as the current quantum gate and subsequent steps until the performance index value of the circuit to be optimized after the quantum gate is removed is greater than the preset index threshold, or there is no quantum gate in the second candidate queue;

[0036] When there is no quantum gate in the second candidate queue, the circuit to be optimized is used as the final target circuit.

[0037] The present application also provides a quantum circuit optimization design device, comprising:

[0038] A quantum circuit acquisition module, used to acquire an initial quantum circuit structure pool consisting of a plurality of initial quantum circuits, and a first candidate queue consisting of blank circuits;

[0039] A candidate queue adjustment module, configured to expand the circuits in the first candidate queue according to each initial quantum circuit, and adjust the size of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue;

[0040] A circuit to be optimized determining module, used to select a circuit whose performance indicator value meets a preset score from the adjusted first candidate queue as a circuit to be optimized, and randomly select a plurality of quantum gates from the circuit to be optimized to form a second candidate queue;

[0041] A quantum circuit optimization module is used to optimize the circuit to be optimized according to each quantum gate in the second candidate queue to obtain a final target circuit.

[0042] The present application also provides a computer-readable storage medium, in which computer-readable instructions are stored. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the steps of the quantum circuit optimization design method described in any one of the above embodiments.

[0043] The present application also provides a computer device, comprising: one or more processors, and a memory;

[0044] The memory stores computer-readable instructions, and when the computer-readable instructions are executed by the one or more processors, the steps of the quantum circuit optimization design method described in any one of the above embodiments are performed.

[0045] It can be seen from the above technical solutions that the embodiments of the present application have the following advantages:

[0046] The quantum circuit optimization design method, device, storage medium and computer equipment provided by the present application can first obtain an initial quantum circuit structure pool composed of multiple initial quantum circuits and a first candidate queue composed of blank circuits when designing a quantum circuit; then expand the circuits in the first candidate queue according to each initial quantum circuit, and adjust the scale of the expanded first candidate queue according to the performance index value of each circuit in the expanded first candidate queue, and then select the circuit whose performance index value meets the preset score from the adjusted first candidate queue as the circuit to be optimized, and then, the present application can randomly select multiple quantum gates from the circuit to be optimized to form a second candidate queue, and then optimize the circuit to be optimized according to each quantum gate in the second candidate queue to obtain the final target circuit. Two rounds of search frameworks are designed in this process. The first round of search framework first performs a round of rough search to effectively evaluate and optimize the expression ability and training gradient stability of the quantum circuit according to the performance index value, and quickly find the circuit to be optimized that can meet the specific QNN training requirements, and then on the basis of the circuit to be optimized, try to reduce the redundant quantum gates in the circuit to be optimized, thereby reducing circuit overhead and improving computing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0048] Figure 1 A schematic diagram of a flow chart of a quantum circuit optimization design method provided in an embodiment of the present application;

[0049] Figure 2 A schematic diagram of a flow chart of selecting a circuit whose performance indicator value satisfies a preset score from the adjusted first candidate queue as a circuit to be optimized provided in an embodiment of the present application;

[0050] Figure 3 A schematic diagram of a flow chart for optimizing a circuit to be optimized provided in an embodiment of the present application;

[0051] Figure 4A schematic diagram of the structure of a quantum circuit optimization design device provided in an embodiment of the present application;

[0052] Figure 5 A schematic diagram of the internal structure of a computer device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0054] In one embodiment, Figure 1 As shown, Figure 1 A schematic diagram of a flow chart of a quantum circuit optimization design method provided in an embodiment of the present application; the present application provides a quantum circuit optimization design method, which may include:

[0055] S110: Acquire an initial quantum circuit structure pool consisting of a plurality of initial quantum circuits and a first candidate queue consisting of blank circuits.

[0056] In this step, when optimizing the quantum circuit design, an initial quantum circuit structure pool consisting of multiple initial quantum circuits and a first candidate queue consisting of multiple blank circuits can be obtained first, and then the blank circuits can be expanded based on each initial quantum circuit to find a circuit to be optimized that meets the training requirements.

[0057] Specifically, in order to design an effective method to dynamically control the expressiveness and trainability of QNN to achieve good performance, this application can use Quantum Architecture Search (QAS) to find a target circuit that can meet the specific QNN training requirements. It can be understood that quantum architecture search (QAS) is a key task in the field of quantum computing, which directly affects the performance and practicality of quantum neural networks (QNNs). By intelligently searching for the optimal quantum circuit design, QAS can not only maximize the performance of quantum algorithms on specific hardware, but also ensure the scalability and robustness of the algorithm.

[0058] Among them, quantum architecture search is not only an important driving force for innovation in quantum computing technology, but also a key factor in promoting the practical application of quantum algorithms. In addition, as quantum technology expands to more complex commercial and scientific research applications, the importance of QAS will become more apparent. In advanced applications such as quantum machine learning and quantum chemistry simulation, optimized quantum circuits can greatly improve the efficiency and accuracy of problem solving and accelerate the application of quantum computing in all walks of life. Therefore, QAS is not only an important branch of the development of quantum computing technology, but also one of the key technologies to promote the practical application and commercialization of quantum computing.

[0059] Current QAS schemes generally face high training costs and insufficient consideration of quantum neural network trainability. To address these challenges, this application designs a two-round search framework based on the existing quantum architecture search. The first round of search framework first conducts a round of coarse search to effectively evaluate and optimize the expressiveness and training gradient stability of quantum circuits based on performance index values, and quickly find circuits to be optimized that can meet specific QNN training requirements. Then, based on the circuits to be optimized, attempts are made to reduce redundant quantum gates in the circuits to be optimized, thereby reducing circuit overhead and improving computational efficiency.

[0060] Based on this, the present application can select multiple initial quantum circuits of single-bit gates or two-bit gates that can be implemented in hardware according to the type of hardware device, and form an initial quantum circuit structure pool. ,in, is the first initial quantum circuit. Then, the present application can initialize the first candidate queue. ,in Indicates a blank circuit.

[0061] It is understandable that the blank circuit here refers to a printed circuit board (PCB) that has no electronic components installed or has not been wired. It is just a physical carrier with circuit path planning (such as the copper foil circuit layer has been pre-designed), but no actual electronic components are soldered on, or the internal integrated circuits and other chips have not been packaged.

[0062] S120: Expanding the circuits in the first candidate queue according to each initial quantum circuit, and adjusting the size of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue.

[0063] In this step, after obtaining multiple initial quantum circuits in the initial quantum circuit structure pool and multiple blank circuits in the first candidate queue through S110, since the blank circuit has no electronic components installed or a printed circuit board that has not been wired, the present application can expand the circuits in the first candidate queue according to each initial quantum circuit, so that the number of circuits in the first candidate queue can be increased, thereby more accurately screening out the circuits to be optimized that meet the training requirements.

[0064] After the present application expands the circuits in the first candidate queue, the present application can also calculate the performance index values ​​of each circuit in the expanded first candidate queue, so that the size of the expanded first candidate queue can be adjusted according to the performance index values ​​of each circuit, which can not only reduce the amount of calculation of subsequent optimized circuits, but also improve the optimization quality of the circuits.

[0065] Among them, the above-mentioned performance index values ​​include but are not limited to one or more of the RF index values, quantum state fidelity, operation complexity, quantum Fisher matrix and other index values ​​in the quantum network. This can form a multi-dimensional evaluation system, and then evaluate the performance of the quantum neural network from a more comprehensive perspective, providing more accurate decision support for quantum architecture search.

[0066] S130: Selecting a circuit whose performance indicator value meets a preset score from the adjusted first candidate queue as a circuit to be optimized, and randomly selecting a plurality of quantum gates from the circuit to be optimized to form a second candidate queue.

[0067] S140: Optimize the circuit to be optimized according to each quantum gate in the second candidate queue to obtain a final target circuit.

[0068] In the above steps, after adjusting the size of the expanded first candidate queue through S120, the present application can select a circuit whose performance indicator value meets the preset score from the adjusted first candidate queue as the circuit to be optimized, and then randomly select multiple quantum gates from the circuit to be optimized to form a second candidate queue. In this way, the circuit to be optimized can be optimized through the second candidate queue to obtain the final target circuit.

[0069] It can be understood that after the present application calculates the performance index value corresponding to each circuit in the adjusted first candidate queue, since the performance index value evaluates the performance of the quantum neural network from a more comprehensive perspective, the circuit whose performance index value meets the preset score is screened out through the performance index value of each circuit as the circuit to be optimized. The circuit to be optimized can better meet the training requirements of the specific quantum neural network.

[0070] In addition, in order to reduce circuit overhead and improve computing efficiency, the present application can also select a second candidate queue after multiple quantum gates are selected based on the circuit to be optimized, so that the circuit to be optimized can be optimized through the second candidate queue, thereby reducing redundant quantum gates in the circuit to be optimized.

[0071] In the above embodiment, when designing a quantum circuit, an initial quantum circuit structure pool consisting of multiple initial quantum circuits and a first candidate queue consisting of blank circuits can be first obtained; then the circuits in the first candidate queue are expanded according to each initial quantum circuit, and the scale of the expanded first candidate queue is adjusted according to the performance index value of each circuit in the expanded first candidate queue, and then the circuit whose performance index value meets the preset score is selected from the adjusted first candidate queue as the circuit to be optimized. Then, the present application can randomly select multiple quantum gates from the circuit to be optimized to form a second candidate queue, and then optimize the circuit to be optimized according to each quantum gate in the second candidate queue to obtain the final target circuit. Two rounds of search frameworks are designed in this process. The first round of search framework first performs a round of rough search to effectively evaluate and optimize the expression ability and training gradient stability of the quantum circuit according to the performance index value, and quickly find the circuit to be optimized that can meet the specific QNN training requirements, and then on the basis of the circuit to be optimized, try to reduce the redundant quantum gates in the circuit to be optimized, thereby reducing circuit overhead and improving computing efficiency.

[0072] In one embodiment, in S120, the circuits in the first candidate queue are expanded according to the initial quantum circuits to obtain the expanded first candidate queue, which may include:

[0073] S121: rank the circuits in the first candidate queue, select the circuit ranked first, and then randomly select other circuits from the remaining circuits.

[0074] S122: Expand the first-ranked circuit and the other circuits respectively according to the initial quantum circuits to obtain a third candidate queue consisting of a plurality of expanded circuits.

[0075] S123: Expand the first candidate queue according to the performance indicator value of each expansion circuit in the third candidate queue to obtain an expanded first candidate queue.

[0076] In this embodiment, when expanding the circuits in the first candidate queue, the circuits in the first candidate queue can be ranked first, and then the circuit ranked first is selected, and then other circuits are randomly selected from the remaining circuits. Then, the present application can expand the circuit ranked first and other circuits according to each initial quantum circuit, and obtain a third candidate queue composed of multiple expanded circuits. Finally, the present application expands the first candidate queue according to the performance indicator values ​​of each expanded circuit, and then obtains the expanded first candidate queue.

[0077] In a specific implementation, the present application may initialize the first candidate queue ,in Indicates a blank circuit, then select The number one circuit in Expand and get the candidate queue . Then, this application can randomly select Circuits other than the first Expand and expand the candidate queue ,in, The smaller it is, the greater the probability of being selected. Finally, after merging the two queues, a third candidate queue consisting of multiple expansion circuits can be obtained.

[0078] Among them, when ranking the various circuits in the first candidate queue, this application can rank them from the perspective of performance indicators, or from the perspective of hardware compatibility, or from the perspective of ease of use and design flexibility. When ranking them from the perspective of performance indicators, they can be ranked from the perspectives of scalability, error rate, stability, operating speed, frequency response, etc. The specific selection can be made according to the actual situation and is not limited here.

[0079] Furthermore, when the present application randomly selects other circuits from the remaining circuits, a commonly used selection function can be used for selection. For example, the present application can use a softmax function to complete the selection work, and then expand the other selected circuits. Of course, the present application can also use other methods for random selection, which can be selected according to the actual situation and is not limited here.

[0080] In one embodiment, in S123, the first candidate queue is expanded according to the performance indicator value of each expansion circuit in the third candidate queue to obtain the expanded first candidate queue, which may include:

[0081] S1231: Calculate the performance indicator value of each expansion circuit in the third candidate queue.

[0082] S1232: According to the performance indicator value of each expansion circuit, select a number of expansion circuits from the third candidate queue and add them to the first candidate queue to obtain an expanded first candidate queue.

[0083] In this embodiment, when expanding the first candidate queue, the present application can first calculate the performance indicator value of each expansion circuit in the third candidate queue, and then select several expansion circuits from the third candidate queue to add to the first candidate queue based on the performance indicator value of each expansion circuit, thereby obtaining the expanded first candidate queue.

[0084] Among them, when expanding the first candidate queue, in order to improve the adaptability of the quantum circuit, the present application can first select the performance indicator that needs to be calculated, and then calculate the performance indicator value of each extended circuit based on the performance indicator. Then, the present application can select multiple extended circuits with higher performance indicator values ​​from the third candidate queue according to the performance indicator values ​​of each extended circuit and add them to the first candidate queue. This can not only increase the number of quantum circuits in the first candidate queue, but also improve the quality of the quantum circuits.

[0085] In one embodiment, calculating the performance indicator value of each expansion circuit in the third candidate queue in S1231 may include:

[0086] S2311: Determine the performance indicator value to be calculated, and the Hamiltonian and sampling times corresponding to the performance indicator value.

[0087] S2312: Discretize the continuous time evolution described by the Hamiltonian by combining Clifford gates to obtain a discretized parameter value combination.

[0088] S2313: For each revolving gate in each extended circuit in the third candidate queue, at each sampling, any one parameter value in the parameter value combination is randomly selected as the parameter value of the revolving gate, and after modifying the extended circuit according to the selected parameter value, the performance indicator value of the modified extended circuit is calculated until the sampling number is reached.

[0089] S2314: Obtain the performance index value calculated after each sampling in each expansion circuit, and calculate the performance index value of each expansion circuit according to the variance corresponding to each performance index value.

[0090] In this embodiment, when calculating the performance index values ​​of each extended circuit in the third candidate queue, the present application can adopt an architecture search strategy based on performance index values, which does not require the implementation of actual quantum circuit training, thereby significantly reducing the operating overhead of quantum computers and effectively optimizing the use of quantum resources, such as quantum chemical simulation, material design and other fields, and significantly enhancing the commercial appeal and competitiveness of quantum computing. In addition, this strategy can also help quantum algorithms maintain good performance under different quantum hardware and task conditions, and enable quantum algorithms to adapt to changing environments and complex task requirements by dynamically adjusting the circuit structure.

[0091] It is understandable that the current QAS schemes generally face high training costs and insufficient consideration of the trainability of quantum neural networks. To address these challenges, this application proposes an automated variational circuit search scheme based on loss function fluctuations. This scheme uses indicators of loss function fluctuations to effectively evaluate and optimize the expressiveness of quantum circuits and the stability of training gradients, thereby more accurately designing quantum circuits suitable for specific QNN training needs.

[0092] In a specific implementation method, the present application can first determine the performance indicator value to be calculated, as well as the Hamiltonian and sampling number corresponding to the performance indicator value, and then discretize the continuous time evolution described by the Hamiltonian by combining Clifford gates, thereby obtaining a discretized parameter value combination. Then, for each revolving gate in each extended circuit in the third candidate queue, at each sampling, the present application can randomly select any parameter value in the parameter value combination as the parameter value of the revolving gate, and after modifying the extended circuit according to the selected parameter value, calculate the performance indicator value of the modified extended circuit until the sampling number is reached. Finally, the present application can obtain the performance indicator value calculated after each sampling in each extended circuit, and calculate the performance indicator value of each extended circuit according to the variance corresponding to each performance indicator value.

[0093] For example, the application may input a Hamiltonian and a sampling number, where the Hamiltonian is represented as a series of Pauli strings and corresponding coefficients in the form , where j is an index marking different Pauli strings, is a Pauli string, is the corresponding coefficient. In quantum mechanics, Hamiltonian is an operator that describes the total energy of a system, which determines the time evolution of a quantum system. Hamiltonian contains various interactions and energy information of the system, such as the kinetic energy, potential energy and interaction energy of particles. The number of samples input in this application can be used for discretization simulation using Clifford gate.

[0094] Understandably, the state space of quantum systems is continuous, which makes accurate simulation very difficult. Clifford sampling exploits the special properties of Clifford circuits to discretize the quantum state space. Since the Clifford circuit operates on quantum states with certain regularity, it can map quantum states to a finite, discrete set of states. In some cases, the Clifford gate can be used to discretize the simulation of the continuous-time evolution described by the Hamiltonian. Although the evolution driven by the Hamiltonian is continuous, this evolution can be approximated by appropriately combining Clifford gates.

[0095] For example, for a simple single-qubit system, the Hamiltonian can be According to the Schrödinger equation, the quantum state will rotate continuously around the z-axis at a certain frequency. Therefore, a series of Clifford gates can be used to approximate this rotation. For example, the present application can simulate this continuous rotation effect in discrete steps by combining Hadamard gates and phase gates. Specifically, when calculating the RF value, the RF index can be defined as ,in , is a uniform ensemble of parameter points, is the 1-norm of the Hamiltonian coefficient vector, is the loss function. Discretize into The operations corresponding to these angles can be implemented by combining basic Clifford gates, such as and , it is also possible to convert the H gate into an S gate by adding a pre- and post-Hadamard gate.

[0096] Next, for a given expansion circuit C, for each revolving door of the expansion circuit, randomly select , and then modify the extended circuit according to the selected parameters and perform efficient calculations on a classical computer. Since this type of calculation utilizes the efficient properties of the Clifford gate, it can be tracked through a stable classical data structure, and there is no exponential growth in the amount of calculation. After repeating the above simulation steps until the preset number of sampling times is reached, the output of all simulation results can be collected, and after calculating the variance of the output results, the performance index value of the extended circuit can be calculated based on the variance.

[0097] In order to demonstrate the effectiveness of this application, the following numerical experiments were conducted: a one-dimensional cluster model (1D-Cluster Model) was selected as the simulated quantum system. Specifically, the mathematical expression of the cluster model is: , where j is the size of the quantum system. This application adopts the above solution and compares and analyzes its effect with the ideal solution and other currently well-known solutions.

[0098] The following table shows the training results of each solution, using the percentage of the final training loss reaching the theoretical minimum as the evaluation indicator, and comparing the number of iterations required to achieve the result. Because the initialization parameters of the circuit will cause the result to fluctuate, this application will run the searched circuit 100 times. The results after running are as follows:

[0099]

[0100] Table 1 is a comparison of the training results of various solutions provided in the embodiments of this application

[0101] The above ideal solution usually refers to the construction of a quantum circuit using two Cartan layers. This structure can achieve excellent training results due to its excellent expressiveness. However, since the current quantum hardware devices are not yet able to directly support this complex circuit design, it is defined as an ideal solution. As can be seen from the above table, the technical solution of this application is superior in performance to other solutions.

[0102] Furthermore, after the quantum circuit with optimized design is obtained by the above method, the present application can apply it to the training process of quantum neural network, which can be applied specifically through the following embodiments.

[0103] Example 1: Basic implementation

[0104] Objective: Describe basic applications of this application, such as optimizing simple quantum algorithms using RF-based automated variational circuit search.

[0105] System configuration: Detailed description of the hardware and software configuration used, including the type of quantum computer, the number of qubits used, and essential software tools.

[0106] Steps:

[0107] 1. Initialize the quantum circuit and RF computing module.

[0108] 2. Set search parameters, such as number of iterations and learning rate.

[0109] 3. Perform circuit search and record the RF value and related performance indicators at each step.

[0110] 4. Select the optimal circuit and perform performance testing.

[0111] Result evaluation: Provide test results and performance analysis of the implementation to demonstrate its effectiveness.

[0112] Example 2: Advanced Implementation

[0113] Goal: Demonstrate the application of the invention to more complex quantum computing tasks such as VQE or quantum machine learning models.

[0114] System configuration: including high-performance quantum computers and advanced algorithm configuration.

[0115] Steps:

[0116] 1. Configure advanced RF evaluation tools and dynamic optimization algorithms.

[0117] 2. Search using complex quantum circuit templates.

[0118] 3. Implement multi-parameter optimization and use machine learning technology to fine-tune circuit parameters.

[0119] 4. Perform extensive testing, including cross-validation and performance benchmarking.

[0120] Evaluation results: Demonstrate performance improvements and resource optimization effects of advanced implementations on more difficult tasks.

[0121] Example 3: Specific application scenario

[0122] Objective: To demonstrate a specific use of the invention in a particular industry or application, such as quantum simulation in drug discovery or materials science research.

[0123] Steps:

[0124] 1. Describe the optimization process of quantum circuit design for specific chemical reactions.

[0125] 2.Introduction to cooperation with industry experts and integration of industry knowledge for circuit design.

[0126] 3. Detailed description of the comparison between the experimental results and existing solutions in the industry.

[0127] Result evaluation: Analyze the economic and technical benefits of this embodiment in actual industry applications, such as cost savings, shortened R&D time, etc.

[0128] Furthermore, in the process of searching for quantum architectures, the present application may also use a cross-validation method to evaluate the generalization ability of quantum neural networks. By testing the performance of the algorithm on different tasks, the practicality and stability of the quantum neural network can be more accurately evaluated. The present application may also introduce a feedback-based adaptive adjustment mechanism to automatically adjust the search strategy and parameter settings according to the current algorithm performance. For example, when the algorithm performs poorly under a certain parameter configuration, the system can automatically adjust the search direction.

[0129] Of course, this application can also design a dynamic learning system (reinforcement learning or machine learning strategy) that can continuously learn and optimize based on the performance of the quantum network in actual applications. This method can not only adjust the configuration of the quantum neural network in real time, but also optimize the algorithm strategy based on application feedback to achieve continuous performance improvement.

[0130] In one embodiment, adjusting the size of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue in S120 may include:

[0131] S124: Calculate the performance indicator value of each circuit in the expanded first candidate queue to obtain a calculation result.

[0132] S125: sorting the circuits in the expanded first candidate queue in descending order according to the calculation result, and adjusting the size of the expanded first candidate queue according to the sorting result and a preset size threshold.

[0133] In this embodiment, when adjusting the size of the expanded first candidate queue, the present application can first calculate the performance indicator value of each circuit in the expanded first candidate queue. The calculation process can refer to the calculation process of the performance indicator value of the above-mentioned expanded circuit. After obtaining the calculation results, the present application can sort the circuits in the expanded first candidate queue in descending order according to the calculation results. In this way, the size of the expanded first candidate queue can be adjusted according to the sorting results and the preset size threshold.

[0134] For example, after obtaining the sorting results, the present application can discard the circuits ranked lower in the sorting results according to a preset size threshold, so that the size of the adjusted first candidate queue does not exceed the preset size threshold, thereby effectively reducing circuit overhead and improving computing efficiency.

[0135] In one embodiment, Figure 2 As shown, Figure 2 A schematic diagram of a flow chart of selecting a circuit whose performance index value satisfies a preset score from the adjusted first candidate queue as a circuit to be optimized provided in an embodiment of the present application; in S130, a circuit whose performance index value satisfies a preset score from the adjusted first candidate queue is selected as a circuit to be optimized, and a plurality of quantum gates are randomly selected from the circuit to be optimized to form a second candidate queue, which may include:

[0136] S131: Determine whether the circuit with the highest performance indicator value in the adjusted first candidate queue meets a preset score; if so, execute S132; if not, execute S133.

[0137] S132: taking a circuit that meets a preset score as a circuit to be optimized, and randomly selecting a plurality of quantum gates from the circuit to be optimized to form a second candidate queue.

[0138] S133: After updating the first candidate queue according to the adjusted first candidate queue, return to execute the step of expanding the circuits in the first candidate queue according to each initial quantum circuit, and adjusting the size of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue.

[0139] In this embodiment, when a circuit whose performance index value meets a preset score is selected from the adjusted first candidate queue as a circuit to be optimized, it can be determined whether the circuit with the highest performance index value in the adjusted first candidate queue meets the preset score. For example, when the performance index value is an RF value, it can be determined whether the RF value score corresponding to the circuit with the highest RF value is greater than 1. If it is, it is used as the circuit to be optimized, and a plurality of quantum gates are randomly selected from the circuit to be optimized to form a second candidate queue; if it is not, the circuit in the adjusted first candidate queue is expanded according to each initial quantum circuit, and the scale of the expanded first candidate queue is adjusted according to the performance index value of each circuit in the expanded first candidate queue, and then it is determined whether the circuit with the highest performance index value in the adjusted first candidate queue meets the preset score, until it is determined that there is a circuit with a performance index value that meets the preset score. At this time, the circuit can be used as the circuit to be optimized, and a plurality of quantum gates are randomly selected from the circuit to be optimized to form a second candidate queue.

[0140] In one embodiment, Figure 3 As shown, Figure 3 A schematic diagram of a process for optimizing a circuit to be optimized provided in an embodiment of the present application; in S140, the circuit to be optimized is optimized according to each quantum gate in the second candidate queue to obtain a final target circuit, which may include:

[0141] S141: Select any quantum gate from the second candidate queue as the current quantum gate.

[0142] S142: After removing the current quantum gate from the circuit to be optimized, determine whether the performance index value of the circuit to be optimized after the quantum gate is removed is greater than a preset index threshold. If so, execute S143; otherwise, execute S144.

[0143] S143: The circuit to be optimized after removing the quantum gate is used as the final target circuit.

[0144] S144: After deleting the current quantum gate from the second candidate queue, continue to execute the steps of selecting any quantum gate from the second candidate queue as the current quantum gate and its subsequent steps until the performance index value of the circuit to be optimized after the quantum gate is removed is greater than a preset index threshold, or there is no quantum gate in the second candidate queue.

[0145] S145: When there is no quantum gate in the second candidate queue, the circuit to be optimized is used as the final target circuit.

[0146] In this embodiment, when optimizing the circuit to be optimized, any quantum gate can be selected from the second candidate queue as the current quantum gate, and then after the current quantum gate is removed from the circuit to be optimized, the performance index value of the circuit to be optimized after the quantum gate is removed is calculated, and it is determined whether the calculated performance index value is greater than the preset index threshold value. If it is, the circuit to be optimized after the quantum gate is removed is used as the final target circuit; if it is not, after the current quantum gate is deleted from the second candidate queue, any quantum gate can be selected from the second candidate queue as the current quantum gate, and after the current quantum gate is removed from the circuit to be optimized, the performance index value of the circuit to be optimized after the quantum gate is removed is calculated, and it is determined whether the calculated performance index value is greater than the preset index threshold value. If it is, the circuit to be optimized after the quantum gate is removed is used as the final target circuit; if it is not, the current quantum gate is deleted from the second candidate queue until the performance index value of the circuit to be optimized after the quantum gate is removed is greater than the preset index threshold value, or there is no quantum gate in the second candidate queue. Further, when there is no quantum gate in the second candidate queue, the circuit to be optimized can be used as the final target circuit.

[0147] For example, the present application can implement micro search through the following process:

[0148] 1. Input: Circuit to be optimized with an RF score greater than 1 , the number of candidates ;

[0149] 2. Treat the optimized circuit The quantum gates in quantum gates, forming a candidate queue ;

[0150] 3. Calculate From the circuit to be optimized The RF value after removal. If the RF value is less than 1, check Repeat this step until the RF value is still greater than 1, then update the circuit to be optimized. ;

[0151] 4. If all the second candidate queues If none of them meet the requirements, the circuit to be optimized is output as the final target circuit, otherwise return to step 2.

[0152] The quantum circuit optimization design device provided in an embodiment of the present application is described below. The quantum circuit optimization design device described below and the quantum circuit optimization design method described above can be referenced to each other.

[0153] In one embodiment, Figure 4 As shown, Figure 4 A schematic diagram of the structure of a quantum circuit optimization design device provided in an embodiment of the present application; the present application also provides a quantum circuit optimization design device, which may include a quantum circuit acquisition module 210, a candidate queue adjustment module 220, a circuit determination module 230 to be optimized, and a quantum circuit optimization module 240, specifically including the following:

[0154] The quantum circuit acquisition module 210 is used to acquire an initial quantum circuit structure pool consisting of a plurality of initial quantum circuits and a first candidate queue consisting of blank circuits.

[0155] The candidate queue adjustment module 220 is used to expand the circuits in the first candidate queue according to each initial quantum circuit, and adjust the size of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue.

[0156] The circuit to be optimized determining module 230 is used to select a circuit whose performance indicator value meets a preset score from the adjusted first candidate queue as a circuit to be optimized, and randomly select a plurality of quantum gates from the circuit to be optimized to form a second candidate queue.

[0157] The quantum circuit optimization module 240 is used to optimize the circuit to be optimized according to each quantum gate in the second candidate queue to obtain a final target circuit.

[0158] In the above embodiment, when designing a quantum circuit, an initial quantum circuit structure pool consisting of multiple initial quantum circuits and a first candidate queue consisting of blank circuits can be first obtained; then the circuits in the first candidate queue are expanded according to each initial quantum circuit, and the scale of the expanded first candidate queue is adjusted according to the performance index value of each circuit in the expanded first candidate queue, and then the circuit whose performance index value meets the preset score is selected from the adjusted first candidate queue as the circuit to be optimized. Then, the present application can randomly select multiple quantum gates from the circuit to be optimized to form a second candidate queue, and then optimize the circuit to be optimized according to each quantum gate in the second candidate queue to obtain the final target circuit. Two rounds of search frameworks are designed in this process. The first round of search framework first performs a round of rough search to effectively evaluate and optimize the expression ability and training gradient stability of the quantum circuit according to the performance index value, and quickly find the circuit to be optimized that can meet the specific QNN training requirements, and then on the basis of the circuit to be optimized, try to reduce the redundant quantum gates in the circuit to be optimized, thereby reducing circuit overhead and improving computing efficiency.

[0159] In one embodiment, the present application also provides a computer-readable storage medium, in which computer-readable instructions are stored. When the computer-readable instructions are executed by one or more processors, the one or more processors execute the steps of the quantum circuit optimization design method described in any one of the above embodiments.

[0160] In one embodiment, the present application also provides a computer device, including: one or more processors, and a memory.

[0161] The memory stores computer-readable instructions, and when the computer-readable instructions are executed by the one or more processors, the steps of the quantum circuit optimization design method described in any one of the above embodiments are performed.

[0162] Indicatively, if Figure 5 As shown, Figure 5 This is a schematic diagram of the internal structure of a computer device provided in an embodiment of the present application. The computer device 300 may be provided as a server. Figure 5 The computer device 300 includes a processing component 302, which further includes one or more processors, and a memory resource represented by a memory 301 for storing instructions executable by the processing component 302, such as an application. The application stored in the memory 301 may include one or more modules, each corresponding to a set of instructions. In addition, the processing component 302 is configured to execute instructions to perform the quantum circuit optimization design method of any of the above embodiments.

[0163] The computer device 300 may further include a power supply component 303 configured to perform power management of the computer device 300, a wired or wireless network interface 304 configured to connect the computer device 300 to a network, and an input / output (I / O) interface 305. The computer device 300 may operate based on an operating system stored in the memory 301, such as Windows Server TM, Mac OS X TM, Unix TM, Linux TM, Free BSD TM, or the like.

[0164] Those skilled in the art will understand that Figure 5 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0165] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0166] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The various embodiments can be combined as needed, and the same or similar parts can refer to each other.

[0167] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A quantum circuit optimization design method, characterized in that: The method comprises: Acquire an initial quantum circuit structure pool consisting of a plurality of initial quantum circuits and a first candidate queue consisting of blank circuits; Expanding the circuits in the first candidate queue according to each initial quantum circuit, and adjusting the size of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue; Selecting a circuit whose performance index value meets a preset score from the adjusted first candidate queue as a circuit to be optimized, and randomly selecting a plurality of quantum gates from the circuit to be optimized to form a second candidate queue; The circuit to be optimized is optimized according to each quantum gate in the second candidate queue to obtain a final target circuit.

2. The quantum circuit optimization design method according to claim 1, characterized in that: The step of expanding the circuits in the first candidate queue according to the initial quantum circuits to obtain an expanded first candidate queue includes: Ranking each circuit in the first candidate queue, selecting the circuit ranked first, and randomly selecting other circuits from the remaining circuits; Expanding the first-ranked circuit and the other circuits respectively according to the initial quantum circuits to obtain a third candidate queue consisting of a plurality of expanded circuits; The first candidate queue is expanded according to the performance indicator value of each expansion circuit in the third candidate queue to obtain an expanded first candidate queue.

3. The quantum circuit optimization design method according to claim 2, characterized in that: The step of expanding the first candidate queue according to the performance indicator value of each expansion circuit in the third candidate queue to obtain the expanded first candidate queue includes: Calculating the performance index value of each expansion circuit in the third candidate queue; According to the performance indicator value of each expansion circuit, several expansion circuits are selected from the third candidate queue and added to the first candidate queue to obtain an expanded first candidate queue.

4. The quantum circuit optimization design method according to claim 3, characterized in that: The calculating the performance indicator value of each expansion circuit in the third candidate queue includes: Determining a performance indicator value to be calculated, and a Hamiltonian and a sampling number corresponding to the performance indicator value; By combining Clifford gates, the continuous time evolution described by the Hamiltonian is discretized to obtain a discretized parameter value combination; For each revolving door in each extension circuit in the third candidate queue, at each sampling, randomly select any one parameter value in the parameter value combination as the parameter value of the revolving door, and after modifying the extension circuit according to the selected parameter value, calculate the performance indicator value of the modified extension circuit until the sampling number is reached; The performance index value calculated after each sampling in each expansion circuit is obtained, and the performance index value of each expansion circuit is calculated according to the variance corresponding to each performance index value.

5. The quantum circuit optimization design method according to any one of claims 1 to 4, characterized in that: The adjusting the size of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue includes: Calculate the performance index value of each circuit in the expanded first candidate queue to obtain a calculation result; The circuits in the expanded first candidate queue are sorted in descending order according to the calculation result, and the size of the expanded first candidate queue is adjusted according to the sorting result and a preset size threshold.

6. The quantum circuit optimization design method according to any one of claims 1 to 4, characterized in that: The step of selecting a circuit whose performance indicator value satisfies a preset score from the adjusted first candidate queue as a circuit to be optimized, and randomly selecting a plurality of quantum gates from the circuit to be optimized to form a second candidate queue includes: Determine whether the circuit with the highest performance indicator value in the adjusted first candidate queue meets a preset score; If the conditions are met, the circuit that meets the preset score is used as the circuit to be optimized, and a plurality of quantum gates are randomly selected from the circuit to be optimized to form a second candidate queue; If not satisfied, after updating the first candidate queue according to the adjusted first candidate queue, return to execute the step of expanding the circuits in the first candidate queue according to each initial quantum circuit, and adjusting the scale of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue.

7. The quantum circuit optimization design method according to any one of claims 1 to 4, characterized in that: The step of optimizing the circuit to be optimized according to each quantum gate in the second candidate queue to obtain a final target circuit includes: Selecting any one quantum gate from the second candidate queue as the current quantum gate; After removing the current quantum gate from the circuit to be optimized, determining whether the performance index value of the circuit to be optimized after the quantum gate is removed is greater than a preset index threshold; If yes, the circuit to be optimized after removing the quantum gate is used as the final target circuit; Otherwise, after deleting the current quantum gate from the second candidate queue, continue to perform the steps of selecting any quantum gate from the second candidate queue as the current quantum gate and subsequent steps until the performance index value of the circuit to be optimized after the quantum gate is removed is greater than the preset index threshold, or there is no quantum gate in the second candidate queue; When there is no quantum gate in the second candidate queue, the circuit to be optimized is used as the final target circuit.

8. A quantum circuit optimization design device, characterized in that: include: A quantum circuit acquisition module, used to acquire an initial quantum circuit structure pool consisting of a plurality of initial quantum circuits, and a first candidate queue consisting of blank circuits; A candidate queue adjustment module, configured to expand the circuits in the first candidate queue according to each initial quantum circuit, and adjust the size of the expanded first candidate queue according to the performance indicator value of each circuit in the expanded first candidate queue; A circuit to be optimized determining module, used to select a circuit whose performance indicator value meets a preset score from the adjusted first candidate queue as a circuit to be optimized, and randomly select a plurality of quantum gates from the circuit to be optimized to form a second candidate queue; A quantum circuit optimization module is used to optimize the circuit to be optimized according to each quantum gate in the second candidate queue to obtain a final target circuit.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-readable instructions, and when the computer-readable instructions are executed by one or more processors, the one or more processors execute the steps of the quantum circuit optimization design method according to any one of claims 1 to 7.

10. A computer device, characterized in that: include: one or more processors, and memory; The memory stores computer-readable instructions, and when the computer-readable instructions are executed by the one or more processors, the steps of the quantum circuit optimization design method according to any one of claims 1 to 7 are performed.

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