Display device and electronic equipment

Abstract

The application discloses a display device and electronic equipment. The display device comprises a data line, a plurality of data lines are arranged in a first direction, the data line extends along a second direction, the first direction and the second direction intersect, the data line comprises a first data line, the first data line is electrically connected to a first sub-pixel column, the first sub-pixel column comprises a first sub-pixel and a second sub-pixel arranged alternately in the second direction, the first sub-pixel and the second sub-pixel in the same row are arranged alternately in the first direction, the light-emitting colors of the first sub-pixel and the second sub-pixel are different, and at least two first data lines are electrically connected to a first transistor; a driving chip comprises a first signal end, the first signal end is electrically connected to the first data line, and the first signal end does not output a data signal when the first transistor is turned on. According to the display device and electronic equipment provided by the embodiment of the application, the power consumption of the driving chip in the display device can be reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device and electronic equipment. BACKGROUND

[0002] With the development of display technology, the application of display devices is more and more common, and the performance requirements of users for display devices are also more and more high. For example, users hope that the display device has longer endurance, therefore, how to reduce the power consumption of the display device and improve the endurance of the display device is a technical problem faced by those skilled in the art. SUMMARY

[0003] The embodiments of the present application provide a display device and electronic equipment, which can reduce the power consumption of the driving chip in the display device.

[0004] In a first aspect, the embodiments of the present application provide a display device, comprising: a data line, a plurality of data lines are arranged in a first direction, the data line extends along a second direction, the first direction and the second direction intersect, the data line comprises a first data line, the first data line is electrically connected to a first sub-pixel column, the first sub-pixel column comprises first sub-pixels and second sub-pixels arranged alternately in the second direction, and the first sub-pixels and the second sub-pixels in the same row are arranged alternately in the first direction, the light-emitting colors of the first sub-pixels and the second sub-pixels are different, and a first transistor is electrically connected between at least two first data lines; a driving chip, comprising a first signal end, the first signal end is electrically connected to the first data line, and the first signal end does not output a data signal when the first transistor is turned on.

[0005] In a second aspect, the embodiments of the present application provide an electronic equipment, comprising the display device as described in the first aspect.

[0006] According to the display device and electronic equipment provided by the embodiments of the present application, when the first transistor is turned on, the two first data lines are short-circuited, the charges on the two first data lines are shared first, and then the charges are provided by the driving signal to charge or discharge the two first data lines, so as to reach the target data voltage required by each other, the amount of charge output by the driving chip is reduced, the power consumption of the driving chip is reduced, and the endurance of the display device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0007] Other characteristics, objects and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments with reference to the attached drawings, wherein the same or similar reference signs refer to the same or similar features, and the drawings are not drawn according to the actual scale.

[0008] Figure 1 Fig. 1 shows a structure schematic diagram of a display device provided by an embodiment of the present application;

[0009] Figure 2 Fig. 1 shows a timing diagram of the display device provided by an embodiment of the present application;

[0010] Figure 3 Fig. 2 shows another structural diagram of the display device provided by an embodiment of the present application;

[0011] Figure 4 Fig. 3 shows yet another structural diagram of the display device provided by an embodiment of the present application;

[0012] Figure 5 Fig. 4 shows yet another structural diagram of the display device provided by an embodiment of the present application;

[0013] Figure 6 Fig. 5 shows a working mode diagram of the display device provided by an embodiment of the present application;

[0014] Figure 7 Fig. 6 shows another working mode diagram of the display device provided by an embodiment of the present application;

[0015] Figure 8 Fig. 7 shows another timing diagram of the display device provided by an embodiment of the present application;

[0016] Figure 9 Fig. 8 shows a circuit structural diagram of a sub-pixel in the display device provided by an embodiment of the present application;

[0017] Figure 10 Fig. 9 shows a timing diagram of the display device provided by an embodiment of the present application; Figure 9

[0018] Figure 11 Fig. 10 shows a structural diagram of the electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0019] The features and exemplary embodiments of various aspects of the present application will be described in detail below, in order to make the purposes, technical solutions and advantages of the present application more clear and apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are configured only to explain the present application, and are not configured to limit the present application. The present application can be implemented without some of these specific details by those skilled in the art. The following description of the embodiments is merely to provide a better understanding of the present application by showing examples of the present application.

[0020] ​It should be noted that, in this document, the terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between such entities or operations. Also, the terms "comprises", "comprising", or any other variations thereof are intended to cover non-exclusive inclusions, so that a process, method, article, or apparatus including a series of elements includes not only those elements, but also other elements not explicitly listed, or other elements inherent in such a process, method, article, or apparatus. Without more limitations, the elements defined by the statement "comprise" do not exclude the presence of other identical elements in the process, method, article, or apparatus including the elements.

[0021] It should be understood that, when describing the structure of a component, when one layer, one region is referred to as being "on" or "above" another layer, another region, it can mean being directly on or above another layer, another region, or other layers or regions are included therebetween. And if the component is turned over, the layer, the region will be "under" or "below" the other layer, the other region.

[0022] It should be understood that the term "and / or" used herein is only to describe the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A alone, A and B together, and B alone. In addition, the character " / " in this document generally represents an "or" relationship between the front and rear associated objects.

[0023] In the embodiments of the present application, the term "electrically connected" can mean that two components are directly electrically connected, or that two components are electrically connected via one or more other components.

[0024] Various modifications and changes can be made to the present application without departing from the spirit or scope of the present application, which will be apparent to one skilled in the art. Therefore, the present application is intended to cover the modifications and variations of the present application falling within the scope of the corresponding claims (claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by the present application can be combined with each other without contradiction.

[0025] The present application provides a display device and an electronic device, which will be described below with reference to the accompanying drawings.

[0026] As shown in FIG. 1, Figure 1 The display device 100 provided by the embodiments of the present application includes a data line 10, a sub-pixel 20, and a driving chip 30.

[0027] The driving chip 30 is configured to output data signals, and the data signals output by the driving chip are transmitted to the sub-pixels 20 through the data lines 10. The sub-pixels 20 emit light or present a black state according to the received data signals.

[0028] The plurality of data lines 10 are arranged in a first direction X, and the data lines 10 extend along a second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X is a row direction, and the second direction Y is a column direction.

[0029] The plurality of sub-pixels 20 are arranged in an array in the first direction X and the second direction Y. The display device includes a first sub-pixel column 20a, and the first sub-pixel column 20a includes first sub-pixels 21 and second sub-pixels 22 arranged alternately in the second direction Y. The first sub-pixels 21 and the second sub-pixels 22 have different light-emitting colors. The first sub-pixels 21 and the second sub-pixels 22 in the same row are arranged in an overlapping manner in the first direction X.

[0030] For example, one of the first sub-pixels 21 and the second sub-pixels 22 is a red sub-pixel, and the other is a blue sub-pixel.

[0031] The data lines 10 include a first data line 11, and the first data line 11 is electrically connected to the first sub-pixel column 20a. The first data line 11 is electrically connected to the first sub-pixels 21 and the second sub-pixels 22, and the first data line 11 transmits data signals required by the first sub-pixels 21 and the second sub-pixels 22 in time division.

[0032] The display device includes a plurality of first sub-pixel columns 20a arranged in the first direction X, and the plurality of first sub-pixel columns 20a correspond to the plurality of first data lines 11 in one-to-one correspondence. The first transistors T1 are electrically connected between at least two first data lines 11.

[0033] One of the first data lines 11 is electrically connected to the first electrode of the first transistor T1, and the other first data line 11 is electrically connected to the second electrode of the first transistor T2. The gate electrode of the first transistor T1 is electrically connected to the first control signal line SW1.

[0034] For example, two first data lines 11 form a first data line group, and the first transistors T1 are electrically connected between the two first data lines 11 in the same first data line group. The first data lines in different first data line groups are not connected. For example, the total number of the first data lines 11 is 2m, and the total number of the first transistors T1 is m. One first transistor T1 is electrically connected between every two first data lines 11.

[0035] The driving chip 30 includes a first signal terminal 31, and the first signal terminal 31 is electrically connected to the first data line 11. The first signal terminal 31 is configured to output data signals required by the first sub-pixels 21 and the second sub-pixels 22. The first signal terminal 31 does not output data signals when the first transistor T1 is turned on.

[0036] The display device includes a display region AA and a non-display region NA, for example. The sub-pixel 10 is located in the display region AA, and the first transistor T1 is located in the non-display region NA.

[0037] The gates of the plurality of first transistors T1 are electrically connected to the same first control signal line SW1, which is electrically connected to the driving chip 30 (not shown in the figure). The driving chip 30 outputs a first control signal to the gates of the first transistors T1 through the first control signal line SW1, thereby controlling the states of the first transistors T1.

[0038] When the first transistor T1 is turned on, the two first data lines 11 connected to the first transistor T1 are in communication, the charges on the two first data lines 11 are shared, and the voltages on the two first data lines 11 are approximately pulled to the average position. For example, the initial voltages on the two first data lines 11 are V1 and V2 respectively, V1 is greater than V2, the first transistor T1 is turned on, the voltage on the first data line 11 with the initial voltage V1 is pulled down to V1-((V1-V2) / 2), and the voltage on the first data line 11 with the initial voltage V2 is pulled up to V2+((V1-V2) / 2).

[0039] The working process of the display device will be described below by taking the first sub-pixel 21 as a red sub-pixel, the second sub-pixel 22 as a blue sub-pixel, and the display device as an example of displaying a pure red picture.

[0040] When displaying a pure red picture, the target data voltage required by the first sub-pixel 21 is 3.5V for example, and the target data voltage required by the second sub-pixel 22 is 7V for example (7V is the black state voltage of the second sub-pixel 22), Figure 1 In the left-to-right direction, the first first data line to the last first data line are arranged respectively, in a frame of picture, each row of sub-pixels is scanned in the top-to-bottom direction, and in the scanning stage corresponding to each row of sub-pixels, the voltage of the first first data line 11_1 in a frame of picture needs to be 3.5V, 7V, 3.5V, 7V, … 3.5V, 7V, and the voltage of the second first data line 11_2 in a frame of picture needs to be 7V, 3.5V, 7V, … 7V, 3.5V.

[0041] The first transistor can be turned on before each row of sub-pixels is scanned, wherein the signal on the data line is written into the sub-pixel when the sub-pixel is scanned.

[0042] Please refer to Figure 1 and Figure 2The first row of sub-pixels to the last row of sub-pixels are arranged in the second direction Y and close to the driving chip 30 in sequence. Taking the second row of sub-pixels as an example, before scanning the second row of sub-pixels, the first transistor T1 is turned on in a time period d1. A time period d0 before the time period d1 is a time period after the first row of sub-pixels is scanned. A time period d2 after the time period d1 includes a time period in which the second row of sub-pixels is scanned.

[0043] In the time period d0, the voltage of the first first data line 11_1 is 3.5V, and the voltage of the second first data line 11_2 is 7V.

[0044] In the time period d1, the first transistor T1 is turned on, and the charges are shared between the first first data line 11_1 and the second first data line 11_2. The voltage of the first first data line 11_1 is pulled up to 5.25V, and the voltage of the second first data line 11_2 is pulled down to 5.25V.

[0045] In the time period d2, the first transistor T1 is turned off, the first signal end 31 of the driving chip 30 outputs a 7V voltage to the first first data line 11_1 and outputs a 3.5V voltage to the second first data line 11_2. The voltage of the first first data line 11_1 is charged from 5.25V to 7V, and the voltage of the second first data line 11_2 is discharged from 5.25V to 3.5V.

[0046] If the first transistor does not short the first first data line 11_1 and the second first data line 11_2 in the time period d1, the voltage provided by the first signal end 31 of the driving chip 30 needs to charge the voltage of the first first data line 11_1 from 3.5V to 7V and discharge the voltage of the second first data line 11_2 from 7V to 3.5V. It can be seen that, in the case that the first transistor shorts the first first data line 11_1 and the second first data line 11_2 in the time period d1, the charges on the two first data lines are shared first, and then the driving signal provides the charges to charge or discharge the two first data lines, so as to reach the respective target data voltages. The amount of charge output by the driving chip can be reduced, thereby reducing the power consumption of the driving chip and improving the endurance of the display device.

[0047] In some embodiments, as shown in FIG. 1, the data line 10 further includes a second data line 12 electrically connected to a second sub-pixel column 20b including a plurality of third sub-pixels 23 arranged in the second direction Y. Figure 1 The light-emitting colors of the first sub-pixels 21, the second sub-pixels 22, and the third sub-pixels 23 are different from each other. For example, one of the first sub-pixels 21 and the second sub-pixels 22 is a red sub-pixel, and the other is a blue sub-pixel; and the third sub-pixels 23 are green sub-pixels.

[0048] For example, the arrangement sequence of the sub-pixels in one of the two adjacent rows is RGBG, and the arrangement sequence of the sub-pixels in the other row is GBRG, where RGB represents a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively.

[0049] The driving chip 30 further includes a second signal terminal 32 electrically connected with the second data line 12. When the first transistor T1 is turned on, the second signal terminal 32 outputs a data signal.

[0050] The second data line 12 is electrically connected with sub-pixels of the same light-emitting color. When a pure red image or a pure blue image is displayed, the voltage of the second data line 12 does not jump. Therefore, no charge sharing is required between different second data lines 12.

[0051] When the first transistor T1 is turned on, the second signal terminal 32 still outputs a data signal, which charges the second data line 12, thereby increasing the charging time of the third sub-pixel 23 and ensuring that the data voltage of the third sub-pixel 23 can be fully written.

[0052] In some embodiments, as shown in Figure 3 or Figure 4 The second data line 12 is connected with a compensation structure 4, which is used to compensate the load of the second data line 12.

[0053] When a white image is displayed, the first transistor T1 is turned off. However, the first transistor T1 connected with the first data line 11 constitutes a load of the first data line 11. If the second data line 12 does not increase the load compensation structure, the loads on the first data line 11 and the second data line 12 will be different, thereby causing display non-uniformity.

[0054] In this embodiment, the second data line is connected with a load compensation structure to balance the loads of the first data line and the second data line, thereby improving display uniformity.

[0055] For example, the compensation structure is located in the non-display area. For example, the compensation structure is located on the side of the display area close to the driving chip.

[0056] For example, as shown in Figure 3 The compensation structure 4 includes a second transistor T2. The second transistor T2 is electrically connected between at least two second data lines 12 and remains in an off state.

[0057] The first electrode of the second transistor T2 is connected to one of the second data lines 12, the second electrode of the second transistor T2 is connected to the other second data line 12, the gate of the second transistor T2 is connected to the second control signal line SW2, and the signal on the second control signal line SW2 is maintained at a non-enable level (for example, the second transistor is a P-type transistor, and the non-enable level is a high level).

[0058] Exemplarily, every two first data lines 11 form a first data line group, a first transistor T1 is electrically connected between the two first data lines 11 in the same first data line group, and the first data lines of different first data line groups are not connected; similarly, every two second data lines 12 form a second data line group, a second transistor T2 is electrically connected between the two second data lines 12 in the same second data line group, and the second data lines of different second data line groups are not connected.

[0059] Exemplarily, the characteristics of the first transistor T1 and the second transistor T2 are the same. For example, both are P-type transistors and have the same size, where "size" includes channel aspect ratio, channel area, channel length, channel width, etc.

[0060] As another example, Figure 4 As shown, the compensation structure 4 includes a capacitor C1, the other end of which is electrically connected to a fixed signal terminal, such as a power signal terminal PVDD, a common signal terminal PVEE, a reference signal terminal Vref, a high level signal terminal VGH, a low level signal terminal VGL, and the like.

[0061] For example, the capacitance of the capacitor C1 is set according to requirements.

[0062] As described in the above embodiment, when the first transistor T1 is turned on, the first signal terminal 31 of the driver chip does not output a data signal, but the second signal terminal 32 still outputs a data signal.

[0063] In some embodiments, the display device 100 further includes a first demultiplexing circuit 51 and a second demultiplexing circuit 52 .

[0064] An input terminal of the first demultiplexing circuit 51 is electrically connected to the first signal terminal 31 , and multiple output terminals of the first demultiplexing circuit 51 are electrically connected to the multiple first data lines 11 in a one-to-one correspondence.

[0065] An input terminal of the second demultiplexing circuit 52 is electrically connected to the second signal terminal 32 , and multiple output terminals of the second demultiplexing circuit 52 are electrically connected to the multiple second data lines 12 in a one-to-one correspondence.

[0066] The first demultiplexing circuit 51 and the second demultiplexing circuit 52 each include one input terminal and multiple output terminals, so that one first signal terminal can output data signals to multiple first data lines in time division through the first demultiplexing circuit, and one second signal terminal can output data signals to multiple second data lines in time division through the second demultiplexing circuit, thereby reducing the number of signal terminals of the driving chip and reducing the cost of the driving chip.

[0067] As an example, the first demultiplexing circuit 51 includes a third transistor T3 and a fourth transistor T4, the first poles of the third transistor T3 and the fourth transistor T4 are electrically connected to the first signal terminal 31, and the second poles of the third transistor T3 and the fourth transistor T4 are respectively electrically connected to different first data lines 11. The third transistor T3 and the fourth transistor T4 are turned on in time division.

[0068] The second demultiplexing circuit 52 includes a fifth transistor T5 and a sixth transistor T6, the first poles of the fifth transistor T5 and the sixth transistor T6 are electrically connected to the second signal terminal 32, and the second poles of the fifth transistor T5 and the sixth transistor T6 are respectively electrically connected to different second data lines 12. The fifth transistor T5 and the sixth transistor T6 are turned on in time division.

[0069] In addition, when the first transistor T1 is turned on, the third transistor T3 and the fourth transistor T4 are both turned off, and the fifth transistor T5 and the sixth transistor T6 are turned on in time division. In this way, the data signals output by the second signal terminal 32 can be transmitted to different second data lines 12 in time division through the fifth transistor T5 and the sixth transistor T6.

[0070] In some embodiments, as shown in Figure 6 or Figure 7 The display device includes multiple sub-pixel rows 20c arranged in the second direction Y. The working process of the display device includes a first mode and a second mode. The sub-pixels in the first mode work as the first sub-pixel row 20c1, and the sub-pixels in the second mode work as the second sub-pixel row 20c2. The first sub-pixel row 20 c The first transistor corresponding to the first sub-pixel row 20c1 is turned on for a first time length, and the first transistor corresponding to the second sub-pixel row 20c2 is turned on for a second time length. The first time length is not equal to the second time length.

[0071] For example, in one frame of picture, each row of sub-pixels is scanned in the direction from top to bottom, and in the scanning stage corresponding to each row of sub-pixels, the first transistor can be turned on before each row of sub-pixels is scanned. Here, the first sub-pixel row 20 c1, can be understood as: the conduction time length of the first transistor before the first sub-pixel row 20c1 is scanned. The conduction time length of the first transistor corresponding to the second sub-pixel row 20c2 can be understood as: the conduction time length of the first transistor before the second sub-pixel row 20c2 is scanned. For example, the first sub-pixel row 20 c 1 includes the second row of sub-pixels, and the conduction time length of the first transistor corresponding to the second row of sub-pixels is: the conduction time length of the first transistor before the second row of sub-pixels are scanned and after the first row of sub-pixels are scanned.

[0072] In this embodiment, in different modes, the conduction time of the first transistor is different, which can flexibly adapt to different requirements of different modes to achieve better power saving effect.

[0073] As an example, Figure 6 As shown, the first sub-pixel row 20c1 and the second sub-pixel row 20c2 are sub-pixel rows at different positions.

[0074] For example, the display area of ​​the display device includes a first display area A1 and a second display area A2. The sub-pixel row in the first display area A1 is a first sub-pixel row 20c1, and the sub-pixel row in the second display area A2 is a second sub-pixel row 20c2.

[0075] For example, the first display area A1 and the second display area A2 display different images. For example, the first display area A1 displays a pure red image with a grayscale of 100, and the second display area A2 displays a pure red image with a grayscale of 200.

[0076] As another example, Figure 7 As shown, the first sub-pixel row 20c1 is a sub-pixel row in the first frame, and the second sub-pixel row 20c2 is a sub-pixel row in the second frame.

[0077] For example, in the first frame, all sub-pixel rows of the display device display a pure red image with a grayscale of 255; in the second frame, all sub-pixel rows of the display device display a pure red image with a grayscale of 100; when displaying the first frame, all sub-pixel rows of the display device serve as the first sub-pixel row 20. c 1; when displaying the second frame, all sub-pixel rows of the display device serve as the second sub-pixel rows 20c2.

[0078] As another example, the first sub-pixel row is refreshed at a first refresh frequency, and the second sub-pixel row is refreshed at a second refresh frequency. The first refresh frequency and the second refresh frequency are different.

[0079] For example, Figure 6 As shown, the first subpixel row 20 cThe first sub-pixel row 20c1 and the second sub-pixel row 20c2 are sub-pixel rows at different positions, and the first sub-pixel row 20c1 and the second sub-pixel row 20c2 are refreshed at different refresh frequencies.

[0080] For example, the display area of ​​the display device includes a first display area A1 and a second display area A2. The sub-pixel row in the first display area A1 is a first sub-pixel row 20c1, and the sub-pixel row in the second display area A2 is a second sub-pixel row 20c2.

[0081] In Example 1, the first display area A1 and the second display area A2 display the same solid color image, but have different refresh rates. For example, the first display area A1 and the second display area A2 both display a 200-grayscale pure red image, with a refresh rate of 90 Hz for the first display area A1 and 15 Hz for the second display area A2.

[0082] Example 2: The first display area A1 and the second display area A2 display different images, and the refresh rates of the first display area A1 and the second display area A2 are different. For example, the first display area A1 displays a pure red image with a grayscale of 50, and the second display area A2 displays a pure red image with a grayscale of 150. The refresh rate of the first display area A1 is 120 Hz, and the refresh rate of the second display area A2 is 30 Hz.

[0083] For example, Figure 7 As shown, the first sub-pixel row 20c1 is a sub-pixel row in the first frame, and the second sub-pixel row 20c2 is a sub-pixel row in the second frame. The first sub-pixel row 20c1 and the second sub-pixel row 20c2 are refreshed at different refresh frequencies.

[0084] Example 3: The grayscale images of the first frame and the second frame are the same (for example, both are 210 grayscale pure red images). In the first frame, all sub-pixel rows of the display device are scanned at a refresh rate of 90 Hz; in the second frame, all sub-pixel rows of the display device are scanned at a refresh rate of 60 Hz. When displaying the first frame, all sub-pixel rows of the display device are used as the first sub-pixel row 20. c 1; when displaying the second frame, all sub-pixel rows of the display device serve as the second sub-pixel rows 20c2.

[0085] In Example 4, the gray scale pictures of the first frame picture and the second frame picture are different, and the refresh frequencies are different. In the first frame picture, all the sub-pixel rows of the display device display a 15 gray scale pure red picture, and are scanned at a refresh frequency of 15 Hz; in the second frame picture, all the sub-pixel rows of the display device display a 90 gray scale pure red picture, and are scanned at a refresh frequency of 60 Hz. When the first frame picture is displayed, all the sub-pixel rows of the display device are the first sub-pixel row 20c1; when the second frame picture is displayed, all the sub-pixel rows of the display device are the second sub-pixel row 20c2.

[0086] In some embodiments, the first sub-pixel row is refreshed at a first refresh frequency, the second sub-pixel row is refreshed at a second refresh frequency, and the first time length is greater than the second time length when the first refresh frequency is less than the second refresh frequency.

[0087] The smaller the refresh frequency is, the longer the scanning time to which the sub-pixel row is divided is, and in this case, the turn-on time length of the first sub-pixel can be appropriately lengthened to ensure that the charge sharing between the first data lines can be better.

[0088] The greater the refresh frequency is, the shorter the scanning time to which the sub-pixel row is divided is, and in this case, the turn-on time length of the first sub-pixel can be appropriately shortened to ensure that there is sufficient time for the signal on the first data line to be fully written into the sub-pixel.

[0089] In some embodiments, as shown in Figure 1 The display device includes a plurality of sub-pixel rows 20c arranged in a second direction Y; the sub-pixel rows include a next sub-pixel row and a previous sub-pixel row; the next sub-pixel row is scanned after the previous sub-pixel row is scanned.

[0090] The i-th first data line and the j-th first data line are electrically connected to the k-th first transistor.

[0091] The data voltages to be written into the first sub-pixel and the second sub-pixel in the next sub-pixel row and electrically connected to the k-th first transistor are respectively a first target data voltage and a second target data voltage; the data voltages already written into the second sub-pixel and the first sub-pixel in the previous sub-pixel row and electrically connected to the k-th first transistor are respectively a first current data voltage and a second current data voltage; the difference between the first target data voltage and the first current data voltage corresponding to the i-th first data line is a first difference, and the difference between the second target data voltage and the second current data voltage corresponding to the j-th first data line is a second difference; the greater the sum of the absolute values of the first difference and the second difference is, the longer the turn-on time of the k-th first transistor is after the previous sub-pixel row is scanned and before the current sub-pixel row is scanned.

[0092] Please refer to Figure 1 and Figure 8For example, the first sub-pixel behavior is the first sub-pixel row 20c_1, the next sub-pixel behavior is the second sub-pixel row 20c_2, the i-th first data line 11_i is the first first data line 11_1, the j-th first data line 11_j is the second first data line 11_2, and the k-th first transistor T1 is electrically connected between the first first data line 11_1 and the second first data line 11_2. _ k.

[0093] After the first sub-pixel row 20c _ 1 is scanned, the voltage on the first first data line 11_1 is the first current data voltage V1_current, and the voltage on the second first data line 11_2 is the second current data voltage V2_current. The first target data voltage V1_target needs to be written into the sub-pixel connected to the first first data line 11_1 in the second sub-pixel row 20c_2, and the second target data voltage V2_target needs to be written into the sub-pixel connected to the second first data line 11_2 in the second sub-pixel row 20c_2. The first difference AV1 = V1_target - V1_current, and the second difference AV2 = V2_target - V2_current.

[0094] For example, V1_target > V1_current, V2_target < V2_current, and the greater the sum of the absolute values of the first difference AV1 and the second difference AV2, the more the voltage on the first first data line 11_1 needs to be pulled up, and the more the voltage on the second first data line 11_2 needs to be pulled down. In this embodiment, the greater the sum of the absolute values of the first difference AV1 and the second difference AV2, the greater the on duration of the corresponding first transistor is designed, so that the two first data lines have a longer time for charge sharing, thereby better ensuring that the voltages of the two first data lines are pulled to an average level, reducing the amount of charge required to be output by the driving chip, thereby reducing the power consumption of the driving chip.

[0095] In some embodiments, as shown in Figure 1 , the display device includes a plurality of sub-pixel rows 20c arranged in a second direction Y.

[0096] Please refer to Figure 1 , Figure 9 and Figure 10 , each sub-pixel in the sub-pixel row is electrically connected to the first scan line S1, and when the first scan signal of the first scan line S1 is at the on level, the signal on the data line 10 is written into the sub-pixel. The on duration of the first transistor is less than the on duration of the first scan signal.

[0097] Exemplarily, the sub-pixel is further electrically connected with a second scan line S2 and a light emitting control signal line Emit. The working process of the sub-pixel is described below by taking the first transistor and the transistor in the sub-pixel as P-type transistors as an example.

[0098] Please refer to Figure 9 and Figure 10 , the working process of the sub-pixel includes a stage t1, a stage t2 and a stage t3.

[0099] In the stage t1, the signal on the second scan line S2 is at a low level, the transistor M5 in the sub-pixel is turned on, and the reset signal of the reset signal end Vref resets the gate of the driving transistor M3.

[0100] In the stage t2, the signal on the first scan line S1 is at a low level, the transistors M2 and M4 are turned on, the data signal on the data line 10 is written to the gate of the driving transistor M3, and the transistor M4 compensates the threshold voltage of the driving transistor M3.

[0101] In the stage t3, the signal on the light emitting control signal line Emit is at a low level, the transistors M1 and M6 are turned on, the driving transistor M3 generates a driving current, and the sub-pixel enters a light emitting stage. In the case that the driving current is not zero, the sub-pixel emits light. In the case that the driving current is zero, the sub-pixel is in a black state.

[0102] The first transistor can be turned on in a stage t0, for example, the stage t0 is before the stage t1.

[0103] The duration of the stage t0 is less than the duration of the stage t2.

[0104] In the stage t2, the data signal of the data line is written to the sub-pixel. If the time in the stage t2 is longer, the sufficiency of the writing of the data signal can be ensured to avoid affecting the light emitting effect of the sub-pixel.

[0105] The application further provides an electronic device including the display device provided by the application. Please refer to Figure 11 , Figure 11 is a structural schematic diagram of a display device provided by an embodiment of the application. Figure 11 The electronic device 1000 provided by the application includes the display device 100 provided by any of the above embodiments of the application. Figure 11 The embodiment only takes a mobile phone as an example to describe the electronic device 1000. It can be understood that the electronic device provided by the embodiment of the application can be a wearable product, a computer, a television, a vehicle-mounted display device or other electronic devices with a display function, and the application does not specifically limit this. The electronic device provided by the embodiment of the application has the beneficial effects of the display device provided by the embodiment of the application, and specific descriptions of the display device can be referred to the above embodiments, which will not be described herein.

[0106] In accordance with the embodiments of the application described above, the embodiments have not been described in detail with respect to every possible modification and alternative. It is realized that many modifications and variations are possible in light of the above description. It is intended that the specification and examples be considered as exemplary only, with the true scope of the application being indicated by the following claims and their full scope of equivalents.

Claims

1. A display device, characterized by comprising: The display device comprises: a plurality of data lines arranged in a first direction, the data lines extending in a second direction, the first direction and the second direction intersecting, the data lines comprising a first data line, the first data line being electrically connected to a first sub-pixel column, the first sub-pixel column comprising first sub-pixels and second sub-pixels arranged alternately in the second direction, and the first sub-pixels and the second sub-pixels in the same row being arranged alternately in the first direction, the first sub-pixels and the second sub-pixels having different light-emitting colors, and at least two of the first data lines being electrically connected to a first transistor; a driving chip comprising a first signal terminal, the first signal terminal being electrically connected to the first data line, and the first transistor being turned on, the first signal terminal not outputting a data signal.

2. The display device according to claim 1, wherein The data lines further comprise a second data line, the second data line being electrically connected to a second sub-pixel column, the second sub-pixel column comprising a plurality of third sub-pixels arranged in the second direction; The driving chip further comprises a second signal terminal, the second signal terminal being electrically connected to the second data line, and the first transistor being turned on, the second signal terminal outputting a data signal.

3. The display device according to claim 2, wherein The second data line is connected to a compensation structure, the compensation structure being used for compensating for a load of the second data line.

4. The display device according to claim 3, wherein The compensation structure comprises a second transistor, at least two of the second data lines being electrically connected to the second transistor, and the second transistor being kept in a turned-off state.

5. The display device according to claim 3, wherein The compensation structure comprises a capacitor, the other end of the capacitor being electrically connected to a fixed signal terminal.

6. The display device according to claim 2, wherein The display device further comprises: a first demultiplexing circuit, an input terminal of the first demultiplexing circuit being electrically connected to the first signal terminal, and a plurality of output terminals of the first demultiplexing circuit being electrically connected to the first data lines one by one; a second demultiplexing circuit, an input terminal of the second demultiplexing circuit being electrically connected to the second signal terminal, and a plurality of output terminals of the second demultiplexing circuit being electrically connected to the second data lines one by one.

7. The display device according to claim 1, wherein The display device comprises a plurality of sub-pixel rows arranged in the second direction, the sub-pixel rows comprising first sub-pixels and second sub-pixels arranged alternately in the first direction; The working process of the display device comprises a first mode and a second mode, sub-pixels working in the first mode being first sub-pixel rows, and sub-pixels working in the second mode being second sub-pixel rows, a duration of the first transistor corresponding to the first sub-pixel rows being a first duration, and a duration of the first transistor corresponding to the second sub-pixel rows being a second duration, the first duration being different from the second duration.

8. The display device according to claim 7, wherein The first sub-pixel rows and the second sub-pixel rows are different sub-pixel rows.

9. The display device according to claim 7, wherein The first sub-pixel rows are sub-pixel rows in a first frame of pictures, and the second sub-pixel rows are sub-pixel rows in a second frame of pictures.

10. The display device according to claim 7, wherein The first sub-pixel rows are refreshed at a first refresh frequency, and the second sub-pixel rows are refreshed at a second refresh frequency.

11. The display device according to claim 10, wherein The first refresh frequency is smaller than the second refresh frequency, and the first duration is greater than the second duration.

12. The display device according to claim 1, wherein The display device comprises a plurality of sub-pixel rows arranged in the second direction, the first sub-pixels and the second sub-pixels in the sub-pixel rows are arranged alternately in the first direction; The sub-pixel row comprises a next sub-pixel row and a previous sub-pixel row; The next sub-pixel row is scanned after the previous sub-pixel row is scanned; The kth first transistor is electrically connected between the ith first data line and the jth first data line; The first sub-pixel and the second sub-pixel in the next sub-pixel row and electrically connected to the kth first transistor need to write data voltages of a first target data voltage and a second target data voltage respectively; The second sub-pixel and the first sub-pixel in the previous sub-pixel row and electrically connected to the kth first transistor have written data voltages of a first current data voltage and a second current data voltage respectively; The difference between the first target data voltage and the first current data voltage corresponding to the ith first data line is a first difference, and the difference between the second target data voltage and the second current data voltage corresponding to the jth first data line is a second difference; The greater the sum of the absolute value of the first difference and the absolute value of the second difference, the longer the conduction time of the kth first transistor after the previous sub-pixel row is scanned and before the current sub-pixel row is scanned.

13. The display device of claim 1, wherein The display device comprises a plurality of sub-pixel rows arranged in the second direction, the first sub-pixels and the second sub-pixels in the sub-pixel rows are arranged alternately in the first direction; The sub-pixel row is electrically connected to a first scan line, and when the first scan signal of the first scan line is at an on level, the signal on the data line writes the sub-pixel; The conduction time of the first transistor is less than the on level time of the first scan signal.

14. An electronic device, comprising: The display device comprises a plurality of sub-pixel rows arranged in the second direction, the first sub-pixels and the second sub-pixels in the sub-pixel rows are arranged alternately in the first direction;

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