Memory system and operating method thereof

Abstract

The invention provides a memory system and an operating method thereof. The operation method comprises the following steps: inputting tracking data to a tracking array; generating a plurality of tracking logic values through a plurality of tracking unit rows in the tracking array according to the tracking data; counting the tracking logic values to generate a sum value; adjusting a sensing time of a sensing device according to the sum value; performing a calculation operation through a calculation array to generate a plurality of calculation signals; and sensing the calculation signal by the sensing device according to the adjusted sensing time.

Description

Technical Field

[0001] The present disclosure relates to a memory technology, and more particularly to a memory system and an operating method of the memory system. Background Art

[0002] The memory system includes a plurality of memory cells for storing data bits. When the memory system performs a calculation operation, a calculation signal is generated. The threshold voltage level of the memory cell is affected by the ambient temperature, retention time, and the threshold voltage shift induced by disturbance, causing the calculation signal to shift. As a result, the result of sensing the calculation signal is inaccurate. Therefore, how to design to solve the above problems is an important topic in the art. Summary of the invention

[0003] The disclosed embodiment includes an operation method of a memory system. The operation method includes: inputting tracking data into a tracking array; generating multiple tracking logic values ​​through multiple tracking unit rows in the tracking array according to the tracking data; counting the tracking logic values ​​to generate a summed value; adjusting a sensing time of a sensing device according to the summed value; performing a calculation operation through a calculation array to generate multiple calculation signals; and sensing the calculation signals through the sensing device according to the adjusted sensing time.

[0004] In some embodiments, adjusting the sensing time of the sensing device according to the summed value further includes: comparing the summed value with the number of tracking unit rows; adjusting the sensing time when the summed value is different from the number of tracking unit rows; and determining the sensing time when the summed value is equal to the number of tracking unit rows.

[0005] In some embodiments, the operating method further includes: setting the sensing time to a first sensing time; sensing the tracking data and the tracking unit rows according to the first sensing time to generate a plurality of first tracking logic values; counting the first tracking logic values ​​to generate a first summed value; and when the first summed value is equal to the number of tracking unit rows, setting the sensing time to a second sensing time, wherein the second sensing time is less than the first sensing time.

[0006] In some embodiments, the operating method further includes: sensing the tracking data and the tracking unit rows according to a second sensing time to generate multiple second tracking logic values; counting the second tracking logic values ​​to generate a second summed value; when the second summed value is different from the number of tracking unit rows, setting the sensing time to the first sensing time; and sensing the calculation signal through the sensing device according to the first sensing time.

[0007] In some embodiments, the operating method further includes: setting the sensing time to a first sensing time; sensing the tracking data and the tracking unit rows according to the first sensing time to generate a plurality of first tracking logic values; counting the first tracking logic values ​​to generate a first summed value; and when the first summed value is different from the number of tracking unit rows, setting the sensing time to a second sensing time, wherein the second sensing time is greater than the first sensing time.

[0008] In some embodiments, the operating method further includes: sensing the tracking data and the tracking unit rows according to a second sensing time to generate a plurality of second tracking logic values; counting the second tracking logic values ​​to generate a second summed value; when the second summed value is equal to the number of tracking unit rows, setting the sensing time to a third sensing time, wherein the third sensing time is greater than the second sensing time.

[0009] In some embodiments, the operating method further includes: sensing the tracking data and the tracking unit rows according to a third sensing time to generate multiple third tracking logic values; counting the third tracking logic values ​​to generate a third summed value; when the third summed value is equal to the number of tracking unit rows, setting the sensing time to a second sensing time; and sensing the calculation signal through the sensing device according to the second sensing time.

[0010] The disclosed embodiment includes a memory system. The memory system includes a plurality of tracking unit rows, a calculation array, and a sensing device. The tracking unit rows are used to generate a plurality of tracking logic values ​​according to tracking data. The calculation array is used to generate a plurality of calculation signals. The sensing device is used to sense the calculation signal according to a clock signal. The sensing device includes a segment circuit, the segment circuit is used to count the tracking logic values ​​to generate a summed value, when the summed value is different from a preset value, a period of the clock signal is adjusted, and when the summed value is equal to the preset value, the period of the clock signal is determined for sensing the calculation signal.

[0011] In some embodiments, the reference data bits stored in each tracking cell row have P first logic values, and P is a positive integer.

[0012] The disclosed embodiment includes an operation method of a memory system. The operation method includes: counting a plurality of tracking logic values ​​to generate a summed value; comparing the summed value with a preset value; when the summed value is different from the preset value, adjusting a cycle of a clock signal; when the summed value is equal to the preset value, determining the cycle; and performing a calculation operation after determining the cycle and sensing a plurality of calculation signals from the calculation operation according to the cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A is a schematic diagram of a memory system according to an embodiment of the present disclosure.

[0014] Figure 1B The diagram is a schematic diagram of a search operation performed on a portion of a memory system according to an embodiment of the present disclosure.

[0015] Figure 2 is a schematic diagram of a tracking array according to some embodiments of the present disclosure.

[0016] Figure 3 It is a schematic diagram of a portion of a memory system performing a tracking operation according to some embodiments of the present disclosure.

[0017] Figure 4 FIG. 4 is a schematic diagram of a method for adjusting a sensing time by performing a tracking operation in a memory system according to some embodiments of the present disclosure.

[0018] Figure 5 FIG. 4 is a schematic diagram of a method for adjusting a sensing time by performing a tracking operation in a memory system according to some embodiments of the present disclosure.

[0019] Figure 6 A timing diagram of a memory system performing a tracking operation to adjust a sensing time according to some embodiments of the present disclosure is shown.

[0020] Figure 7 A timing diagram of a memory system performing a tracking operation to adjust a sensing time according to some embodiments of the present disclosure is shown.

[0021] Figure 8 is a schematic diagram of a portion of a sensing device according to some embodiments of the present disclosure.

[0022] Fig. 9 The diagram is a schematic diagram of a portion of a memory system performing a computing operation according to some embodiments of the present disclosure.

[0023]

Explanation of symbols

[0024] 100: Memory System

[0025] 110: Three-dimensional memory array

[0026] 120: Sensing device

[0027] 130: Temporary encoding device

[0028] 140: Output device

[0029] CLK: Clock signal

[0030] BK1~BKM:Block

[0031] SSL1~SSLM: string selection line signal

[0032] GSL1~GSLM: Ground selection line signal

[0033] BL0~BL128K: bit line signal

[0034] MC: Memory Cell

[0035] FC0N, FC0N-1: Switching element

[0036] WL0N, WL0N-1, WL00: word line signal

[0037] TKDT: Tracking Data

[0038] SDT2, SDT3, SDTM: Search Data

[0039] 150: Calculation Array

[0040] 152: Sense Amplifier

[0041] 151: Search Data

[0042] CL0~CL128K: memory cell row

[0043] NMB: Number of mismatched bits

[0044] 200: Tracking Array

[0045] 201, 203, 205, 206: Tracking unit rows

[0046] 202: Rectangle

[0047] 204: Arrow

[0048] TKCL0~TKCL128K: Tracking unit line

[0049] SEG0~SEGM: Segment circuit

[0050] TKDTALL1, TKDTALL0: Tracking data

[0051] 400, 500: Method

[0052] OP41~OP46、OP51~OP56:Operation

[0053] 401-405, 501-505: Tracking logical value

[0054] P61~P65、P71~P75:Period

[0055] VH, VL: voltage level

[0056] SEG1~SEGN: Segment circuit

[0057] 901: Computational Array

[0058] 902: Search Data

[0059] 903: Memory cell row DETAILED DESCRIPTION

[0060] In this document, when an element is referred to as being "connected" or "coupled", it may refer to being "electrically connected" or "electrically coupled". "Connected" or "coupled" may also be used to indicate that two or more elements cooperate or interact with each other. In addition, although the terms "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish between elements or operations described by the same technical terms. Unless the context clearly indicates otherwise, the terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present disclosure.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the present disclosure, and will not be interpreted as an idealized or overly formal meaning unless explicitly defined as such herein.

[0062] The terms used herein are only for the purpose of describing specific embodiments and are not restrictive. As used herein, unless the content clearly indicates, the singular forms "one", "an" and "the" are intended to include multiple forms, including "at least one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It should also be understood that when used in this specification, the terms "include" and / or "comprise" specify the presence and / or parts of the features, regions, entireties, steps, operations, elements, but do not exclude the presence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their combinations.

[0063] The following will describe multiple embodiments of the present disclosure with drawings. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details should not be used to limit the present disclosure. In other words, in some embodiments of the present disclosure, these practical details are not necessary. In addition, in order to simplify the drawings, some conventional structures and components will be depicted in a simple schematic manner in the drawings.

[0064] Figure 1A FIG. 1 is a schematic diagram of a memory system 100 according to an embodiment of the present disclosure. Figure 1AAs shown, the memory system 100 includes a three-dimensional (3D) memory array 110 , a sensing device 120 , a temporary encoding device 130 , and an output device 140 .

[0065] In some embodiments, the sensing device 120 may include a page buffer and a sense amplifier, and is used to sense the tracking signal and the calculation signal generated by the three-dimensional memory array 110 according to the clock signal CLK. The temporary encoding device 130 may include a cache buffer and a priority encoder. The output device 140 is used to output the pairing result of the three-dimensional memory array 110.

[0066] like Figure 1A As shown, the three-dimensional memory array 110 includes a plurality of blocks BK1-BKM, where M is a positive integer. Blocks BK1-BKM are arranged in sequence. Blocks BK1-BKM are used to receive string selection line signals SSL1-SSLM, respectively. String selection line signal SSL1 is used to control the tracking array in block BK1. String selection line signal SSL2 is used to control the calculation array in block BK2. String selection line signal SSL3 is used to control the calculation array in block BK3, and so on. String selection line signal SSLM is used to control the calculation array in block BKM. In some embodiments, blocks BK1-BKM are used to receive ground selection line signals GSL1-GSLM, respectively.

[0067] like Figure 1A As shown, each of the blocks BK1-BKM includes a plurality of switch elements. The switch elements are used to form a plurality of memory cell rows. The memory cell rows are used to output corresponding bit line signals BL0-BL128K to the sensing device 120, where K represents 1000. In various embodiments, 128K may also be replaced by other positive integers.

[0068] In some embodiments, each memory cell in a memory cell row may be composed of two switch elements that are adjacent to each other and coupled in series. Figure 1A The memory cell MC in the embodiment can be formed by switch elements FC0N and FC0N-1, where N is a positive integer. The control end of the switch element FC0N is used to receive the word line signal WL0N, and the control end of the switch element FC0N-1 is used to receive the word line signal WL0N-1.

[0069] In some embodiments, a memory cell can store a data bit through the threshold voltage level of the switch element. For example, when the data bit of the memory cell MC has a logic value of 0, the switch element FC0N has a threshold voltage level VTH and the switch element FC0N-1 has a threshold voltage level VTL. When the data bit of the memory cell MC has a logic value of 1, the switch element FC0N has a threshold voltage level VTL and the switch element FC0N-1 has a threshold voltage level VTH. In some embodiments, the threshold voltage level VTH is greater than the threshold voltage level VTL.

[0070] In some embodiments, two word line signals may be used to carry one search bit. For example, when the search bit carried by word line signals WL0N and WL0N-1 has a logic value of 0, word line signal WL0N has a word line bias level VWH and word line signal WL0N-1 has a word line bias level VWL. When the search bit carried by word line signals WL0N and WL0N-1 has a logic value of 1, word line signal WL0N has a word line bias level VWL and word line signal WL0N-1 has a word line bias level VWH. In some embodiments, word line bias level VWH is greater than word line bias level VWL. In some embodiments, the search bit may be referred to as an in-memory search (IMS) search bit.

[0071] In some embodiments, when the logic value of the data bit of the memory cell MC is the same as the logic value of the search bit carried by the word line signals WL0N and WL0N-1, the data bit and the search bit match each other. At this time, the current flowing through the memory cell MC is large, so that the current of the bit line signal BL0 is large. When the logic value of the data bit of the memory cell MC is different from the logic value of the search bit carried by the word line signals WL0N and WL0N-1, the data bit and the search bit do not match each other. At this time, the current flowing through the memory cell MC is small, so that the current of the bit line signal BL0 is small. Other memory cells and bit line signals BL0~BL128K in the three-dimensional memory array 110 also have a similar relationship. In other words, the current of the bit line signals BL0~BL128K can correspond to the matching result when the three-dimensional memory array 110 performs a search operation.

[0072] In some embodiments, the tracking array in block BK1 can track the ambient temperature, retention time, and disturbance-induced threshold voltage shift, and redefine the sensing time of the page buffer in the sensing device 120 for the computing arrays in blocks BK2 ˜BKM according to the tracking results.

[0073] In some embodiments, the tracking data TKDT is input to the tracking array in the block BK1 to perform a tracking operation. During the tracking operation, the string selection line signal SSL1 has an enable voltage level, so that the tracking array in the block BK1 is activated. At this time, the tracking array compares the tracking data TKDT with the reference data bits stored in the tracking array to generate bit line signals BL0-BL128K carrying tracking logic values. Then, the sensing device 120 receives the bit line signals BL0-BL128K and redefines the sensing time according to the tracking logic value, such as adjusting the period of the clock signal CLK.

[0074] In some embodiments, after the sensing time is redefined, the calculation arrays in the blocks BK2-BKM are sequentially activated by the string selection line signals SSL2-SSLM to perform a calculation operation, such as a search operation, to generate the bit line signals BL0-BL128K carrying the matching results. In other words, when performing the calculation operation, the bit line signals BL0-BL128K can be referred to as calculation signals generated by the calculation arrays in the blocks BK2-BKM.

[0075] For example, after the tracking operation, the string selection line signal SSL2 has an enable voltage level, so that the calculation array in the block BK2 is activated and receives the search data SDT2 to perform a calculation operation, such as comparing the search data SDT2 with the data bits stored in the block BK2 to generate a corresponding calculation signal. At this time, the other string selection line signals SSL1 and SSL3-SSLM have a disable voltage level, so that the tracking array in the block BK1 and the calculation arrays in the blocks BK3-BKM are turned off.

[0076] Next, after the block BK2 performs the calculation operation, the string selection line signal SSL3 has an enable voltage level, so that the calculation array in the block BK3 is activated and receives the search data SDT3 to perform the calculation operation, such as comparing the search data SDT3 with the data bits stored in the block BK3 to generate a corresponding calculation signal. At this time, the other string selection line signals SSL1, SSL2 and SSL4~SSLM have a disable voltage level, so that the tracking array in the block BK1 and the calculation arrays in the blocks BK2, BK4~BKM are turned off, and so on.

[0077] Finally, after the block BKM-1 performs the calculation operation, the string selection line signal SSLM has an enable voltage level, so that the calculation array in the block BKM is activated and receives the search data SDTM to perform the calculation operation, such as comparing the search data SDTM with the data bits stored in the block BKM to generate a corresponding calculation signal. At this time, the other string selection line signals SSL1~SSLM-1 have a disable voltage level, so that the tracking array in the block BK1 and the calculation arrays in the blocks BK2~BKM-1 are turned off.

[0078] In some embodiments, the search data SDT2-SDTM may be carried by word line signals. For example, the search data SDTM may be carried by word line signals WL00-WL0N. Word line signals WL00 and WL01 may carry the first search bit in the search data SDTM. Word line signals WL02 and WL03 may carry the second search bit in the search data SDTM. Word line signals WL04 and WL05 may carry the third search bit in the search data SDTM. Word line signals WL06 and WL07 may carry the fourth search bit in the search data SDTM, and so on.

[0079] In some embodiments, the calculation array in block BKM can perform a search operation according to the search data SDTM carried by word line signals WL00-WL0N to compare the search bits with the data bits of the memory cells stored in block BKM and generate corresponding bit line signals BL0-BL128K as calculation signals.

[0080] In some embodiments, the sensing device 120 may sense the calculation signals generated by the calculation arrays in the blocks BK2 ˜BKM according to a redefined sensing time, such as an adjusted period of the clock signal CLK.

[0081] In some cases, the threshold voltage level of a memory cell is affected by the ambient temperature, retention time, and disturbance-induced threshold voltage shift, causing the calculation signal to shift. As a result, the result of sensing the calculation signal generated by the calculation operation is inaccurate.

[0082] Compared to the above approach, in the embodiment of the present disclosure, before performing the calculation operation, the tracking array in block BK1 performs a tracking operation to adjust the sensing time so that the influence of the threshold voltage shift can be eliminated. In this way, the accuracy of the sensing device 120 sensing the calculation signal generated by the calculation operation is improved.

[0083] In some embodiments, the memory cells in the three-dimensional memory array 110 may be referred to as in-memory searching (IMS) cells. The IMS cells may be implemented by floating gate memory, split-gate memory, Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory, floating dot memory, dynamic random-access memory (DRAM) and / or other DRAM-like devices, such as 2TOC memory. In some embodiments, the memory cells may also be implemented by emerging memories, such as ferroelectric field-effect transistors (FeFETs). In various embodiments, the memory system 100 may be implemented by a two-dimensional cache structure or a three-dimensional cache structure.

[0084] Figure 1B FIG. 1 is a schematic diagram of a portion of a memory system 100 performing a search operation according to an embodiment of the present disclosure. Figure 1B As shown, the memory system 100 includes a computing array 150 and a sense amplifier 152. The computing array 150 is used to receive search data 151 and compare the search data 151 with data bits stored in the computing array 150. Figure 1B and Figure 1A , the calculation array 150 may be an embodiment of a calculation array in one of the blocks BK2 ˜BKM, the search data 151 may be a corresponding one of the search data SDT2 ˜SDTM, and the sense amplifier 152 may be included in the sensing device 120 .

[0085] like Figure 1B As shown, the calculation array 150 includes a plurality of memory cell rows CL0-CL128K. The memory cell rows CL0-CL128K are used to output bit line signals BL0-BL128K respectively. The current levels of the bit line signals BL0-BL128K correspond to the matching results of the search data 151 and the data bits stored in the memory cell rows CL0-CL128K respectively. For example, when the number of data bits in the memory cell row CL0 that match the search data 151 is greater, the current level of the bit line signal BL0 is greater. Conversely, when the number of data bits in the memory cell row CL0 that match the search data 151 is less, the current level of the bit line signal BL0 is smaller.

[0086] In other words, the bit line signals BL0-BL128K can be used to carry the number of mismatched bits NMB between the search data 151 and the memory cell rows CL0-CL128K. Figure 1B In the illustrated embodiment, the slashed dots represent memory cells that match the search data 151 , and the dotted dots represent memory cells that do not match the search data 151 .

[0087] For example, there are 3 mismatch bits between the search bit in response to the search data 151 and the data bit stored in the memory cell row CL0, and the mismatch bit number NMB corresponding to the memory cell row CL0 is 3. There are 7 mismatch bits between the search bit in response to the search data 151 and the data bit stored in the memory cell row CL1, and the mismatch bit number NMB corresponding to the memory cell row CL1 is 7. There are 4 mismatch bits between the search bit in response to the search data 151 and the data bit stored in the memory cell row CL2, and the mismatch bit number NMB corresponding to the memory cell row CL2 is 4. There are 6 mismatch bits between the search bit in response to the search data 151 and the data bit stored in the memory cell row CL128K-2, and the mismatch bit number NMB corresponding to the memory cell row CL128K-2 is 6. In response to 7 mismatch bits between the search bit of the search data 151 and the data bits stored in the memory cell row CL128K-1, the mismatch bit number NMB corresponding to the memory cell row CL128K-1 is 7. In response to 24 mismatch bits between the search bit of the search data 151 and the data bits stored in the memory cell row CL128K, the mismatch bit number NMB corresponding to the memory cell row CL128K is 24. In some embodiments, the mismatch bit number NMB represents the Hamming distance between the search data 151 and the string data of the memory cell rows CL0-CL128K.

[0088] In some embodiments, the sense amplifier 152 is used to output a corresponding logic value according to the mismatch threshold and the mismatch bit number NMB. Specifically, when the mismatch bit number NMB is greater than the mismatch threshold, the sense amplifier 152 outputs a logic value of 0. When the mismatch bit number NMB is less than or equal to the mismatch threshold, the sense amplifier 152 outputs a logic value of 1.

[0089] For example, in the case where the mismatch threshold is 4, in response to the mismatch bit number NMB corresponding to the memory cell row CL0 being 3, the sense amplifier 152 outputs a logic value of 1. In response to the mismatch bit number NMB corresponding to the memory cell row CL1 being 7, the sense amplifier 152 outputs a logic value of 0. In response to the mismatch bit number NMB corresponding to the memory cell row CL2 being 4, the sense amplifier 152 outputs a logic value of 1. In response to the mismatch bit number NMB corresponding to the memory cell row CL128K-2 being 6, the sense amplifier 152 outputs a logic value of 0. In response to the mismatch bit number NMB corresponding to the memory cell row CL128K-1 being 7, the sense amplifier 152 outputs a logic value of 0. In response to the mismatch bit number NMB corresponding to the memory cell row CL128K being 24, the sense amplifier 152 outputs a logic value of 0. In this way, the memory system 100 can perform an approximate search operation by setting the mismatch threshold.

[0090] Figure 2 FIG. 2 is a schematic diagram of a tracking array 200 according to some embodiments of the present disclosure. Figure 2 As shown, the tracking cell rows included in the tracking array 200 can be represented by rectangles, and the data bits stored in the tracking cell rows can be represented by rectangular dots.

[0091] For example, the tracking cell row 201 may be represented by a rectangle 202, and the data bits stored in the tracking cell row 201 may be represented by dots in the rectangle 202. Figure 2 In the illustrated embodiment, the slash dots correspond to a logic value of 1. Accordingly, each of the data bits stored in the tracking cell row 201 has a logic value of 1.

[0092] like Figure 2 As shown, the tracking array 200 includes a plurality of tracking cell rows 203. The plurality of tracking cell rows 203 are arranged in sequence along the direction of arrow 204. Each of the data bits stored in the leftmost tracking cell row 205 of the plurality of tracking cell rows 203 has a logic value of 0. Figure 2 In the illustrated embodiment, the dot-shaped dots correspond to a logic value of 0. Each of the data bits stored in the rightmost tracking cell row 206 of the plurality of tracking cell rows 203 has a logic value of 1. Along the direction of arrow 204, the number of logic values ​​1 in the plurality of tracking cell rows 203 gradually increases, and the number of logic values ​​0 in the plurality of tracking cell rows 203 gradually decreases.

[0093] In some embodiments, all trace bits may have a logic value of 1, such as trace data. Figure 3The tracking data TKDTALL1 is input into the tracking array 200 to generate a corresponding string current. The current level of the string current gradually increases along the direction of arrow 204. For example, the current level of the string current flowing through the tracking cell row 205 is the smallest, and the current level of the string current flowing through the tracking cell row 206 is the largest.

[0094] Please refer to Figure 1A and Figure 2 The tracking array 200 may be an embodiment of the tracking array in the block BK1. Therefore, for the sake of brevity, some descriptions are not repeated.

[0095] Figure 3 FIG. 1 is a schematic diagram of a portion of a memory system 100 performing a tracking operation according to some embodiments of the present disclosure. Figure 3 As shown, the tracking array in block BK1 includes tracking cell rows TKCL0 ˜TKCL128K, and the sensing device 120 includes segment circuits SEG0 ˜SEGM, where M is a positive integer. In some embodiments, the segment circuits SEG0 ˜SEGM are included in a page buffer of the sensing device 120 .

[0096] In some embodiments, the tracking cell rows TKCL0 ˜TKCL128K are coupled to the segment circuits SEG0 ˜SEGM and are used to output tracking logic values ​​to the corresponding segment circuits SEG0 ˜SEGM. In some embodiments, the number of tracking cell rows coupled to each of the segment circuits SEG0 ˜SEGM is the same.

[0097] In some embodiments, the segment circuits SEG0-SEGM are used to count and track the logic values ​​to generate the corresponding summed value. In some embodiments, the sensing device 120 is used to determine the sensing time according to the summed value.

[0098] like Figure 3As shown, the reference data bits stored in each tracking cell row coupled to one of the segment circuits SEG0 to SEGM are the same. For example, the reference data bits stored in each tracking cell row coupled to the segment circuit SEG0 have M logic values ​​1 and 0 logic values ​​0. The reference data bits stored in each tracking cell row coupled to the segment circuit SEG1 have M-1 logic values ​​1 and 1 logic value 0, and so on. The reference data bits stored in each tracking cell row coupled to the segment circuit SEG8 have 8 logic values ​​0. The reference data bits stored in each tracking cell row coupled to the segment circuit SEG48 have 48 logic values ​​0. The reference data bits stored in each tracking cell row coupled to the segment circuit SEG49 have 49 logic values ​​0. The reference data bits stored in each tracking cell row coupled to the segment circuit SEGM-1 have 1 logic value 1 and M-1 logic values ​​0. The reference data bits stored in each of the tracking cell rows coupled to the segment circuit SEGM have 0 logic values ​​1 and M logic values ​​0.

[0099] In other words, for a positive integer P, the reference data bits stored in each tracking cell row coupled to the segment circuit SEGP have MP logic values ​​1 and P logic values ​​0.

[0100] In some embodiments, the tracking data TKDTALL1 or TKDTALL0 may be input into the tracking cell rows TKCL0-TKCL128K to perform a tracking operation. The tracking bits of the tracking data TKDTALL1 have M logic values ​​1, and the tracking bits of the tracking data TKDTALL0 have M logic values ​​0. In other words, the tracking bits of the tracking data TKDTALL1 are all logic values ​​1, and the tracking bits of the tracking data TKDTALL0 are all logic values ​​0.

[0101] Correspondingly, the Hamming distance between the tracking data TKDTALL1 and the reference data bit stored in the tracking cell row of the segment circuit SEG0 is 0. The Hamming distance between the tracking data TKDTALL1 and the reference data bit stored in the tracking cell row of the segment circuit SEG1 is 1, and so on. The Hamming distance between the tracking data TKDTALL1 and the reference data bit stored in the tracking cell row of the segment circuit SEG8 is 8. The Hamming distance between the tracking data TKDTALL1 and the reference data bit stored in the tracking cell row of the segment circuit SEG48 is 48. The Hamming distance between the tracking data TKDTALL1 and the reference data bit stored in the tracking cell row of the segment circuit SEG49 is 49. The Hamming distance between the tracking data TKDTALL1 and the reference data bit stored in the tracking cell row of the segment circuit SEGM-1 is M-1. The Hamming distance between the tracking data TKDTALL1 and the reference data bit stored in the tracking cell row of the segment circuit SEGM is M.

[0102] In various embodiments, the Hamming distance may be set as a mismatch threshold to perform a tracking operation and a subsequent approximate search operation. The following is an example of setting the mismatch threshold to 8 to distinguish whether the Hamming distance is less than or equal to 8. However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the mismatch threshold may also be set to other values ​​to distinguish other Hamming distances.

[0103] In some embodiments, in response to the mismatch threshold being 8, the tracking cell row coupled to the segment circuit SEG8 generates a tracking logic value according to the tracking data TKDTALL1. Figure 2 and Figure 1B The tracking cell row generates a bit line signal carrying the mismatch bit number NMB, and the sense amplifier 152 generates a corresponding tracking logic value according to the mismatch threshold and the bit line signal. Then, the segment circuit SEG8 is used to count the tracking logic values ​​of the tracking cell row to generate a sum value.

[0104] In some embodiments, when the sensing time at which the sense amplifier 152 performs sensing to generate the tracking logic value is redefined by the tracking operation, each of the tracking logic values ​​is a logic value 1. For example, when the number of tracking cell rows coupled to the segment circuit SEG8 is one thousand, each of the one thousand tracking cell rows generates a logic value 1, so that the segment circuit SEG8 receives and counts one thousand logic values ​​1.

[0105] On the other hand, when a portion of the tracking logic values ​​have a logic value of 0, it means that the current sensing time is not suitable for distinguishing the case where the mismatch threshold is 8. Accordingly, the sensing device 120 can finely adjust the sensing time until each of the tracking logic values ​​of the tracking unit row coupled to the segment circuit SEG8 is a logic value of 1, so that the segment circuit SEG8 can receive and count one thousand logic values ​​1.

[0106] In some cases, the high temperature and retention time may increase the current level of the string current, so that the string current of the redundant string (e.g., one or more of the tracking cell rows coupled to the segment circuit SEG8) may exceed the current standard after baking. Accordingly, the sensing time needs to be reduced to create a new reference current standard to avoid the redundant string current. The details of the sensing device 120 performing the tracking operation to adjust the sensing time are described below with respect to Figures 4 to 7 The embodiments are further described in the examples.

[0107] Figure 4 FIG. 4 is a schematic diagram of a method 400 for adjusting a sensing time by performing a tracking operation in a memory system 100 according to some embodiments of the present disclosure. Figure 4 In the illustrated embodiment, the mismatch threshold is set to 8 to distinguish whether the Hamming distance is less than or equal to 8 and the corresponding initial sensing time is 20 microseconds (us). However, the embodiments of the present disclosure are not limited thereto. In other embodiments, the mismatch threshold may be set to other values ​​to distinguish other Hamming distances and the corresponding initial sensing time may have a time length other than 20 microseconds.

[0108] In some embodiments, method 400 is a method for redefining a sensing time in response to temperature and / or retention time. Figure 4 As shown, the method 400 includes operations OP41 to OP46. In operations OP41 to OP46, the sensing time is set to a plurality of different sensing times to perform corresponding tracking operations.

[0109] In operation OP41, the tracking cell row coupled to the segment circuit SEG8 receives the tracking data TKDTALL1 to output a bit line signal, and the sensing device 120 senses the bit line signal according to the initial sensing time of 20 microseconds to generate tracking logic values ​​401. Each of the tracking logic values ​​401 has a logic value of 1. In other words, the tracking logic value 401 does not include a logic value of 0.

[0110] At this time, the segment circuit SEG8 can count the tracking logic value 401 to generate a summed value corresponding to the tracking logic value 401. For example, when the number of the tracking cell rows coupled to the segment circuit SEG8 is one thousand, the tracking logic value 401 has one thousand logic values ​​1. Correspondingly, the summed value of the tracking logic value 401 is one thousand.

[0111] In operation OP42, in response to the tracking logic value 401 not including the logic value 0, the sensing device 120 adjusts the sensing time from 20 microseconds to 19 microseconds. Figure 4 In the illustrated embodiment, each time the adjustment is made, the sensing device 120 adjusts the sensing time by a time length of 1 microsecond. However, the embodiments of the present disclosure are not limited thereto. In various embodiments, the sensing time may be adjusted by various time lengths, such as 0.5 microseconds or 2 microseconds.

[0112] Next, in operation OP42, the tracking cell row coupled to the segment circuit SEG8 receives the tracking data TKDTALL1 to output a bit line signal, and the sensing device 120 senses the bit line signal according to the sensing time of 19 microseconds to generate a tracking logic value 402. Each of the tracking logic values ​​402 has a logic value of 1. In other words, the tracking logic value 402 does not include a logic value of 0.

[0113] At this time, the segment circuit SEG8 can count the tracking logic value 402 to generate a summed value corresponding to the tracking logic value 402. For example, when the number of the tracking cell rows coupled to the segment circuit SEG8 is one thousand, the tracking logic value 402 has one thousand logic values ​​1. Correspondingly, the summed value of the tracking logic value 402 is one thousand.

[0114] In operation OP43, in response to the tracking logic value 402 not including the logic value 0, the sensing device 120 adjusts the sensing time from 19 microseconds to 18 microseconds. Then, the tracking cell row coupled to the segment circuit SEG8 receives the tracking data TKDTALL1 to output the bit line signal, and the sensing device 120 senses the bit line signal according to the sensing time of 18 microseconds to generate the tracking logic value 403. Each of the tracking logic values ​​403 has a logic value of 1. In other words, the tracking logic value 403 does not include the logic value 0.

[0115] At this time, the segment circuit SEG8 can count the tracking logic value 403 to generate a summed value corresponding to the tracking logic value 403. For example, when the number of the tracking cell rows coupled to the segment circuit SEG8 is one thousand, the tracking logic value 403 has one thousand logic values ​​1. Correspondingly, the summed value of the tracking logic value 403 is one thousand.

[0116] In operation OP44, in response to the tracking logic value 403 not including the logic value 0, the sensing device 120 adjusts the sensing time from 18 microseconds to 17 microseconds. Then, the tracking cell row coupled to the segment circuit SEG8 receives the tracking data TKDTALL1 to output the bit line signal, and the sensing device 120 senses the bit line signal according to the sensing time of 17 microseconds to generate the tracking logic value 404. Each of the tracking logic values ​​404 has a logic value of 1. In other words, the tracking logic value 404 does not include the logic value 0.

[0117] At this time, the segment circuit SEG8 can count the tracking logic value 404 to generate a summed value corresponding to the tracking logic value 404. For example, when the number of the tracking cell rows coupled to the segment circuit SEG8 is one thousand, the tracking logic value 404 has one thousand logic values ​​1. Correspondingly, the summed value of the tracking logic value 404 is one thousand.

[0118] In operation OP45, in response to the tracking logic value 404 not including the logic value 0, the sensing device 120 adjusts the sensing time from 17 microseconds to 16 microseconds. Then, the tracking cell row coupled to the segment circuit SEG8 receives the tracking data TKDTALL1 to output a bit line signal, and the sensing device 120 senses the bit line signal according to the sensing time of 16 microseconds to generate the tracking logic value 405. A portion of the tracking logic value 405 has a logic value of 0.

[0119] At this time, the segment circuit SEG8 can count the tracking logic value 405 to generate a summed value corresponding to the tracking logic value 405. For example, when the number of the tracking cell rows coupled to the segment circuit SEG8 is one thousand, and two of the tracking cell rows generate bit line signals corresponding to the logic value 0, the tracking logic value 405 has 998 logic values ​​1 and two logic values ​​0. Correspondingly, the summed value of the tracking logic value 405 is 998. The summed value of the tracking logic value 405 being less than one thousand indicates that the sensing time of 16 microseconds is not suitable for the current temperature and / or retention time.

[0120] Correspondingly, in operation OP46 , in response to the tracking logic value 405 having a logic value of 0, the sensing device 120 adjusts the sensing time back from 16 microseconds to 17 microseconds, and sets 17 microseconds as the reset sensing time.

[0121] After operation OP46 , the sensing device 120 may sense the bit line signals outputted by the calculation arrays in the blocks BK2 ˜BKM according to the sensing time of 17 μs to perform a search operation with a mismatch threshold of 8.

[0122] In summary, when the sum of the tracking logic values ​​is equal to the number of tracking cell rows of the coupling segment circuit SEG8, the sensing device 120 can gradually reduce the sensing time and count the sum until the sum of the tracking logic values ​​405 is less than the number of tracking cell rows of the coupling segment circuit SEG8. After the sum of the tracking logic values ​​405 is less than the number of tracking cell rows of the coupling segment circuit SEG8, the sensing device 120 can set the last sensing time corresponding to the sum equal to the number of tracking cell rows of the coupling segment circuit SEG8 as the new sensing time, and perform the search operation according to the new sensing time.

[0123] In some embodiments, the number of tracking unit rows of the coupled segment circuit SEG8 can be referred to as a preset value. Correspondingly, when the sum value is different from the preset value, the sensing device 120 adjusts the sensing time. For example, the sensing device 120 adjusts the sensing time by adjusting the period of the clock signal CLK. When the sum value is equal to the preset value, the sensing device 120 determines the sensing time. For example, the sensing device 120 determines the sensing time according to the period of the clock signal CLK, and uses the period of the clock signal CLK to sense the calculation signal generated by the calculation operation.

[0124] Figure 5 FIG. 5 is a schematic diagram of a method 500 for adjusting a sensing time by performing a tracking operation in a memory system 100 according to some embodiments of the present disclosure. Figure 4 and Figure 5 , method 500 is a variation of method 400. Therefore, some details are not repeated.

[0125] In some embodiments, method 500 is a method for redefining a sensing time in response to a disturbance. Figure 5 As shown, the method 500 includes operations OP51 ˜ OP56 . In operations OP51 ˜ OP56 , the sensing time is set to a plurality of different sensing times to perform corresponding tracking operations.

[0126] In operation OP51, the tracking cell row coupled to the segment circuit SEG8 receives the tracking data TKDTALL1 to output a bit line signal, and the sensing device 120 senses the bit line signal according to the initial sensing time of 20 microseconds to generate a tracking logic value 501. A portion of the tracking logic value 501 has a logic value of 0.

[0127] At this time, the segment circuit SEG8 can count the tracking logic value 501 to generate a summed value corresponding to the tracking logic value 501. For example, when the number of the tracking cell rows coupled to the segment circuit SEG8 is one thousand, and four of the tracking cell rows generate bit line signals corresponding to the logic value 0, the tracking logic value 501 has 996 logic values ​​1 and four logic values ​​0. Correspondingly, the summed value of the tracking logic value 501 is 996.

[0128] In operation OP52, in response to the tracking logic value 501 including the logic value 0, the sensing device 120 adjusts the sensing time from 20 microseconds to 21 microseconds. Then, the tracking cell row coupled to the segment circuit SEG8 receives the tracking data TKDTALL1 to output a bit line signal, and the sensing device 120 senses the bit line signal according to the sensing time of 21 microseconds to generate the tracking logic value 502. A portion of the tracking logic value 502 has a logic value of 0.

[0129] At this time, the segment circuit SEG8 can count the tracking logic value 502 to generate a summed value corresponding to the tracking logic value 502. For example, when the number of the tracking cell rows coupled to the segment circuit SEG8 is one thousand, and three of the tracking cell rows generate bit line signals corresponding to the logic value 0, the tracking logic value 502 has 997 logic values ​​1 and three logic values ​​0. Correspondingly, the summed value of the tracking logic value 502 is 997.

[0130] In operation OP53, in response to the tracking logic value 502 including the logic value 0, the sensing device 120 adjusts the sensing time from 21 microseconds to 22 microseconds. Then, the tracking cell row coupled to the segment circuit SEG8 receives the tracking data TKDTALL1 to output a bit line signal, and the sensing device 120 senses the bit line signal according to the sensing time of 22 microseconds to generate the tracking logic value 503. A portion of the tracking logic value 503 has a logic value of 0.

[0131] At this time, the segment circuit SEG8 can count the tracking logic value 503 to generate a summed value corresponding to the tracking logic value 503. For example, when the number of the tracking cell rows coupled to the segment circuit SEG8 is one thousand, and two of the tracking cell rows generate bit line signals corresponding to the logic value 0, the tracking logic value 503 has 998 logic values ​​1 and two logic values ​​0. Correspondingly, the summed value of the tracking logic value 503 is 998.

[0132] In operation OP54, in response to the tracking logic value 503 including the logic value 0, the sensing device 120 adjusts the sensing time from 22 microseconds to 23 microseconds. Then, the tracking cell row coupled to the segment circuit SEG8 receives the tracking data TKDTALL1 to output the bit line signal, and the sensing device 120 senses the bit line signal according to the sensing time of 23 microseconds to generate the tracking logic value 504. Each of the tracking logic values ​​504 has a logic value of 1. In other words, the tracking logic value 504 does not include the logic value 0.

[0133] At this time, the segment circuit SEG8 can count the tracking logic value 504 to generate a summed value corresponding to the tracking logic value 504. For example, when the number of the tracking cell rows coupled to the segment circuit SEG8 is one thousand, the tracking logic value 504 has one thousand logic values ​​1. Correspondingly, the summed value of the tracking logic value 504 is one thousand.

[0134] In operation OP55, the sensing device 120 adjusts the sensing time from 23 microseconds to 24 microseconds. Then, the tracking cell row coupled to the segment circuit SEG8 receives the tracking data TKDTALL1 to output a bit line signal, and the sensing device 120 senses the bit line signal according to the sensing time of 24 microseconds to generate a tracking logic value 505. Each of the tracking logic values ​​505 has a logic value of 1. In other words, the tracking logic value 505 does not include a logic value of 0.

[0135] At this time, the segment circuit SEG8 can count the tracking logic value 505 to generate a summed value corresponding to the tracking logic value 505. For example, when the number of the tracking cell rows coupled to the segment circuit SEG8 is one thousand, the tracking logic value 505 has one thousand logic values ​​1. Correspondingly, the summed value of the tracking logic value 505 is one thousand.

[0136] In operation OP56 , in response to the tracking logic value 505 not including the logic value 0 and the tracking logic value 504 not including the logic value 0, the sensing device 120 adjusts the sensing time from 24 μs back to 23 μs and sets 23 μs as the reset sensing time.

[0137] After operation OP56 , the sensing device 120 may sense the bit line signals outputted by the calculation arrays in the blocks BK2 ˜BKM according to the sensing time of 23 μs to perform a search operation with a mismatch threshold of 8.

[0138] In summary, when the sum of the tracking logic values ​​is less than the number of the tracking cell rows of the coupling segment circuit SEG8, the sensing device 120 can continuously increase the sensing time and count the sum until the sum of the tracking logic values ​​504 and 505 is equal to the number of the tracking cell rows of the coupling segment circuit SEG8. After the sum of the tracking logic value 505 is equal to the number of the tracking cell rows of the coupling segment circuit SEG8, the sensing device 120 can set the sensing time corresponding to the tracking logic value 504 as a new sensing time, and perform a search operation according to the new sensing time.

[0139] Figure 6 FIG. 6 is a timing diagram 600 of the memory system 100 performing a tracking operation to adjust a sensing time according to some embodiments of the present disclosure. Figure 6 As shown, the timing diagram 600 includes periods P61 to P65 that are sequentially and continuously arranged.

[0140] During period P61, the clock signal CLK has a period corresponding to 20 microseconds and is maintained at the voltage level VH for 20 microseconds. In some embodiments, the time when the clock signal CLK is maintained at the voltage level VH corresponds to the sensing time of the sensing device 120. Correspondingly, the sensing device 120 can adjust the sensing time by adjusting the period of the clock signal CLK. For example, the sensing device 120 can perform a sensing operation when the clock signal CLK has the voltage level VH, and not perform a sensing operation when the clock signal CLK has the voltage level VL.

[0141] Next, between periods P61 and P62, the clock signal CLK has a voltage level VL. In some embodiments, the voltage level VH is higher than the voltage level VL.

[0142] During the period P62, the clock signal CLK has a period corresponding to 19 microseconds and is maintained at the voltage level VH for 19 microseconds. Next, between the periods P62 and P63, the clock signal CLK has a voltage level VL.

[0143] During the period P63, the clock signal CLK has a period corresponding to 18 microseconds and is maintained at the voltage level VH for 18 microseconds. Next, between the periods P63 and P64, the clock signal CLK has a voltage level VL.

[0144] During the period P64, the clock signal CLK has a period corresponding to 17 microseconds and is maintained at the voltage level VH for 17 microseconds. Next, between the periods P64 and P65, the clock signal CLK has a voltage level VL.

[0145] During the period P65, the clock signal CLK has a period corresponding to 16 microseconds and is maintained at the voltage level VH for 16 microseconds. Then, after the period P65, the clock signal CLK has the voltage level VL.

[0146] Please refer to Figure 4 and Figure 6 The periods P61 to P65 may correspond to the operations OP41 to OP45, respectively. For example, the sensing device 120 may perform the operations OP41 to OP45, respectively, according to the clock signal CLK during the periods P61 to P65.

[0147] In summary, in operations OP41-OP46, the sensing device 120 counts the tracking logic values ​​of the segment circuit SEG8 to generate a summed value, and compares the summed value with a preset value (e.g., the number of tracking logic rows coupled to the segment circuit SEG8). When the summed value is equal to the preset value, the sensing device 120 reduces the period of the clock signal CLK, for example, gradually reducing it from a period corresponding to 20 microseconds to a period corresponding to 16 microseconds. When the summed value is different from the preset value, the sensing device 120 increases the period of the clock signal CLK, for example, from a period corresponding to 16 microseconds to a period corresponding to 17 microseconds, and determines the period corresponding to 17 microseconds as the period used in the calculation operation. Then, after determining the period of the clock signal CLK, the memory system 100 can perform the calculation operation and sense the calculation signal from the calculation operation according to the period corresponding to 17 microseconds.

[0148] Figure 7 FIG. 7 is a timing diagram 700 of the memory system 100 performing a tracking operation to adjust a sensing time according to some embodiments of the present disclosure. Figure 7 As shown, the timing diagram 700 includes periods P71 to P75 that are arranged sequentially and continuously.

[0149] During period P71, the clock signal CLK has a period corresponding to 20 microseconds and is maintained at the voltage level VH for 20 microseconds. Then, between periods P71 and P72, the clock signal CLK has a voltage level VL. In some embodiments, the voltage level VH is higher than the voltage level VL.

[0150] During the period P72, the clock signal CLK has a period corresponding to 21 microseconds and is maintained at the voltage level VH for 21 microseconds. Next, between the periods P72 and P73, the clock signal CLK has a voltage level VL.

[0151] During the period P73, the clock signal CLK has a period corresponding to 22 microseconds and is maintained at the voltage level VH for 22 microseconds. Next, between the periods P73 and P74, the clock signal CLK has a voltage level VL.

[0152] During the period P74, the clock signal CLK has a period corresponding to 23 microseconds and is maintained at the voltage level VH for 23 microseconds. Next, between the periods P74 and P75, the clock signal CLK has a voltage level VL.

[0153] During the period P75, the clock signal CLK has a period corresponding to 24 microseconds and is maintained at the voltage level VH for 24 microseconds. Then, after the period P75, the clock signal CLK has the voltage level VL.

[0154] Please refer to Figure 5 and Figure 7The periods P71 to P75 may correspond to the operations OP51 to OP55, respectively. For example, the sensing device 120 may perform the operations OP51 to OP55, respectively, according to the clock signal CLK during the periods P71 to P75.

[0155] In summary, in operations OP51-OP56, the sensing device 120 counts the tracking logic values ​​of the segment circuit SEG8 to generate a summed value, and compares the summed value with a preset value (e.g., the number of tracking logic rows coupled to the segment circuit SEG8). When the summed value is different from the preset value, the sensing device 120 increases the cycle of the clock signal CLK, for example, gradually increasing from a cycle corresponding to 20 microseconds to a cycle corresponding to 24 microseconds. When the summed values ​​corresponding to two cycles are both equal to the preset value, the sensing device 120 decreases the cycle of the clock signal CLK.

[0156] For example, when the two summed values ​​generated by the period corresponding to 23 microseconds and the period corresponding to 24 microseconds are both one thousand, the sensing device 120 reduces the clock signal CLK from the period corresponding to 24 microseconds to the period corresponding to 23 microseconds, and determines the period corresponding to 23 microseconds as the period used in the computing operation. Then, after determining the period of the clock signal CLK, the memory system 100 can perform the computing operation and sense the computing signal from the computing operation according to the period corresponding to 23 microseconds.

[0157] Figure 8 FIG. 1 is a schematic diagram of a portion of a sensing device 120 according to some embodiments of the present disclosure. Figure 8 As shown, the sensing device 120 includes N segment circuits SEG1 ˜SEGN, where N is a positive integer. Each of the segment circuits SEG1 ˜SEGN is included in a page buffer.

[0158] exist Figure 8 In the illustrated embodiment, the page buffer is used to process 128K bit line signals. Correspondingly, the size of the page buffer is 128K. However, the embodiments of the present disclosure are not limited thereto. In various embodiments, the page buffer may have various sizes.

[0159] In some embodiments, the memory system 100 can adjust the size of the segment circuits SEG1-SEGN by adjusting the positive integer N. For example, when the positive integer N is 128, each of the segment circuits SEG1-SEGN has a size of 1K (e.g., 1024 bits). At this time, the segment circuits SEG1-SEGN can be used to distinguish the Hamming distance from 0 to 127.

[0160] For another example, when the positive integer N is 256, each of the segment circuits SEG1-SEGN has a size of 0.5K (eg, 512 bits). In this case, the segment circuits SEG1-SEGN can be used to distinguish the Hamming distance from 0 to 255.

[0161] In summary, when the size of the segment circuits SEG1-SEGN is small, the number of Hamming distances that can be distinguished by the segment circuits SEG1-SEGN is larger. On the other hand, when the size of the segment circuits SEG1-SEGN is large, the tracking operation performed by the segment circuits SEG1-SEGN is more accurate. In various embodiments, the size of the segment circuits SEG1-SEGN can be selected according to various specification requirements.

[0162] Fig. 9 FIG. 1 is a schematic diagram of a portion of a memory system 100 performing a computing operation according to some embodiments of the present disclosure. Fig. 9 As shown, the memory system 100 includes a computing array 901. The computing array 901 includes a plurality of memory cell rows. Figure 1A and Fig. 9 , the computing array 901 may be a computing array in one of the blocks BK2 to BKM. Figure 1B and Fig. 9 , the memory cell rows in the calculation array 901 can be implemented by memory cell rows CL0~CL128K.

[0163] In some embodiments, the calculation array 901 is used to receive the search data 902 to perform a calculation operation, such as a search operation. When performing the search operation, the calculation array 901 compares the search bits of the search data 902 with the data bits of the memory cell row in the calculation array 901 to generate corresponding bit line signals BL0-BL128K. In some embodiments, when performing the search operation, the bit line signals BL0-BL128K can be referred to as calculation signals.

[0164] In some embodiments, the search operation is performed via Figure 3 The tracking operation described in the illustrated embodiment is performed after the redefined sensing time is generated. Correspondingly, the sensing device 120 can store the redefined sensing time and perform a sensing operation on the calculation signal according to the redefined sensing time.

[0165] When the sensing device 120 performs a sensing operation, the sensing device 120 determines whether the search data 902 matches the data bit of the memory cell row according to the calculation signal and the mismatch threshold. When the search data 902 does not match the data bit of the memory cell row, the sensing device 120 generates a logic value of 0. When the search data 902 matches the data bit of the memory cell row, the sensing device 120 generates a logic value of 1.

[0166] For example, in Fig. 9 In the illustrated embodiment, the data bits of the memory cell row 903 in the calculation array 901 match the search data 902, and the data bits of the other memory cell rows in the calculation array 901 do not match the search data 902. Correspondingly, the sensing device 120 generates a logic value of 1 in response to the calculation signal of the memory cell row 903, and generates a logic value of 0 in response to the calculation signals of the other memory cell rows.

[0167] Please refer to Figure 3 and Fig. 9 , when the tracking array of block BK1 performs a tracking operation, the segment circuits SEG0~SEGM are activated. When the calculation array 901 performs a calculation operation, the segment circuits SEG0~SEGM are turned off. The reference data bits stored in the tracking array of block BK1 have a regular pattern. For example, the tracking unit rows coupled to the same segment circuit have the same reference data bits, the number of reference data bits with a logic value of 1 gradually increases from left to right, and the number of reference data bits with a logic value of 0 gradually decreases from left to right. On the other hand, the data bits stored in the calculation array 901 have a random pattern.

[0168] Furthermore, when performing a tracking operation, the tracking data TKDTALL1 or TKDTALL0 input to the tracking array of the block BK1 has a uniform pattern, that is, all tracking bits of the tracking data TKDTALL1 have a logic value of 1 and all tracking bits of the tracking data TKDTALL0 have a logic value of 0. On the other hand, when performing a calculation operation, the search data 902 input to the calculation array 901 has a random pattern.

[0169] Although the present disclosure has been described above with reference to the embodiments, it is not intended to limit the present disclosure. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be determined by the scope of the appended claims.

Claims

1. A method for operating a memory system, characterized in that: Include: Inputting tracking data into a tracking array; generating a plurality of tracking logic values ​​through a plurality of tracking cell rows in the tracking array according to the tracking data; counting the tracking logic values ​​to generate a sum value; adjusting a sensing time of a sensing device according to the summed value; Performing a computing operation through a computing array to generate a plurality of computing signals; as well as The calculation signals are sensed by the sensing device according to the adjusted sensing time.

2. The operating method according to claim 1, characterized in that: Wherein adjusting the sensing time of the sensing device according to the sum value further comprises: comparing the total value to the number of tracking cell rows; When the sum is different from the number of the tracking unit rows, adjusting the sensing time; and When the sum is equal to the number of the tracking unit rows, the sensing time is determined.

3. The operating method according to claim 1, characterized in that: Also includes: Setting the sensing time as a first sensing time; Generate a plurality of tracking signals according to the tracking data through the tracking unit rows; sensing the tracking signals according to the first sensing time to generate a plurality of first tracking logic values; Counting the first tracking logic values ​​to generate a first summed value; as well as When the first sum is equal to the number of the tracking unit rows, the sensing time is set to a second sensing time. The second sensing time is shorter than the first sensing time.

4. The operating method according to claim 3, characterized in that: Also includes: sensing the tracking signals according to the second sensing time to generate a plurality of second tracking logic values; Counting the second tracking logic values ​​to generate a second summed value; When the second summed value is different from the number of the tracking unit rows, setting the sensing time to the first sensing time; as well as The calculation signals are sensed by the sensing device according to the first sensing time.

5. The operating method according to claim 1, characterized in that: Also includes: Setting the sensing time as a first sensing time; Generate a plurality of tracking signals according to the tracking data through the tracking unit rows; sensing the tracking signals according to the first sensing time to generate a plurality of first tracking logic values; Counting the first tracking logic values ​​to generate a first summed value; as well as When the first sum value is different from the number of the tracking unit rows, the sensing time is set to a second sensing time, The second sensing time is greater than the first sensing time.

6. The operating method according to claim 5, characterized in that: Also includes: sensing the tracking signals according to the second sensing time to generate a plurality of second tracking logic values; Counting the second tracking logic values ​​to generate a second summed value; When the second sum is equal to the number of the tracking unit rows, the sensing time is set to a third sensing time, The third sensing time is greater than the second sensing time.

7. The operating method according to claim 6, characterized in that: Also includes: sensing the tracking signals according to the third sensing time to generate a plurality of third tracking logic values; counting the third tracking logic values ​​to generate a third summed value; When the third summed value is equal to the number of the tracking unit rows, setting the sensing time to the second sensing time; as well as The calculation signals are sensed by the sensing device according to the second sensing time.

8. A memory system, characterized in that: Include: A plurality of tracking unit rows, for generating a plurality of tracking logic values ​​according to the tracking data; a computing array for generating a plurality of computing signals; and a sensing device for sensing the calculation signals according to a clock signal, The sensing device includes a segment circuit, and the segment circuit is used to count the tracking logic values ​​to generate a sum value. When the sum is different from a preset value, a period of the clock signal is adjusted, and When the sum value is equal to the preset value, the period of the clock signal is determined to be used for sensing the calculation signals.

9. The memory system according to claim 8, characterized in that: The reference data bits stored in each of the tracking cell rows have P first logic values, and P is a positive integer.

10. A method for operating a memory system, characterized in that: Include: Counting a plurality of tracking logic values ​​to generate a sum value; comparing the summed value with a preset value; When the sum is different from a preset value, adjusting a period of a clock signal; When the sum is equal to the preset value, the cycle is determined; as well as A computing operation is performed after determining the cycle and a plurality of computing signals from the computing operation are sensed according to the cycle.

Images