Self-adaptive path selection logic generation circuit, double-path rectifier and radio frequency energy collection system

Abstract

The invention belongs to the technical field of integrated circuits, and discloses a self-adaptive path selection logic generation circuit, a double-path rectifier and a radio frequency energy collection system. The adaptive path selection logic generation circuit comprises a voltage sampling and holding sub-circuit, a dynamic latch comparator sub-circuit and a control signal generation sub-circuit. The invention further discloses a dual-path rectifier comprising the adaptive path selection logic generation circuit, and a radio frequency energy collection system comprising the dual-path rectifier. According to the path switching logic provided by the invention, optimal power point switching can be realized within a relatively large range of load resistance values; the provided dual-path rectifier can improve the conversion efficiency and sensitivity of the rectifier, widen the input power range, and continuously widen the application range for a radio frequency energy collection system. The invention is suitable for the design of an integrated circuit for radio frequency energy collection.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits and relates to an adaptive path selection logic generation circuit, a dual-path rectifier, and a radio frequency energy collection system. Background Art

[0002] Energy harvesting is a technology that provides wireless power to electronic devices. In recent years, it has provided more power supply solutions in the fields of Internet of Things, biomedical and industrial application equipment. Among them, RF energy harvesting has become an excellent solution for powering circuits in wearable electronic devices, radio frequency identification (RFID), and implantable medical devices due to its flexibility and convenience. However, RF signals in the environment often have low power density, so it is necessary to study efficient energy conversion circuits at low power levels.

[0003] The RF energy harvesting system mainly includes energy source, antenna, matching network, rectifier, energy management circuit and energy storage element, etc. Among them, the RF-DC rectifier plays the role of converting AC RF energy into DC signal and powering the subsequent system. It is the key module of the entire RF energy harvesting system and plays a decisive role in the energy conversion efficiency of the system.

[0004] At present, the main challenges faced by RF-DC rectifiers are the low power density of RF energy in the environment, the low energy conversion efficiency of the rectifier, and the narrow input power range for the rectifier to maintain high conversion efficiency. At present, the two topologies commonly used in mainstream research on rectifiers are cross-coupling and Dickson rectifiers. The cross-coupled rectifier achieves a higher rectification efficiency at low input power due to the bias effect of its internal nodes on the gate of the rectifier tube. The Dickson rectifier suppresses the reverse leakage current of the rectifier at high input power due to its unidirectional connection form of the rectifier tube, and obtains a higher energy conversion efficiency at high input power. Therefore, in order to combine the advantages of the two topologies, some studies have proposed a dual-path rectifier solution. However, the energy distribution problem on different paths and the problem of finding the optimal path switching point in the dual-path rectifier lead to poor system sensitivity and conversion efficiency.

[0005] For example, the Chinese invention patent with the authorization announcement number CN114244149B discloses a dual-path RF-DC rectifier applied to a radio frequency energy harvesting system, which introduces a dynamically selected dual-path structure. However, 1. The rectifier uses the auxiliary rectifier paths RVG and NVG to provide VREF and VSS signals for the comparator CMP, and uses the output voltage V OUT The output V REF The comparison output switch selection signal SW is used; since the load of RVG is a capacitive load and the load of the rectifier path is a resistive load, the path selection logic cannot guarantee that the VREF Greater than V OUT When V OUT It is greatly affected by the load resistance and cannot guarantee more accurate path selection and more efficient energy conversion within a larger load variation range; 3. The rectifier switching switch only has one switch between the rectifier and the ground, and cannot completely shut down the rectification path. During the energy collection process, the shut-off rectification path will cause crosstalk to the turned-on rectification path, resulting in energy loss. Summary of the invention

[0006] The first object of the present invention is to provide an adaptive path selection logic generation circuit, which provides a path switching logic capable of achieving optimal power point switching within a wide range of load resistance values;

[0007] The second object of the present invention is to provide a dual-path rectifier including the above-mentioned adaptive path selection logic generation circuit to improve the conversion efficiency and sensitivity of the rectifier, broaden the input power range, and continuously broaden the application scope of the radio frequency energy harvesting system;

[0008] The third object of the present invention is to provide a radio frequency energy harvesting system including the dual-path rectifier.

[0009] An adaptive path selection logic generation circuit includes a voltage sampling and holding subcircuit, a dynamic latch comparator subcircuit and a control signal generation subcircuit;

[0010] The control signal generating subcircuit is powered by the load voltage, and generates first to fourth sampling control signals in response to the load voltage, and outputs the first to fourth sampling control signals to the voltage sampling and holding subcircuit;

[0011] The voltage sampling and holding subcircuit samples the load voltage in response to the first to fourth sampling control signals, generates a first sampling and holding voltage and a second sampling and holding voltage, and outputs the first sampling and holding voltage and the second sampling and holding voltage to the dynamic latch comparator subcircuit;

[0012] The control signal generating subcircuit is powered by a load voltage and generates a first latch control signal and a second latch control signal in response to the load voltage, and outputs the signals to the dynamic latch comparator subcircuit;

[0013] The dynamic latch comparator subcircuit generates a first comparison control signal and a second comparison control signal in response to the first sample-and-hold voltage, the second sample-and-hold voltage, the first latch control signal and the second latch control signal, and outputs the signals to the control signal generation subcircuit;

[0014] The control signal generating sub-circuit generates first to fourth timing control signals in response to the first comparison control signal and the second comparison control signal, and outputs the signals to the external circuit.

[0015] As a limitation, the control signal generation subcircuit includes a current-starved ring oscillator, a nine-stage frequency divider, a sample-and-hold signal generation submodule, a charge pump submodule, a latch control signal generation submodule, and a switch control signal generation submodule;

[0016] The current-starved ring oscillator comprises first to fifth ring oscillator minimum units which are cascaded in sequence, wherein the output end of the fifth ring oscillator minimum unit is connected to the input end of a nine-stage frequency divider through two serially connected inverters; the current-starved ring oscillator is externally connected to a load voltage, generates a clock signal in response to the load voltage and outputs the clock signal to the nine-stage frequency divider through two serially connected inverters, and the nine-stage frequency divider generates first to ninth clock signals in response to the clock signal;

[0017] The fifth and sixth output terminals of the nine-level frequency divider are directly connected to the clock control input terminal of the sampling and holding signal generating submodule on the one hand, and are connected to the pulse signal input terminal of the sampling and holding signal generating submodule through a logic gate circuit together with the seventh to ninth output terminals on the other hand;

[0018] The nine-stage frequency divider outputs the fifth clock signal and the sixth clock signal to the sampling and holding signal generating submodule on the one hand, and outputs the fifth to ninth clock signals to the logic gate circuit on the other hand; the logic gate circuit generates the first to fourth single-peak pulse signals in response to the fifth to ninth clock signals, outputs the first to fourth single-peak pulse signals to the sampling and holding signal generating submodule on the one hand, outputs the second single-peak pulse signal and the third single-peak pulse signal to the latch control signal generating submodule on the second hand, and outputs the third single-peak pulse signal to the switch control signal generating submodule on the third hand;

[0019] The sampling and holding signal generating submodule generates first to third path selection first stage enable signals, a first sampling signal, a second sampling signal, a first holding control signal, and a second holding control signal in response to the fifth clock signal, the sixth clock signal, and the first to fourth single-peak pulse signals, and outputs the first sampling signal, the second sampling signal, the first holding control signal, and the second holding control signal to the charge pump submodule on the one hand; and outputs the third path selection first stage enable signal to the latch control signal generating submodule on the other hand;

[0020] The charge pump submodule generates first to fourth sampling control signals in response to the first sampling signal, the second sampling signal, the first holding control signal and the second holding control signal and outputs the first to fourth sampling control signals to the voltage sampling and holding subcircuit;

[0021] The latch control signal generating submodule generates a first latch control signal, a second latch control signal and a switching control signal in response to the second single-peak pulse signal, the third single-peak pulse signal and the third path selection first stage enabling signal, and outputs the first latch control signal and the second latch control signal to the dynamic latch comparator subcircuit on the one hand, and outputs the switching control signal to the switch control signal generating submodule on the other hand;

[0022] The dynamic latch comparator sub-circuit generates a first comparison control signal and a second comparison control signal in response to the first sample-and-hold voltage, the second sample-and-hold voltage, the first latch control signal and the second latch control signal, and outputs the signals to the switch control signal generation sub-module;

[0023] The switch control signal generating submodule generates first to fourth timing control signals in response to the third single-peak pulse signal, the switching control signal, the first comparison control signal and the second comparison control signal, and outputs the first to fourth timing control signals to the external circuit.

[0024] As a second limitation, the voltage sample and hold subcircuit includes a first sampling path subcircuit and a second sampling path subcircuit;

[0025] The first sampling path subcircuit includes first to third NMOS transistors, a first capacitor and a second capacitor; the second sampling path subcircuit includes fourth to sixth NMOS transistors, a third capacitor and a fourth capacitor;

[0026] The drains of the first NMOS tube and the fourth NMOS tube are connected to the load voltage, the gates of the first NMOS tube and the third NMOS tube are connected to the first sampling control signal, the gate of the second NMOS tube is connected to the third sampling control signal, the gates of the fourth NMOS tube and the sixth NMOS tube are connected to the second sampling control signal, and the gate of the fifth NMOS tube is connected to the fourth sampling control signal;

[0027] The source of the first NMOS tube is grounded through the first capacitor on the one hand, and connected to the drain of the second NMOS tube on the other hand. The source of the second NMOS tube is grounded through the second capacitor on the one hand, and connected to the drain of the third NMOS tube on the other hand. The source of the third NMOS tube is grounded; the common end of the second NMOS tube, the third NMOS tube and the second capacitor serves as the output end of the first sampling and holding voltage;

[0028] The source of the fourth NMOS tube is grounded through the third capacitor on the one hand, and connected to the drain of the fifth NMOS tube on the other hand. The source of the fifth NMOS tube is grounded through the fourth capacitor on the one hand, and connected to the drain of the sixth NMOS tube on the other hand. The source of the sixth NMOS tube is grounded; the common end of the fifth NMOS tube, the sixth NMOS tube and the fourth capacitor serves as the output end of the second sampling and holding voltage;

[0029] In the sampling and holding stage of the first sampling path sub-circuit, in the initial state, the first sampling control signal is at a high level, and the second to fourth sampling control signals are all at a low level. At this time, the load voltage is sampled on the first capacitor, and the voltage on the second capacitor is reset; then the third sampling control signal is kept at a high level, and the first sampling control signal, the second sampling control signal and the fourth sampling control signal are all at a low level. At this time, the charge stored on the first capacitor is equally divided by the second capacitor, and the second capacitor outputs the first sampling and holding voltage;

[0030] In the sampling and holding stage of the second sampling path sub-circuit, in the initial state, the second sampling control signal is at a high level, and the first sampling control signal, the third sampling control signal and the fourth sampling control signal are all at low levels. At this time, the load voltage is sampled on the third capacitor, and the voltage on the fourth capacitor is reset; then the fourth sampling control signal is kept at a high level, and the first to third sampling control signals are all at low levels. At this time, the charge stored on the third capacitor is equally divided by the fourth capacitor, and the fourth capacitor outputs the second sampling and holding voltage.

[0031] A dual-path rectifier includes the above-mentioned adaptive path selection logic generation circuit.

[0032] As a limitation, the dual-path rectifier further includes a ground path switch module, an RF-DC rectifier module and a load path switch module; the RF-DC rectifier module is externally connected to an RF signal source, and the output end of the load path switch module is externally connected to a load circuit; the ground path switch module includes a first ground path switch submodule and a second ground path switch submodule; the load path switch module includes a first pair of load path switch submodules and a second pair of load path switch submodules;

[0033] The RF-DC rectifier module includes a low-power path circuit based on a second-order cross-coupled rectifier and a high-power path circuit based on a second-order full-NMOS rectifier device;

[0034] The RF+ input terminals of the low power path circuit and the high power path circuit are both connected to the RF+ signal of the RF signal source, and the RF- input terminals are both connected to the RF- signal of the RF signal source;

[0035] Low Power Path Circuit V IN The output terminal of the first ground path switch submodule is terminated, V out The first input terminal of the first load path switch submodule is connected to the first input terminal of the first load path switch submodule, and the first ground path switch submodule constitutes the V of the low power path circuit. IN The first pair of load path switch submodules form the V of the low power path circuit. outThe first input terminal of the first ground path switch submodule is connected to the first timing control signal, and the second input terminal is connected to the third timing control signal, and the first timing control signal and the third timing control signal control the closing and closing of the submodule; the second input terminal of the first load path switch submodule is connected to the first timing control signal, and the first timing control signal controls the closing and closing of the submodule;

[0036] High Power Path Circuit V IN Terminate the output of the second ground path switch submodule, V out The first input terminal of the second load path switch submodule is connected to the V of the second ground path switch submodule forming a high power path circuit. IN The second pair of load path switch submodules form the V out The first input terminal of the second ground path switch submodule is connected to the second timing control signal, and the second input terminal is connected to the fourth timing control signal, and its closing and closing are controlled by the second timing control signal and the fourth timing control signal; the second input terminal of the second load path switch submodule is connected to the second timing control signal, and its closing and closing are controlled by the second timing control signal.

[0037] As a further limitation, the first ground path switch submodule is composed of a first PMOS tube and a seventh NMOS tube, the source of the first PMOS tube is connected to the substrate and the drain of the seventh NMOS tube, and serves as the output end of the first ground path switch submodule, and the drain of the first PMOS tube, the source of the seventh NMOS tube and the substrate are grounded; the gate of the first PMOS tube serves as the first input end of the first ground path switch submodule, and the gate of the seventh NMOS tube serves as the second input end of the first ground path switch submodule;

[0038] The second ground path switch submodule is composed of a second PMOS tube and an eighth NMOS tube. The source of the second PMOS tube is connected to the substrate and the drain of the eighth NMOS tube, serving as the output end of the second ground path switch submodule. The drain of the second PMOS tube, the source of the eighth NMOS tube and the substrate are grounded. The gate of the second PMOS tube serves as the first input end of the second ground path switch submodule, and the gate of the eighth NMOS tube serves as the second input end of the second ground path switch submodule.

[0039] The first pair of load path switch submodules is composed of a third PMOS tube, and the second pair of load path switch submodules is composed of a fourth PMOS tube; the drain of the third PMOS tube serves as the first input end of the first pair of load path switch submodules, and the gate of the third PMOS tube serves as the second input end of the first pair of load path switch submodules; the drain of the fourth PMOS tube serves as the first input end of the second pair of load path switch submodules, and the gate of the fourth PMOS tube serves as the second input end of the second pair of load path switch submodules; the source and substrate of the third PMOS tube, and the source and substrate of the fourth PMOS tube are connected, and together serve as the output end of the load path switch module.

[0040] A radio frequency energy collection system comprises the above-mentioned dual-path rectifier.

[0041] The adaptive path selection logic generation circuit in the present invention provides a path switching logic capable of achieving optimal power point switching within a relatively large range of load resistance values.

[0042] The dual-path rectifier in the present invention can improve the conversion efficiency and sensitivity of the rectifier, widen the input power range, and continuously expand the application scope of the radio frequency energy harvesting system.

[0043] The present invention designs a low-power path circuit based on a second-order cross-coupled rectifier and a high-power path circuit based on a second-order full NMOS rectifier device, and designs a ground path switch module as a V switch for the high-power path circuit and the low-power path circuit. IN The switch from terminal to ground is designed to be used as a V switch for the load path switch module as a high power path circuit and a low power path circuit. out The switch from the end to the load is controlled by the adaptive path selection logic generation circuit. The path switching logic adopted is to respectively turn on the high-power path circuit and the low-power path circuit, and respectively sample and hold the load voltage of this stage. By comparing the load voltages when the two rectifier paths are respectively turned on, the rectifier path with a larger load voltage is selectively turned on, and the rectifier path with a smaller load voltage is turned off. In this way, it is ensured that when the path is switched, the rectifier path with higher energy conversion efficiency is correctly selected; the energy distribution of the idle rectifier path can be reduced, the adaptive path switching is realized, and the search for the optimal path switching point is ensured.

[0044] The path switching logic adopted by the present invention has a high tolerance to load changes, and can achieve accurate selection of the rectification path and efficient collection of energy within a larger load change range.

[0045] The present invention adopts a switching scheme on two current transmission paths, that is, the RF-DC rectifier module to the ground and the RF-DC rectifier module to the load, to achieve a better shutoff effect of the rectifier, reduce the crosstalk of the shutoff path to the conduction path, and increase the energy conversion efficiency.

[0046] Compared with the dual-path RF-DC rectifier applied to the radio frequency energy collection system disclosed in the Chinese invention patent with authorization announcement number CN114244149B, the present invention reduces the use of two auxiliary rectification paths and reduces energy waste.

[0047] The present invention belongs to the technical field of integrated circuits, can improve the conversion efficiency and sensitivity of a rectifier, broaden the input power range, and continuously broaden the application scope of a radio frequency energy collection system. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0049] In the attached picture:

[0050] Figure 1 This is a circuit principle block diagram of Embodiment 1 of the present invention;

[0051] Figures 2A-2J A circuit diagram of each module of the control signal generating subcircuit and the dynamic latch comparator subcircuit of Embodiment 1 of the present invention;

[0052] Figure 3 4 is a circuit schematic diagram of a voltage sampling and holding sub-circuit according to Embodiment 1 of the present invention;

[0053] Figure 4 This is a timing diagram of control signals of the voltage sampling and holding sub-circuit in Embodiment 2 of the present invention;

[0054] Figure 5 This is a circuit diagram of Embodiment 2 of the present invention;

[0055] Figure 6 FIG. 4 is a graph showing a trend of conversion efficiency of a dual-path rectifier according to an embodiment of the present invention as a function of input power. DETAILED DESCRIPTION

[0056] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0057] Embodiment 1 An adaptive path selection logic generation circuit

[0058] like Figure 1As shown, this embodiment includes a voltage sampling and holding subcircuit, a dynamic latch comparator subcircuit and a control signal generating subcircuit. The control signal generating subcircuit is composed of a load voltage V rect power supply, while responding to the load voltage V rect The first sampling control signal V S1 , the second sampling control signal V S2 , the third sampling control signal V H1 and the fourth sampling control signal V H2 , and output to the voltage sampling and holding sub-circuit. The voltage sampling and holding sub-circuit responds to the first sampling control signal V S1 , the second sampling control signal V S2 , the third sampling control signal V H1 and the fourth sampling control signal V H2 For the load voltage V rect Sampling is performed and a first sample-and-hold voltage V is generated. INP and the second sample-and-hold voltage V INN , the first sample hold voltage V INP and the second sample-and-hold voltage V INN The output is sent to the dynamic latch comparator subcircuit. The control signal generation subcircuit is controlled by the load voltage V rect power supply, while responding to the load voltage V rect The first latch control signal V lock and the second latch control signal V unlock , and output to the dynamic latch comparator sub-circuit; the dynamic latch comparator sub-circuit responds to the first sampling and holding voltage V INP , the second sampling and holding voltage V INN , the first latch control signal V lock and the second latch control signal V unlock The first comparison control signal COMP is generated P and the second comparison control signal COMP N , and outputs to the control signal generating sub-circuit. The control signal generating sub-circuit responds to the first comparison control signal COMP P and the second comparison control signal COMP N The first timing control signal V S1P , the second timing control signal V S2P , the third timing control signal V S1N and the fourth timing control signal V S2N , and output to the external circuit.

[0059] Specifically, Figure 2AAs shown, the control signal generating subcircuit includes a current starved ring oscillator, a nine-stage frequency divider, a sampling and holding signal generating submodule, a charge pump submodule, a latch control signal generating submodule and a switch control signal generating submodule.

[0060] like Figure 2B As shown, the current starved ring oscillator includes the first ring oscillator minimum unit to the fifth ring oscillator minimum unit, which are cascaded in sequence, and the NMOS tube M NA1 And PMOS tube M PA1 Provide bias current for ring oscillator, PMOS tube M PA1 The source and substrate are connected to the load voltage V rect , PMOS tube M PA1 The drain of NMOS tube M NA1 The drain of NMOS tube M NA1 The source and substrate of the PMOS tube are grounded to gnd. PA1 The gate of the PMOS tube M PA2 、M PA3 、M PA4 、M PA5 and M PA6 The gate of NMOS tube M NA1 、M NA2 、M NA3 、M NA4 、M NA5 and M NA6 The gate connection bias voltage V bias .

[0061] The minimum ring oscillator unit structure is the source and substrate of the PMOS tube connected to the load voltage V rect The drain of the PMOS tube is connected to the power supply terminal of the inverter INV. The substrate and source of the NMOS tube are grounded to gnd, and the drain of the NMOS tube is connected to the ground gnd of the inverter.

[0062] Among them, the five-stage ring oscillator minimum unit is cascaded, the output end of the inverter of the previous stage in the first ring oscillator minimum unit to the fourth ring oscillator minimum unit is connected to the input end of the inverter of the next stage, and the inverter INV of the fifth ring oscillator minimum unit is connected to the input end of the inverter of the next stage. A5 The output terminal is connected to the first ring oscillator minimum unit inverter INV A1 The inverter INV of the fifth ring oscillator minimum unit A5 The output of the inverter INV A6 and inverter INV A7 The clock signal CLK is then formed and output to a nine-stage frequency divider.

[0063] In this application, see Figure 2C As shown, a nine-stage frequency divider is formed by cascading multiple nine-stage D flip-flops, wherein the connection mode of the D flip-flops is D interface connection. The Q interface is connected to the Clk interface of the next-stage D flip-flop. The Clk interface of the first-stage D flip-flop is connected to the clock signal CLK output by the current-starved ring oscillator.

[0064] The nine-stage frequency divider of the present application generates a first clock signal to a ninth clock signal CLK in response to the clock signal CLK. 1stg ~CLK 9stg , wherein the Q interfaces of the fifth to ninth level D flip-flops sequentially output the fifth to ninth clock signals CLK 5stg ,CLK 6stg ,CLK 7stg ,CLK 8stg and CLK 9stg .

[0065] The fifth-level output terminal and the sixth-level output terminal of the nine-level frequency divider of the present application, that is, the Q interface of the fifth-level D flip-flop and the Q interface of the sixth-level D flip-flop, are directly connected to the clock control input terminal of the sampling and holding signal generating submodule on the one hand, and are connected to the pulse signal input terminal of the sampling and holding signal generating submodule through a logic gate circuit that generates a MONO signal together with the seventh output terminal to the ninth-level output terminal, that is, the Q interface of the seventh-level D flip-flop to the ninth-level D flip-flop, on the other hand.

[0066] The nine-stage frequency divider in the present application converts the fifth clock signal CLK 5stg and the sixth clock signal CLK 6stg The output is sent to the sampling and holding signal generating submodule, and the fifth clock signal to the ninth clock signal CLK 1stg ~CLK 9stg Output to the logic gate circuit; the logic gate circuit responds to the fifth clock signal to the ninth clock signal CLK 1stg ~CLK 9stg The first to fourth single-peak pulse signals MONO1 to MONO4 are generated. On the one hand, the first to fourth single-peak pulse signals MONO1 to MONO4 are output to the sampling and holding signal generating submodule. On the second hand, the second single-peak pulse signal MONO2 and the third single-peak pulse signal MONO3 are output to the latch control signal generating submodule. On the third hand, the third single-peak pulse signal MONO3 is output to the switch control signal generating submodule.

[0067] Specifically, as shown in FIG2 , see Figure 2D As shown, the logic gate circuit of the present application is composed of four minimum units, and the structure of the minimum unit is: NAND gate BNThe two signal input terminals are connected to the signal CLK(10-N)stg and the signal CLK[10-(N+1)]stg respectively, and the NAND gate NAND BN The output terminal is connected to the inverter INV BN The input terminal of the inverter INV BN The output terminal outputs the signal MONO N , where N=1, 2, 3, 4.

[0068] See also Figure 2E As shown, the sampling and holding signal generating submodule of the present application responds to the fifth clock signal CLK 5stg , the sixth clock signal CLK 6stg , the first single-peak pulse signal to the fourth single-peak pulse signal MONO1~MONO4 to generate the first path~the third path selecting the first stage enable signal STAGE1~STAGE3, the first sampling signal Sample1, the second sampling signal Sample2, the first hold control signal HOLD1 and the second hold control signal HOLD2, on the one hand, the first sampling signal Sample1, the second sampling signal Sample2, the first hold control signal HOLD1 and the second hold control signal HOLD2 are output to the charge pump sub-module; on the other hand, the third path selects the first stage enable signal STAGE3 to be output to the latch control signal generating sub-module.

[0069] Specifically, Figure 2E As shown, in the sampling and holding signal generating submodule of the present application, BUFFER C1 The input terminal is connected to the first single peak pulse signal MONO1, BUFFER C1 The output terminal of the first sampling signal Sample1 is output and connected to the inverter INV C1 Input terminal; BUFFER C2 The input end of BUFFER is connected to the second single peak pulse signal MONO2. C2 The output terminal outputs the first path selection first stage enable signal STAGE1; and the NAND gate NAND C1 The two input terminals of the inverter INV are connected C1 and BUFFER C2 The output terminal of the NAND gate C1 The output terminal of the inverter INV C2 The input terminal of the inverter INV C2 The output terminal of the inverter INV outputs the first hold control signal Hold1. C3 The input end of is connected to the third single peak pulse signal MONO3; and the NAND gate NAND C2 The two input terminals of the inverter INV are connected C3The output terminal and the fourth single peak pulse signal MONO4, and the NAND gate NAND C2 The output terminal of the inverter INV C4 The input terminal.

[0070] In the sample-and-hold signal generation submodule of the present application, BUFFER C3 The input terminal is connected to the sixth clock signal CLK 6stg , NAND gate C3 The two input terminals of the inverter INV are connected C4 and BUFFER C3 The output terminal of the NAND gate C3 The output terminal of the inverter INV C5 The input terminal of the inverter INV C5 The output terminal of the inverter INV outputs the third path selection first stage enable signal STAGE3. C6 The input end is connected to the second single peak pulse signal MONO2, and the NAND gate NAND C4 The two input terminals of the inverter INV are connected C6 The output terminal and the sixth clock signal CLK 6stg , NAND gate C4 The output terminal of the inverter INV C7 The input terminal of the inverter INV C7 The output terminal outputs the second path selection first stage enable signal STAGE2.

[0071] In the sample-and-hold signal generation submodule of the present application, BUFFER C4 The input terminal is connected to the fifth clock signal CLK 5stg , NAND gate C5 The two input terminals are connected to the third path selection first stage enable signal STAGE3 and BUFFER C4 The output terminal of the NAND gate C5 The output terminal of the inverter INV C8 The input terminal of the inverter INV C8 The output terminal of the inverter INV outputs the second sampling signal Sample2. C9 The input end of the BUFFER C4 The output terminal of the NAND gate C6 The two input terminals of the inverter INV are connected C9 The output end and the third single peak pulse signal STAGE3, and the NAND gate NAND C6 The output terminal of the inverter INV C10 The input terminal of the inverter INV C10The output terminal outputs a second hold control signal Hold2.

[0072] like Figure 2E As shown, the charge pump submodule of the present application generates a first sampling control signal S in response to a first sampling signal Sample1, a second sampling signal Sample2, a first holding control signal Hold1 and a second holding control signal Hold2. S1 , the second sampling control signal S S2 , the third sampling control signal S H1 and the fourth sampling control signal S H2 And output to the voltage sampling and holding sub-circuit.

[0073] In this application, the minimum unit structure of the charge pump submodule is as follows: Figure 2F Shown: Inverter INV D1 The input terminal of the inverter INV is connected to the input signal input. D1 The output end of the capacitor C1 is connected to one end of the inverter INV D2 The other end of capacitor C1 is connected to the input end of NMOS tube M NC1 The source and M NC2 The gate of capacitor C2 is connected to the output of inverter INVD2 and the other end is connected to NMOS tube M. NC1 The gate, M NC2 The source of the NMOS tube M NC1 and M NC1 The drain is connected to the load voltage V rect , the substrate is connected to the ground gnd. The inverter INVD3 outputs the boosted signal Output.

[0074] In this application, if Figure 2G As shown, the latch control signal generating submodule generates a first latch control signal V in response to the second single-peak pulse signal MONO2, the third single-peak pulse signal MONO3 and the third path selection first stage enable signal STAGE3. lock , the second latch control signal V unlock and the switching control signal SwitchH, on the one hand, the first latch control signal V lock , the second latch control signal V unlock On the one hand, the switching control signal SwitchH is output to the switch control signal generating sub-module.

[0075] like Fig.2I As shown, in this application, in the latch control signal generating submodule, the inverter INV E1 The input end is connected to the second single peak pulse signal MONO2, and the NAND gate NANDE2 The two input terminals of the inverter INV are connected E1 The output end and the third single peak pulse signal MONO3, and the NAND gate NAND E1 The output terminal of the inverter INV E2 The input terminal of the NOR gate E1 The two input terminals of the inverter INV are connected E2 The output terminal and the third path select the first stage enable signal STAGE3, or the NOR gate NOR E1 The output terminal of the inverter INV E3 The input terminal of the inverter INV E3 The output terminal outputs a switching control signal SwitchH.

[0076] In this application, in the latch control signal generating submodule, BUFFER E1 The input end of the signal is connected to the third single-peak pulse signal MONO3, or the NOR gate NOR E2 The two input terminals are connected to BUFFER E1 The output terminal and the third path select the first stage enable signal STAGE3, or the NOR gate NOR E2 The output terminal of the inverter INV E4 The input terminal of the inverter INV E4 The output terminal outputs the first latch control signal V lock , inverter INV E5 The input terminal is connected to the first latch control signal V lock , inverter INV E5 The output terminal outputs the second latch control signal V unlock .

[0077] In the present application, the dynamic latch comparator subcircuit responds to the first sample and hold voltage V INP , the second sampling and holding voltage V INN , the first latch control signal V lock and the second latch control signal V unlock The first comparison control signal COMP is generated N and the second comparison control signal COMP P , and output to the switch control signal generating submodule.

[0078] Figure 2H The circuit topology diagram of the dynamic latch comparator subcircuit is given in the figure. PB1 The source and substrate are connected to the load voltage V rect The gate of the PMOS tube MPB1 is connected to the first latch control signal V lock The drain of the PMOS tube MPB1 is connected to the PMOS tube MPB2 and M PB3 The source of PMOS tube M PB2 and M PB3 The substrate is connected to the load voltage V rect , the gates are connected to the drains of the other side. PB2 The drain outputs the second comparison control signal COMP P , PMOS tube M PB3 The drain of the first comparison control signal COMP N . NMOS tube M NB1 and M NB2 The drain of the PMOS tube M PB2 The drain of NMOS tube M NB3 and M NB4 The drain of the PMOS tube M PB3 The drain of NMOS tube M NB2 The gate of the PMOS tube M PB2 The gate of NMOS tube M NB3 The gate of the PMOS tube M PB3 The gate of NMOS tube M NB1 、M NB2 、M NB3 and M NB4 The source and substrate are both grounded to gnd.

[0079] In the dynamic latch comparator sub-circuit of the present application, the PMOS tube M PB4 and M PB5 The source and substrate are connected to the load voltage V rect ; PMOS tube M PB4 The gate and PMOS tube M PB5 The gates of the two terminals are connected to the second latch control signal V unlock ; PMOS tube M PB4 The drain of NMOS tube M NB5 The drain of the NMOS tube M NB1 The gate of PMOS tube M PB5 The drain of NMOS tube M NB6 The drain of the NMOS tube M NB4 The gate of NMOS tube M NB5 The substrate is connected to the ground gnd, and the gate is connected to the first sampling and holding voltage V INP . NMOS tube M NB6 The substrate is connected to the ground gnd, and the gate is connected to the second sampling and holding voltage V INN . NMOS tube M NB7 The drain of NMOS tube M NB5 and M NB6 The source of NMOS tube MNB7 The source and substrate of NMOS tube M are connected to ground gnd. NB7 The gate of the second latch control signal V unlock .

[0080] The switch control signal generating submodule of the present application responds to the third single-peak pulse signal MONO3, the switching control signal SwitchH, the first comparison control signal COMP N and the second comparison control signal COMP P The first timing control signal V S1P , the second timing control signal V S2P , the third timing control signal V S1N and the fourth timing control signal V S2N , and output to the external circuit.

[0081] like Figure 2J As shown, in the switch control signal generating submodule of the present application, the NOR gate E3 The two input ends are connected to the third single-peak pulse signal MONO3 and the first comparison control signal COMP respectively. N , NOR gate E3 The output terminal outputs the first timing control signal V S1P ; Inverter INV E6 The output end is connected to the first timing control signal V S1P , inverter INV E6 The output end of the charge pump CP is connected to the input end of a charge pump CP, and the output end of the charge pump CP outputs a third timing control signal V S1N ;

[0082] In the switch control signal generating submodule of the present application, the NOR gate E4 The two input terminals are connected to the switching control signal SwitchH and the second comparison control signal COMP respectively. P , NOR gate E4 The output terminal outputs the second timing control signal V S2P , inverter INV E7 The output terminal is connected to the second timing control signal V S2P , inverter INV E7 The output end of the charge pump CP is connected to the input end of another charge pump CP, and the output end of the charge pump CP outputs a fourth timing control signal V S2N .

[0083] like Figure 3 As shown, in this embodiment, the voltage sampling and holding subcircuit includes a first sampling path subcircuit and a second sampling path subcircuit; the first sampling path subcircuit includes first to third NMOS transistors M A1 ~MA3 , the first capacitor C S1 and the second capacitor C H1 The second sampling path sub-circuit includes the fourth to sixth NMOS tubes M A4 ~M A6 , the third capacitor C S2 and the fourth capacitor C H2 The first NMOS tube M A1 and the fourth NMOS tube M A4 The drain is connected to the load voltage V rect , the first NMOS tube M A1 And the third NMOS tube M A3 The gates of the two terminals are connected to the first sampling control signal V S1 , the second NMOS tube M A2 The gate is connected to the third sampling control signal V H1 , the fourth NMOS tube M A4 and the sixth NMOS tube M A6 The gates of the two terminals are connected to the second sampling control signal V S2 , the fifth NMOS tube M A5 The gate of is connected to the fourth sampling control signal V H2 .

[0084] The first NMOS tube M A1 The source of the first capacitor C S1 Gnd is grounded, and the other side is connected to the second NMOS tube M A2 The drain of the second NMOS tube M A2 The source of the H1 Gnd is grounded, and the other side is connected to the third NMOS tube M A3 The drain of the third NMOS tube M A3 The source of the second NMOS tube M is grounded gnd; A2 , the third NMOS tube M A3 and the second capacitor C H1 The common terminal is used as the first sample and hold voltage V INP The output terminal.

[0085] The fourth NMOS tube M A4 The source of S2 Gnd is grounded, and the fifth NMOS tube M A5 The drain of the fifth NMOS tube M A5 The source of H2 The ground gnd, on the other hand, is connected to the sixth NMOS tube M A6 The drain of the sixth NMOS tube M A6 The source of the fifth NMOS tube M is grounded gnd;A5 , the sixth NMOS tube M A6 and the fourth capacitor C H2 The common terminal is used as the second sample and hold voltage V INN The output terminal.

[0086] The voltage sampling and holding subcircuit control signal timing is as follows Figure 4 As shown: In the first sampling path sub-circuit sampling and holding phase, the initial state, the first sampling control signal V S1 is high level, the second to fourth sampling control signals V S2 、V H1 、V H2 are both low level. At this time, the first capacitor C S1 Up-sampling load voltage V rect , the second capacitor C H1 The voltage on is reset; then the third sampling control signal V H1 is high level, the first sampling control signal V S1 , the second sampling control signal V S2 and the fourth sampling control signal V H2 Both are low level, at this time the first capacitor C S1 The charge stored on the second capacitor C H1 The second capacitor C H1 Output the first sample hold voltage V INP In the sampling and holding phase of the second sampling path subcircuit, in the initial state, the second sampling control signal V H1 is high level, the first sampling control signal V S1 , the third sampling control signal V H1 and the fourth sampling control signal V H2 are all low level. At this time, the third capacitor C S2 Up-sampling load voltage V rect , the fourth capacitor C H2 The voltage on is reset; then the fourth sampling control signal V H2 is high level, the first to third sampling control signals V S1 、V S2 、V H1 All are low level, at this time the third capacitor C S2 The charge stored on the fourth capacitor V H2 Bisect, the fourth capacitor V H2 Output the second sample and hold voltage V INN .

[0087] Example 2 Dual-path rectifier

[0088] like Figure 5As shown, this embodiment includes an adaptive path selection logic generation circuit in Embodiment 1, and also includes a ground path switch module, an RF-DC rectifier module, and a load path switch module. Among them, the RF-DC rectifier module is externally connected to the RF signal source, and the output end of the load path switch module is externally connected to the load circuit; the ground path switch module includes a first ground path switch submodule and a second ground path switch submodule; the load path switch module includes a first pair of load path switch submodules and a second pair of load path switch submodules.

[0089] The RF-DC rectifier module includes a low-power path circuit based on a second-order cross-coupled rectifier and a high-power path circuit based on a second-order full NMOS rectifier device. The RF+ input terminals of the low-power path circuit and the high-power path circuit are both connected to the RF+ signal of the RF signal source, and the RF- input terminals are both connected to the RF- signal of the RF signal source.

[0090] Among them, the low power path circuit V IN The output terminal of the first ground path switch submodule is terminated, V out The first input terminal of the first load path switch submodule is connected to the first input terminal of the first load path switch submodule, and the first ground path switch submodule constitutes the V of the low power path circuit. IN The first pair of load path switch submodules form the V of the low power path circuit. out The first input terminal of the first ground path switch submodule is connected to the first timing control signal, and the second input terminal is connected to the third timing control signal, and its closing and closing are controlled by the first timing control signal and the third timing control signal; the second input terminal of the first load path switch submodule is connected to the first timing control signal, and its closing and closing are controlled by the first timing control signal.

[0091] Among them, the high power path circuit V IN Terminate the output of the second ground path switch submodule, V out The first input terminal of the second load path switch submodule is connected to the V of the second ground path switch submodule forming a high power path circuit. IN The second pair of load path switch submodules form the V out The first input terminal of the second ground path switch submodule is connected to the second timing control signal, and the second input terminal is connected to the fourth timing control signal, and its closing and closing are controlled by the second timing control signal and the fourth timing control signal; the second input terminal of the second load path switch submodule is connected to the second timing control signal, and its closing and closing are controlled by the second timing control signal.

[0092] Specifically, Figure 5 As shown, the first ground path switch submodule is composed of a first PMOS transistor M P1and the seventh NMOS tube M N1 The first PMOS tube M P1 The source and substrate of the seventh NMOS tube M N1 The first PMOS tube M is connected to the drain of the first PMOS tube M as the output end of the first ground path switch submodule. P1 The drain of the seventh NMOS tube M N1 The source and substrate of the first PMOS tube M are grounded to gnd; P1 The gate of the first ground path switch submodule is connected to the first timing control signal V S1P , the seventh NMOS tube M N1 The gate of the first ground path switch submodule is connected to the third timing control signal V S1N .

[0093] like Figure 5 As shown, the second ground path switch submodule is composed of a second PMOS transistor M P2 and the eighth NMOS tube M N2 The second PMOS tube M P2 The source and substrate of the eighth NMOS tube M N2 The second PMOS tube M is connected to the drain of the second PMOS tube M and serves as the output end of the second ground path switch submodule. P2 The drain of the eighth NMOS tube M N2 The source and substrate of the second PMOS tube M are grounded to gnd; P2 The gate of the second ground path switch submodule is connected to the second timing control signal V S2P , the eighth NMOS tube M N2 The gate of the second ground path switch submodule is connected to the fourth timing control signal V S2N .

[0094] like Figure 5 As shown, the first pair of load path switch submodules are composed of the third PMOS transistor M P3 The second pair of load path switch submodules is composed of a fourth PMOS transistor M P4 The third PMOS tube M P3 The drain of the third PMOS tube M is used as the first input terminal of the first pair of load path switch submodules. P3 The gate of the first pair of load path switch submodules is connected to the first timing control signal V S1P ; The fourth PMOS tube M P4 The drain of the fourth PMOS tube M is used as the first input terminal of the second pair of load path switch submodules. P4 The gate of the second pair of load path switch submodules is connected to the second timing control signal V S2PThe third PMOS tube M P3 The source and substrate of the fourth PMOS tube M P4 The source and substrate are connected together as the output end of the load path switch module to connect an external load circuit, such as a parallel capacitor C L , resistor R L , the parallel capacitor C L , resistor R L The other end is grounded.

[0095] The following describes the underlying logic of opening and closing the rectification path by controlling the ground path switch module and the load path switch module in this embodiment.

[0096] like Figure 5 As shown, when the switch control signals VS1N and VS2P are at a high level, and VS1P and VS2N are at a low level, the path switch of the 2nd-order cross-coupled rectifier is turned on, and the path switch of the 2nd-order full NMOS rectifier is turned off; at this time, the path of the 2nd-order cross-coupled rectifier is in a low-impedance state to the RF source, and the path of the 2nd-order full NMOS rectifier is in a high-impedance state to the RF source, and the RF energy mainly flows into the path of the 2nd-order cross-coupled rectifier. Similarly, when the switch control signals VS1N and VS2P are at a low level, and VS1P and VS2N are at a high level, the path switch of the 2nd-order cross-coupled rectifier is turned off, and the path switch of the 2nd-order full NMOS rectifier is turned on; at this time, the path of the 2nd-order cross-coupled rectifier is in a high-impedance state to the RF source, and the path of the 2nd-order full NMOS rectifier is in a low-impedance state to the RF source, and the RF energy mainly flows into the path of the 2nd-order full NMOS rectifier.

[0097] From the above analysis, it can be seen that this example realizes the switching between the on mode and the off mode of the rectification path by controlling the gate voltages of the two switches.

[0098] Figure 6 The figure shows the trend of the conversion efficiency of the dual-path rectifier changing with the input power. Generally, the PCE curve of the rectifier using a single topology shows a single peak. Figure 6 It can be seen that the PCE curve of the dual-path rectifier provided in this embodiment reaches a peak at -7dBm and then continues to rise after -4dBm. This shows that the dual-path rectifier combines the advantages of high energy conversion efficiency of the cross-coupled topology rectifier at low input power and the advantages of high energy conversion efficiency of the full NMOS topology rectifier at high input power, broadening the dynamic energy collection range of the rectifier.

[0099] Example 3 RF Energy Harvesting System

[0100] This embodiment provides a radio frequency energy collection system, which includes the dual-path rectifier in embodiment 2. It also includes an antenna, a matching network, a rectifier, an energy management circuit and an energy storage element; the dual-path rectifier converts AC radio frequency energy into a DC signal and powers the entire radio frequency energy collection system.

Claims

1. An adaptive path selection logic generation circuit, characterized in that: It includes a voltage sampling and holding subcircuit, a dynamic latch comparator subcircuit and a control signal generating subcircuit; The control signal generating subcircuit is powered by the load voltage, and generates first to fourth sampling control signals in response to the load voltage, and outputs the first to fourth sampling control signals to the voltage sampling and holding subcircuit; The voltage sampling and holding subcircuit samples the load voltage in response to the first to fourth sampling control signals, generates a first sampling and holding voltage and a second sampling and holding voltage, and outputs the first sampling and holding voltage and the second sampling and holding voltage to the dynamic latch comparator subcircuit; The control signal generating subcircuit is powered by a load voltage and generates a first latch control signal and a second latch control signal in response to the load voltage, and outputs the signals to the dynamic latch comparator subcircuit; The dynamic latch comparator subcircuit generates a first comparison control signal and a second comparison control signal in response to the first sample-and-hold voltage, the second sample-and-hold voltage, the first latch control signal and the second latch control signal, and outputs the signals to the control signal generation subcircuit; The control signal generating sub-circuit generates first to fourth timing control signals in response to the first comparison control signal and the second comparison control signal, and outputs the signals to the external circuit.

2. The adaptive path selection logic generation circuit according to claim 1, characterized in that: The control signal generating subcircuit includes a current starved ring oscillator, a nine-stage frequency divider, a sample and hold signal generating submodule, a charge pump submodule, a latch control signal generating submodule and a switch control signal generating submodule; The current-starved ring oscillator comprises first to fifth ring oscillator minimum units which are cascaded in sequence, wherein the output end of the fifth ring oscillator minimum unit is connected to the input end of a nine-stage frequency divider through two serially connected inverters; the current-starved ring oscillator is externally connected to a load voltage, generates a clock signal in response to the load voltage and outputs the clock signal to the nine-stage frequency divider through two serially connected inverters, and the nine-stage frequency divider generates first to ninth clock signals in response to the clock signal; The fifth and sixth output terminals of the nine-level frequency divider are directly connected to the clock control input terminal of the sampling and holding signal generating submodule on the one hand, and are connected to the pulse signal input terminal of the sampling and holding signal generating submodule through a logic gate circuit together with the seventh to ninth output terminals on the other hand; The nine-stage frequency divider outputs the fifth clock signal and the sixth clock signal to the sampling and holding signal generating submodule on the one hand, and outputs the fifth to ninth clock signals to the logic gate circuit on the other hand; the logic gate circuit generates the first to fourth single-peak pulse signals in response to the fifth to ninth clock signals, outputs the first to fourth single-peak pulse signals to the sampling and holding signal generating submodule on the one hand, outputs the second single-peak pulse signal and the third single-peak pulse signal to the latch control signal generating submodule on the second hand, and outputs the third single-peak pulse signal to the switch control signal generating submodule on the third hand; The sampling and holding signal generating submodule generates first to third path selection first stage enable signals, a first sampling signal, a second sampling signal, a first holding control signal, and a second holding control signal in response to the fifth clock signal, the sixth clock signal, and the first to fourth single-peak pulse signals, and outputs the first sampling signal, the second sampling signal, the first holding control signal, and the second holding control signal to the charge pump submodule on the one hand; and outputs the third path selection first stage enable signal to the latch control signal generating submodule on the other hand; The charge pump submodule generates first to fourth sampling control signals in response to the first sampling signal, the second sampling signal, the first holding control signal and the second holding control signal and outputs the first to fourth sampling control signals to the voltage sampling and holding subcircuit; The latch control signal generating submodule generates a first latch control signal, a second latch control signal and a switching control signal in response to the second single-peak pulse signal, the third single-peak pulse signal and the third path selection first stage enabling signal, and outputs the first latch control signal and the second latch control signal to the dynamic latch comparator subcircuit on the one hand, and outputs the switching control signal to the switch control signal generating submodule on the other hand; The dynamic latch comparator sub-circuit generates a first comparison control signal and a second comparison control signal in response to the first sample-and-hold voltage, the second sample-and-hold voltage, the first latch control signal and the second latch control signal, and outputs the signals to the switch control signal generation sub-module; The switch control signal generating submodule generates first to fourth timing control signals in response to the third single-peak pulse signal, the switching control signal, the first comparison control signal and the second comparison control signal, and outputs the first to fourth timing control signals to the external circuit.

3. The adaptive path selection logic generation circuit according to claim 1 or 2, characterized in that: The voltage sample and hold subcircuit includes a first sampling path subcircuit and a second sampling path subcircuit; The first sampling path subcircuit includes first to third NMOS transistors, a first capacitor and a second capacitor; the second sampling path subcircuit includes fourth to sixth NMOS transistors, a third capacitor and a fourth capacitor; The drains of the first NMOS tube and the fourth NMOS tube are connected to the load voltage, the gates of the first NMOS tube and the third NMOS tube are connected to the first sampling control signal, the gate of the second NMOS tube is connected to the third sampling control signal, the gates of the fourth NMOS tube and the sixth NMOS tube are connected to the second sampling control signal, and the gate of the fifth NMOS tube is connected to the fourth sampling control signal; The source of the first NMOS tube is grounded through the first capacitor on the one hand, and connected to the drain of the second NMOS tube on the other hand. The source of the second NMOS tube is grounded through the second capacitor on the one hand, and connected to the drain of the third NMOS tube on the other hand. The source of the third NMOS tube is grounded; the common end of the second NMOS tube, the third NMOS tube and the second capacitor serves as the output end of the first sampling and holding voltage; The source of the fourth NMOS tube is grounded through the third capacitor on the one hand, and connected to the drain of the fifth NMOS tube on the other hand. The source of the fifth NMOS tube is grounded through the fourth capacitor on the one hand, and connected to the drain of the sixth NMOS tube on the other hand. The source of the sixth NMOS tube is grounded; the common end of the fifth NMOS tube, the sixth NMOS tube and the fourth capacitor serves as the output end of the second sampling and holding voltage; In the sampling and holding stage of the first sampling path sub-circuit, in the initial state, the first sampling control signal is at a high level, and the second to fourth sampling control signals are all at a low level. At this time, the load voltage is sampled on the first capacitor, and the voltage on the second capacitor is reset; then the third sampling control signal is kept at a high level, and the first sampling control signal, the second sampling control signal and the fourth sampling control signal are all at a low level. At this time, the charge stored on the first capacitor is equally divided by the second capacitor, and the second capacitor outputs the first sampling and holding voltage; In the sampling and holding stage of the second sampling path sub-circuit, in the initial state, the second sampling control signal is at a high level, and the first sampling control signal, the third sampling control signal and the fourth sampling control signal are all at low levels. At this time, the load voltage is sampled on the third capacitor, and the voltage on the fourth capacitor is reset; then the fourth sampling control signal is kept at a high level, and the first to third sampling control signals are all at low levels. At this time, the charge stored on the third capacitor is equally divided by the fourth capacitor, and the fourth capacitor outputs the second sampling and holding voltage.

4. Dual-path rectifier, characterized in that, The adaptive path selection logic generation circuit comprises the adaptive path selection logic generation circuit as described in any one of claims 1 to 3.

5. The dual-path rectifier according to claim 4, characterized in that: The dual-path rectifier further includes a ground path switch module, an RF-DC rectifier module and a load path switch module; the RF-DC rectifier module is externally connected to an RF signal source, and the output end of the load path switch module is externally connected to a load circuit; the ground path switch module includes a first ground path switch submodule and a second ground path switch submodule; the load path switch module includes a first pair of load path switch submodules and a second pair of load path switch submodules; The RF-DC rectifier module includes a low-power path circuit based on a second-order cross-coupled rectifier and a high-power path circuit based on a second-order full-NMOS rectifier device; The RF+ input terminals of the low power path circuit and the high power path circuit are both connected to the RF+ signal of the RF signal source, and the RF- input terminals are both connected to the RF- signal of the RF signal source; Low Power Path Circuit V IN The output terminal of the first ground path switch submodule is terminated, V out The first input terminal of the first load path switch submodule is connected to the first input terminal of the first load path switch submodule, and the first ground path switch submodule constitutes the V of the low power path circuit. IN The first pair of load path switch submodules form the V of the low power path circuit. out The first input terminal of the first ground path switch submodule is connected to the first timing control signal, and the second input terminal is connected to the third timing control signal, and the first timing control signal and the third timing control signal control the closing and closing of the submodule; the second input terminal of the first load path switch submodule is connected to the first timing control signal, and the first timing control signal controls the closing and closing of the submodule; High Power Path Circuit V IN The output terminal of the second ground path switch submodule is terminated, V out The first input terminal of the second load path switch submodule is connected to the V of the second ground path switch submodule forming a high power path circuit. IN The second pair of load path switch submodules form the V out The first input terminal of the second ground path switch submodule is connected to the second timing control signal, and the second input terminal is connected to the fourth timing control signal, and its closing and closing are controlled by the second timing control signal and the fourth timing control signal; the second input terminal of the second load path switch submodule is connected to the second timing control signal, and its closing and closing are controlled by the second timing control signal.

6. The dual-path rectifier according to claim 5, characterized in that: The first ground path switch submodule is composed of a first PMOS tube and a seventh NMOS tube. The source of the first PMOS tube is connected to the substrate and the drain of the seventh NMOS tube, serving as the output end of the first ground path switch submodule. The drain of the first PMOS tube, the source of the seventh NMOS tube and the substrate are grounded. The gate of the first PMOS tube serves as the first input end of the first ground path switch submodule, and the gate of the seventh NMOS tube serves as the second input end of the first ground path switch submodule. The second ground path switch submodule is composed of a second PMOS tube and an eighth NMOS tube. The source of the second PMOS tube is connected to the substrate and the drain of the eighth NMOS tube, serving as the output end of the second ground path switch submodule. The drain of the second PMOS tube, the source of the eighth NMOS tube and the substrate are grounded. The gate of the second PMOS tube serves as the first input end of the second ground path switch submodule, and the gate of the eighth NMOS tube serves as the second input end of the second ground path switch submodule. The first pair of load path switch submodules is composed of a third PMOS tube, and the second pair of load path switch submodules is composed of a fourth PMOS tube; the drain of the third PMOS tube serves as the first input end of the first pair of load path switch submodules, and the gate of the third PMOS tube serves as the second input end of the first pair of load path switch submodules; the drain of the fourth PMOS tube serves as the first input end of the second pair of load path switch submodules, and the gate of the fourth PMOS tube serves as the second input end of the second pair of load path switch submodules; the source and substrate of the third PMOS tube, and the source and substrate of the fourth PMOS tube are connected, and together serve as the output end of the load path switch module.

7. A radio frequency energy harvesting system, characterized in that: A dual-path rectifier comprising the dual-path rectifier described in any one of claims 4-6.

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