An adc based on a neural network enhanced heterogeneous channel architecture

Abstract

The application discloses an ADC based on a neural network enhanced heterogeneous channel architecture and relates to the technical field of ADC design.The ADC comprises two-way heterogeneous ADC channels, a delay module, a neural network circuit and a streaming training controller.The two-way heterogeneous ADC channels are a high-speed low-precision channel and a low-speed high-precision channel, and the two channels are connected to the same signal source.The delay module performs delay and alignment processing on the output data of the two-way channels, the multi-time dimension data formed after the high-speed channel is delayed is aligned with the single time dimension data of the low-speed channel, the high-speed channel data is taken as training data, the low-speed channel data is taken as label data, the neural network circuit is used for training to generate high-speed high-precision quantization output, and the streaming training controller globally manages data acquisition and batch processing operations and generates training data through downsampling, time offset and batch processing.The application can realize the combination of high speed and high precision and meet the complex signal processing requirement.

Description

Technical Field

[0001] This invention relates to the technical field of ADC design, and more specifically, to an ADC based on a heterogeneous channel architecture enhanced by neural networks. Background Technology

[0002] An analog-to-digital converter (ADC) is a core component in modern electronic devices that converts analog signals into digital signals. It is widely used in communications, medical devices, industrial control, and consumer electronics. To meet the needs of different applications, ADCs typically require a balance between high sampling speed and high quantization accuracy.

[0003] High-speed, low-precision ADC: It captures signals quickly with a higher sampling frequency, but due to limitations in hardware design, its quantization accuracy is low and it is prone to introducing errors.

[0004] Low-speed, high-precision ADCs can provide accurate signal quantization, but their low sampling frequency makes it difficult to meet the needs of real-time processing of dynamic signals.

[0005] While high-speed, low-precision ADCs and low-speed, high-precision ADCs each have their advantages, current technologies struggle to effectively combine the two. In applications requiring both rapid response and high-precision quantization, such as real-time data analysis and dynamic signal detection, a single type of ADC often cannot meet the demands simultaneously. Some systems have attempted to combine high-speed, low-precision ADCs with low-speed, high-precision ADCs, but due to the fundamental difference in their sampling frequencies, their data outputs are difficult to synchronize on the time axis, and the lack of efficient data fusion methods results in a failure to significantly improve the overall system performance. Summary of the Invention

[0006] The purpose of this invention is to construct a heterogeneous channel architecture based on neural network enhancement, which integrates the advantages of high-speed low-precision channels and low-speed high-precision channels, to realize an ADC system that combines high-speed sampling and high-precision quantization output, so as to meet the needs of complex signal processing.

[0007] The technical solution of the present invention is: to provide an ADC based on a heterogeneous channel architecture enhanced by a neural network, the ADC including: two heterogeneous ADC channels, a delay module, a neural network circuit, and a streaming training controller;

[0008] The two heterogeneous ADC channels are a high-speed low-precision channel and a low-speed high-precision channel, respectively. The two channels are ADCs with different performance and are connected to the same signal source. The high-speed low-precision channel has a higher sampling frequency than the low-speed high-precision channel, which is used to quickly capture changes in high-frequency signals; the low-speed high-precision channel is used to provide high-precision quantization data as a reference.

[0009] The delay module is connected to the output of the two heterogeneous ADC channels to perform delay and alignment processing on the two output data. The multi-time dimension data of the high-speed low-precision channel is aligned with the single-time dimension data of the low-speed high-precision channel after delay processing.

[0010] The neural network circuit consists of an input layer, a hidden layer, and an output layer. The number of neurons in the input layer is consistent with the feature dimension of the input data, the number of neurons in the hidden layer is adjustable, and the number of neurons in the output layer is 1. All nodes in the preceding and following layers are interconnected. The neural network circuit integrates the advantages of high-speed low-precision channels and low-speed high-precision channels during training. The output of the high-speed low-precision channel is used as training data, and the output of the low-speed high-precision channel is used as label data. During training, the weights and biases are adjusted to generate high-speed and high-precision quantized output.

[0011] The streaming training controller is used for global control of data acquisition from two heterogeneous ADC channels, alignment of delay modules, and generation of training data for neural network circuits. It generates diverse training data through downsampling, time offsetting, and batch processing operations.

[0012] In any of the above technical solutions, the delay module is further connected to the outputs of the high-speed low-precision channel and the low-speed high-precision channel respectively. The delay module delays the high-speed data according to the sampling clock frequency of the low-speed high-precision channel to ensure that the high-speed data is aligned with the low-speed data. The delay module temporarily stores the multi-time dimension data output by the high-speed low-precision channel through a register. After the delay, it is aligned with the single-time dimension data of the low-speed high-precision channel and outputs synchronous data for use by the neural network circuit.

[0013] In any of the above technical solutions, the workflow of the streaming training controller is further as follows:

[0014] S1. Parameter settings: Set the sampling clock frequency fa of the high-speed low-precision channel ADC and the sampling clock frequency fb of the low-speed high-precision channel ADC, and set the interval sampling number N that determines the amount of high-speed low-precision data collected each time, and the offset constant M that controls the time offset number of the low-speed channel.

[0015] S2. Downsampling operation: After the sampling clocks of the two ADC channels are aligned for the first time, the sampling clock of the low-speed channel ADC is used as the reference. The output data of N high-speed low-precision channel ADCs in multiple time dimensions are collected as training data, and the output data of the low-speed high-precision channel ADC in one time dimension is collected as label data.

[0016] S3, Offset Operation: After each downsampling operation is completed, the streaming training controller performs a time offset on the sampling clock of the low-speed high-precision channel. The offset is 1 / fa of the high-speed low-precision channel clock period. The low-speed high-precision channel data after the time offset will be downsampled with the new high-speed low-precision data.

[0017] S4. Batch processing operation: M offset operations are used as a batch processing cycle. Each batch contains N*(M+1) label data and corresponding training data, which are input into the neural network circuit for training.

[0018] In any of the above technical solutions, the neural network circuit further adapts to the quantization requirements of different signal characteristics by adjusting the number of neurons in the input layer and hidden layer, thereby improving the generalization performance and inference accuracy of the model.

[0019] In any of the above technical solutions, a verification system for an ADC based on a heterogeneous channel architecture enhanced by a neural network is further constructed. The verification system uses a signal fitting method to obtain high-precision quantization results as label data for the neural network circuit, in order to replace the output of the low-speed, high-precision channel.

[0020] The beneficial effects of this invention are:

[0021] The technical solution in this invention achieves a balance between high speed and high precision through a combination of hardware and software. By using two heterogeneous ADC channels (high-speed low-precision channel and low-speed high-precision channel), the high-speed channel captures dynamic signal characteristics, while the low-speed channel provides accurate reference data, giving full play to the advantages of both. A delay module is used to synchronize the output of the heterogeneous channels, overcoming the data alignment problem caused by the difference in sampling frequency in traditional methods.

[0022] The neural network circuit takes multi-time dimension data provided by the high-speed channel as input and high-precision data provided by the low-speed channel as labels. Through training, it achieves fast and high-precision signal quantization output, which greatly improves the intelligence level of the system and can significantly improve performance without increasing hardware complexity.

[0023] In a preferred embodiment of the present invention, training data is dynamically generated through a streaming training controller. A combination strategy of downsampling, time offsetting, and batch processing is adopted to effectively overcome the problem of sparsity of low-speed, high-precision channel data, generate rich training data, and ensure the training effect of the model. This strategy also generates diverse label data through time offsetting operations, which significantly improves the generalization ability of the neural network model.

[0024] This invention does not rely on expensive hardware optimization. Instead, it achieves high-speed and high-precision collaborative operation through delay modules and AI algorithms, which greatly reduces the complexity and cost of hardware design.

[0025] This invention provides a novel ADC architecture and enables chip-level verification of this architecture. In addition to calibrating the errors of high-speed, low-precision channels in the ADC, this architecture also enables the expression limit of the ADC channel to exceed the expression limit of the target to be calibrated, providing a new quantization bit depth, which is groundbreaking. Attached Figure Description

[0026] The advantages of the above and additional aspects of the present invention will become apparent and readily understood in the description of the embodiments in conjunction with the following drawings, wherein:

[0027] Figure 1 This is a schematic diagram of the principle of an ADC based on a neural network-enhanced heterogeneous channel architecture according to an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the operation of a streaming training controller for an ADC based on a neural network-enhanced heterogeneous channel architecture according to an embodiment of the present invention.

[0029] Figure 3 This is a schematic diagram of the verification system principle of an ADC based on a neural network-enhanced heterogeneous channel architecture according to an embodiment of the present invention;

[0030] Figure 4 This is a pipelined ADC output spectrum diagram of an ADC based on a neural network-enhanced heterogeneous channel architecture according to an embodiment of the present invention.

[0031] Figure 5 This is a fitted output spectrum of an ADC based on a neural network-enhanced heterogeneous channel architecture according to an embodiment of the present invention.

[0032] Figure 6 This is a schematic diagram of the neural network quantization output of an ADC based on a heterogeneous channel architecture with neural network enhancement according to an embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of a signal acquisition system for an ADC based on a neural network-enhanced heterogeneous channel architecture according to an embodiment of the present invention. Detailed Implementation

[0034] To better understand the above-mentioned objectives, features, and advantages of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, unless otherwise specified, the embodiments of the present invention and the features thereof can be combined with each other.

[0035] In the following description, many specific details are set forth in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0036] like Figure 1 As shown, this embodiment provides an ADC based on a heterogeneous channel architecture enhanced by a neural network. The ADC includes: two heterogeneous ADC channels, a delay module, a neural network circuit, and a streaming training controller.

[0037] The two heterogeneous ADC channels consist of two ADCs with different performances, a high-speed low-precision channel and a low-speed high-precision channel, connected to the same signal source. The two channels of the heterogeneous channel architecture have different output characteristics. The high-speed low-precision channel is responsible for quickly capturing changes in high-frequency signals, while the low-speed high-precision channel is responsible for providing high-precision quantization data as a reference.

[0038] The high-speed, low-precision channel can compensate for the delay problem of the low-speed, high-precision channel under rapidly changing signals, while the low-speed, high-precision channel can compensate for the error caused by the insufficient precision of the high-speed, low-precision channel. When facing different signal requirements, the two data channels can be flexibly combined to improve overall performance. The data from the two channels provide richer and more complete information for subsequent AI neural networks: the high-speed, low-precision channel provides multi-time dimension data, which can provide training data for subsequent neural network circuit training; the low-speed, high-precision channel provides accurate reference data, which provides label data for neural network training.

[0039] Because the two heterogeneous ADC channels have different sampling rates, the high-speed, low-precision channel has a higher data acquisition frequency, generates a large amount of data with short intervals, while the low-speed, high-precision channel has a lower data acquisition frequency, generates a smaller amount of data with long intervals. The outputs of the two are mismatched in the time dimension and cannot be directly used for training and inference of neural network circuits. They need to be aligned and processed by subsequent delay modules to ensure the timing consistency of the data.

[0040] The delay module is a crucial part of the entire system for processing the data output from two heterogeneous ADC channels. It connects to the outputs of both the high-speed, low-precision channel and the low-speed, high-precision channel. The delay module calculates an appropriate delay time based on the sampling clock of the low-speed, high-precision channel, delaying the high-speed data to ensure alignment with the low-speed data. It uses registers (…) Figure 1 The "+" module temporarily stores multi-time dimension data output from the high-speed, low-precision channel, aligns it with the output frequency of the low-speed, high-precision channel, and outputs it synchronously to the neural network circuit.

[0041] The neural network circuit learns the data characteristics of two heterogeneous ADC channels, integrates the advantages of the two channels, and finally achieves high-speed and high-precision signal quantization output.

[0042] A neural network circuit consists of an input layer, hidden layers, and an output layer. The number of neurons in the input layer is consistent with the feature dimension of the input data. The number of neurons in the hidden layer is adjustable, and the number of neurons in the output layer is 1. All nodes in the preceding and following layers are interconnected. By adjusting the number of neurons in the input and hidden layers, the model can adapt to the quantization requirements of different signal characteristics, thereby improving its generalization performance and inference accuracy.

[0043] The neural network circuit uses the output of the high-speed, low-precision channel as training data and the output of the low-speed, high-precision channel as label data. The neural network circuit adjusts its own weights and biases to minimize the error between the output of the output layer neurons and the label data, providing users with near-high-precision and high-speed quantized data.

[0044] The streaming training controller manages the global operation of this neural network-enhanced heterogeneous channel architecture ADC, such as... Figure 2 As shown, the workflow of the streaming training controller is as follows:

[0045] S1. Parameter settings: Set the sampling clock frequency fa of the high-speed low-precision channel ADC and the sampling clock frequency fb of the low-speed high-precision channel ADC, and set the interval sampling number N that determines the amount of high-speed low-precision data collected each time, and the offset constant M that controls the time offset number of the low-speed channel.

[0046] S2. Downsampling operation: After the sampling clocks of the two ADC channels are aligned for the first time, the sampling clock of the low-speed channel ADC is used as the reference. The output data of N high-speed low-precision channel ADCs in multiple time dimensions are collected as training data each time, and the output data of the low-speed high-precision channel ADC in one time dimension is collected as label data.

[0047] S3. Offset Operation: After each downsampling operation, the streaming training controller performs a time offset on the sampling clock of the low-speed high-precision channel. The offset is 1 / fa of the high-speed low-precision channel clock period. The low-speed high-precision channel data after the time offset will be downsampled with the new high-speed low-precision data.

[0048] S4. Batch processing operation: M offset operations are used as a batch processing cycle. Each batch contains N*(M+1) label data and corresponding training data, which are input into the neural network circuit for training.

[0049] Because the high-speed channel has dense data but the low-speed channel has sparse data, the above offset operation creates a new alignment between the low-speed high-precision channel and the high-speed low-precision channel on the time axis, generating more diverse label data and making up for the scarcity of low-speed high-precision channel data.

[0050] This invention employs a novel ADC architecture, which not only calibrates the errors of the high-speed, low-precision channel in the ADC, but also allows the ADC's expression limit to exceed the expression limit of the target being calibrated, providing a new quantization bit depth, thus possessing pioneering value. For example, in the heterogeneous channel architecture of this invention, the high-speed, low-precision channel is a 14-bit ADC, and this invention has achieved an effective expression accuracy exceeding 14.3 bits through the following verification system.

[0051] like Figure 3 and Figure 7 As shown, a verification system for the aforementioned ADC based on a neural network-enhanced heterogeneous channel architecture was constructed:

[0052] To verify the proposed heterogeneous channel architecture ADC based on neural network enhancement, data acquisition and reconstruction are first required to construct heterogeneous channel architectures with high speed and low precision and low speed and high precision. Then, the neural network is trained to obtain high speed and high precision quantization output.

[0053] The data acquisition system utilizes a 14-bit, 1Gsps commercial pipelined ADC chip as a high-speed, low-precision channel to achieve a high-speed, low-precision quantization channel. The system includes a signal generator, clock board, chip test board, FPGA development board, and computer. The signal generator provides the analog signal to the ADC, the clock board provides the operating clock for the ADC, the chip test board provides the carrier and interface for the ADC, and the FPGA development board performs the signal protocol conversion, transmitting the signal to the computer's host software and ultimately saving it as dataset D1.

[0054] Data reconstruction utilizes signal fitting methods to obtain high-precision quantization results, and then constructs a low-speed, high-precision quantization channel and neural network training dataset using offset downsampling. First, the sine fitting tool in MATLAB's fitting toolbox is used to fit the signal output from the signal acquisition system, thereby obtaining high-precision quantization results, which are saved as dataset D2. Subsequently, offset downsampling is used to construct the low-speed, high-precision quantization channel and neural network training dataset. The specific process is as follows:

[0055] Parameter settings: Set the downsampling factor P, the number of interval sampling times N, the offset constant M, and the number of feature dimensions T.

[0056] Split the dataset: After aligning the datasets D1 and D2 by time, split them into a training set Dtrain1 and a test set Dtest1 in an 8:2 ratio.

[0057] Reconstructing the training dataset: Based on the training set data, downsampling is performed using a downsampling factor, meaning the frequency is reduced to 1 / P of the original frequency after downsampling. Each time, T time-dimension data from channel D1 are collected as input data for neural network training, while one time-dimension data from channel D2 is collected as label data for neural network training. After N collections, a time-cycle shift is performed, and downsampling is performed again to obtain a low-speed, high-precision quantization channel. The downsampled data is then batched into N*(M+1) groups to obtain the final neural network reconstruction training dataset Dtrain2.

[0058] The neural network is trained using a batch processing method to output high-speed, high-precision quantization results. A three-layer backpropagation (BP) neural network is constructed based on the MATLAB platform. The number of neurons in the input layer is consistent with the dimension T of the input data in the training dataset, the number of neurons in the hidden layer is adjustable, and the number of neurons in the output layer is 1. The neural network is trained using the reconstructed training dataset Dtrain2, and then tested using the unreconstructed test set Dtest1.

[0059] In the verification experiment, the pipelined ADC was set to operate at 1GHz. A 10.3MHz sine wave was generated by adjusting the signal generator to ensure the ADC operated normally at -1dBFS. The host computer received and saved the signal, and its spectrum was tested as follows. Figure 4 As shown, SNDR is 63.80dB, SFDR is 83.60dB, and ENOB is 10.30 bits.

[0060] After performing sine fitting on the above data, high-precision quantized data was obtained. The resulting spectrum is shown in the figure below. Figure 5 As shown, SNDR is 157.40dB, SFDR is 196.70dB, and ENOB is 25.85 bits.

[0061] With a sampling factor of 128, 128 interval sampling times, an offset constant of 127, and a feature dimension of 41, the data size of a batch after reconstruction is 128*(127+1) = 16384. A neural network is used to train the reconstructed training dataset in batches, iterating 10 times until convergence, after which training stops. The neural network performs inference based on the test set, and the spectrum of the output is shown below. Figure 6As shown, SNDR is 88.0dB, SFDR is 95.6dB, and ENOB is 14.33 bits, exceeding the effective precision limit of a 14-bit ADC.

[0062] Thus, we achieved an effective quantization output with an accuracy of up to 14.33 bits at a working frequency of 1 GHz. In addition, its SNDR reached 88.0 dB and SFDR reached 95.6 dB, verifying the excellent performance of the ADC based on the neural network-enhanced heterogeneous channel architecture proposed in this invention.

[0063] In summary, this invention proposes an ADC based on a heterogeneous channel architecture enhanced by a neural network, comprising: two heterogeneous ADC channels, a delay module, a neural network circuit, and a streaming training controller.

[0064] The two heterogeneous ADC channels are a high-speed low-precision channel and a low-speed high-precision channel, respectively. The two channels are ADCs with different performance and are connected to the same signal source. The high-speed low-precision channel has a higher sampling frequency, which can quickly capture changes in high-frequency signals, but the accuracy is lower. The low-speed high-precision channel has a lower sampling frequency, which can provide high-precision quantization data as a reference.

[0065] The delay module is connected to the output of the two heterogeneous ADC channels to perform delay and alignment processing on the two output data. The multi-time dimension data of the high-speed low-precision channel is aligned with the single-time dimension data of the low-speed high-precision channel after delay processing.

[0066] The neural network circuit consists of an input layer, a hidden layer, and an output layer. The number of neurons in the input layer is consistent with the feature dimension of the input data, the number of neurons in the hidden layer is adjustable, and the number of neurons in the output layer is 1. All nodes in the preceding and following layers are interconnected. The neural network circuit integrates the advantages of high-speed low-precision channels and low-speed high-precision channels during training. The output of the high-speed low-precision channel is used as training data, and the output of the low-speed high-precision channel is used as label data. During training, the weights and biases are adjusted to generate high-speed and high-precision quantized output.

[0067] The streaming training controller is used for global control of data acquisition from two heterogeneous ADC channels, alignment of delay modules, and generation of training data for neural network circuits. It generates diverse training data through downsampling, time offsetting, and batch processing operations.

[0068] The steps in this invention can be adjusted, combined, or deleted according to actual needs.

[0069] The units in the device of the present invention can be merged, divided, or reduced according to actual needs.

[0070] Although the invention has been disclosed in detail with reference to the accompanying drawings, it should be understood that these descriptions are merely exemplary and not intended to limit the application of the invention. The scope of protection of the invention is defined by the appended claims and may include various variations, modifications, and equivalents made to the invention without departing from the scope and spirit of the invention.

Claims

1. An ADC based on a heterogeneous channel architecture enhanced by neural networks, characterized in that, The ADC includes: two heterogeneous ADC channels, a delay module, a neural network circuit, and a streaming training controller; The two heterogeneous ADC channels are a high-speed low-precision channel and a low-speed high-precision channel, respectively. The two channels are ADCs with different performance and are connected to the same signal source. The high-speed low-precision channel has a higher sampling frequency than the low-speed high-precision channel, which is used to quickly capture changes in high-frequency signals; the low-speed high-precision channel is used to provide high-precision quantization data as a reference. The delay module is connected to the output of the two heterogeneous ADC channels to delay and align the two output data. The high-speed, low-precision channel is processed by delay to form multi-time dimension data, which is then aligned with the single-time dimension data of the low-speed, high-precision channel. The neural network circuit consists of an input layer, a hidden layer, and an output layer. The number of neurons in the input layer is consistent with the feature dimension of the input data, the number of neurons in the hidden layer is adjustable, and the number of neurons in the output layer is 1. All nodes in the preceding and following layers are interconnected. The neural network circuit integrates the advantages of high-speed low-precision channels and low-speed high-precision channels during training. The output of the high-speed low-precision channel is used as training data, and the output of the low-speed high-precision channel is used as label data. During training, the weights and biases are adjusted to generate high-speed and high-precision quantized output. The streaming training controller is used for global control of data acquisition from two heterogeneous ADC channels, alignment of delay modules, and generation of training data for neural network circuits. It generates training data through downsampling, time offsetting, and batch processing operations. The workflow of the streaming training controller is as follows: S1. Parameter settings: Set the sampling clock frequency fa of the high-speed low-precision channel ADC and the sampling clock frequency fb of the low-speed high-precision channel ADC, and set the number of interval sampling times N and the number of intervals M. S2, Interval downsampling operation: After the sampling clocks of the two ADC channels are aligned for the first time, the first interval data downsampling is performed with the sampling clock of the low-speed channel ADC as the reference. A total of N data acquisitions are performed. Each time, the output data of multiple time dimensions is collected as training data, and the output data of one time dimension of the low-speed high-precision channel ADC is collected as label data. S3, Offset Operation: After each interval downsampling operation is completed, the streaming training controller performs a time offset on the sampling clock of the low-speed high-precision channel. The offset is 1 / fa of the high-speed low-precision channel clock period. The low-speed high-precision channel data after the time offset will be used in the next interval downsampling operation with the new high-speed low-precision data. S4. Batch processing operation: M interval downsampling operations are used as a batch processing cycle. Each batch contains N*(M+1) label data and corresponding multi-time dimension training data, which are input into the neural network circuit for training.

2. The ADC based on a neural network-enhanced heterogeneous channel architecture as described in claim 1, characterized in that, The delay module is connected to the output of the high-speed low-precision channel and the low-speed high-precision channel respectively. The delay module delays the high-speed data according to the sampling clock frequency of the low-speed high-precision channel to ensure that the high-speed data is aligned with the low-speed data. The delay module temporarily stores the multi-time dimension data output by the high-speed low-precision channel through a register. After the delay, it is aligned with the single-time dimension data of the low-speed high-precision channel and outputs synchronous data for use by the neural network circuit.

3. The ADC based on a neural network-enhanced heterogeneous channel architecture as described in claim 1, characterized in that, The neural network circuit adjusts the number of neurons in the input layer and hidden layer to adapt to the quantization requirements of different signal characteristics, thereby improving the model's generalization performance and inference accuracy.

4. The ADC based on a neural network-enhanced heterogeneous channel architecture as described in claim 1, characterized in that, A verification system for an ADC based on a heterogeneous channel architecture enhanced by a neural network is constructed. The verification system uses a signal fitting method to obtain high-precision quantization results as label data for the neural network circuit, in order to replace the output of the low-speed, high-precision channel.

Images