Channel simulation system capable of being flexibly established and expanded

Abstract

The invention discloses a channel simulation system capable of being flexibly established and expanded, and relates to the technical field of signal receiving, transmitting and processing. The system comprises a multi-element expansion interconnection calculation matrix, and calculation arrays with different topological structures and different scales can be constructed through connection relations between upper and lower expansion interconnection calculation matrix hierarchies, between expansion interconnection calculation matrixes and interconnection calculation matrixes and between internal calculation units of the interconnection calculation matrixes. The larger the number of array elements of the interconnection calculation matrix is, the larger the number of layers of the expansion interconnection is, the larger the scale of the calculation matrix is, the larger the total computing power and the larger the storage space are, the larger-scale channel simulation requirement can be met, and the target of adapting to different channel scales and instantaneous bandwidths is achieved. Therefore, a user can easily customize the channel simulation system according to own requirements, product functions and channel scales can be gradually expanded through staged construction, the cost is reduced, and the product utilization rate is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of signal receiving, transmitting and processing, and in particular relates to a channel simulation system which can be flexibly constructed and expanded so as to meet the channel simulation needs of different channel scales and different instantaneous bandwidths. Background Art

[0002] A channel emulator is a device used to simulate the characteristics of an electromagnetic wave propagation channel. It can reproduce the propagation characteristics of electromagnetic signals in a real environment, including path loss, multipath effects, Doppler shift, fading, and interference. Channel emulators are very important in fields such as wireless communications, radar systems, and electronic countermeasures because they allow engineers and researchers to test and evaluate the performance of RF systems under controlled laboratory conditions.

[0003] At present, there are mature commercial channel simulators on the market, which are mainly used to simulate the propagation channels of wireless communication systems, and generally have an instantaneous bandwidth of hundreds of MHz. If it is necessary to simulate the propagation channels of RF signals in the field of radar and electronic countermeasures, the instantaneous bandwidth of the channel simulator needs to reach 1GHz or 2GHz. At this time, the amount of data that the channel simulator needs to calculate and transmit will increase greatly, resulting in a significant increase in the cost and difficulty of system construction.

[0004] Take a typical 32-receive 32-transmit channel simulation system with 2 GHz instantaneous bandwidth as an example: (1) the total system bandwidth is 64 GHz, and the total external data throughput is 320 GB / s; (2) the number of system channels is 32 2 , that is, 1024 channels, the computing data throughput of each channel is 10GB / s, and the total internal data throughput is 10TB / s; (3) The number of calculations for each channel is generally dozens of complex multiplication and addition operations. Calculated as 20 operations and 2 bytes each time, 1024 channels need to complete a total of 20×10÷2=100TOps, where TOps refers to one trillion operations per second (full name: Tera Operations PerSecond), which is the unit of processor computing power.

[0005] In order to cope with such a large amount of data transmission and computing, the related products on the market are all customized medium-to-large instruments and equipment, which have the disadvantages of relatively single functions and extremely high prices. It is difficult to change product characteristics, expand product functions and adjust channel scale according to different user needs. Summary of the invention

[0006] The purpose of the present invention is to provide a channel simulation system that can be flexibly assembled and expanded, so as to solve the problems of existing medium and large channel simulation instruments and equipment, such as fixed form, relatively single function, extremely high price, and difficulty in changing product characteristics, expanding product functions and adjusting channel scale according to different user needs.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions: The present invention provides a channel simulation system which can be flexibly constructed and expanded, comprising Meta-extended interconnection computing matrix, wherein the Meta-Extended Interconnection Computing Matrix includes indivual Meta-Extended Interconnection Computing Matrix, the Meta-Extended Interconnection Computing Matrix includes indivual Meta-extended interconnected computing matrix, and so on Meta-Extended Interconnection Computing Matrix includes indivual Meta-extends the interconnected computing matrix until Meta-Extended Interconnection Computing Matrix includes indivual Meta-interconnection computing matrix, The Meta-interconnection Computing Matrix includes A computing unit, for The abbreviation of , wherein the calculation unit is used to perform a signal propagation simulation calculation on an input digital signal obtained by converting an input radio frequency signal to obtain an output digital signal for conversion into an output radio frequency signal, , , , and Respectively represent integers greater than or equal to 2, represents an integer greater than or equal to 2, exist Exists when greater than or equal to 3, and indicates greater than or equal to 0 and less than integer; In the Any two of the computing units are connected in communication; For any Each of the computing units in the element interconnection computing matrix enables the corresponding units to be respectively connected to Other The computing units in the corresponding positions in the meta-interconnect computing matrix are connected in communication, wherein any one Meta-interconnection computing matrix and the Other The meta-interconnection computing matrix is ​​described Meta-extended interconnected computing matrix; For any Each of the computing units in the interconnected computing matrix is ​​extended so that the corresponding units are connected to each other in Other The computing units in corresponding positions in the meta-extension interconnection computing matrix are connected in communication, wherein any one Meta-Extended Interconnection Computing Matrix and the Other The meta-extension interconnection computing matrix is ​​described Meta-extended interconnected computing matrix.

[0008] Based on the above invention content, a flexible and expandable large-bandwidth real-time channel simulation system is provided, which includes a multi-element extended interconnected computing matrix, and through the connection relationship between the upper and lower extended interconnected computing matrix levels, between the extended interconnected computing matrix and the interconnected computing matrix, and between the computing units inside the interconnected computing matrix, computing arrays with different topological structures and different scales can be constructed, and the more array elements of the interconnected computing matrix and the more levels of the extended interconnection, the larger the scale of the computing matrix, the larger the total computing power and storage space, and the larger the channel simulation needs can be met, so as to achieve the goal of adapting to different channel scales and instantaneous bandwidths, and then users can easily customize the channel simulation system according to their own needs, and can gradually expand product functions and channel scales through phased construction, thereby reducing costs and improving product utilization, solving the problems of existing medium and large channel simulation instruments and equipment, such as fixed form, relatively single function, extremely expensive price, and difficulty in changing product characteristics, expanding product functions and adjusting channel scales according to different user needs, and facilitating practical application and promotion.

[0009] In a possible design, a control computer is also included, wherein the control computer is communicatively connected to the The controlled end of each computing unit in the meta-extended interconnected computing matrix is ​​used to read and write parameters and / or data of the computing unit.

[0010] In one possible design, the computing unit is communicatively connected to at least one signal transceiver unit; The signal transceiver unit is used to receive the input digital signal obtained by conversion based on the input radio frequency signal, and send the output digital signal for conversion into the output radio frequency signal; Alternatively, the signal transceiver unit is used to receive the input radio frequency signal and convert it into the input digital signal, and to convert the output digital signal into the output radio frequency signal and send it out.

[0011] In a possible design, when the signal transceiver unit is used to receive the input RF signal and convert it into the input digital signal and convert the output digital signal into the output RF signal and send it out, the signal transceiver unit includes an analog receiving front-end module, an analog transmitting front-end module, an ADC module, a DAC module, a second FPGA module, a second storage module and a second high-speed serial interface, wherein the analog receiving front-end module is used to receive the input RF signal, the analog transmitting front-end module is used to send the output RF signal, and the second high-speed serial interface is used to communicate with the computing unit; The output end of the analog receiving front-end module is communicatively connected to the input end of the ADC module, the output end of the ADC module is communicatively connected to the input end of the second FPGA module, the input end of the analog transmitting front-end module is communicatively connected to the output end of the DAC module, the input end of the DAC module is communicatively connected to the output end of the second FPGA module, and the second FPGA module is also communicatively connected to the second storage module and the second high-speed serial interface respectively.

[0012] In a possible design, the signal transceiver unit further includes a clock and trigger signal interface, an onboard OCXO module and a clock generation and distribution circuit module based on a phase-locked loop mechanism, wherein the clock and trigger signal interface is used to receive an external sampling clock signal, a reference clock signal, a GPS second pulse signal and a trigger signal, and the onboard OCXO module is used to generate a time base signal; The trigger signal output end of the clock and trigger signal interface is communicatively connected to the second FPGA module, the non-trigger signal output end of the clock and trigger signal interface and the time base signal output end of the onboard OCXO module are respectively communicatively connected to the input end of the clock generation and distribution circuit module, and the clock signal output end of the clock generation and distribution circuit module is respectively communicatively connected to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module and the second FPGA module.

[0013] In a possible design, when the signal transceiver unit includes a second FPGA module and a second storage module and a second high-speed serial interface respectively communicatively connected to the second FPGA module, the signal transceiver unit is also used as an extended computing unit relative to the computing unit, and is used to perform any one of the following extended computing tasks (A) to (I) or any combination thereof: (A) Using interpolation processing to increase the instantaneous bandwidth of the signal; (B) Using decimation to reduce the instantaneous bandwidth of the signal; (C) Using digital frequency conversion to change the center frequency of the signal; (D) Calculate the signal spectrum in real time; (E) Real-time calculation of target echo or clutter; (F) Simulate the phase offset of the signal arriving at each port of the multi-channel direction finding receiver; (G) Simulating the signal amplitude and phase of each channel in the radar sum and difference channels; (H) Data transmission and reception via a high-speed serial bus; (I) Perform amplitude calibration and phase calibration of the transmit and receive signals.

[0014] In one possible design, the signal propagation simulation calculation includes calculation of spatial fading, multipath effect, Doppler effect, time delay and / or interference superposition during the signal propagation process.

[0015] In one possible design, the The meta-extended interconnection computing matrix is ​​used to perform symmetric computation of channel simulation in the following manner: set up Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the The Meta-interconnection Computational Matrix is ​​described in Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates that the computing unit is in the Unique number in the meta-interconnection matrix and in the integer range In order to make Each of the computing units in the meta-extension interconnection computing matrix has a corresponding numbering sequence ; If in the Each of the computing units in the meta-extended interconnected computing matrix is ​​independently connected to each other in communication. For the signal receiving and sending channel, set Indicates that the signal receiving and sending channel is in A unique number in the signal receiving and sending channel and is in the integer range In order to make Each pair of signal transceiver channels in the signal transceiver channel has a corresponding number sequence ,in, represents a positive integer; For numbered series The target signal sending channel is calculated to obtain the corresponding output digital signal for conversion into the output RF signal, and the output digital signal is sent out through the corresponding channel, wherein, represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has The output digital signal is as follows The round step calculation yields: First round: In each of the The interior of the meta-interconnection computing matrix consists of a numbered sequence The first computing unit starts with the first computing unit and Other computing units communicate with each other The signal data to be channel simulated is obtained on a signal receiving channel, and then the target signal sending channel is calculated based on the signal data and the The given channel parameters of each signal receiving channel in the signal receiving channels relative to the corresponding transmitting channel are simulated and calculated. signal propagation process, and superimpose the calculation results to obtain the corresponding first round of superposition calculation results; Second round: In each of the The interior of the meta-extension interconnection computing matrix consists of a numbered sequence The second computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence Performing a transmission delay effect calibration and deduction process on all the calculation units and the corresponding first round superposition calculation results, and superimposing the processing results to obtain the corresponding second round superposition calculation results; No. Wheel: In each The interior of the meta-extension interconnection computing matrix consists of a numbered sequence The third computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence All of the computing units and the corresponding The transmission delay effect calibration and deduction processing are performed on the results of the round superposition calculation, and the processing results are superimposed to obtain the corresponding Wheel superposition calculation results; No. Round: consists of a numbered sequence The fourth computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence All of the computing units and the corresponding The round superposition calculation results are subjected to transmission delay effect calibration and subtraction processing, and the processing results are superimposed to obtain the corresponding output digital signal.

[0016] In a possible design, the computing unit includes a first FPGA module, a first storage module and a first high-speed serial interface, wherein the first high-speed serial interface has at least one and is used for communication connection with a signal transceiver unit or other computing units; The first FPGA module is communicatively connected to the first storage module and the first high-speed serial interface respectively.

[0017] In one possible design, the first storage module uses a dynamic random access memory, and the first high-speed serial interface uses a Nano-Pitch interface.

[0018] Beneficial effects of the above scheme: (1) The present invention provides a flexible and expandable large-bandwidth real-time channel simulation system, which includes a multi-element expansion interconnection computing matrix. Through the connection relationship between the upper and lower expansion interconnection computing matrix levels, between the expansion interconnection computing matrix and the interconnection computing matrix, and between the computing units within the interconnection computing matrix, computing arrays of different topological structures and different scales can be constructed. The more array elements in the interconnection computing matrix and the more levels of expansion interconnection, the larger the scale of the computing matrix, the larger the total computing power and storage space, and the larger the channel simulation needs can be met, so as to achieve the goal of adapting to different channel scales and instantaneous bandwidths. Therefore, users can easily customize the channel simulation system according to their own needs, and can gradually expand product functions and channel scales through phased construction, thereby reducing costs and improving product utilization. The existing medium and large channel simulation instruments and equipment have fixed forms, relatively single functions, and extremely high prices, and it is difficult to change product characteristics, expand product functions, and adjust channel scales according to different user needs. The problem is easy to be applied and promoted. (2) Flexible expansion and splitting: The computing topology designed by the present invention is applicable to channel simulation systems with a few channels to hundreds of channels. It can easily expand a small-scale channel simulation system into a large-scale system, and can also easily split a large-scale system into several small-scale systems. (3) Large simulation bandwidth: The bandwidth that a channel simulation system can simulate mainly depends on the computing power and data access capability of a single computing unit. The computing topology structure designed by the present invention can flexibly configure the ratio of computing units to signal transceiver units (as well as the number of transceiver channel groups), and the signal transceiver unit can also provide additional computing power and data access capability support. Therefore, when the ratio of computing units is increased (the maximum ratio of transceiver channel groups to computing units can be 1:1), the current advanced FPGA has a computing power of more than 3TOps. Under a 1:1 ratio, that is, with 32 computing units plus extended computing units, a total computing power of more than 100TOps can be provided. Under a 2GHz instantaneous bandwidth, 32T32R channel simulation with a total of 64 channels can also be achieved. (4) Low computing delay: The hardware circuit characteristics of the FPGA itself have the characteristics of low computing delay. At the same time, the computing matrix topology designed by the present invention makes it possible for any two computing units to interact with each other through only a very short data exchange path, so the entire computing matrix has the advantage of low computing delay. (5) Low cost: Due to the standardization of computing units and interconnected computing matrices, the construction and expansion of large-scale channel simulation systems no longer need to be customized, thus achieving low cost; (6) Easy to develop: Since the computing topology designed by the present invention is a completely symmetrical structure, it is only necessary to design algorithms and programs for a single computing unit to complete the programming of the entire computing matrix; (7) Customizability: The signal transceiver unit provides extended computing power, and the implementation of this computing power is completely decoupled from the computing matrix, so it is easy to provide customized signal processing capabilities for the channel simulation port device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of the specific structure of a computing unit in a channel simulation system provided by an embodiment of the present invention.

[0021] Figure 2A schematic diagram of the specific structure of a two-element interconnection computing matrix provided in an embodiment of the present invention.

[0022] Figure 3 The embodiment of the present invention provides Schematic diagram of the structure of the meta-interconnection computing matrix, where: Figure 3 (a) shows the schematic diagram of the structure of the 3-element interconnected computing matrix. Figure 3 (b) shows the schematic diagram of the structure of the 4-element interconnection computing matrix. Figure 3 (c) shows the structural schematic diagram of the 5-element interconnected computing matrix.

[0023] Figure 4 A schematic diagram of the structure of a 3×3 element extended interconnection computing matrix provided in an embodiment of the present invention.

[0024] Figure 5 A schematic diagram of the structure of a 4×3 element extended interconnection computing matrix provided in an embodiment of the present invention.

[0025] Figure 6 A schematic diagram of the structure of a 4×4 element extended interconnection computing matrix provided in an embodiment of the present invention.

[0026] Figure 7 A schematic diagram of the specific structure of a signal transceiver unit in a channel simulation system provided by an embodiment of the present invention.

[0027] Figure 8 This is an example diagram of the connection relationship between the 4×4 element interconnection computing matrix and the signal transceiver unit provided in an embodiment of the present invention.

[0028] Fig. 9 This is an example diagram of the topological structure of the 4×4 element interconnection computing matrix after calculation extension provided in an embodiment of the present invention.

[0029] Fig.10 This is an example diagram of the connection relationship between the 4×3 element interconnection computing matrix and the signal transceiver unit provided in an embodiment of the present invention.

[0030] Fig.11 An example diagram of implementing channel simulation computing logic based on a 4×4 element extended interconnect computing matrix provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the present invention will be briefly introduced below in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structures of the drawings is only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these embodiments without creative work. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention.

[0032] It should be understood that although the terms first and second, etc. may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another object. For example, a first object can be referred to as a second object, and similarly, a second object can be referred to as a first object without departing from the scope of the exemplary embodiments of the present invention.

[0033] It should be understood that the term "and / or" that may appear in this document is merely a description of the association relationship between associated objects, indicating that there may be three relationships. For example, A and / or B can indicate three situations: A exists alone, B exists alone, or A and B exist at the same time. For another example, A, B and / or C can indicate the existence of any one of A, B and C or any combination of them. The term " / and" that may appear in this document describes another type of association object relationship, indicating that there may be two relationships. For example, A / and B can indicate two situations: A exists alone or A and B exist at the same time. In addition, the character " / " that may appear in this document generally indicates that the previous and next associated objects are in an "or" relationship.

[0034] Example like Figures 1 to 11 As shown, the channel simulation system provided in this embodiment and which can be flexibly constructed and expanded includes but is not limited to Meta-extended interconnection computing matrix, wherein the Meta-Extended Interconnection Computing Matrix includes indivual Meta-Extended Interconnection Computing Matrix, the Meta-Extended Interconnection Computing Matrix includes indivual Meta-extended interconnected computing matrix, and so on Meta-Extended Interconnection Computing Matrix includes indivual Meta-extends the interconnected computing matrix until Meta-Extended Interconnection Computing Matrix includes indivual Meta-interconnection computing matrix, The Meta-interconnection Computing Matrix includes A computing unit, for The abbreviation of , wherein the calculation unit is used to perform a signal propagation simulation calculation on an input digital signal obtained by converting an input radio frequency signal to obtain an output digital signal for conversion into an output radio frequency signal, , , , and Respectively represent integers greater than or equal to 2, represents an integer greater than or equal to 2, exist Exists when greater than or equal to 3, and indicates greater than or equal to 0 and less than An integer; in the Any two of the computing units are connected in communication; for any Each of the computing units in the element interconnection computing matrix enables the corresponding units to be respectively connected to Other The computing units in the corresponding positions in the meta-interconnect computing matrix are connected in communication, wherein any one Meta-interconnection computing matrix and the Other The meta-interconnection computing matrix is ​​described Meta-extended interconnected computing matrix; for any Each of the computing units in the interconnected computing matrix is ​​extended so that the corresponding units are connected to each other in Other The computing units in corresponding positions in the meta-extension interconnection computing matrix are connected in communication, wherein any one Meta-Extended Interconnection Computing Matrix and the Other The meta-extension interconnection computing matrix is ​​described Meta-extended interconnected computing matrix.

[0035] like Figures 1 to 11 As shown, in the specific structure of the channel simulation system, the The meta-extended interconnection computing matrix is ​​the main body for signal propagation simulation calculation, and can be based on , , , , and The scale of the computing unit can be expanded at will by taking different values ​​of , so as to change product characteristics, expand product functions and adjust channel scale according to different user needs, thereby solving the problems of fixed form, relatively single function and extremely expensive price of existing medium and large channel simulation instruments and equipment. In addition, since the construction of the aforementioned computing matrix is ​​completely symmetrical, when performing channel simulation calculations, the embedded computing program of a computing unit can be designed to complete the embedded computing program of the entire computing matrix.

[0036] like Figure 1 As shown, specifically, the computing unit includes but is not limited to a first FPGA module, a first storage module and a first high-speed serial interface, wherein the number of the first high-speed serial interfaces is multiple and is used to communicate and connect the signal transceiver unit or other computing units; the first FPGA module is respectively communicated and connected to the first storage module and the first high-speed serial interface. The first FPGA (Field Programmable Gate Array) module is used to perform signal propagation simulation calculations, which can be specifically implemented using existing device products; the number of the first FPGA modules can be one or more, and when there are multiple first FPGA modules, the multiple first FPGA modules can be interconnected through a high-speed communication interface, so that the data required for the calculation can be shared between the FPGA modules (at this time, the computing unit composed of multiple first FPGA modules is still logically regarded as an integral computing unit to the outside, thereby enhancing the computing power, storage capacity and number of high-speed serial interfaces of a single computing unit, and improving the overall computing power and expansion capabilities of the interconnected computing matrix). The first storage module (i.e. Figure 1 DRAM) is used to temporarily store the data of the computing unit, which can be implemented by using dynamic random access memory (DRAM); when there are multiple first FPGA modules, each of the first FPGA modules can be independently connected to the first storage module (that is, there are multiple first storage modules). The first high-speed serial interface (that is, Figure 1The first high-speed serial interface can be, but is not limited to, a Nano-Pitch interface, preferably a Nano-Pitch standard 42-pin (not limited to this standard) connector as a compact and high-speed connection interface, each of which can provide up to 6 bidirectional data transmission links with a unidirectional rate of up to 16 Gbps, for a total of 96 Gbps (12 GB / s).

[0037] like Figure 2 As shown, the two computing units can communicate with each other through a high-speed serial interface to form a two-element interconnected computing matrix; the two-element interconnected computing matrix can be connected through a high-speed serial cable, or it can be implemented on the same circuit board, the latter can save high-speed serial connectors and cables, simplify the connection between each other, reduce the interconnection cost, and increase the interconnection data rate; the two computing units can exchange and share data at high speed through high-speed interconnection, and perform parallel calculations on different data at the same time, thereby increasing the computing power. Moreover, the two two-element interconnected computing matrices can be further extended and interconnected through a high-speed serial interface to form a 2 2 The 2-element interconnection computing matrix is ​​connected to each computing unit in a 2-element interconnection computing matrix and the computing units in the corresponding positions in another 2-element interconnection computing matrix are connected to each other. 2 Each computing unit in the meta-extension interconnection matrix can exchange high-speed data with any other computing unit through at most one intermediate computing unit, thereby ensuring that each computing unit can efficiently obtain the required computing data from other computing units.

[0038] Based on the above-mentioned construction method of the two-element interconnection computing matrix, further: The computing units are fully interconnected (here fully interconnected means: any computing unit is connected to other The computing units are directly connected in pairs through high-speed serial connections), forming The element interconnection calculation matrix; for example, the 3-element interconnection calculation matrix is ​​as follows Figure 3 As shown in (a) in the figure, the 4-element interconnection calculation matrix is ​​as follows Figure 3 As shown in (b) in the figure, the 5-element interconnection calculation matrix is ​​as follows Figure 3 As shown in (c) in , and so on.

[0039] Based on the above 2 2The construction method of the meta-extended interconnected computing matrix is ​​further: a The Meta-Interconnect Computing Matrix can connect to other indivual The meta-interconnection computing matrix is ​​extended and interconnected to form a maximum Meta-extended interconnection computing matrix (its extended interconnection method is Each computing unit of the meta-interconnect computing matrix and other The computing units at the corresponding positions of the meta-interconnection computing matrix are connected in pairs). For example, Figure 4 As shown: 3 3-element interconnection computing matrices are expanded into 3×3-element extended interconnection computing matrices; Figure 5 As shown: 4 3-element interconnection computing matrices are expanded into 4×3-element extended interconnection computing matrices; Figure 6 As shown: 4 4-element interconnection computing matrices are expanded to a 4×4-element expanded interconnection computing matrix, and so on.

[0040] Based on the above Figures 4 to 6 It can be seen that: The topology of the extended interconnected computing matrix is ​​completely symmetrical; that is, the position and connection relationship of each computing unit in the matrix are completely consistent and symmetrical with respect to other computing units, so each computing unit in the extended interconnected computing matrix is ​​equivalent, which makes the computing matrix very suitable for performing highly parallel and symmetrical calculations. In addition to the symmetry of the topology, Each computing unit in the meta-extended interconnected computing matrix can exchange data with any other computing unit through at most one intermediate computing unit, ensuring that each computing unit can easily establish low-latency communication with other computing units, so that all data in the entire computing matrix can be obtained with low latency. At the same time, the calculation of large-scale signal propagation simulation just meets these two characteristics: (1) The calculation of each channel is related to all input signals; (2) The calculation of each channel is completely consistent and symmetrical. Therefore, a The meta-extension interconnection computing matrix can be connected with other indivual Meta-interconnection computing matrix for extended interconnection (here represents an integer greater than or equal to 2), and is constructed to have a maximum value of Meta-Extended Interconnection Computing Matrix (i.e. Meta-interconnection computing matrix), and can be further extended by analogy as Meta-Extended Interconnection Computing Matrix (i.e. Meta-Extended Interconnection Computing Matrix). Each computing unit in the meta-extension interconnection computing matrix is ​​also equivalent, and the connection between it and any other computing unit only needs to pass through The intermediate computing units can exchange data at high speed, thus ensuring that each computing unit can obtain the required computing data from other computing units efficiently and with low latency. Based on the aforementioned expansion method of the interconnected computing matrix, computing arrays of different topologies and sizes can be constructed according to different channel simulation computing requirements. The more array elements in the interconnected computing matrix and the more levels of extended interconnection, the larger the scale of the computing matrix, the greater the total computing power and storage space, and the larger the channel simulation requirements can be adapted to, thereby solving the problems of existing medium and large channel simulation instruments and equipment, such as fixed form, relatively single function, extremely expensive price, and difficulty in changing product features, expanding product functions, and adjusting channel scale according to different user needs.

[0041] Preferably, a control computer is also included, wherein the control computer is communicatively connected to the The controlled end of each computing unit in the meta-extended interconnected computing matrix is ​​used to read and write parameters and / or data of the computing unit. Figure 1 and Figure 2 As shown, the controlled end of the computing unit is specifically a control bus interface (i.e. Figure 1 The bus interface circuit is preferably connected to the bus interface circuit using the PCIe bus or the PCIe-based instrument expansion bus (such as PXIe, CPCIe, VPX, etc.) as the communication and control bus. The PCIe bus and the PCIe-based instrument expansion bus have a mature and complete hardware and software ecosystem, which allows users to easily add a variety of I / O modules based on such bus platforms and use mature system and data management software to control and manage the system. Such bus platforms also provide a modular architecture, allowing users to easily use different types and quantities of modules to expand the functions and capabilities of the system.

[0042] Preferably, the computing unit is communicatively connected with at least one signal transceiver unit; the signal transceiver unit is used to receive the input digital signal obtained based on the conversion of the input RF signal, and to send the output digital signal for conversion into the output RF signal; or, the signal transceiver unit is used to receive the input RF signal and convert it into the input digital signal, and to convert the output digital signal into the output RF signal and send it out. Since the computing input of the aforementioned interconnected computing matrix usually comes from an external RF signal, and the computing output usually needs to be sent to the outside, the signal transceiver unit is required to collect and acquire or generate and send. In addition to being responsible for the high-speed transmission and reception of digital signals or analog signals, the signal transceiver unit can also perform signal processing according to specific needs, and is mainly composed of an FPGA module and a high-speed serial interface. Specifically, when the signal transceiver unit is used to receive the input RF signal and convert it into the input digital signal and convert the output digital signal into the output RF signal and send it out, the signal transceiver unit includes but is not limited to an analog receiving front-end module, an analog transmitting front-end module, an ADC module, a DAC module, a second FPGA module, a second storage module and a second high-speed serial interface, etc., wherein the analog receiving front-end module is used to receive the input RF signal, the analog transmitting front-end module is used to send the output RF signal, and the second high-speed serial interface is used to communicate with the calculation unit; the output end of the analog receiving front-end module is communicatively connected to the input end of the ADC module, the output end of the ADC module is communicatively connected to the input end of the second FPGA module, the input end of the analog transmitting front-end module is communicatively connected to the output end of the DAC module, the input end of the DAC module is communicatively connected to the output end of the second FPGA module, and the second FPGA module is also communicatively connected to the second storage module and the second high-speed serial interface respectively.

[0043] like Figure 7As shown, in the specific structure of the signal transceiver unit, the analog receiving front-end module and the analog transmitting front-end module respectively cooperate with the ADC module and the DAC module in a one-to-one correspondence, and are used for frequency conversion, amplification, conditioning, filtering, receiving and transmitting analog signals, and realizing the conversion between analog signals and digital signals. The second FPGA module has high-speed data throughput capability and is a key component connecting ADC / DAC and analog front end. With its characteristics suitable for high-speed parallel fixed-point number calculation, it can provide real-time signal preprocessing capabilities for the system. On the one hand, it completes part of the signal processing work, and on the other hand, it can also complete the extraction and compression of effective data, reducing the amount of data transmitted between the back-end signal processor. The second FPGA module can also have a signal processing delay as low as ns level, and realize low-latency signal transceiver through the ADC module and the DAC module. The second storage module specifically includes but is not limited to DRAM and FLASH, wherein the former is used for local caching and temporary storage of high-speed signal data, and the latter is used to store firmware programs. The second high-speed serial interface can be specifically implemented as a high-speed serial bus interface using the Aurora communication protocol, that is, preferably using the Aurora 16Gbps x6 or higher high-speed serial transmission protocol, which has a peak data throughput of 11GB / s and a transmission delay as short as microseconds, which can provide a sufficiently large transmission bandwidth and a sufficiently short transmission delay for most real-time signal processing applications, ensure the continuity and timeliness of data transmission, and provide basic conditions for real-time signal processing; the second high-speed serial interface further preferably uses the Nano-Pitch series connectors produced by Molex, which can provide a maximum data transmission capacity of 25Gbps x8, which is sufficient to meet the full-duplex transmission requirements of 2-way 2GHz instantaneous bandwidth signals.

[0044] Further preferably, the signal transceiver unit further includes but is not limited to a clock and trigger signal interface, an onboard OCXO module, and a clock generation and distribution circuit module based on a phase-locked loop mechanism, wherein the clock and trigger signal interface ( Figure 7 The onboard OCXO module (denoted by DIO) is used for but not limited to receiving external sampling clock signals, reference clock signals, GPS second pulse signals and trigger signals, etc. Figure 7 The trigger signal output terminal of the clock and trigger signal interface is communicatively connected to the second FPGA module, and the non-trigger signal output terminal of the clock and trigger signal interface and the time base signal output terminal of the onboard OCXO module are communicatively connected to the input terminal of the clock generation and distribution circuit module respectively. The clock generation and distribution circuit module ( Figure 7The clock signal output end of the analog receiving front-end module (represented by PLL in the figure) is respectively connected to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module and the second FPGA module. The connector of the clock and trigger signal interface can be selected according to the specific signal frequency and quantity. The sampling clock signal, the reference clock signal, the GPS second pulse signal and the time base signal are used to provide clock signals to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module and the second FPGA module respectively through the clock generation and distribution circuit module based on the phase-locked loop. The trigger signal is connected to the second FPGA module and is used for the internal processing logic triggered by external events. In this way, through the aforementioned clock and trigger mechanism, multiple parallel or distributed signal transceiver units can work synchronously to achieve the reception or transmission of coherent signals.

[0045] Since the connection between the complete interconnection computing matrix and the signal transceiver unit is also completely symmetrical, Meta-extended interconnected computing matrix, if all Each computing unit is connected ( represents a positive integer) the signal transceiver units, and each of the signal transceiver units has For the transceiver channel, this channel simulation system has a total of For the transceiver channel, receive At the same time, according to the structure of the signal transceiver unit, it can be known that the signal transceiver unit actually also includes the structure of the computing unit, that is, the combination of FPGA, DRAM and high-speed serial port. Therefore, when the signal transceiver unit is connected to the interconnected computing matrix, it is actually equivalent to connecting a new computing unit to each node of the interconnected computing matrix. Figure 8 As shown, in the 4-element interconnected computing matrix, each computing unit is connected to two signal transceiver units, and the signal transceiver unit receives and sends the radio frequency signal; since the signal transceiver unit includes the computing unit structure, this interconnected computing matrix is ​​equivalent to being expanded as follows Fig. 9The extended interconnection computing matrix topology is shown. Although each computing unit of the extended interconnection computing matrix does not have sufficient computing unit interconnection like the interconnection computing matrix or the extended interconnection computing matrix (that is, each computing unit is interconnected with other computing units by multiple high-speed serial interfaces), the computing power of each computing unit of the original extended interconnection computing matrix has been enhanced, which enables the extended interconnection computing matrix to perform further signal processing related to the devices connected to each channel simulation port in addition to performing fully symmetrical channel simulation calculations, that is, further preferably, when the signal transceiver unit includes a second FPGA module and a second storage module and a second high-speed serial interface respectively connected to the second FPGA module for communication, the signal receiving The transmitting unit is also used as an extended computing unit relative to the computing unit, and is used to perform any one of the following extended computing tasks (A) to (I) or any combination thereof: (A) increasing the instantaneous bandwidth of the signal by interpolation processing; (B) reducing the instantaneous bandwidth of the signal by extraction processing; (C) changing the center frequency of the signal by digital frequency conversion; (D) calculating the spectrum of the signal in real time; (E) calculating the target echo or clutter in real time; (F) simulating the phase offset of the signal reaching each port of the multi-channel direction-finding receiver; (G) simulating the signal amplitude and phase of each channel in the radar and difference channels; (H) transmitting and receiving data through a high-speed serial bus; (I) performing amplitude calibration and phase calibration of the transmitted and received signals. The aforementioned extended computing capability greatly increases the functions that can be simulated by the channel simulation system. Fig. 9 The topological structure of the 4-element interconnected computing matrix after the calculation is extended is shown. Similarly, all The extended interconnection computing matrix can be formed by connecting the signal transceiver unit to any number of computing units, such as Fig.10 As shown, 3 2 The interconnected computing matrix is ​​extended, and each computing unit is connected to a signal transceiver unit. In addition, the computing input of the interconnected computing matrix can also be injected in the form of digital signals via a high-speed serial interface, and its computing output can also be output in the form of digital signals via a high-speed serial interface. In this case, the relevant computing unit may not be connected to the signal transceiver unit.

[0046] Since the signal generated by each RF output channel of the channel simulation is obtained by performing independent channel propagation simulation calculations on the signals received by all RF input channels, specifically, the signal propagation simulation calculations include but are not limited to calculations of spatial fading, multipath effect, Doppler effect, time delay and / or interference superposition during signal propagation. At the same time, since in the extended interconnected computing matrix, the position and connection relationship of each computing unit in the matrix are completely consistent and symmetrical, when the number of transceiver channels connected to each computing unit is consistent and the topological structure of the channel simulation is also consistent and symmetrical, the calculation logic of each computing unit will be completely symmetrical and consistent. The specific calculation process of the channel simulation is: according to the given channel parameters of a certain RF output channel for the selected RF input channel, the corresponding signal propagation simulation calculation is performed on the signal received by the selected RF input channel, and then a superposition calculation (i.e., a mathematical addition calculation of the signal type) is performed, and the result of the superposition calculation is transmitted from the selected RF output channel (the above process is repeated for all selected RF output channels). In this way, it is preferred that the The extended interconnection calculation matrix is ​​used to perform symmetric calculation of channel simulation as follows: Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the The Meta-interconnection Computational Matrix is ​​described in Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates that the computing unit is in the Unique number in the meta-interconnection matrix and in the integer range In order to make Each of the computing units in the meta-extension interconnection computing matrix has a corresponding numbering sequence ; If in the Each of the computing units in the meta-extended interconnected computing matrix is ​​independently connected to each other in communication. For signal transceiver channels (i.e. communication connections signal receiving channels and signal transmission channel), then set Indicates that the signal receiving and sending channel is in A unique number in the signal receiving and sending channel and is in the integer range In order to make Each pair of signal transceiver channels in the signal transceiver channel has a corresponding number sequence (That is, each signal receiving channel or each signal sending channel has a corresponding number sequence ),in, Represents a positive integer; for a numbered sequence The target signal sending channel is calculated to obtain the corresponding output digital signal for conversion into the output RF signal, and the output digital signal is sent out through the corresponding channel, wherein, represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has The output digital signal is as follows The round steps are calculated.

[0047] First round: In each of the The interior of the meta-interconnection computing matrix consists of a numbered sequence The first computing unit starts with the first computing unit and Other computing units communicate with each other The signal data to be channel simulated is obtained on a signal receiving channel, and then the target signal sending channel is calculated based on the signal data and the The given channel parameters of each signal receiving channel in the signal receiving channels relative to the corresponding transmitting channel are simulated and calculated. The signal propagation process is performed, and the calculation results are superimposed to obtain the corresponding first round superposition calculation results.

[0048] In the first round, since there are described Meta-interconnection computing matrix, each of which The meta-interconnection computing matrix has a numbered sequence each of the first computing units has signal transmission channel, and will be all the first computing units The signal transmission channels are used to simulate the signal propagation process. Therefore, each of the first computing units will actually calculate a total of signal propagation process, and for each signal transmission channel, superimpose all corresponding calculation results to obtain the corresponding first round of superposition calculation results, that is, The specific simulation calculation process and superposition technology process of the above-mentioned signal propagation process are all prior art and will not be described in detail here. The first signal data obtained on the signal receiving channel is obtained from the Other computing units communicate with each other The second signal data obtained on the signal receiving channel will be There is a certain transmission delay due to the transmission path from the other calculation units to the first calculation unit. Therefore, before superimposing all the corresponding calculation results for the target signal sending channel, the transmission delay effect calibration and deduction processing can be performed on all the calculation results, and then the processing results are superimposed to obtain the corresponding first round of superimposed calculation results. In addition, the first round can also be subdivided into the following A1 round and A2 round.

[0049] Round A1: In each of the The interior of the meta-interconnection computing matrix consists of a numbered sequence The fifth computing unit is first connected to the fifth computing unit by communication The signal data to be channel simulated is obtained on a signal receiving channel, and then the target signal sending channel is calculated based on the signal data and the The given channel parameters of each signal receiving channel in the signal receiving channels relative to the corresponding transmission channel are simulated and calculated. signal propagation process.

[0050] In the A1 round, each of the The Meta-interconnection Computing Matrix contains The numbered sequence The fifth computing unit.

[0051] Round A2: In each of the The interior of the meta-interconnection computing matrix consists of a numbered sequence The first computing unit, for the target signal sending channel, respectively calculates the number of The fifth computing unit and the corresponding The simulation calculation results of each signal propagation process are subjected to transmission delay effect calibration and deduction processing, and the processing results are superimposed to obtain the corresponding first round of superposition calculation results.

[0052] In the A2 round, the The simulation calculation result of the signal propagation process is specifically transmitted at a high speed through a high-speed serial connection between the fifth computing unit and the first computing unit (if the first computing unit is also the fifth computing unit, then due to the high-speed serial connection between the first computing unit and the fifth computing unit, the first computing unit is connected to the fifth computing unit at the same time). The simulation calculation results of the signal propagation process are already locally available and can be transmitted at high speed without the need for the aforementioned high-speed serial connection).

[0053] Second round: In each of the The interior of the meta-extension interconnection computing matrix consists of a numbered sequence The second computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence All the calculation units and the corresponding first-round superposition calculation results are subjected to transmission delay effect calibration and subtraction processing, and the processing results are superimposed to obtain corresponding second-round superposition calculation results.

[0054] In the second round, the first round superposition calculation result is specifically transmitted through a high-speed serial connection between the second calculation unit and the first calculation unit (if the second calculation unit is also the first calculation unit, since the first round superposition calculation result of the first calculation unit is already locally, it is not necessary to complete the high-speed transmission through the aforementioned high-speed serial connection). In addition, the specific process of the transmission delay effect calibration subtraction processing is a prior art and will not be described in detail here.

[0055] No. Wheel: In each The interior of the meta-extension interconnection computing matrix consists of a numbered sequence The third computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence All of the computing units and the corresponding The transmission delay effect calibration and deduction processing are performed on the results of the round superposition calculation, and the processing results are superimposed to obtain the corresponding Wheel superposition calculation results.

[0056] In the said In the round, the The transmission method of the round superposition calculation result is similar to that of the first round superposition calculation result, which can be conventionally derived and will not be repeated here.

[0057] No. Round: consists of a numbered sequence The fourth computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence All of the computing units and the corresponding The round superposition calculation results are subjected to transmission delay effect calibration and subtraction processing, and the processing results are superimposed to obtain the corresponding output digital signal.

[0058] In the said In the round, the The transmission method of the round superposition calculation result is similar to that of the first round superposition calculation result, and can also be conventionally derived, so it will not be repeated here.

[0059] To facilitate the explanation of the calculation logic of the calculation unit, a 4 2 The meta-extension interconnection calculation matrix is ​​taken as an example of the (0, 0, 0) signal sending channel. Fig.11 As shown, the channel simulation calculation is divided into two rounds: In the first round, within all four 4-element interconnected computing matrices, a first computing unit with a numbering sequence (N2,0) first obtains signal data to be channel simulated from 4×2 signal receiving channels that are communicatively connected to the first computing unit and three other computing units, and then for the (0,0,0) signal sending channel, based on the signal data and given channel parameters of each signal receiving channel in the 4×2 signal receiving channels relative to the corresponding sending channel, simulates and calculates 4×2 signal propagation processes of each signal receiving channel relative to the corresponding sending channel, and superimposes the calculation results to obtain the corresponding first round superposition calculation results, wherein the values ​​of N2 are 0, 1, 2 and 3 respectively, the values ​​of N1 are 0, 1, 2 and 3 respectively, and the value of J is an integer (for example, 0 and 1); In the second round, the first computing unit with the numbering sequence (N2,0) transmits the first round of superposition calculation results of the (0,0,0) signal sending channel to the second computing unit with the numbering sequence (0,0) through a high-speed serial connection (the above-mentioned superposition calculation results of the first computing unit with the numbering sequence (0,0) are locally available and do not need to be transmitted through the aforementioned high-speed serial connection). Then, the second computing unit calibrates the local superposition calculation results of the (0,0,0) signal sending channel with the foreign superposition calculation results (i.e., from the first computing unit with the numbering sequence (1,0), the first computing unit with the numbering sequence (2,0) and the first computing unit with the numbering sequence (3,0)) and deducts the data transmission delay effect, and then performs superposition calculation on these four superposition calculation results again to obtain the calculation result of the final signal propagation process of the (0,0,0) signal sending channel, and sends the signal generation through the (0,0,0) signal sending channel.

[0060] All other channels should be configured similarly.

[0061] The extended interconnection computing matrix is ​​further expanded to When the number of elements is 1, the calculation process is divided into three rounds, that is, for any (n3, n2, n1, j) signal sending channel: In the first round, within all the basic N1-element interconnected computing matrices, the first computing unit with the numbering sequence (N3, N2, n1) obtains the signal data to be channel simulated from all N1×J signal receiving channels connected to itself and the other N1-1 other computing units, and simulates and calculates a total of N1×J signal propagation processes of the (n3, n2, n1, j) signal sending channels based on the signal data and the given channel parameters of each signal receiving channel relative to the (n3, n2, n1, j) signal sending channel, and then performs superposition calculation to obtain the first round of superposition calculation results of the (n3, n2, n1, j) signal sending channel; In the second round, inside all the basic N2×N1 element extended interconnection computing matrices, the second computing units with the numbering sequence (N3,n2,n1) aggregate all the first-round superposition computing results of the (n3,n2,n1,j) signal transmission channels through high-speed serial connections between each other, and after calibration and deducting the data transmission delay effect, perform superposition computing again on the above superposition computing results to obtain the second-round superposition computing results of the (n3,n2,n1,j) signal transmission channel; In the third round, the third computing unit with the numbering sequence (n3, n2, n1) aggregates all the second-round superposition calculation results of the (n3, n2, n1, j) signal transmission channel through the high-speed serial connection between the computing unit and the second computing units with the numbering sequence (N3, n2, n1) in the other N3-1 N2×N1 element computing matrices, and performs superposition calculation on the above superposition calculation results again after calibration to deduct the data transmission delay effect, and obtains the calculation result of the final signal propagation process of the (n3, n2, n1, j) signal transmission channel, and sends the signal through the (n3, n2, n1, j) signal transmission channel.

[0062] All other channels should be configured similarly.

[0063] all The calculation method of the meta-extension interconnection calculation matrix can be further deduced by analogy. The calculation needs to be divided into Round proceed.

[0064] In summary, the channel simulation system provided by this embodiment has the following technical effects: (1) This embodiment provides a flexible and scalable large bandwidth real-time channel simulation system, which includes N M The interconnection computing matrix is ​​extended by the element, and the connection relationship between the upper and lower extended interconnection computing matrix levels, between the extended interconnection computing matrix and the interconnection computing matrix, and between the computing units inside the interconnection computing matrix can be constructed to form computing arrays of different topological structures and different scales. The more array elements in the interconnection computing matrix and the more levels of extended interconnection, the larger the scale of the computing matrix, the larger the total computing power and storage space, and the larger the channel simulation needs can be met, so as to achieve the goal of adapting to different channel scales and instantaneous bandwidths. Therefore, users can easily customize the channel simulation system according to their own needs, and can gradually expand product functions and channel scales through phased construction, thereby reducing costs and improving product utilization rates. The problems of existing medium and large channel simulation instruments and equipment, such as fixed form, relatively single function, extremely expensive price, and difficulty in changing product characteristics, expanding product functions and adjusting channel scales according to different user needs, are solved, which is convenient for practical application and promotion. (2) Flexible expansion and splitting: The computing topology structure designed in this embodiment is applicable to channel simulation systems with a few channels to hundreds of channels. A small-scale channel simulation system can be easily expanded into a large-scale system, and a large-scale system can also be easily split into several small-scale systems. (3) Large simulation bandwidth: The bandwidth that a channel simulation system can simulate mainly depends on the computing power and data access capability of a single computing unit. The computing topology structure designed in this embodiment can flexibly configure the ratio of the number of computing units and signal transceiver units (as well as the number of transceiver channel groups). The signal transceiver unit can also provide additional computing power and data access capability support. Therefore, when the ratio of computing units is increased (the maximum ratio of transceiver channel groups to computing units can be 1:1), the current advanced FPGA has a computing power of more than 3TOps. Under a 1:1 ratio, that is, with 32 computing units and extended computing units, a total computing power of more than 100TOps can be provided. Under a 2GHz instantaneous bandwidth, 32T32R channel simulation with a total of 64 channels can also be achieved. (4) Low computing delay: The hardware circuit characteristics of the FPGA itself have the characteristics of low computing delay. At the same time, the computing matrix topology designed in this embodiment makes it possible for any two computing units to interact with each other through only a very short data exchange path, so the entire computing matrix has the advantage of low computing delay. (5) Low cost: Due to the standardization of computing units and interconnected computing matrices, the construction and expansion of large-scale channel simulation systems no longer need to be customized, thus achieving low cost; (6) Easy to develop: Since the computing topology designed in this embodiment is a completely symmetrical structure, it is only necessary to design algorithms and programs for a single computing unit to complete the programming of the entire computing matrix; (7) Customizability: The signal transceiver unit provides extended computing power, and the implementation of this computing power is completely decoupled from the computing matrix, so it is easy to provide customized signal processing capabilities for the channel simulation port device.

[0065] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A flexibly constructed and expandable channel simulation system, characterized in that: Included Meta-extended interconnection computing matrix, wherein the Meta-Extended Interconnection Computing Matrix includes indivual Meta-Extended Interconnection Computing Matrix, the Meta-Extended Interconnection Computing Matrix includes indivual Meta-extended interconnected computing matrix, and so on Meta-Extended Interconnection Computing Matrix includes indivual Meta-extends the interconnected computing matrix until Meta-Extended Interconnection Computing Matrix includes indivual Meta-interconnection computing matrix, The Meta-interconnection Computing Matrix includes A computing unit, for The abbreviation of , wherein the computing unit is used to perform a signal propagation simulation calculation on an input digital signal obtained by converting an input radio frequency signal to obtain an output digital signal for converting into an output radio frequency signal, , , , and Respectively represent integers greater than or equal to 2, represents an integer greater than or equal to 2, exist Exists when greater than or equal to 3, and indicates greater than or equal to 0 and less than integer; In the Any two of the computing units are connected in communication; For any Each of the computing units in the element interconnection computing matrix enables the corresponding units to be respectively connected to Other The computing units in corresponding positions in the meta-interconnect computing matrix are connected in communication, wherein any one Meta-interconnection computing matrix and the Other The meta-interconnection computing matrix is ​​described Meta-extended interconnected computing matrix; For any Each of the computing units in the interconnected computing matrix is ​​extended so that the corresponding units are connected to each other in Other The computing units in corresponding positions in the meta-extension interconnection computing matrix are connected in communication, wherein any one Meta-Extended Interconnection Computing Matrix and the Other The meta-extension interconnection computing matrix is ​​described Meta-extended interconnected computing matrix.

2. The channel simulation system as claimed in claim 1, characterized in that: Also included is a control computer, wherein the control computer is communicatively connected to the The controlled end of each computing unit in the meta-extended interconnected computing matrix is ​​used to read and write parameters and / or data of the computing unit.

3. The channel simulation system as claimed in claim 1, characterized in that: The computing unit is communicatively connected to at least one signal transceiver unit; The signal transceiver unit is used to receive the input digital signal obtained by conversion based on the input radio frequency signal, and send the output digital signal for conversion into the output radio frequency signal; Alternatively, the signal transceiver unit is used to receive the input radio frequency signal and convert it into the input digital signal, and to convert the output digital signal into the output radio frequency signal and send it out.

4. The channel simulation system as claimed in claim 3, characterized in that: When the signal transceiver unit is used to receive the input RF signal and convert it into the input digital signal, and convert the output digital signal into the output RF signal and send it out, the signal transceiver unit includes an analog receiving front-end module, an analog transmitting front-end module, an ADC module, a DAC module, a second FPGA module, a second storage module and a second high-speed serial interface, wherein the analog receiving front-end module is used to receive the input RF signal, the analog transmitting front-end module is used to send the output RF signal, and the second high-speed serial interface is used to communicate with the computing unit; The output end of the analog receiving front-end module is communicatively connected to the input end of the ADC module, the output end of the ADC module is communicatively connected to the input end of the second FPGA module, the input end of the analog transmitting front-end module is communicatively connected to the output end of the DAC module, the input end of the DAC module is communicatively connected to the output end of the second FPGA module, and the second FPGA module is also communicatively connected to the second storage module and the second high-speed serial interface respectively.

5. The channel simulation system as claimed in claim 4, characterized in that: The signal transceiver unit also includes a clock and trigger signal interface, an onboard OCXO module and a clock generation and distribution circuit module based on a phase-locked loop mechanism, wherein the clock and trigger signal interface is used to receive an external sampling clock signal, a reference clock signal, a GPS second pulse signal and a trigger signal, and the onboard OCXO module is used to generate a time base signal; The trigger signal output end of the clock and trigger signal interface is communicatively connected to the second FPGA module, the non-trigger signal output end of the clock and trigger signal interface and the time base signal output end of the onboard OCXO module are respectively communicatively connected to the input end of the clock generation and distribution circuit module, and the clock signal output end of the clock generation and distribution circuit module is respectively communicatively connected to the analog receiving front-end module, the analog transmitting front-end module, the ADC module, the DAC module and the second FPGA module.

6. The channel simulation system as claimed in claim 3, characterized in that: When the signal transceiver unit includes a second FPGA module and a second storage module and a second high-speed serial interface respectively communicatively connected to the second FPGA module, the signal transceiver unit is also used as an extended computing unit relative to the computing unit, and is used to perform any one of the following extended computing tasks (A) to (I) or any combination thereof: (A) Using interpolation processing to increase the instantaneous bandwidth of the signal; (B) Using decimation to reduce the instantaneous bandwidth of the signal; (C) Using digital frequency conversion to change the center frequency of the signal; (D) Calculate the spectrum of the signal in real time; (E) Real-time calculation of target echo or clutter; (F) Simulate the phase offset of the signal arriving at each port of the multi-channel direction finding receiver; (G) Simulating the signal amplitude and phase of each channel in the radar sum and difference channels; (H) Data transmission and reception via a high-speed serial bus; (I) Perform amplitude calibration and phase calibration of the transmit and receive signals.

7. The channel simulation system as claimed in claim 1, characterized in that: The signal propagation simulation calculation includes calculation of spatial fading, multipath effect, Doppler effect, time delay and / or interference superposition during the signal propagation process.

8. The channel simulation system as claimed in claim 1, characterized in that: Said The meta-extended interconnection computing matrix is ​​used to perform symmetric computation of channel simulation in the following manner: set up Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the Meta-Extended Interconnection Computing Matrix Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates the The Meta-interconnection Computational Matrix is ​​described in Unique number in the meta-extension interconnection calculation matrix and in the integer range Any value in Indicates that the computing unit is in the Unique number in the meta-interconnection matrix and in the integer range In order to make Each of the computing units in the meta-extension interconnection computing matrix has a corresponding numbering sequence ; If in the Each of the computing units in the meta-extended interconnected computing matrix is ​​independently connected to each other in communication. For the signal receiving and sending channel, set Indicates that the signal receiving and sending channel is in A unique number in the signal receiving and sending channel and is in the integer range In order to make Each pair of signal transceiver channels in the signal transceiver channel has a corresponding number sequence ,in, represents a positive integer; For numbered sequences The target signal sending channel is calculated to obtain the corresponding output digital signal for conversion into the output RF signal, and the output digital signal is sent out through the corresponding channel, wherein, represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has , represents an integer and has The output digital signal is as follows The round step calculation yields: First round: In each of the The interior of the meta-interconnection computing matrix consists of a numbered sequence The first computing unit starts with the first computing unit and Other computing units communicate with each other The signal data to be channel simulated is obtained on a signal receiving channel, and then the target signal sending channel is calculated based on the signal data and the The given channel parameters of each signal receiving channel in the signal receiving channels relative to the corresponding transmitting channel are simulated and calculated. signal propagation process, and superimpose the calculation results to obtain the corresponding first round of superposition calculation results; Second round: In each of the The interior of the meta-extension interconnection computing matrix consists of a numbered sequence The second computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence Performing a transmission delay effect calibration and deduction process on all the calculation units and the corresponding first round superposition calculation results, and superimposing the processing results to obtain the corresponding second round superposition calculation results; No. Wheel: In each The interior of the meta-extension interconnection computing matrix consists of a numbered sequence The third computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence All of the computing units and the corresponding The transmission delay effect calibration and deduction processing are performed on the results of the round superposition calculation, and the processing results are superimposed to obtain the corresponding Wheel superposition calculation results; No. Round: consists of a numbered sequence The fourth computing unit, for the target signal sending channel, respectively calculates the signals from the numbered sequence All of the computing units and the corresponding The round superposition calculation results are subjected to transmission delay effect calibration and subtraction processing, and the processing results are superimposed to obtain the corresponding output digital signal.

9. The channel simulation system as claimed in claim 1, characterized in that: The computing unit includes a first FPGA module, a first storage module and a first high-speed serial interface, wherein the first high-speed serial interface has at least one and is used for communication connection with a signal transceiver unit or other computing units; The first FPGA module is communicatively connected to the first storage module and the first high-speed serial interface respectively.

10. The channel simulation system according to claim 9, characterized in that: The first storage module adopts dynamic random access memory, and the first high-speed serial interface adopts Nano-Pitch interface, MiniSAS HD interface, SFP interface, SFP+ interface, QSFP interface, QSFP+ interface, QSFP28 interface or QSFP56 interface.

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