Tail Bit Decoding Device, Decoding Method of Turbo Code and Beidou Receiver

Abstract

The present invention relates to a tail bit decoding device, a decoding method and a Beidou receiver for Turbo codes. The device includes: a first decoder for calculating first LLR information according to the input soft information of parity bit 1 including tail bits, L21 information and first systematic bit soft information; a second decoder for calculating second LLR information according to the input soft information of parity bit 2 including tail bits, L12 information and second systematic bit soft information; an L12 calculation module for outputting L12 information after performing extrinsic information calculation, interleaving and zero padding on the first LLR information; an L21 calculation module for outputting L21 information after performing extrinsic information calculation, deinterleaving and zero padding on the second LLR information; a decision output module for making a decision on the second LLR information after stopping iteration and deinterleaving to output the Turbo code decoding result. The present invention decodes by using the tail bit information of the Turbo code, improving the performance of the decoder.

Description

Technical Field

[0001] The present invention relates to the technical fields of decoding and satellite navigation, and particularly to a tail bit decoding device for Turbo codes, a decoding method, and a Beidou receiver. Background Art

[0002] Turbo codes are a channel error correction coding scheme that can approach the Shannon limit. Many communication systems, such as the 3G and 4G mobile communication systems supported by 3GPP, have adopted Turbo codes as their channel coding schemes. In recent years, with the popularization of LDPC codes and Polar codes, 5G NR has adopted LDPC codes and Polar codes as its channel coding schemes. However, many communication systems, especially some satellite communication systems, such as the RDSS subsystem in the Beidou satellite navigation system BDS in China, still adopt the Turbo code coding scheme due to the good performance shown by the Turbo code scheme.

[0003] In the bit sequence output by the encoder of Turbo codes, in addition to the soft information bits of length K, there are also tail bits of length T; the role of the tail bits is to finally zero the trellis of the encoder, which is beneficial to the correct decoding of the receiver. Therefore, the tail bit sequence also carries some useful information and cannot be ignored.

[0004] In existing Turbo code decoders, the tail bits are not used because the length of the interleaver is K and it cannot additionally process the tail bit sequence of length T. Therefore, the external information can only be retained with a length of K, and thus the sub-decoder can only receive and process the systematic bit soft information sequence or the parity bit soft information sequence of length K, discarding the additional tail bit soft information sequence of length T.

[0005] The tail bits carry some useful information, and the existing Turbo code decoders that do not utilize the tail bits will cause a reduction in decoding performance. Summary of the Invention

[0006] In view of the above analysis, the present invention aims to disclose a tail bit decoding device for Turbo codes, a decoding method, and a Beidou receiver, so as to solve the problem that the traditional Turbo code decoder cannot utilize the tail bits, resulting in a reduction in decoding performance.

[0007] On the one hand, the present invention discloses a tail bit decoding device for Turbo codes, including: a first decoder, a second decoder, an L12 calculation module, an L21 calculation module, and a decision output module; wherein,

[0008] The first decoder is configured to calculate first LLR information according to the input parity bit 1 soft information including tail bits, L21 information, and first systematic bit soft information;

[0009] A second decoder, configured to calculate second LLR information according to input check bit 2 soft information including tail bits, L12 information, and second system bit soft information;

[0010] The second system bit soft information is the soft information obtained by interleaving the information before the tail bits of the first system bit soft information and then concatenating the tail bits;

[0011] An L12 calculation module, configured to perform external information calculation, interleaving, and zero padding on the first LLR information, and then output L12 information including tail bits;

[0012] An L21 calculation module, configured to perform external information calculation, deinterleaving, and zero padding on the second LLR information, and then output L21 information including tail bits;

[0013] A decision output module, configured to perform decision and deinterleaving on the second LLR information that meets the stop iteration condition, and output the Turbo code decoding result.

[0014] Further, the first and second decoders are both tail bit sub-decoders; the length of the input information of the tail bit sub-decoder is K + T; K is the length of the encoded input data block, and T is the data length of the tail bits; decoding algorithms including the log-map algorithm and the max-log-map algorithm are adopted in the tail bit sub-decoder, and the decoding output LLR information is obtained after operating in a loop for K + T times;

[0015] During the decoding process, first perform the decoding operation of the first decoder to obtain L12 information; input the L12 information into the second decoder for decoding operation to obtain L21 information; then perform the decoding operation of the first decoder again; iterate in this way until the maximum number of iterations is met.

[0016] Further, it further includes: a first interleaver and a splicer, configured to generate second system bit soft information;

[0017] The first interleaver is a K-bit interleaver; it is configured to interleave the first K-bit soft information of the first system bit soft information, and output the interleaved data to the splicer;

[0018] The splicer is configured to splice the accessed interleaved data and the last T tail bit soft information of the first system bit soft information together, and output the second system bit soft information.

[0019] Further, the L12 calculation module includes a first external information calculation module, a second interleaver, and a first zero padding module;

[0020] The first external information calculation module is configured to access the first K data of the first LLR information with a length of K + T output by the first decoder, discard the last T data, perform calculations using the first K data of the first LLR information, remove the influence brought by the prior information and the systematic bit soft information, and obtain pure external information with a length of K;

[0021] The second interleaver is a K-bit interleaver, which is configured to interleave the external data with a length of K output by the first external information calculation module;

[0022] The first zero-padding module is configured to perform zero-padding operation on the data output by the second interleaver with a length of T bits, and output L12 information with a length of K + T as the external information input to the second decoder.

[0023] Further, the L21 calculation module includes a second external information calculation module, a second deinterleaver, and a second zero-padding module;

[0024] The second external information calculation module is configured to access the first K data of the second LLR information with a length of K + T output by the second decoder, discard the last T data, perform calculations using the first K data of the second LLR information, remove the influence brought by the prior information and the systematic bit soft information, and thus obtain pure external information with a length of K;

[0025] The second deinterleaver is a K-bit deinterleaver, which is configured to deinterleave the external data with a length of K output by the second external information calculation module;

[0026] The second zero-padding module is configured to perform zero-padding operation on the data output by the second deinterleaver with a length of T bits, and output L21 information with a length of K + T as the external information input to the first decoder.

[0027] Further, the calculation method of the external information is as follows:

[0028] ;

[0029] where LLR ext1 and LLR ext2 are the external information calculated by the first and second external information calculation modules in the current calculation respectively, LLR 1 and LLR 2 are the first and second LLR information output by the first and second decoders respectively, LLR sys1 and LLR sys2 are the first and second systematic bit soft information input to the first and second decoders respectively, and LLR a1 and LLR a2 are the external information input to the first and second decoders.

[0030] Further, the decision output module includes a decision maker and a first deinterleaver;

[0031] The input end of the decision maker is connected to the output end of the second decoder, and the second LLR information output by the second decoder is accessed, which is used to perform a hard decision on the second LLR information that meets the stop iteration condition; the decision result is output to the input end of the first deinterleaver;

[0032] The first deinterleaver deinterleaves the decision result output by the decision maker and outputs the Turbo code decoding result.

[0033] The present invention also discloses a decoding method for a tail bit decoding device based on the Turbo code as described above, including the following steps:

[0034] Step S1: Obtain the first system bit soft information with a length of K+T input by the system, the parity bit 1 soft information and the parity bit 2 soft information with lengths of K+T; initialize the L21 information and L12 information with lengths of K+T; set the decoding iteration times;

[0035] Step S2: Interleave the first K data of the first system bit soft information, and then splice it with the last T tail bit soft information of the first system bit soft information to obtain the soft information with a length of K+T as the second system bit soft information;

[0036] Step S3: Perform the operation of the first decoder, input the parity bit 1 soft information, L21 information and the first system bit soft information into the first decoder to calculate the first LLR information; input the first LLR information into the L12 calculation module for external information calculation, interleaving and zero padding, and then output the L12 information including the tail bits;

[0037] Step S4: Perform the operation of the second decoder, input the parity bit 2 soft information, L12 information and the second system bit soft information into the second decoder to calculate the second LLR information; input the second LLR information into the L21 calculation module for external information calculation, deinterleaving and zero padding, and then output the L21 information including the tail bits;

[0038] Step S5: Jump to step S3, perform the operation of the sub-first decoder, and then perform the operation of the second decoder, and iterate in this way until the preset maximum iteration times are reached;

[0039] Step S6: For the second LLR information output by the second decoder, first perform a hard decision, and then perform a deinterleaving operation to output the Turbo code decoding result.

[0040] Further, the external information calculation method in the L12 calculation module and the L21 calculation module is:

[0041] ;

[0042] Among them, LLR ext1 and LLR ext2 are respectively the external information of the L12 and L21 calculation modules in the current calculation. LLR 1 and LLR 2 are respectively the first and second LLR information output by the first and second decoders. LLR sys1 and LLR sys2 are respectively the first and second systematic bit soft information input to the first and second decoders. LLR a1 and LLR a2 are the external information input to the first and second decoders.

[0043] The present invention also discloses a Beidou receiver. The Beidou receiver receives the signals of the RDSS subsystem in the Beidou satellite navigation system BDS. When performing Turbo code decoding, it uses the tail bit decoding device of the Turbo code as described above and decodes using the tail bit information of the Turbo code, improving the decoding performance.

[0044] One of the beneficial effects that the present invention can achieve is as follows:

[0045] In the tail bit decoding device, decoding method, and Beidou receiver of the Turbo code disclosed by the present invention, decoding is performed using the tail bit information of the Turbo code, improving the performance of the decoder; it is applicable to reliable data transmission under relatively low signal-to-noise ratio (SNR) conditions and can gradually improve the decoding accuracy through iteration; when applied to the RDSS subsystem in the Beidou satellite navigation system BDS, it improves the performance of the Beidou receiver. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The drawings are only for the purpose of illustrating specific embodiments and are not considered to be a limitation of the present invention. Throughout the drawings, the same reference signs denote the same components;

[0047] Figure 1 is a schematic block diagram of the composition and connection of the tail bit decoding device of the Turbo code in the embodiment of the present invention;

[0048] Figure 2 is a schematic diagram of the coding scheme of the Turbo code in the embodiment of the present invention;

[0049] Figure 3 is a schematic diagram of the coding of the Turbo code adopted by the CDMA2000 system in the embodiment of the present invention;

[0050] Figure 4Schematic diagram of the signal processing structure of the sub-encoder in the embodiment of the present invention;

[0051] Figure 5 Flowchart of the decoding method of the tail bit decoding device of the Turbo code in the embodiment of the present invention. Detailed implementation manners

[0052] The preferred embodiments of the present invention will be specifically described below with reference to the accompanying drawings, where the accompanying drawings form a part of this application and are used together with the embodiments of the present invention to explain the principles of the present invention.

[0053] Embodiment 1

[0054] An embodiment of the present invention discloses a tail bit decoding device for a Turbo code; as Figure 1 shown, it includes: a first decoder, a second decoder, an L12 calculation module, an L21 calculation module, and a decision output module; wherein, the first and second decoders are both tail bit sub-decoders,

[0055] The first decoder is used to calculate the first LLR (log-likelihood ratio) information according to the input parity bit 1 soft information including tail bits, L21 information, and first systematic bit soft information;

[0056] The second decoder is used to calculate the second LLR information according to the input parity bit 2 soft information including tail bits, L12 information, and second systematic bit soft information;

[0057] The second systematic bit soft information is the soft information of the tail bits spliced after interleaving the information before the tail bits of the first systematic bit soft information;

[0058] The L12 calculation module is used to perform external information calculation, interleaving, and zero-padding on the first LLR information and then output the L12 information including tail bits;

[0059] The L21 calculation module is used to perform external information calculation, de-interleaving, and zero-padding on the second LLR information and then output the L21 information including tail bits;

[0060] The decision output module is used to make a decision and de-interleave the second LLR information that meets the stop iteration condition, and output the Turbo code decoding result.

[0061] Specifically, for the tail bit sub-decoders of the first and second decoders, since they include tail bits, the length of the input information is K + T; K is the length of the encoded input data block, and T is the data length of the tail bits; decoding algorithms including the log-map algorithm and the max-log-map algorithm are adopted in the tail bit sub-decoders, and the operation loops K + T times to obtain the decoded output LLR information;

[0062] During the decoding process, first perform the decoding operation of the first decoder to obtain the L12 information; input the L12 information into the second decoder for decoding operation to obtain the L21 information; perform the decoding operation of the first decoder again; iterate in this way until the maximum number of iterations is satisfied.

[0063] As Figure 2 shown, in the encoding scheme of Turbo codes, it mainly includes two sub-encoders, an interleaver, and a rate matching module. The rate matching module mainly performs the puncturing function, discarding some parity bits or repeated systematic bits to meet the requirements of the transmission data rate. We usually call the above sub-encoder sub-encoder 1 and the following sub-encoder sub-encoder 2. The structures of the two sub-encoders are the same, and they also output systematic bits and parity bits. Therefore, the structures of their corresponding sub-decoders are also the same. Different from sub-encoder 1, the input bits of sub-encoder 2 have been interleaved.

[0064] It should be noted that in the tail bit decoding scheme of the Turbo code in the embodiments of the present invention, rate matching is not the focus. Therefore, the de-rate matching sub-module is not involved.

[0065] As Figure 3 shown, the Turbo code used in the CDMA2000 system; for each input information bit, each sub-encoder of this encoder outputs three bits, X, Y, Z, where X is the systematic bit and Y and Z are both parity bits. The systematic bit is the bit with the same value as the input bit of the sub-encoder; however, the X bit sequence may also include tail bits in addition to the bit sequence input by the sub-encoder.

[0066] The signal processing structures of the two sub-encoders are the same. For details, please refer to Figure 4 .

[0067] As Figure 4 shown, for each input bit I of the sub-encoder, three bits X, Y, Z are output. Assume that the length of each information data block, that is, the sequence length of the encoding input bit I, is K. Then Figure 1 and Figure 2 the length of the interleaver in Figure 2 is also K. However, due to the encoding mechanism of the tail bits, the lengths of the three output sequences X, Y, and Z of the sub-encoder are all K + T. Denote the length of the tail bit sequence corresponding to each output bit sequence as T (such as Figure 2 where T = 3).

[0068] Additionally, before performing Turbo code encoding on each block of data, the initial values of the three registers in Figure 3 are set to 0.

[0069] Specifically, takingFigure 4 For example, in the generation scheme of tail bits, when the sequence of input bits I, that is, the first K bits are input, the switch branch is closed with the upper branch for encoding to generate three output bit sequences X, Y, and Z with a length of K respectively; then, the switch branch is switched to the lower branch and closed with the lower branch, and the sub-encoder continues to operate to generate three tail bit sequences with a length of T (here T = 3) respectively, and are appended to the sequences of X, Y, and Z respectively. Finally, the lengths of the sequences of X, Y, and Z are all K + T, that is, all K + 3 bits. The role of the tail bits is to finally zero the trellis of the sub-encoder, which is beneficial for the receiver to correctly decode. Therefore, the tail bit sequence also carries non-negligible useful information.

[0070] Specifically, the input information of the first decoder in this embodiment is the parity bit 1 soft information including tail bits, L21 information, and the first system bit soft information with a length of K + T;

[0071] Among them, the parity bit 1 soft information and the first system bit soft information are the information for decoding transmitted by the system; the L21 information is the external information with a length of K + T calculated by the L21 calculation module;

[0072] The input information of the second bit sub-decoder in this embodiment is the parity bit 2 soft information including tail bits, L12 information, and the second system bit soft information obtained by interleaving the information before the tail bits and splicing the tail bit soft information, with a length of K + T;

[0073] Among them, the parity bit 2 soft information is the information for decoding transmitted by the system; the L12 information is the external information with a length of K + T calculated by the L12 calculation module;

[0074] The solution in this embodiment further includes: a first interleaver and a splicer for generating the second system bit soft information;

[0075] The first interleaver is a K-bit interleaver; it is used to interleave the first K bit soft information of the first system bit soft information and output the interleaved data to the splicer;

[0076] The splicer is used to splice the accessed interleaved data and the last T tail bit soft information of the first system bit soft information together and output the second system bit soft information.

[0077] Specifically, the L12 calculation module includes a first external information calculation module, a second interleaver, and a first zero-padding module;

[0078] The first external information calculation module is configured to access the first K data of the first LLR information with a length of K+T output by the first decoder, discard the last T data, and perform calculations using the first K data of the first LLR information to remove the influence brought by the prior information and the systematic bit soft information, so as to obtain pure external information with a length of K;

[0079] The calculation method of the external information is as follows:

[0080] ;

[0081] wherein, LLR ext1 is the external information output by the first external information calculation module in the current calculation, LLR 1 is the first LLR information output by the first decoder, LLR sys1 is the first systematic bit soft information input to the first decoder, and LLR a1 is the external information input to the first decoder;

[0082] The second interleaver is a K-bit interleaver, which is configured to interleave the external data with a length of K output by the first external information calculation module;

[0083] The first zero-padding module is configured to perform a zero-padding operation with a length of T bits on the data output by the second interleaver, and output L12 information with a length of K+T as the external information input to the second decoder.

[0084] Specifically, the L21 calculation module includes a second external information calculation module, a second deinterleaver, and a second zero-padding module;

[0085] The second external information calculation module is configured to access the first K data of the second LLR information with a length of K+T output by the second decoder, discard the last T data, and perform calculations using the first K data of the second LLR information to remove the influence brought by the prior information and the systematic bit soft information, so as to obtain pure external information with a length of K;

[0086] The calculation method of the external information is as follows:

[0087] ;

[0088] wherein, LLR ext2 is the external information output by the second external information calculation module in the current calculation, LLR 2 is the second LLR information output by the second decoder, LLR sys2 is the second systematic bit soft information input to the second decoder, and LLR a2 is the external information input to the second decoder;

[0089] The second deinterleaver is a K-bit deinterleaver, which is used to deinterleave the external data of length K output by the second external information calculation module;

[0090] The second zero-padding module is used to perform zero-padding operation on the data output by the second deinterleaver for T bits in length, and output the L21 information of length K + T as the external information input to the first decoder.

[0091] The purpose of the calculation formula of the external information is to remove the influence brought by the prior information and the system bit soft information in the LLR information output by the first and second decoders, so as to obtain pure external information. This part of information will be transmitted to the next sub-decoder to improve the performance of the entire Turbo decoding process.

[0092] The decision output module includes a decision maker and a first deinterleaver;

[0093] The input end of the decision maker is connected to the output end of the second decoder, and accesses the second LLR information output by the second decoder, which is used to perform hard decision on the second LLR information that meets the stop iteration condition; the decision result is output to the input end of the first deinterleaver;

[0094] The stop iteration condition is that the iteration reaches the preset maximum number of iterations;

[0095] The first deinterleaver deinterleaves the decision result output by the decision maker and outputs the Turbo code decoding result.

[0096] In the decoding operation of the tail bit sub-decoder of the solution in this embodiment, the length of the input data is K + T. Therefore, the operation loop in the tail bit sub-decoder is K + T times, rather than K times of the traditional sub-decoder;

[0097] Referring to the max-log-map decoding algorithm, the tail bit sub-decoder needs to perform the following operations:

[0098] 1) Initialize variables; the variables include branch metric values, forward state metric values, backward state metric values, and output LLR values, all of which are initialized to zero vectors;

[0099] 2) Perform backward iteration; perform bit-by-bit calculation on the input information from back to front for K + T times to obtain the branch metric value gamma and the backward state metric value beta;

[0100] Among them, the initial value of the backward state metric value utilizes the trellis 0 state information brought by the tail bits;

[0101] 3) Perform forward iteration; perform bit-by-bit calculation on the input information from front to back to obtain the branch metric value gamma and the forward state metric value alpha;

[0102] Among them, the initial value of the forward state metric utilizes the state information with the initial value of the encoder register being 0;

[0103] 4) Calculate the output LLR information;

[0104] Calculate the LLR information by using the forward state metric alpha and the backward state metric beta.

[0105] During the operation, the calculation methods of the branch metric gamma, the backward state metric beta, the forward state metric alpha, and the LLR information can all refer to the existing calculation methods.

[0106] In summary, the tail bit decoding device of the Turbo code disclosed in this embodiment decodes by using the tail bit information of the Turbo code, improving the performance of the decoder; it is applicable to realizing reliable data transmission under lower signal-to-noise ratio (SNR) conditions and can gradually improve the decoding accuracy through iteration.

[0107] Embodiment 2

[0108] Another embodiment of the present invention discloses a decoding method using the tail bit decoding device of the Turbo code disclosed in Embodiment 1, as Figure 5 shown, including the following steps:

[0109] Step S1: Obtain the first systematic bit soft information with a length of K + T input by the system, the parity bit 1 soft information and the parity bit 2 soft information both with a length of K + T; initialize the L21 information and the L12 information with a length of K + T; set the decoding iteration times;

[0110] Step S2: Interleave the first K data of the first systematic bit soft information, and then splice it with the last T tail bit soft information of the first systematic bit soft information to obtain the soft information with a length of K + T as the second systematic bit soft information;

[0111] Step S3: Perform the operation of the first decoder, input the parity bit 1 soft information, the L21 information and the first systematic bit soft information into the first decoder to calculate the first LLR information; input the first LLR information into the L12 calculation module for external information calculation, interleaving and zero-padding, and then output the L12 information including the tail bits;

[0112] Step S4: Perform the operation of the second decoder, input the parity bit 2 soft information, the L12 information and the second systematic bit soft information into the second decoder to calculate the second LLR information; input the second LLR information into the L21 calculation module for external information calculation, de-interleaving and zero-padding, and then output the L21 information including the tail bits;

[0113] Step S5: Jump to step S3, perform the operations of the first sub-decoder, and then perform the operations of the second decoder, and iterate in this way until the preset maximum number of iterations is reached;

[0114] Step S6: For the second LLR information output by the second decoder, first perform hard decision, and then perform deinterleaving operation to output the Turbo code decoding result.

[0115] Specifically, the external information calculation methods in the L12 calculation module and the L21 calculation module are as follows:

[0116] ;

[0117] Among them, LLR ext1 and LLR ext2 are the external information calculated by the L12 and L21 calculation modules in the current calculation respectively, LLR 1 and LLR 2 are the first and second LLR information output by the first and second decoders respectively, LLR sys1 and LLR sys2 are the first and second systematic bit soft information input to the first and second decoders respectively, and LLR a1 and LLR a2 are the external information input to the first and second decoders.

[0118] The specific technical details and beneficial effects in this embodiment are the same as those described in Embodiment 1. Please refer to them specifically and will not be elaborated here one by one.

[0119] Embodiment 3

[0120] Another embodiment of the present invention discloses a Beidou receiver; the Beidou receiver receives the signals of the RDSS subsystem in the Beidou satellite navigation system BDS. When performing Turbo code decoding, it uses the tail bit decoding device of the Turbo code in Embodiment 1 and decodes using the tail bit information of the Turbo code, improving the decoding performance.

[0121] The specific technical details and beneficial effects in this embodiment are the same as those described in Embodiment 1. Please refer to them specifically and will not be elaborated here one by one.

[0122] The above is only a preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention.

Claims

1. A Turbo code tail bit decoding device, characterized in that: include: A first decoder, a second decoder, an L12 calculation module, an L21 calculation module and a decision output module; wherein, A first decoder, configured to calculate first LLR information according to input parity bit 1 soft information including tail bits, L21 information, and first system bit soft information; A second decoder, configured to calculate second LLR information according to the input check bit 2 soft information including tail bits, L12 information, and second system bit soft information; The second system bit soft information is the soft information of the tail bits obtained by interleaving the information before the tail bits of the first system bit soft information and then concatenating the tail bits; An L12 calculation module, configured to perform external information calculation, interleave and zero padding on the first LLR information, and then output L12 information including tail bits; An L21 calculation module, configured to perform external information calculation, deinterleave and zero padding on the second LLR information, and then output L21 information including tail bits; The decision output module is used to make a decision and deinterleave the second LLR information that meets the iteration stop condition, and output the Turbo code decoding result.

2. The tail bit decoding device of Turbo code according to claim 1, characterized in that: The first and second decoders are both tail bit sub-decoders; the length of the input information of the tail bit sub-decoder is K+T; K is the length of the encoded input data block, and T is the data length of the tail bit; the tail bit sub-decoder adopts decoding algorithms including log-map algorithm and max-log-map algorithm, and operates K+T times to obtain the LLR information of the decoded output; In the decoding process, the decoding operation of the first decoder is first performed to obtain L12 information; Input the L12 information into the second decoder for decoding operation to obtain the L21 information; perform the decoding operation of the first decoder again; and iterate in this manner until the maximum number of iterations is met.

3. The tail bit decoding device of Turbo code according to claim 2, characterized in that: Also includes: A first interleaver and splicer, used for generating second system bit soft information; The first interleaver is a K-bit interleaver; used to interleave the first K bits of the first system bit soft information, and output the interleaved data to the splicer; The splicer is used to splice the accessed interleaved data and the last T tail bit soft information of the first system bit soft information together to output the second system bit soft information.

4. The tail bit decoding device of Turbo code according to claim 2, characterized in that: The L12 calculation module includes a first external information calculation module, a second interleaver and a first zero padding module; The first external information calculation module is used to access the first K data of the first LLR information with a length of K+T output by the first decoder, discard the last T data, use the first K data of the first LLR information for calculation, remove the influence of prior information and system bit soft information, and obtain pure external information with a length of K; The second interleaver is a K-bit interleaver, configured to interleave external data of length K output by the first external information calculation module; The first zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second interleaver, and output L12 information with a length of K+T as external information input by the second decoder.

5. The tail bit decoding device of Turbo code according to claim 2, characterized in that: The L21 calculation module includes a second external information calculation module, a second deinterleaver and a second zero padding module; The second external information calculation module is used to access the first K data of the second LLR information with a length of K+T output by the second decoder, discard the last T data, use the first K data of the second LLR information for calculation, remove the influence of prior information and system bit soft information, so as to obtain pure external information with a length of K; The second deinterleaver is a K-bit deinterleaver, configured to deinterleave external data of length K output by the second external information calculation module; The second zero-padding module is used to perform a zero-padding operation with a length of T bits on the data output by the second deinterleaver, and output L21 information with a length of K+T as external information input by the first decoder.

6. The tail bit decoding device of Turbo code according to claim 4 or 5, characterized in that: The calculation method of the external information is: ； Among them, LLR ext1 , LLR ext2 are the external information calculated by the first and second external information calculation modules at the current time, LLR1 and LLR2 are the first and second LLR information output by the first and second decoders, respectively. sys1 , LLR sys2 The first and second systematic bit soft information of the input of the first and second decoders are LLR a1 , LLR a2 It is the external information input by the first and second decoders.

7. The tail bit decoding device of Turbo code according to claim 6, characterized in that: The decision output module includes a decision device and a first deinterleaver; The input end of the decision device is connected to the output end of the second decoder, accesses the second LLR information output by the second decoder, and is used to make a hard decision on the second LLR information that meets the condition for stopping iteration; and outputs the decision result to the input end of the first deinterleaver; The first deinterleaver deinterleaves the decision result output by the decider and outputs a Turbo code decoding result.

8. A decoding method based on the tail bit decoding device of a Turbo code according to any one of claims 1 to 7, characterized in that: The following steps are involved: Step S1, obtaining the first system bit soft information of the length K+T of the system input, the check bit 1 soft information and the check bit 2 soft information of the length K+T; initializing the L21 information and L12 information of the length K+T; setting the number of decoding iterations; Step S2, interleave the first K data of the first system bit soft information, and then concatenate them with the last T tail bit soft information of the first system bit soft information to obtain soft information with a length of K+T as the second system bit soft information; Step S3, executing the operation of the first decoder, inputting the check bit 1 soft information, L21 information and the first system bit soft information into the first decoder to calculate the first LLR information; Input the first LLR information into the L12 calculation module to perform external information calculation, interleaving and zero padding, and then output the L12 information including the tail bits; Step S4, executing the operation of the second decoder, inputting the check bit 2 soft information, L12 information and the second system bit soft information into the second decoder to calculate the second LLR information; Input the second LLR information into the L21 calculation module to perform external information calculation, deinterleaving and zero padding, and then output the L21 information including the tail bits; Step S5, jump to step S3, execute the operation of the first sub-decoder, and then execute the operation of the second sub-decoder, and perform iteratively until a preset maximum number of iterations is reached; Step S6: Perform a hard decision on the second LLR information output by the second decoder, and then perform a deinterleaving operation to output a Turbo code decoding result.

9. The decoding method according to claim 8, characterized in that: The external information calculation method in the L12 calculation module and the L21 calculation module is: ； Among them, LLR ext1 , LLR ext2 LLR1 and LLR2 are the external information calculated by the L12 and L21 calculation modules in the current calculation respectively. LLR1 and LLR2 are the first and second LLR information output by the first and second decoders respectively. sys1 , LLR sys2 The first and second systematic bit soft information of the input of the first and second decoders are LLR a1 , LLR a2 It is the external information input by the first and second decoders.

10. A Beidou receiver, characterized in that: The Beidou receiver receives the RDSS subsystem signal in the Beidou satellite navigation system BDS, and when performing Turbo code decoding, adopts the Turbo code tail bit decoding device as described in any one of claims 1-7, and uses the tail bit information of the Turbo code for decoding, thereby improving the decoding performance.

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