Low-power-consumption message analysis and interface recovery architecture and method based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a low-power-consumption message analysis and interface recovery architecture and method based on an FPGA (Field Programmable Gate Array), and the architecture comprises an optical port receiving module, a flow monitoring module, a cross-clock domain transmission module, a message analysis module and an interface recovery module, then a flow monitoring module adds a message timestamp and monitors data flow in real time, a cross-clock-domain transmission module transmits a message collected by an optical port clock domain to a message analysis clock domain through asynchronous FIFO, and a message analysis module analyzes effective data and a data ID according to a self-defined message format; the message analysis frequency can be adjusted in real time according to the data flow, and finally the interface recovery module outputs the effective data and the data ID from the user-defined logic interface. According to the method, message analysis and interface recovery are realized through a self-defined message protocol, the architecture is realized by FPGA logic, and the method has the characteristics of flexible message analysis, low power consumption, high message transmission rate and stable time sequence.

Description

Technical Field

[0001] The present invention belongs to the technical field of data transmission, and specifically refers to a low-power message parsing and interface recovery architecture and method based on FPGA. Background Art

[0002] With the development of the Internet, the Internet of Things, and industrial automation, the speed and bandwidth requirements of data transmission are constantly increasing. FPGA, due to its parallel processing capabilities, can support real-time processing of high-speed data streams and meet the requirements of high throughput. FPGA can achieve efficient parallel computing at the hardware level, thereby significantly reducing the delay of data processing and transmission and ensuring real-time performance. FPGA can support multiple communication protocols, such as Ethernet, CAN, UART, etc., making it widely compatible in different application scenarios and able to meet the communication needs between different devices and systems.

[0003] The relationship between power consumption and operating frequency of FPGA (Field Programmable Gate Array) modules is a very important topic, especially in high-performance and low-power designs. Power consumption not only affects the thermal management of the device, but also its overall performance and reliability. The dynamic power consumption of FPGAs is related to signal switching and is usually calculated by the following formula: P dynamic =C load ×V 2 ×f Among them, C load is the load capacitance, V is the operating voltage, and f is the operating frequency. It can be seen that the dynamic power consumption is proportional to the operating frequency. The higher the frequency, the greater the dynamic power consumption.

[0004] In the field of message transmission, in order to increase the speed of message transmission, the working frequency of the message parsing module needs to be continuously increased, which leads to increasing power consumption of the module. In the traditional message parsing module, the entire module works at a constant frequency, but the data flow on the message transmission network changes in real time and is not always transmitted at the maximum flow. Although the high processing frequency meets the processing requirements of the module, it causes waste of bandwidth and power consumption due to excessive consumption of resources.

[0005] Therefore, the present invention provides a low-power message parsing and interface recovery architecture and method based on FPGA. The present invention is implemented through a customized message transmission protocol, and uses customized optical port message collection, flow detection, asynchronous FIFO, message parsing, and interface recovery methods to realize a low-power message parsing and transmission system that can dynamically control its own processing frequency. The entire architecture is implemented by FPGA logic, and the customized logic interface is simple and easy to develop, with the characteristics of flexible message parsing, low power consumption, high message transmission rate, and stable timing. Summary of the invention

[0006] The purpose of the present invention is to provide a low-power message parsing and interface recovery architecture and method based on FPGA, so as to overcome the problem of bandwidth and power consumption waste caused by too high message processing frequency.

[0007] In order to achieve the above-mentioned purpose, the present invention designs a low-power message parsing and interface recovery architecture and method based on FPGA, which includes an optical port receiving module, a flow monitoring module, a cross-clock domain transmission module, a message parsing module and an interface recovery module. The flow monitoring module is respectively connected to the data output port of the optical port receiving module, the data input port of the cross-clock domain transmission module and the flow input port of the message parsing module, and the message parsing module is respectively connected to the data output port of the cross-clock domain transmission module and the data input port of the interface recovery module.

[0008] Preferably, the traffic monitoring module includes a timestamp adding module and a traffic calculation module. The timestamp adding module is used to add a time tag to the message received from the optical port receiving module to provide a time reference for the traffic calculation module to process. The traffic calculation module is used to detect the data traffic information and traffic offset of the message, which can be used as the control basis of the frequency switching module. Assuming that the total number of bits of the message arriving within the time from t1 to t2 is b1, and the total number of bits of the message arriving within the time from t2 to t3 is b2, the calculation formulas for the traffic g and the offset e are as follows.

[0009] The cross-clock domain transmission module includes a message collection module and an asynchronous FIFO module, which are used to collect custom protocol messages from the traffic monitoring module and transmit the messages in the optical port clock domain to the message parsing clock domain across the clock domain through the asynchronous FIFO.

[0010] The message parsing module includes a message matching module, a data extraction module, an SRAM cache module and a frequency switching module. The message matching module is used to match the message header from the data stream and analyze the message type. The data extraction module is used to extract valid data and data ID according to the message type and store them in the SRAM cache module. The frequency switching module is used to adjust the message parsing frequency according to the flow g and the offset e to reduce the module power consumption.

[0011] The interface recovery module includes a read cache module and a timing generation module. The read cache module is used to read valid data or signals in the SRAM cache according to the custom address table. The timing generation module is used to restore the timing of the valid data and signals according to the custom protocol requirements and output them from the custom logic interface.

[0012] The custom logic interface is used to output messages generated according to the custom protocol, including a clock signal clk_out, a data interface data_out[W-1:0] (where W value ranges from 1 to 512), a data valid signal data_valid, and a data ID interface id_out[7:0]. When the custom logic interface outputs valid data, the data_valid signal is pulled high, and the data ID interface outputs a specific ID so that the user can determine the expected output port of the current data. If the last beat of data does not fill data_out[W-1:0], the high bit of the last beat of data is padded with zeros.

[0013] The present invention abandons the conventional message parsing architecture. The present invention is implemented through a customized message transmission protocol, and uses customized optical port message collection, flow detection, asynchronous FIFO, message parsing, and interface recovery methods to realize a low-power message parsing and transmission system that can dynamically control its own processing frequency. The entire architecture is implemented by FPGA logic, and the customized logic interface is simple and easy to develop. It has the characteristics of flexible message parsing, low power consumption, high message transmission rate, and stable timing. Even different series of FPGAs are suitable for this architecture, and it has strong adaptability and portability.

[0014] The optical port receiving module is used to provide the hardware implementation basis for high-speed serial data transmission. It is connected to the optical module through multiple FPAGSerdes high-speed serial differential lines for data reception, and then sent to the traffic monitoring module after serial-to-parallel conversion. The main function of the optical module is to convert the electrical signal of the device into an optical signal at the sending end and the optical signal into the electrical signal of the device at the receiving end, thereby realizing the conversion of photoelectric signals.

[0015] The transmission bandwidth of the present invention can dynamically adjust the architecture bandwidth by adjusting the number of transmission channels of the optical port or the data bit width configuration of the FPAG Serdes interface, and the message parsing module can select the parsing frequency gear according to the flow size to reduce power consumption.

[0016] The present invention designs a low-power message parsing and interface recovery architecture and method based on FPGA. Taking the message parsing of 4-channel optical ports and 5 frequency gears as an example, the message parsing steps are as follows:

[0017] Step S1, the optical port receiving module performs serial-to-parallel conversion on the data received from the four FPAG Serdes high-speed serial differential lines, collects the data stream and sends it to the flow monitoring module;

[0018] Step S2, the traffic monitoring module adds a timestamp to the data flow message, monitors the data flow in real time and sends the result to the message parsing module;

[0019] Step S3, the cross-clock domain transmission module transmits the custom protocol message output by the traffic monitoring module to the message parsing clock domain through the asynchronous FIFO;

[0020] Step S4, the message parsing module accurately identifies the message type and extracts valid data and data ID into the SRAM cache, and adjusts the message parsing frequency according to the data flow to reduce module power consumption;

[0021] Step S5, the interface recovery module reads the SRAM cache and restores the timing of the valid data and data ID according to the custom protocol requirements, and finally outputs them from the custom logic interface.

[0022] Preferably, in step S1, four FPAG Serdes channels, with a single channel rate of 16 Gbps and a total bit width of 256 bits, are connected to an optical module for transmission;

[0023] Preferably, in step S2, a timestamp is added to the data stream message, the bit width of the timestamp is 112 bits, of which 1 to 32 bits are identification code AF47, 33 to 96 bits are time value t in nanoseconds, and 97 to 112 bits are message length l. The data flow is monitored in real time and the result is sent to the message parsing module. Assuming that the number of messages arriving within t1 to t2 is k1, the total number of bits is b1, and the number of messages arriving within t2 to t3 is k2, and the total number of bits is b2, the flow g and the offset e are calculated as follows:

[0024] Preferably, in step S3, the cross-clock domain transmission module transmits the custom protocol message output by the traffic monitoring module to the message parsing clock domain through an asynchronous FIFO, and the data bit width of the interface of the asynchronous FIFO is 256 bits and the depth is 4096;

[0025] Preferably, the message parsing module in step S4 matches the 32-bit message header pkt_header. When the 256-bit data is valid, a custom pkt_header sequence is used for traversal detection, starting from the lower 32 bits, and shifting 1 bit to the left of the higher bits each time until traversing 256 bits. If the match is successful in the process, it means that the message type has been accurately identified and the valid data and data ID are extracted from the next transmitted data and put into the SRAM cache. There can be multiple pkt_header sequences according to the custom protocol, and sequence matching can be performed simultaneously;

[0026] Preferably, in step S4, the message parsing frequency is adjusted according to the data flow g and the offset e to reduce the power consumption of the module, the bit width of the flow g and the offset e are both 16 bits, and the mapping relationship of the 5 frequency gears is: if the g+e value is 0-4Gb, the parsing frequency f1=100MHz, if the g+e value is 4-8Gb, the parsing frequency f2=150MHz, if the g+e value is 8-16Gb, the parsing frequency f3=200MHz, if the g+e value is 16-32Gb, the parsing frequency f4=300MHz, if the g+e value is 32-64Gb, the parsing frequency f5=400MHz;

[0027] Preferably, in step S4, the SRAM cache size is 32MB, the data ID bit width is 8 bits, the SRAM read / write interface is AXI4, and the interface data bit width is 256 bits;

[0028] Preferably, in step S5, the custom logic interface is used to output a message generated according to the custom protocol, including a clock signal clk_out, a data interface data_out[W-1:0] (wherein the W value ranges from 1 to 512), a data valid signal data_valid, and a data ID interface id_out[7:0]. When the custom logic interface outputs valid data, the data_valid signal is pulled high, and the data ID interface outputs a specific ID so that the user can determine the expected output port of the current data. If the last beat of data does not fill data_out[W-1:0], the high bit of the last beat of data is padded with zeros.

[0029] Preferably, the principle of custom message is: the message size is 32 to 512 bytes, the first 32 bits of the message are the message header, and the rest are the message payload. The message header content can be customized according to the custom protocol, and the message header can include the message type, message length, etc.;

[0030] Preferably, the FPGA Serdes interface uses Xilinx FPGA as an example, and its configuration is as follows: the total link rate must be greater than or equal to the maximum rate of a single data stream; the number of channels can be configured according to bandwidth requirements; the user data width (User datawidth) is selected as 256bit; the Dataflow Mode is configured as RX-only Simplex; the encoding method selects Aurora64B66B; and the GT Refalk Selection selects MGTREFCLK0.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention provides an FPGA-based low-power message parsing and interface recovery architecture and method, which is implemented through a custom message transmission protocol, and uses custom optical port message collection, flow detection, asynchronous FIFO, message parsing, and interface recovery methods to realize a low-power message parsing and transmission system that can dynamically control its own processing frequency. The entire architecture is implemented by FPGA logic, and the custom logic interface is simple and easy to develop, with the characteristics of flexible message parsing, low power consumption, high message transmission rate, and stable timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 This is the overall framework diagram of low-power message parsing based on FPGA of the present invention;

[0033] Figure 2 This is a detailed framework diagram of low-power message parsing based on FPGA of the present invention;

[0034] Figure 3 Schematic diagram of message header sequence traversal detection;

[0035] Figure 4 It is a diagram of a custom logic interface. DETAILED DESCRIPTION

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, but the embodiments of the present invention are not limited thereto.

[0037] like Figure 1 As shown, the present invention proposes a low-power message parsing and interface recovery architecture and method based on FPGA, which includes an optical port receiving module, a flow monitoring module, a cross-clock domain transmission module, a message parsing module and an interface recovery module. The flow monitoring module is respectively connected to the data output port of the optical port receiving module, the data input port of the cross-clock domain transmission module and the flow input port of the message parsing module, and the message parsing module is respectively connected to the data output port of the cross-clock domain transmission module and the data input port of the interface recovery module.

[0038] The optical port receiving module is used to receive data streams from the optical port. The traffic monitoring module then adds message timestamps and monitors data traffic in real time. The cross-clock domain transmission module transmits the messages collected in the optical port clock domain to the message parsing clock domain through asynchronous FIFO. The message parsing module then parses out valid data and data ID according to the custom message format. The message parsing frequency can be adjusted in real time according to the data traffic. Finally, the interface recovery module outputs the valid data and data ID from the custom logic interface.

[0039] Specifically, Figure 2As shown, the traffic monitoring module includes a timestamp adding module and a traffic calculation module. The timestamp adding module is used to add a time tag to the message received from the optical port receiving module to provide a time reference for the traffic calculation module to process. The traffic calculation module is used to detect the data traffic information and traffic offset of the message, which can be used as the control basis of the frequency switching module. Assuming that the total number of bits of the message arriving within the time of t1 to t2 is b1, and the total number of bits of the message arriving within the time of t2 to t3 is b2, the calculation formula of the traffic g and the offset e is as follows.

[0040] Specifically, Figure 2 As shown, the cross-clock domain transmission module includes a message collection module and an asynchronous FIFO module, which are used to collect custom protocol messages from the traffic monitoring module, and transmit the messages in the optical port clock domain across the clock domain to the message parsing clock domain through the asynchronous FIFO.

[0041] Specifically, Figure 2 As shown, the message parsing module includes a message matching module, a data extraction module, an SRAM cache module and a frequency switching module. The message matching module is used to match the message header from the data stream and analyze the message type. The data extraction module is used to extract valid data and data ID according to the message type and store them in the SRAM cache module. The frequency switching module is used to adjust the message parsing frequency according to the flow g and the offset e to reduce the module power consumption.

[0042] Specifically, Figure 2 As shown, the interface recovery module includes a read cache module and a timing generation module. The read cache module is used to read valid data or signals in the SRAM cache according to the custom address table, and the timing generation module is used to restore the timing of the valid data and signals according to the custom protocol requirements and output them from the custom logic interface.

[0043] More specifically, if Figure 3 As shown, when 256-bit data is valid, a custom 32-bit message header pkt_header sequence is required for traversal detection, wherein there can be multiple pkt_header sequences according to the custom protocol, and sequence matching can be performed simultaneously. Three pkt_header sequences are taken as an example, as shown in Table 1. Table 1pkt_header sequence table sequence name Sequence Content pkt_header1 FEC12345(32bit) pkt_header2 FEC6789A(32bit) pkt_header3 FECBCDEF(32bit)

[0044] More specifically, according to the custom protocol, the cross-clock domain transmission module in this architecture includes a set of asynchronous FIFOs with a bit width of 256 bits and a depth of 4096.

[0045] Specifically, the optical port receiving module is an internal resource of the FPGA and is implemented by calling the optical port module IP core. The receiving end converts 4 serial data into 1 256-bit parallel data and sends it to the traffic monitoring module. The IP core configuration is as follows: the total link bandwidth can be configured in the range of 1 to 64 Gbps; the number of channels can be configured according to bandwidth requirements; the user data width (User datawidth) is consistent with the input port width of the interface traffic monitoring module; the Dataflow Mode is configured as RX-onlySimplex; the encoding method selects Aurora 64B66B; and the GT Refalk Selection selects MGTREFCLK0.

[0046] In this embodiment, the present invention designs a low-power message parsing and interface recovery architecture and method based on FPGA, taking 4-channel optical port and 5 frequency gear message parsing as an example, the message parsing steps are as follows:

[0047] S1, the optical port receiving module converts the data received from the four FPAG Serdes high-speed serial differential lines into serial-to-parallel, collects the data stream and sends it to the traffic monitoring module, where the four FPAG Serdes channels, with a single channel rate of 16Gbps and a total bit width of 256bit, are connected to the optical module for transmission;

[0048] S2, the traffic monitoring module adds a timestamp to the data flow message, monitors the data flow in real time and sends the result to the message parsing module, wherein a timestamp is added to the data flow message, the bit width of the timestamp is 112 bits, wherein 1 to 32 bits are identification code AF47, 33 to 96 bits are time value t in nanoseconds, 97 to 112 bits are message length l, and the data flow is monitored in real time and the result is sent to the message parsing module. Assuming that the number of messages arriving within t1 to t2 is k1, the total number of bits is b1, and the number of messages arriving within t2 to t3 is k2, the total number of bits is b2, then the calculation formula of the flow g and the offset e is:

[0049] S3, the cross-clock domain transmission module transmits the custom protocol message output by the traffic monitoring module to the message parsing clock domain through the asynchronous FIFO, wherein the cross-clock domain transmission module transmits the custom protocol message output by the traffic monitoring module to the message parsing clock domain through the asynchronous FIFO, and the data bit width of the interface of the asynchronous FIFO is 256 bits and the depth is 4096;

[0050] S4, the message parsing module accurately identifies the message type and extracts valid data and data ID into the SRAM cache, and adjusts the message parsing frequency according to the data flow to reduce module power consumption;

[0051] Specifically, in step S4, the message parsing module matches the 32-bit message header pkt_header. When the 256-bit data is valid, a custom pkt_header sequence is used for traversal detection, starting from the lower 32 bits, and shifting 1 bit to the left each time until the 256 bits are traversed. If the match is successful in the process, it means that the message type has been accurately identified and the valid data and data ID are extracted from the next transmitted data and put into the SRAM cache. There can be multiple pkt_header sequences according to the custom protocol, and sequence matching can be performed simultaneously;

[0052] Specifically, in step S4, the message parsing frequency is adjusted according to the data flow g and the offset e to reduce the power consumption of the module. The bit widths of the flow g and the offset e are both 16 bits, and the mapping relationship of the 5 frequency gears is: if the g+e value is 0-4Gb, the parsing frequency f1=100MHz, if the g+e value is 4-8Gb, the parsing frequency f2=150MHz, if the g+e value is 8-16Gb, the parsing frequency f3=200MNz, if the g+e value is 16-32Gb, the parsing frequency f4=300MHz, if the g+e value is 32-64Gb, the parsing frequency f5=400MHz;

[0053] Specifically, in step S4, the SRAM cache size is 32MB, the data ID bit width is 8bit, the SRAM read / write interface is AXI4, and the interface data bit width is 256bit;

[0054] S5, the interface recovery module reads the SRAM cache and restores the timing of the valid data and data ID according to the custom protocol requirements, and finally outputs them from the custom logic interface.

[0055] Specifically, Figure 3 As shown, in this embodiment, the 32-bit message header sequence pkt_header is traversed and detected, and the specific operations are as follows:

[0056] a1) When the 256-bit data of the message parsing module input interface is valid, a Data_reg[31:0] register is defined to store the 32-bit message header sequence pkt_header;

[0057] a2) Start matching from the lower 32 bits, shifting 1 bit to the left each time. If the match fails during the process, continue until all 256 bits are traversed;

[0058] a3) If the match is successful during the process, and there are continuous 32-bit data in the 256-bit data that are equal to the sequence pkt_header, it means that the message type has been accurately identified, the traversal ends, and the valid data and data ID are extracted from the next transmitted data and put into the SRAM cache.

[0059] Specifically, Figure 4 As shown, in this embodiment, the external interface of the interface recovery module is a custom logic interface, including a clock signal clk_out, a data interface data_out[W-1:0] (wherein the W value ranges from 1 to 512), a data valid signal data_valid, and a data ID interface id_out[7:0]. When the custom logic interface outputs valid data, the data_valid signal is pulled high, and the data ID interface outputs a specific ID so that the user can determine the expected output port of the current data. If the last beat of data does not fill data_out[W-1:0], the high bit of the last beat of data is padded with zeros.

[0060] The above are only preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A low-power message parsing and interface recovery architecture and method based on FPGA, the architecture is: The invention comprises an optical port receiving module, a flow monitoring module, a cross-clock domain transmission module, a message parsing module and an interface recovery module. The flow monitoring module is respectively connected to the data output port of the optical port receiving module, the data input port of the cross-clock domain transmission module and the flow input port of the message parsing module, and the message parsing module is respectively connected to the data output port of the cross-clock domain transmission module and the data input port of the interface recovery module. The flow monitoring module comprises: Add a timestamp module and a flow calculation module, the flow monitoring module is used to measure the data flow information in real time under the optical port clock domain, and send the calculation result to the message parsing module; The cross-clock domain transmission module includes: a message collection module and an asynchronous FIFO module. The cross-clock domain transmission module is used to collect the custom protocol message from the traffic monitoring module, and transmit the message in the optical port clock domain to the message parsing clock domain through the asynchronous FIFO; The message parsing module includes: a message matching module, a data extraction module, an SRAM cache module and a frequency switching module. The message parsing module is used to accurately identify the message type and extract valid data and data ID and put them into the SRAM cache, and adjust the message parsing frequency according to the data flow to reduce the module power consumption. The interface recovery module includes: a read cache module and a timing generation module. The interface recovery module is used to read the SRAM cache and restore the timing of valid data and data ID according to the custom protocol requirements, and finally output them from the custom logic interface.

2. According to claim 1, a low-power message parsing and interface recovery architecture and method based on FPGA, the architecture is characterized in that: The timestamp adding module is used to add a time tag to the message received from the optical port receiving module to provide a time reference for the flow calculation module to process. The flow calculation module is used to detect the data flow information and flow offset of the message, which can be used as the control basis of the frequency switching module. Assuming that the total number of bits of the message arriving within the time from t1 to t2 is b1, and the total number of bits of the message arriving within the time from t2 to t3 is b2, the calculation formula of the flow g and the offset e is as follows.

3. According to claim 1, a low-power message parsing and interface recovery architecture and method based on FPGA, the architecture is characterized in that: The message matching module is used to match the message header from the data stream and analyze the message type. The data extraction module is used to extract valid data and data ID according to the message type and store them in the SRAM cache module. The frequency switching module is used to adjust the message parsing frequency according to the flow g and the offset e to reduce the module power consumption.

4. According to claim 1, a low-power message parsing and interface recovery architecture and method based on FPGA, the architecture is characterized in that: The read cache module is used to read valid data or signals in the SRAM cache according to the custom address table, and the timing generation module is used to restore the timing of the valid data and signals according to the custom protocol requirements and output them from the custom logic interface. The custom logic interface is used to output the message generated according to the custom protocol, including the clock signal clk_out, the data interface data_out[W-1:0] (wherein the W value ranges from 1 to 512), the data valid signal data_valid, and the data ID interface id_out[7:0]. When the custom logic interface outputs valid data, the data_valid signal is pulled high, and the data ID interface outputs a specific ID so that the user can determine the expected output port of the current data. If the last beat of data does not fill data_out[W-1:0], the high bit of the last beat of data is padded with zeros.

5. A low-power message parsing and interface recovery architecture and method based on FPGA, and its transmission method is: Step S1, the optical port receiving module performs serial-to-parallel conversion on the data received from the FPAG Serdes high-speed serial differential line, collects the data stream and sends it to the flow monitoring module; Step S2, the traffic monitoring module adds a timestamp to the data flow message, monitors the data flow in real time and sends the result to the message parsing module; Step S3, the cross-clock domain transmission module transmits the custom protocol message output by the traffic monitoring module to the message parsing clock domain through the asynchronous FIFO; Step S4, the message parsing module accurately identifies the message type and extracts valid data and data ID into the SRAM cache, and adjusts the message parsing frequency according to the data flow to reduce module power consumption; Step S5, the interface recovery module reads the SRAM cache and restores the timing of the valid data and data ID according to the custom protocol requirements, and finally outputs them from the custom logic interface.

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