Stereoscopic image display system and method based on FPGA

Abstract

The present invention provides a FPGA-based stereoscopic image display system and method, including: an acquisition module receives two image source signals and obtains two YUV single-edge data signals; a processing module stores one single-edge data signal in a DDR particle and uses the clock of another single-edge data signal to read the data in the DDR particle; a stereoscopic image signal is obtained by using the two single-edge data signals; and an output module outputs the stereoscopic image signal. Since the signal frequency of the YUV format is low and the bit width is large, it is conducive to FPGA to process data in parallel, and the amount of data is small, saving the internal resources of the FPGA; by storing one data signal in the DDR particle and reading from the DDR particle using the clock of the other data signal, not only can the space cost of storing the image in the DDR be saved, but also the resolution information can be efficiently identified, and the image frame rate can be improved, thereby improving the clarity of the stereoscopic image display, solving the problem that the existing FPGA-based stereoscopic image display technology occupies a large amount of storage resources and has a low display clarity.

Description

Technical Field

[0001] The present invention relates to the technical field of image display, and particularly relates to a stereoscopic image display system and method based on FPGA. Background Art

[0002] With the improvement of people's living standards, there are more and more display devices with 3D stereoscopic display effects. The display principle of existing 3D stereoscopic display devices is usually to generate two different images based on the different visual distances of people's left and right eyes for a 2D planar image, and then integrate and display them on the screen to achieve a 3D stereoscopic display effect. Since the video clarity depends on the high resolution of the display device, and high resolution means that a larger storage capacity device is required, therefore, in order to obtain a clearer display effect, existing display devices need to be configured with hardware having a larger storage capacity, resulting in increased costs.

[0003] Currently, in the field of image display, DDR is usually used as a storage device based on FPGA. By controlling the read and write of DDR, the display of stereoscopic images is realized. However, currently, images are generally in the RGB888 format, that is, each color component of RGB is 8 bits, thus constituting a 256 pixel value space. This image format requires a large amount of storage space, resulting in a large consumption of DDR resources.

[0004] In addition, since FPGA itself is a data chip for logical operations and is not good at data storage, therefore, existing image display technologies cannot perform stereoscopic image processing with higher resolution based on FPGA, making the clarity of its image display unable to meet the requirements and restricting the scope of use. Summary of the Invention

[0005] The purpose of the present invention is to provide a stereoscopic image display system and method based on FPGA to solve the problems that the existing stereoscopic image display technology based on FPGA occupies a large amount of storage resources and has a low display clarity.

[0006] To solve the above technical problems, the present invention provides a stereoscopic image display system based on FPGA, including:

[0007] An acquisition module, configured to receive an A-channel image source signal and a B-channel image source signal, and respectively perform sampling processing on the A-channel image source signal and the B-channel image source signal to obtain an A-channel single-edge data signal in YUV format and a B-channel single-edge data signal in YUV format;

[0008] A processing module, configured to store the B-channel single-edge data signal into a DDR particle, use the clock of the A-channel single-edge data signal as a reference clock, read the B-channel single-edge data signal in the DDR particle, and then perform image coincidence processing on the A-channel single-edge data signal and the B-channel single-edge data signal according to the chrominance value to obtain a fused stereoscopic image signal;

[0009] An output module, configured to output a stereoscopic image signal for displaying a stereoscopic image.

[0010] Optionally, in the FPGA-based stereoscopic image display system, the acquisition module includes an A-channel image source acquisition unit and a B-channel image source acquisition unit;

[0011] The A-channel image source acquisition unit is configured to acquire an A-channel image source signal, and perform sampling processing on the A-channel image source signal to generate an A-channel single-edge data signal in YUV format, an A-channel synchronization signal, and A-channel image coordinate information;

[0012] The B-channel image source acquisition unit is configured to acquire a B-channel image source signal, and perform sampling processing on the B-channel image source signal to generate a B-channel single-edge data signal in YUV format, a storage indication signal, and a write instruction, and store the B-channel single-edge data signal in YUV format in a write storage space according to the storage indication signal and the write instruction.

[0013] Optionally, in the FPGA-based stereoscopic image display system, the A-channel image source signal includes an A-channel image data signal, an A-channel DE synchronization signal, an A-channel VS synchronization signal, and an A-channel HS synchronization signal; the A-channel image source acquisition unit includes an A-channel image data processing circuit and an A-channel synchronization signal processing circuit;

[0014] The A-channel image data processing circuit is configured to use IDDR to convert the A-channel image data signal from a double-edge data signal to a clock single-edge data signal, and then perform splicing processing to obtain an A-channel single-edge data signal in YUV format;

[0015] The A-channel synchronization signal processing circuit is configured to use IDDR to convert the A-channel DE synchronization signal, the A-channel VS synchronization signal, and the A-channel HS synchronization signal from double-edge data signals to clock single-edge data signals respectively, and then perform OR operation processing respectively to obtain an A-channel single-edge DE synchronization signal, an A-channel single-edge VS synchronization signal, and an A-channel single-edge HS synchronization signal respectively; it is further configured to generate an A-channel coordinate flag signal according to the A-channel single-edge VS synchronization signal, and generate A-channel image coordinate information according to the A-channel coordinate flag signal and the A-channel single-edge HS synchronization signal.

[0016] Optionally, in the FPGA-based stereoscopic image display system, the B-channel image source signal includes a B-channel image data signal, a B-channel DE synchronization signal, a B-channel VS synchronization signal, and a B-channel HS synchronization signal; the B-channel image source acquisition unit includes a B-channel image data processing circuit and a B-channel synchronization signal processing circuit;

[0017] The B-channel image data processing circuit is used to convert the B-channel image data signal from a double-edge data signal to a clock single-edge data signal by using IDDR, and then perform splicing processing to obtain the B-channel single-edge data signal in YUV format;

[0018] The B-channel synchronization signal processing circuit is used to convert the B-channel DE synchronization signal, B-channel VS synchronization signal, and B-channel HS synchronization signal from double-edge data signals to clock single-edge data signals by using IDDR, and then perform OR operation processing respectively to obtain the B-channel single-edge DE synchronization signal, B-channel single-edge VS synchronization signal, and B-channel single-edge HS synchronization signal respectively; It is also used to generate a B-channel coordinate flag signal and a storage indication signal according to the B-channel single-edge VS synchronization signal, generate B-channel image coordinate information according to the B-channel coordinate flag signal and the B-channel single-edge HS synchronization signal, and generate a write command according to the B-channel image coordinate information and the B-channel single-edge DE synchronization signal.

[0019] Optionally, in the FPGA-based stereoscopic image display system, the processing module includes an image restoration unit, a storage control unit, and a color gamut conversion unit;

[0020] The image restoration unit is used to restore the synchronization information and the bit width of the image data according to the A-channel image coordinate information, and generate a read command at the same time;

[0021] The storage control unit is used to parse the write command and the read command to read the B-channel single-edge data signal in YUV format stored in the write storage space into the read storage space;

[0022] The color gamut conversion unit is used to convert the A-channel single-edge data signal in YUV format generated by the A-channel image source acquisition unit into an A-channel image signal in RGB format, and convert the B-channel single-edge data signal in YUV format in the read storage space into a B-channel image signal in RGB format; It is also used to judge whether the A-channel image signal and the B-channel image signal meet the preset conditions, and select to output the A-channel image signal or the B-channel image signal according to the judgment result;

[0023] The image restoration unit is also used to receive the image signal output by the color gamut conversion unit, and output a stereoscopic image signal after adding synchronization information to the image signal.

[0024] Optionally, in the FPGA-based stereoscopic image display system, the storage control unit includes a command arbitration circuit, a read / write data state machine, a control signal generation circuit, a memory controller, and a DDR physical layer;

[0025] The command arbitration circuit is used to receive the write command and the read command, and start the read / write data state machine according to the write command or the read command in a first-in-first-out arbitration manner;

[0026] The read / write data state machine is used to generate an address signal and a read / write command for controlling the DDR physical layer according to a write instruction or a read instruction;

[0027] The control signal generation circuit is used to generate a read address signal and a read enable signal according to a write instruction; and is further used to generate a write address signal and a write enable signal according to a read instruction;

[0028] The memory controller is used to send the data signal in the write storage space to the DDR chip through the DDR physical layer by using the address signal, the read / write command, the read address signal and the read enable signal; and is further used to read the data signal from the DDR chip through the DDR physical layer by using the address signal, the read / write command, the write address signal and the write enable signal and write it into the read storage space.

[0029] To solve the above technical problems, the present invention further provides a stereoscopic image display method based on FPGA, which is applied to the stereoscopic image display system based on FPGA as described in any one of the above, and the stereoscopic image display method based on FPGA includes:

[0030] Receiving an A-channel image source signal and a B-channel image source signal respectively;

[0031] Obtaining a single-edge data signal of the A channel in YUV format from the A-channel image source signal, and generating A-channel image coordinate information and a read instruction;

[0032] Obtaining a single-edge data signal of the B channel in YUV format from the B-channel image source signal, and generating a storage indication signal and a write instruction;

[0033] Storing the single-edge data signal of the B channel in YUV format in the write storage space according to the storage indication signal and the write instruction;

[0034] Analyzing the read instruction and the write instruction to read the single-edge data signal of the B channel in YUV format stored in the write storage space to the read storage space through the DDR chip;

[0035] Converting the single-edge data signal of the A channel in YUV format into an A-channel image signal in RGB888 format, and converting the single-edge data signal of the B channel in YUV format in the read storage space into a B-channel image signal in RGB888 format;

[0036] Judging whether the A-channel image signal and the B-channel image signal meet a preset condition, and selecting to output the A-channel image signal or the B-channel image signal according to the judgment result;

[0037] Adding synchronization information to the output image signal and then outputting a stereoscopic image signal.

[0038] Optionally, in the FPGA-based stereoscopic image display method, the method for obtaining the single-edge data signal of channel A in YUV format from the image source signal of channel A and generating the coordinate information of the image of channel A includes:

[0039] Using IDDR, convert the dual-edge data signal of the image data signal of channel A into a single-edge data signal of the clock, and then perform splicing processing to obtain the single-edge data signal of channel A in YUV format;

[0040] Using IDDR, convert the dual-edge data signals of the DE synchronization signal of channel A, the VS synchronization signal of channel A, and the HS synchronization signal of channel A into single-edge data signals of the clock respectively, and then perform OR operation processing respectively to obtain the single-edge DE synchronization signal of channel A, the single-edge VS synchronization signal of channel A, and the single-edge HS synchronization signal of channel A;

[0041] Detect the rising edge of the single-edge VS synchronization signal of channel A according to the sampling clock to generate the coordinate flag signal of channel A;

[0042] Generate the coordinate information of the image of channel A according to the coordinate flag signal of channel A and the single-edge HS synchronization signal of channel A.

[0043] Optionally, in the FPGA-based stereoscopic image display method, the method for obtaining the single-edge data signal of channel B in YUV format from the image source signal of channel B and generating the storage indication signal and the write instruction includes:

[0044] Using IDDR, convert the dual-edge data signal of the image data signal of channel B into a single-edge data signal of the clock, and then perform splicing processing to obtain the single-edge data signal of channel B in YUV format;

[0045] Using IDDR, convert the dual-edge data signals of the DE synchronization signal of channel B, the VS synchronization signal of channel B, and the HS synchronization signal of channel B into single-edge data signals of the clock respectively, and then perform OR operation processing respectively to obtain the single-edge DE synchronization signal of channel B, the single-edge VS synchronization signal of channel B, and the single-edge HS synchronization signal of channel B;

[0046] Detect the rising edge of the single-edge VS synchronization signal of channel B according to the sampling clock to generate the coordinate flag signal of channel B and the storage indication signal;

[0047] Generate the coordinate information of the image of channel B according to the coordinate flag signal of channel B and the single-edge HS synchronization signal of channel B;

[0048] Generate the write instruction according to the coordinate information of the image of channel B and the single-edge DE synchronization signal of channel B.

[0049] Optionally, in the above FPGA-based stereoscopic image display method, the method of parsing read instructions and write instructions to read the single-edge data signal of the B channel in YUV format stored in the write storage space to the read storage space via the DDR particles includes:

[0050] Receiving write instructions and read instructions;

[0051] According to the first-in-first-out arbitration method, generating a read address signal and a read enable signal according to the write instruction;

[0052] According to the read address signal and the read enable signal, reading the data signal from the write storage space, and according to the address signal and the read / write command, sending the read data signal to the DDR particles through the DDR physical layer;

[0053] According to the first-in-first-out arbitration method, generating a write address signal and a write enable signal according to the read instruction;

[0054] According to the address signal and the read / write command, reading the data signal from the DDR particles through the DDR physical layer, and writing the read data signal into the read storage space according to the write address signal and the write enable signal.

[0055] Optionally, in the above FPGA-based stereoscopic image display method, before converting the single-edge data signal of the A channel in YUV format into the image signal of the A channel in RGB888 format, the FPGA-based stereoscopic image display method further includes:

[0056] Obtaining the initial coordinate position of the currently executed image row according to the A-channel image coordinate information;

[0057] Reading the single-edge data signal of the B channel two rows in advance of the currently executed image row.

[0058] Optionally, in the above FPGA-based stereoscopic image display method, the method of determining whether the A-channel image signal and the B-channel image signal meet the preset conditions and selecting to output the A-channel image signal or the B-channel image signal according to the determination result includes:

[0059] Judging whether the R-channel value, B-channel value, and G-channel value in the B-channel image signal are all greater than the first preset channel threshold. If so, outputting the B-channel image signal; otherwise, judging whether the R-channel value, B-channel value, and G-channel value in the A-channel image signal are all greater than the second preset channel threshold. If so, outputting the A-channel image signal; otherwise, outputting the default blue background image.

[0060] The stereoscopic image display system and method based on FPGA provided by the present invention include: an acquisition module, configured to receive an A-channel image source signal and a B-channel image source signal, and respectively perform sampling processing on the A-channel image source signal and the B-channel image source signal to obtain an A-channel single-edge data signal in YUV format and a B-channel single-edge data signal in YUV format; a processing module, configured to store the B-channel single-edge data signal into a DDR particle, and use the clock of the A-channel single-edge data signal as a reference clock to read the B-channel single-edge data signal in the DDR particle, and then perform image coincidence processing on the A-channel single-edge data signal and the B-channel single-edge data signal according to the chromaticity value to obtain a fused stereoscopic image signal; an output module, configured to output the stereoscopic image signal to display a stereoscopic image. By performing sampling processing on the image source signal to obtain a single-edge data signal in YUV format, the frequency of the image data becomes lower and the bit width becomes larger, which is beneficial to giving play to the advantage of the FPGA in processing parallel data. At the same time, the amount of image data is reduced by half compared with the RGB format, thus effectively saving the internal storage resources of the FPGA; by storing the B-channel single-edge data signal into the DDR particle and using the clock of the A-channel single-edge data signal as a reference clock to read the data in the DDR particle, not only can the space cost of storing the image in the DDR be saved, but also the resolution information of the image source signal can be automatically recognized more efficiently, avoiding asynchronous timing caused by using a local clock, improving the image frame rate, thereby improving the clarity of the stereoscopic image display, and solving the problems of large storage resource occupation and low display clarity in the existing FPGA-based stereoscopic image display technology. Description of the Drawings

[0061] Figure 1 is a structural block diagram of the stereoscopic image display system based on FPGA provided in this embodiment;

[0062] Figure 2 is a structural schematic diagram of the A-channel image source acquisition unit provided in this embodiment;

[0063] Figure 3 is a structural schematic diagram of the B-channel image source acquisition unit provided in this embodiment;

[0064] Figure 4 is a structural schematic diagram of the processing module provided in this embodiment;

[0065] Figure 5 is a structural schematic diagram of the storage control unit provided in this embodiment;

[0066] Figure 6 is a structural schematic diagram of the color gamut conversion unit provided in this embodiment;

[0067] Figure 7 is a flowchart of the stereoscopic image display method based on FPGA provided in this embodiment;

[0068] Figure 8 Data storage schematic diagram of the read storage space provided in this embodiment;

[0069] Figure 9 Schematic diagram of the color gamut conversion unit reading the B-channel single-edge data signal from the read storage space provided in this embodiment;

[0070] Figure 10 Schematic diagram of converting the B-channel signal from YUV format to RGB format provided in this embodiment. Detailed implementation manners

[0071] The following further elaborates on the FPGA-based three-dimensional image display system and method proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different emphases and sometimes use different scales.

[0072] It should be noted that the "first", "second", etc. in the description, claims and drawings of the present invention are used to distinguish similar objects in order to describe the embodiments of the present invention, rather than to describe a specific order or sequence. It should be understood that such structures can be interchanged under appropriate circumstances. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0073] To clearly illustrate the implementation scheme of the transceiver delay calibration system and method provided in this embodiment, the technical terms involved in this embodiment are explained as follows:

[0074] FPGA: Field Programmable Gate Array, field programmable gate array;

[0075] DDR SDRAM: Double Data Rate Synchronous Dynamic Random Access Memory, double data rate synchronous dynamic random access memory, simply referred to as DDR;

[0076] IDDR: input double-data-rate, input double data rate;

[0077] MC: Memory Controller, memory controller;

[0078] PHY: Physical Layer, physical layer;

[0079] FIFO: First Input First Output, first in first out;

[0080] RAM: Random Access Memory, random access memory;

[0081] RGB: Read Green Blue, red, green, and blue primary colors;

[0082] YUV: YCbCr, a color encoding based on luminance and chrominance;

[0083] CMD: Command, command;

[0084] BANK: Block in DDR;

[0085] TTL: Transistor Transistor Logic, level standard;

[0086] HDMI: High Definition Multimedia Interface, high-definition multimedia interface;

[0087] DE: Single-bit synchronization signal for stereoscopic image display, indicating the valid display part of the image;

[0088] HS: Single-bit synchronization signal for stereoscopic image display, indicating the starting point of each line of the image;

[0089] VS: Single-bit synchronization signal for stereoscopic image display, indicating the starting flag of each frame of the image.

[0090] This embodiment provides a stereoscopic image display system based on FPGA, as Figure 1 shown, including:

[0091] An acquisition module, configured to receive the A-channel image source signal and the B-channel image source signal, and respectively sample and process the A-channel image source signal and the B-channel image source signal to obtain the A-channel single-edge data signal in YUV format and the B-channel single-edge data signal in YUV format;

[0092] A processing module, configured to store the single-edge data signal of channel B into the DDR chip, use the clock of the single-edge data signal of channel A as the reference clock, read the single-edge data signal of channel B in the DDR chip, and then perform image coincidence processing on the single-edge data signals of channels A and B according to the chrominance value to obtain a fused stereoscopic image signal;

[0093] An output module, configured to output a stereoscopic image signal to display a stereoscopic image.

[0094] The stereoscopic image display system based on FPGA provided in this embodiment samples the image source signal to obtain a single-edge data signal in YUV format, which reduces the frequency of the image data and increases the bit width, facilitating the use of the FPGA's ability to process parallel data. At the same time, the amount of image data is reduced by half compared to the RGB format, effectively saving the internal storage resources of the FPGA. By storing the single-edge data signal of channel B into the DDR chip and using the clock of the single-edge data signal of channel A as the reference clock to read the data in the DDR chip, not only can the space cost of storing the image in the DDR be saved, but also the resolution information of the image source signal can be automatically recognized more efficiently, avoiding asynchronous timing caused by using the local clock, improving the image frame rate, and thus improving the clarity of the stereoscopic image display, solving the problems of large storage resource occupation and low display clarity in the existing FPGA-based stereoscopic image display technology.

[0095] Specifically, in this embodiment, the acquisition module includes a channel A image source acquisition unit and a channel B image source acquisition unit.

[0096] Among them, the channel A image source acquisition unit is configured to acquire a channel A image source signal, and perform sampling processing on the channel A image source signal to generate a channel A single-edge data signal, a channel A synchronization signal, and channel A image coordinate information in YUV format.

[0097] In a specific embodiment, the channel A image source signal includes a channel A image data signal rxa_ttl, a channel A DE synchronization signal rxa_rtl_de, a channel A VS synchronization signal rxa_rtl_vs, and a channel A HS synchronization signal rxa_rtl_hs. As Figure 2 shown, the channel A image source acquisition unit includes a channel A image data processing circuit and a channel A synchronization signal processing circuit. Specifically, the channel A synchronization signal processing circuit includes 3 branches to process 3 synchronization signals respectively.

[0098] The channel A image data processing circuit is configured to use an IDDR to convert the channel A image data signal from a double-edge data signal to a clock single-edge data signal, and then perform splicing processing to obtain a channel A single-edge data signal in YUV format. As Figure 2As shown, the A-channel image data signal rxa_ttl is a signal for double data transmission, usually with a bit width of 36 bits. For the convenience of subsequent data processing, in this embodiment, the high 32-bit data is intercepted as the A-channel valid image data signal. After passing through the internal hard core IDDR of the FPGA, the double-data A-channel valid image data signal rxa_ttl is parsed into a group of two 32-bit wide clock single-edge data rxa_ttl_x and rxa_ttl_y. These two data are parallel, so they can be spliced to form a group of 64-bit data, thereby obtaining the A-channel single-edge data signal rxa_data. In addition, since the input A-channel image data signal is in YUV format, the obtained A-channel single-edge data signal is also in YUV format. Specifically, it can be YUV420 format.

[0099] The A-channel synchronization signal processing circuit is used to use IDDR to convert the A-channel DE synchronization signal, the A-channel VS synchronization signal, and the A-channel HS synchronization signal from double-edge data signals into clock single-edge data signals respectively, and then perform OR operation processing respectively to obtain the A-channel single-edge DE synchronization signal, the A-channel single-edge VS synchronization signal, and the A-channel single-edge HS synchronization signal respectively. As Figure 2 shown, the A-channel DE synchronization signal rxa_rtl_de, the A-channel VS synchronization signal rxa_rtl_vs, and the A-channel HS synchronization signal rxa_rtl_hs are single-bit indication signals. After passing through the internal hard core IDDR of the FPGA, the double-data A-channel DE synchronization signal rxa_rtl_de is parsed into a group of two clock single-edge data rxa_de_x and rxa_de_y; similarly, the double-data A-channel VS synchronization signal rxa_rtl_vs is parsed into a group of two clock single-edge data rxa_vs_x and rxa_vs_y, and the double-data A-channel HS synchronization signal rxa_rtl_hs is parsed into a group of two clock single-edge data rxa_hs_x and rxa_hs_y. Then, OR operations are performed on each group of clock single-edge data respectively to obtain the single-edge image synchronization signals, that is, OR operation is performed on rxa_de_x and rxa_de_y to obtain the A-channel single-edge DE synchronization signal rxa_de; OR operation is performed on rxa_vs_x and rxa_vs_y to obtain the A-channel single-edge VS synchronization signal rxa_vs; OR operation is performed on rxa_hs_x and rxa_hs_y to obtain the A-channel single-edge HS synchronization signal rxa_hs.

[0100] The A-channel image source acquisition unit further includes an A-channel frame start circuit and an A-channel coordinate generation circuit. Among them, as Figure 2As shown, the single-edge VS synchronization signal rxa_vs of path A is input to the frame start circuit of path A. Its rising edge is detected according to the sampling clock, thereby generating the coordinate flag signal vsa_flag of path A. Since the VS synchronization signal represents the starting coordinates of each frame, the coordinate flag signal vsa_flag of path A is used to inform the starting and ending points of coordinate generation. The coordinate flag signal vsa_flag of path A and the single-edge HS synchronization signal rxa_hs of path A are input to the coordinate generation circuit of path A. Since the HS synchronization signal represents the starting point of each row of the image, that is, the starting point of the coordinate of cnt_x. When the coordinate flag signal vsa_flag of path A is received, cnt_y in the coordinate generation circuit starts to accumulate. For each additional single-edge HS synchronization signal rxa_hs of path A in one row, the row number of cnt_y is incremented by 1, thereby generating the image coordinate information cnt_x and cnt_y of path A.

[0101] Moreover, the B-channel image source acquisition unit is used to acquire the B-channel image source signal, and perform sampling processing on the B-channel image source signal to generate a single-edge data signal of the B-channel in YUV format, a storage indication signal, and a write instruction, and store the single-edge data signal of the B-channel in YUV format in the write storage space according to the storage indication signal and the write instruction.

[0102] In a specific embodiment, the B-channel image source signal includes a B-channel image data signal rxb_ttl, a B-channel DE synchronization signal rxb_rtl_de, a B-channel VS synchronization signal rxb_rtl_vs, and a B-channel HS synchronization signal rxb_rtl_hs. As Figure 3 shown, the B-channel image source acquisition unit includes a B-channel image data processing circuit and a B-channel synchronization signal processing circuit. Similar to the A-channel synchronization signal processing circuit, the B-channel synchronization signal processing circuit also includes 3 branches to process 3 synchronization signals respectively.

[0103] The B-channel image data processing circuit is used to convert the B-channel image data signal from a double-edge data signal to a clock single-edge data signal using IDDR, and then perform splicing processing to obtain a single-edge data signal of the B-channel in YUV format. Similar to the processing process of the A-channel image data processing circuit, as Figure 3As shown, the B-channel image data signal rxb_ttl is a signal for double data transmission, usually with a bit width of 36 bits. For the convenience of subsequent data processing, in this embodiment, the high 32-bit data is intercepted as the B-channel valid image data signal. After passing through the internal hard core IDDR of the FPGB, the double-data B-channel valid image data signal rxb_ttl is parsed into a group of two 32-bit wide clock single-edge data rxb_ttl_x and rxb_ttl_y. These two data are parallel, so they can be spliced to form a group of 64-bit data, thereby obtaining the B-channel single-edge data signal rxb_data. In addition, since the input B-channel image data signal is in YUV format, the obtained B-channel single-edge data signal is also in YUV format, specifically, it can be YUV420 format.

[0104] The B-channel synchronization signal processing circuit is used to use the IDDR to convert the B-channel DE synchronization signal, the B-channel VS synchronization signal, and the B-channel HS synchronization signal from double-edge data signals into clock single-edge data signals respectively, and then perform OR operation processing respectively to obtain the B-channel single-edge DE synchronization signal, the B-channel single-edge VS synchronization signal, and the B-channel single-edge HS synchronization signal respectively. Similar to the processing process of the A-channel synchronization signal processing circuit, as Figure 3 shown, the B-channel DE synchronization signal rxb_rtl_de, the B-channel VS synchronization signal rxb_rtl_vs, and the B-channel HS synchronization signal rxb_rtl_hs are single-bit indication signals. After passing through the internal hard core IDDR of the FPGB, the double-data B-channel DE synchronization signal rxb_rtl_de is parsed into a group of two clock single-edge data rxb_de_x and rxb_de_y; similarly, the double-data B-channel VS synchronization signal rxb_rtl_vs is parsed into a group of two clock single-edge data rxb_vs_x and rxb_vs_y, and the double-data B-channel HS synchronization signal rxb_rtl_hs is parsed into a group of two clock single-edge data rxb_hs_x and rxb_hs_y. Then, OR operations are performed on each group of clock single-edge data respectively to obtain the single-edge image synchronization signals, that is, OR operation is performed on rxb_de_x and rxb_de_y to obtain the B-channel single-edge DE synchronization signal rxb_de; OR operation is performed on rxb_vs_x and rxb_vs_y to obtain the B-channel single-edge VS synchronization signal rxb_vs; OR operation is performed on rxb_hs_x and rxb_hs_y to obtain the B-channel single-edge HS synchronization signal rxb_hs.

[0105] The B-channel image source acquisition unit further includes a B-channel frame start circuit, a B-channel coordinate generation circuit, and a write address generation circuit. Among them, as Figure 3As shown, the single-edge VS synchronization signal rxb_vs of path B is input to the frame start circuit of path B. Its rising edge is detected according to the sampling clock, thereby generating the coordinate flag signal vsb_flag of path B. Since the VS synchronization signal represents the starting coordinates of each frame, the coordinate flag signal vsb_flag of path B is used to inform the starting and ending points of coordinate generation. At the same time, the frame start circuit of path B also outputs a storage indication signal fram, which is used to guide the data to be stored in a specific BANK area of the DDR particle. The coordinate flag signal vsb_flag of path B and the single-edge HS synchronization signal rxb_hs of path B are input to the coordinate generation circuit of path B. Since the HS synchronization signal represents the starting point of each row of the image, that is, the starting point of the cnt_x coordinate, when the coordinate flag signal vsb_flag of path B is received, the cnt_y in the coordinate generation circuit starts to accumulate. For each increase in the single-edge HS synchronization signal rxb_hs of path B, the number of rows of cnt_y increases by 1, thereby generating the image coordinate information cnt_x and cnt_y of path B. The single-edge DE synchronization signal rxb_de of path B, the image coordinate information cnt_x and cnt_y of path B are input to the write address generation circuit, and the write address generation circuit generates a write instruction. The write instruction includes the write FIFO command signal rx_rfifo_we (write FIFO enable signal), rx_rfifo_wdata (write FIFO data signal), rx_ram_we (write storage enable signal), rx_ram_addr (write storage address signal). Among them, rx_rfifo_wdata can identify the data image width and the current number of rows from the single-edge data signal rxb_data of path B.

[0106] Preferably, in order to temporarily store the generated write instructions and the single-edge data signal of path B for subsequent retrieval and use by the functional units in the subsequent processing module, in this embodiment, the acquisition module is further configured with a storage unit of path B and a FIFO unit of path B. When the input of a row of valid image data ends, that is, when the falling edge of the single-edge DE synchronization signal rxb_de of path B arrives, the generated rx_rfifo_we (write FIFO enable signal) and rx_rfifo_wdata (write FIFO data signal) are sent to the FIFO unit of path B. At the same time, according to the valid image interval, that is, according to the rising edge of the single-edge DE synchronization signal rxb_de of path B and the row-column information of the coordinate generation circuit of path B, the generated rx_ram_we (write storage enable signal) and rx_ram_addr (write storage address signal) are alternately sent to the storage unit of path B. When the HS synchronization signal comes, it means that a new row of image data arrives, the low bit of the address information is reset to 0, and the high bit is inverted to achieve ping-pong storage.

[0107] Furthermore, in this embodiment, as Figure 4As shown, the processing module includes an image restoration unit, a storage control unit, and a color gamut conversion unit.

[0108] Among them, the image restoration unit is used to restore the synchronization information and the bit width of the image data according to the A-channel image coordinate information, and at the same time generate a read instruction. As Figure 4 shown, the image restoration unit receives the A-channel image coordinate information cnt_x / cnt_y output by the A-channel image source acquisition unit, and then performs restoration processing on the image signal converted by the color gamut conversion unit; the generated read instruction is sent to the storage control unit to read the required B-channel single-edge data signal through the storage control unit. In addition, the image restoration unit is also used to receive the image signal output by the color gamut conversion unit, and output a stereoscopic image signal after adding synchronization information to the image signal.

[0109] In addition, the storage control unit is used to parse the write instruction and the read instruction to read the B-channel single-edge data signal in YUV format stored in the write storage space into the read storage space. In this embodiment, the write storage space can be the B-channel storage unit.

[0110] In practical applications, as Figure 4 and Figure 5 shown, the storage control unit is externally connected with DDR particles. In this embodiment, the DDR particles can specifically be DDR2. In addition, as Figure 4 shown, the storage control unit includes a command arbitration circuit, a read / write data state machine, a control signal generation circuit, a memory controller, and a DDR physical layer.

[0111] Among them, the command arbitration circuit is used to receive the write instruction and the read instruction, and start the read / write data state machine according to the write instruction or the read instruction in the first-in-first-out arbitration manner. Specifically, the write instruction and the read instruction are obtained through the control pins rx_fifo_re and rx_fifo_rdata of the external write FIFO module and the control pins tx_fifo_re and tx_fifo_rdata of the external read FIFO module.

[0112] It should be noted that the write instruction here is different from the write instruction generated by the write address generation circuit in the B-channel image acquisition unit; the read instruction is different from the read instruction generated by the image restoration unit. The write instruction and the read instruction here are both issued by an external module, used to control the start of the read / write data state machine, and confirm whether it is a read operation or a write operation.

[0113] In addition, the read / write data state machine is used to generate an address signal and a read / write command for controlling the DDR physical layer according to the write instruction or the read instruction.

[0114] In addition, the control signal generation circuit is used to generate a read address signal and a read enable signal according to a write instruction; it is also used to generate a write address signal and a write enable signal according to a read instruction. Specifically, as Figure 5 shown, the control signal generation circuit includes a read signal generation circuit and a write signal generation circuit. The read signal generation circuit is used to generate a read address signal rx_ram_raddr and a read enable signal rx_ram_re according to a read stored data signal rx_ram_rdata. Among them, the read stored data signal rx_ram_rdata is a 128-bit data signal provided by an external module according to a write instruction. Similarly, the write signal generation circuit is used to generate a write address signal tx_ram_waddr and a write enable signal tx_ram_we according to a write stored data signal tx_ram_wdata. Among them, the write stored data signal tx_ram_wdata is a 128-bit data signal provided by an external module according to a read instruction.

[0115] In addition, the memory controller is used to send the data signal in the write storage space to the DDR die through the DDR physical layer by using the address signal, read / write command, read address signal, and read enable signal; it is also used to read the data signal from the DDR die through the DDR physical layer according to the address signal, read / write command, write address signal, and write enable signal and write it into the read storage space.

[0116] The entire write process of the storage control unit is roughly as follows: The command arbitration circuit controls the read / write data state machine to start according to an external control write signal; the read / write data state machine correspondingly generates the address signal and write instruction necessary to control the DDR physical layer. The read signal generation circuit reads the data in the write storage space according to the read address signal and the read enable signal and transmits it to the memory controller; the memory controller writes the obtained data into the DDR die through the DDR physical layer according to the address signal and the write instruction.

[0117] The entire read process of the storage control unit is roughly as follows: The command arbitration circuit controls the read / write data state machine to start according to an external control read signal; the read / write data state machine correspondingly generates the address signal and read instruction necessary to control the DDR physical layer. The memory controller reads the data in the DDR die through the DDR physical layer according to the address signal and the read instruction and provides it to the write signal generation circuit; the write signal generation circuit writes the read data into the read storage space according to the write address signal and the write enable signal.

[0118] In practical applications, the storage control unit can use the clock of the A-channel single-edge data signal to generate the working clock of the DDR die, so as to maximize the high-bandwidth performance of the DDR die and improve the data read / write efficiency.

[0119] In this embodiment, the storage control unit stores the B-channel single-edge data signal read from the write storage space in the DDR particles, and then reads the data in the DDR particles to the read storage space by the storage control unit. Since the DDR particles themselves operate at a very high speed, the DDR physical layer (DDR PHY) in the storage control unit is a hard core in the FPGA, which can perform frequency doubling processing on the data and better adapt the data output by the memory controller (MC) to the timing of the DDR particles. In this way, the MC can quickly operate the DDR particles. By using the time-division multiplexing method, the reading and writing of multiple lines of DDR data can be completed within the display period of one line of the image.

[0120] Moreover, the color gamut conversion unit is used to convert the A-channel single-edge data signal in YUV format generated by the A-channel image source acquisition unit into an A-channel image signal in RGB format, and convert the B-channel single-edge data signal in YUV format in the read storage space into a B-channel image signal in RGB format; it is also used to judge whether the A-channel image signal and the B-channel image signal meet the preset conditions, and select and output the A-channel image signal or the B-channel image signal according to the judgment result.

[0121] In practical applications, through the input A-channel image coordinate information cnt_x / cnt_y, the color gamut conversion unit can know the specific position of the real-time image in one frame. According to the initial coordinate position of each line, it reads the data of the corresponding line of the B-channel image stored in the DDR particles 2 lines in advance. The BANK for reading the data is the position where the previous frame of the image written to the DDR is stored. In this way, it can effectively prevent the display frame offset caused by the difference in the frequencies of the A- and B-channel image data and ensure the final stereoscopic display effect of the output image.

[0122] Since the RGB image data is the most basic three primary colors, and the color levels increase in decimal order; while the YUV format is converted according to the brightness and weakness of the colors, and the value of Y does not increase with the deepening of the color, it is necessary to convert the image data into the RGB format to accurately judge the pixel values.

[0123] Such as Figure 6As shown in the figure, the single-edge data signal of Channel A in YUV format output by the Channel A image source acquisition unit is converted into the Channel A image signal in RGB format via the Channel A RGB conversion circuit; the single-edge data signal of Channel B read from the read storage space is converted into the Channel B image signal in RGB format via the Channel B RGB conversion circuit. Then, the Channel A image signal and the Channel B image signal in RGB format are judged via the judgment and selection circuit to decide whether to output the Channel A image signal or the Channel B image signal according to the judgment result, so as to obtain the image signal. In a specific embodiment, it is possible to first judge whether the R-channel value, the B-channel value, and the G-channel value in the Channel B image signal are all greater than the first preset channel threshold. If so, the Channel B image signal is output. Otherwise, it is judged whether the R-channel value, the B-channel value, and the G-channel value in the Channel A image signal are all greater than the second preset channel threshold. If so, the Channel A image signal is output. Otherwise, the default blue background image is output, thereby obtaining the image signal.

[0124] Among them, the values of the first preset channel threshold and the second preset channel threshold can be reasonably set according to actual requirements, and the two values can be the same or different. The present application does not limit this.

[0125] In practical applications, in order to reduce the conversion calculation amount of the color gamut conversion unit, only the single-edge data signal of Channel B can be converted, and the single-edge data signal of Channel A is used as the background image without conversion. In this way, when making a judgment, it is only judged whether the R-channel value, the B-channel value, and the G-channel value in the Channel B image signal are all greater than the preset channel threshold. If so, the single-edge data signal of Channel B is output. Otherwise, the single-edge data signal of Channel A is output.

[0126] In practical applications, the FPGA-based stereoscopic image display system provided in this embodiment can also be configured with a Flash memory module, a power supply module, etc., so as to store the programs of the internal functions of the FPGA using the Flash memory module, and supply power to each module through the power supply module, so that the FPGA automatically loads the program after power-on to achieve stereoscopic image display.

[0127] The FPGA-based stereoscopic image display system provided in this embodiment inputs two different image sources, divides them into the upper-layer image and the lower-layer background image, then overlaps the images according to the chromaticity value, selectively outputs the pixel points of the upper-layer image, and uses the background image to replace the unselected part, thereby achieving a stereoscopic effect. The difference between this system and the prior art is that it uses built-in DDR particles to reduce the external circuit design process for users; at the same time, the data processing part uses the YUV format, thereby effectively compressing the data volume and achieving low-cost stereoscopic image display; in addition, users can also create the text to be displayed by themselves to achieve the function of watermarking, and can also add some dynamic drawing effects on the basis of the original background image to enhance the visual appeal of the original image.

[0128] The stereoscopic image display system based on FPGA provided in this embodiment uses the clock of the A-channel image as the reference clock for both input and output, making it easier for the product to converge in timing and run at a faster rate. It can easily achieve two-channel image display with a resolution of 2K and a frame rate of 144 or a display of 4K at 60Hz. If the DDR performance is further improved or a higher-grade FPGA is used, a display of 4K at 144Hz can also be achieved. This system is suitable for application scenarios with extremely high requirements for the refresh rate. In addition, this system is based on FPGA, reducing the internal logic circuit of the FPGA, thereby reducing the power consumption of the system, and the highly integrated functional modules are conducive to the long-term maintenance of the product.

[0129] This embodiment also provides a stereoscopic image display method based on FPGA, which is applied to the stereoscopic image display system based on FPGA as described above. As Figure 7 shown, the stereoscopic image display method based on FPGA includes:

[0130] S1, respectively receive the A-channel image source signal and the B-channel image source signal.

[0131] Specifically, in this embodiment, the A-channel image source signal includes an A-channel image data signal, an A-channel DE synchronization signal, an A-channel VS synchronization signal, and an A-channel HS synchronization signal; the B-channel image source signal includes a B-channel image data signal, a B-channel DE synchronization signal, a B-channel VS synchronization signal, and a B-channel HS synchronization signal.

[0132] In practical applications, the A-channel image source signal and the B-channel image source signal can be input through an external high-definition video chip (HDMI chip). Moreover, the A-channel image data signal and the B-channel image data signal can be image data signals in the YUV420 format, thereby effectively reducing the amount of image data.

[0133] The data format output by the HDMI chip used here is the YUV420 format of HDMI2.0 converted to TTL36bit.

[0134] S2, obtain the A-channel single-edge data signal in the YUV format from the A-channel image source signal, and generate the A-channel image coordinate information and read instruction.

[0135] Specifically, in this embodiment, the implementation method of this step includes:

[0136] S21, use the IDDR to convert the A-channel image data signal from a double-edge data signal to a clock single-edge data signal, and then perform splicing processing to obtain the A-channel single-edge data signal in the YUV format;

[0137] S22. Using IDDR, convert the A-channel DE synchronization signal, A-channel VS synchronization signal, and A-channel HS synchronization signal from double-edge data signals to clock single-edge data signals respectively, and then perform OR operation processing respectively to obtain the A-channel single-edge DE synchronization signal, A-channel single-edge VS synchronization signal, and A-channel single-edge HS synchronization signal respectively;

[0138] S23. Detect the rising edge of the A-channel single-edge VS synchronization signal according to the sampling clock to generate the A-channel coordinate flag signal;

[0139] S24. Generate the A-channel image coordinate information according to the A-channel coordinate flag signal and the A-channel single-edge HS synchronization signal.

[0140] S3. Obtain the B-channel single-edge data signal in YUV format from the B-channel image source signal, and generate a storage indication signal and a write command.

[0141] Specifically, in this embodiment, the implementation method of this step includes:

[0142] S31. Using IDDR, convert the B-channel image data signal from a double-edge data signal to a clock single-edge data signal, and then perform splicing processing to obtain the B-channel single-edge data signal in YUV format;

[0143] S32. Using IDDR, convert the B-channel DE synchronization signal, B-channel VS synchronization signal, and B-channel HS synchronization signal from double-edge data signals to clock single-edge data signals respectively, and then perform OR operation processing respectively to obtain the B-channel single-edge DE synchronization signal, B-channel single-edge VS synchronization signal, and B-channel single-edge HS synchronization signal respectively;

[0144] S33. Detect the rising edge of the B-channel single-edge VS synchronization signal according to the sampling clock to generate the B-channel coordinate flag signal and the storage indication signal;

[0145] S34. Generate the B-channel image coordinate information according to the B-channel coordinate flag signal and the B-channel single-edge HS synchronization signal;

[0146] S35. Generate a write command according to the B-channel image coordinate information and the B-channel single-edge DE synchronization signal.

[0147] It should be noted that in practical applications, the implementation order of step S2 and step S3 can be swapped or carried out simultaneously, and the adjustment of the order does not affect the implementation of the stereoscopic image display method provided by this application. The technical solution after the order adjustment without violating the main idea of this application should also fall within the protection scope of this application.

[0148] S4. Store the B-channel single-edge data signal in YUV format in the write storage space according to the storage indication signal and the write command. Specifically, the write storage space can be RAM.

[0149] S5. Parse the read instruction and the write instruction to read the single-edge data signal of the B channel in YUV format stored in the write storage space to the read storage space via the DDR particles.

[0150] Specifically, in this embodiment, the implementation method of this step includes:

[0151] S51. Receive the write instruction and the read instruction;

[0152] S52. According to the first-in-first-out arbitration method, generate a read address signal and a read enable signal according to the write instruction;

[0153] S53. According to the read address signal and the read enable signal, read the data signal from the write storage space, and according to the address signal and the read / write command, send the read data signal to the DDR particles through the DDR physical layer;

[0154] S54. According to the first-in-first-out arbitration method, generate a write address signal and a write enable signal according to the read instruction;

[0155] S55. According to the address signal and the read / write command, read the data signal from the DDR particles through the DDR physical layer, and write the read data signal into the read storage space according to the write address signal and the write enable signal.

[0156] Specifically, in this embodiment, considering that the data signal in the read storage space needs to be converted from YUV format to RGB format subsequently, therefore, the read storage space needs to be divided into two independent RAMs to sequentially store the data signals of the B channel read out. As Figure 8 shown, the B-channel image data read out from the DDR particles is sequentially stored in order: sequentially stored in the lower bit txb_ram00 of the first RAM, the lower bit txb_ram10 of the second RAM, the upper bit rxb_ram01 of the first RAM, and the upper bit rxb_ram11 of the second RAM. The read data is read out in parallel with the same address according to the lower or upper bits of the two RAMs to the color gamut conversion unit for format conversion calculation.

[0157] S6. Convert the single-edge data signal of the A channel in YUV format to the image signal of the A channel in RGB888 format, and convert the single-edge data signal of the B channel in YUV format in the read storage space to the image signal of the B channel in RGB888 format.

[0158] Specifically, in practical applications, the method of converting the single-edge data signal of the A channel in YUV format to the image signal of the A channel in RGB888 format can be implemented by using the existing conventional format conversion method. Even, in order to reduce the calculation amount of color gamut conversion, the single-edge data signal of the A channel can not be converted.

[0159] For the conversion of the single-edge data signal of the B path, it is necessary to first obtain the initial coordinate position of the currently executed image row according to the image coordinate information of the A path; then, read the single-edge data signal of the B path two rows ahead of the currently executed image row, and then perform format conversion.

[0160] When converting the single-edge data signal of the B path to the RGB format, since the single-edge data signal of the B path is stored in the YUV format, that is, storing one YUV data is converted from the image data distributed on two rows of RGB, at least two rows of YUV420 images are required to calculate the corresponding two complete RGB image rows. The specific calculation formula is as follows. The YUV to RGB formula in the BT2020 protocol is used, where Cb corresponds to U and Cr corresponds to V:

[0161]

[0162]

[0163]

[0164] Since the calculation method of the stereoscopic image display system in this embodiment is implemented based on FPGA, therefore, both sides of the above formula can be multiplied by 256, and the decimal places in the formula can be removed, so that the FPGA can directly perform calculations.

[0165] Taking the conversion of the first pixel point to RGB888 as an example, as Figure 9 and Figure 10 shown, the pixel values stored in the first positions of txb_ram0 and txb_ram1 are read out simultaneously. The pixel information of the first row is stored in txb_ram0. Then, the first YUV pixel point of the first row is represented by Figure 10 shown Y00, U00, V10. Similarly, the first pixel point of the second row is represented by Y10, U00, V10, and so on. The first "RGB0" pixel value of the first row can be obtained through the logical operation of the FPGA. Similarly, the next pixel point to be calculated is the third YUV value "RGB2" of the first row.

[0166] S7. Determine whether the A-path image signal and the B-path image signal meet the preset conditions, and select to output the A-path image signal or the B-path image signal according to the judgment result.

[0167] Specifically, after performing color gamut conversion on both the single-edge data signal of path A and the single-edge data signal of path B, it can be determined whether the R-channel value, B-channel value, and G-channel value in the image signal of path B are all greater than the first preset channel threshold. If so, the image signal of path B is output. Otherwise, it is determined whether the R-channel value, B-channel value, and G-channel value in the image signal of path A are all greater than the second preset channel threshold. If so, the image signal of path A is output. Otherwise, the default blue background image is output.

[0168] If color gamut conversion is only performed on the single-edge data signal of path B, it can be determined whether the R-channel value, B-channel value, and G-channel value in the image signal of path B are all greater than the preset channel threshold. If so, the single-edge data signal of path B is output. Otherwise, the single-edge data signal of path A is output.

[0169] In a specific embodiment, the value of the preset channel threshold can be 50. Of course, in other embodiments, the value of the channel threshold can also be reasonably set according to actual needs, and the present application does not limit this.

[0170] S8, add synchronization information to the output image signal and then output the stereoscopic image signal.

[0171] In this embodiment, the image restoration unit can be used to add synchronization information to the output image signal. At this time, the format of the output image signal is still the YUV format. That is to say, the purpose of performing color gamut conversion in step S6 by the color gamut conversion unit is to achieve the judgment in step S7, but when outputting the image signal, the image signal in the YUV format is still selected for output to reduce the amount of data in the FPGA.

[0172] Moreover, in this embodiment, the image restoration unit generates external synchronization data of the valid image according to the image coordinate information, including HS, DE, and VS information, and at the same time restores the image data to 36 bits and outputs the stereoscopic image signal after aligning the synchronization information.

[0173] Finally, the stereoscopic image signal is output through an external high-definition video chip (HDMI chip), thereby displaying a stereoscopic effect.

[0174] The data format output by the HDMI chip used here converts the YUV420 36-bit TTL data into HDMI2.0 data that can be transmitted over a long distance.

[0175] The stereoscopic image display method based on FPGA provided in this embodiment receives two different image sources, divides them into an upper layer image and a lower layer background image, then overlaps the images according to the chromaticity value, selectively outputs the pixel points of the upper layer image, and uses the background image to replace the unselected part, thereby achieving a stereoscopic effect. At the same time, the data processing part uses the YUV format, thereby effectively compressing the amount of data and realizing low-cost stereoscopic image display.

[0176] The stereoscopic image display method based on FPGA provided in this embodiment uses the clock of the A-channel image for both input and output as the reference clock of the system, making it easier for the product to converge in timing and run at a faster rate. It can easily achieve dual-channel image display with a resolution of 2K and a frame rate of 144fps or a display of 4K at 60Hz. If the DDR performance is further improved or a higher-grade FPGA is used, a display of 4K at 144Hz can also be achieved. This system is applicable to application scenarios with extremely high requirements for the refresh rate. In addition, this system is based on FPGA, reducing the internal logic circuit of the FPGA, thereby reducing the power consumption of the system, and the highly integrated functional modules are conducive to the long-term maintenance of the product.

[0177] The stereoscopic image display method based on FPGA provided in this embodiment reads the B-channel image data read from the DDR particles by using 2 blocks of RAM for cross-storage in the read storage space. At the same time, data is read in advance according to the synchronization information of the A-channel image, saving the space cost of storing this channel of image in the DDR and avoiding the asynchronous timing caused by using the local clock, resulting in a situation where the output frame rate is not high. In addition, the converted RGB format data is only used for the judgment of the output image signal, and the YUV format is still used during transmission, thereby avoiding the image color error during the transmission of RGB data and improving the display effect of the stereoscopic image.

[0178] The stereoscopic image display method based on FPGA provided in this embodiment is different from the prior art in that it uses the built-in DDR particles of the FPGA, reducing the external circuit design process for users and lowering the debugging cost and circuit development cost. In addition, users can also create the text to be displayed by themselves to implement the function of watermark, or add some dynamic drawing effects on the basis of the original background image to enhance the visual appeal of the original image.

[0179] It should be noted that the various embodiments in this specification are described in a progressive manner. The key points of each embodiment are the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. In addition, the different parts between the various embodiments can also be combined and used, and the present invention does not limit this.

[0180] The stereoscopic image display system and method based on FPGA provided by this embodiment include: an acquisition module, configured to receive an A-channel image source signal and a B-channel image source signal, and respectively perform sampling processing on the A-channel image source signal and the B-channel image source signal to obtain an A-channel single-edge data signal in YUV format and a B-channel single-edge data signal in YUV format; a processing module, configured to store the B-channel single-edge data signal into a DDR particle, and use the clock of the A-channel single-edge data signal as a reference clock to read the B-channel single-edge data signal in the DDR particle, and then perform image coincidence processing on the A-channel single-edge data signal and the B-channel single-edge data signal according to the chrominance value to obtain a fused stereoscopic image signal; an output module, configured to output the stereoscopic image signal to display a stereoscopic image. By performing sampling processing on the image source signal to obtain a single-edge data signal in YUV format, the frequency of the image data becomes lower and the bit width becomes larger, which is beneficial to giving play to the advantage of the FPGA in processing parallel data. At the same time, the amount of image data is reduced by half compared with the RGB format, thus effectively saving the internal storage resources of the FPGA; by storing the B-channel single-edge data signal into the DDR particle and using the clock of the A-channel single-edge data signal as a reference clock to read the data in the DDR particle, not only can the space cost of storing the image into the DDR be saved, but also the resolution information of the image source signal can be automatically recognized more efficiently, avoiding asynchronous timing caused by using a local clock, improving the image frame rate, thereby improving the clarity of the stereoscopic image display, and solving the problems of large storage resource occupation and low display clarity in the existing FPGA-based stereoscopic image display technology.

[0181] The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention according to the above disclosure shall fall within the protection scope of the claims.

Claims

1. A 3D image display system based on FPGA, characterized in that: include: An acquisition module is used to receive an A-channel image source signal and a B-channel image source signal, and sample and process the A-channel image source signal and the B-channel image source signal to obtain an A-channel single-edge data signal in a YUV format and a B-channel single-edge data signal in a YUV format; A processing module is used to store the B-channel single-edge data signal in the DDR particle, and use the clock of the A-channel single-edge data signal as the reference clock to read the B-channel single-edge data signal in the DDR particle, and then perform image overlap processing on the A-channel single-edge data signal and the B-channel single-edge data signal according to the chrominance value to obtain a fused stereoscopic image signal, which includes: converting the A-channel single-edge data signal in the YUV format into the A-channel image signal in the RGB format, and converting the B-channel single-edge data signal in the YUV format into the B-channel image signal in the RGB format; judging whether the R channel value, the B channel value and the G channel value in the B-channel image signal are all greater than the first preset channel threshold value, if so, outputting the B-channel image signal, otherwise, judging whether the R channel value, the B channel value and the G channel value in the A-channel image signal are all greater than the second preset channel threshold value, if so, outputting the A-channel image signal, otherwise outputting a default blue background image; receiving the output image signal, and outputting the stereoscopic image signal after adding synchronization information to the image signal; The output module is used to output a stereoscopic image signal to display a stereoscopic image.

2. The FPGA-based stereoscopic image display system according to claim 1, characterized in that: The acquisition module includes an A-channel image source acquisition unit and a B-channel image source acquisition unit; The A-channel image source acquisition unit is used to acquire the A-channel image source signal, and perform sampling processing on the A-channel image source signal to generate the A-channel single-edge data signal, the A-channel synchronization signal and the A-channel image coordinate information in the YUV format; The B-channel image source acquisition unit is used to acquire the B-channel image source signal, and sample and process the B-channel image source signal to generate a B-channel single-edge data signal in YUV format, a storage indication signal and a write instruction, so as to store the B-channel single-edge data signal in YUV format in the write storage space according to the storage indication signal and the write instruction.

3. The FPGA-based stereoscopic image display system according to claim 2, characterized in that: The A-channel image source signal includes an A-channel image data signal, an A-channel DE synchronization signal, an A-channel VS synchronization signal and an A-channel HS synchronization signal; the A-channel image source acquisition unit includes an A-channel image data processing circuit and an A-channel synchronization signal processing circuit; The A-channel image data processing circuit is used to convert the A-channel image data signal from a double-edge data signal to a clock single-edge data signal by using IDDR, and then perform splicing processing to obtain the A-channel single-edge data signal in YUV format; The A-channel synchronization signal processing circuit is used to use IDDR to convert the A-channel DE synchronization signal, the A-channel VS synchronization signal and the A-channel HS synchronization signal from double-edge data signals to clock single-edge data signals, and then perform OR operations on them to obtain the A-channel single-edge DE synchronization signal, the A-channel single-edge VS synchronization signal and the A-channel single-edge HS synchronization signal respectively; it is also used to generate the A-channel coordinate mark signal according to the A-channel single-edge VS synchronization signal, and generate the A-channel image coordinate information according to the A-channel coordinate mark signal and the A-channel single-edge HS synchronization signal.

4. The FPGA-based stereoscopic image display system according to claim 2, characterized in that: The B-channel image source signal includes a B-channel image data signal, a B-channel DE synchronization signal, a B-channel VS synchronization signal and a B-channel HS synchronization signal; the B-channel image source acquisition unit includes a B-channel image data processing circuit and a B-channel synchronization signal processing circuit; The B-channel image data processing circuit is used to convert the B-channel image data signal from a double-edge data signal to a clock single-edge data signal by using IDDR, and then perform splicing processing to obtain the B-channel single-edge data signal in YUV format; The B-channel synchronization signal processing circuit is used to use IDDR to convert the B-channel DE synchronization signal, the B-channel VS synchronization signal and the B-channel HS synchronization signal from double-edge data signals to clock single-edge data signals, and then perform OR operation processing to obtain the B-channel single-edge DE synchronization signal, the B-channel single-edge VS synchronization signal and the B-channel single-edge HS synchronization signal respectively; it is also used to generate a B-channel coordinate flag signal and a storage indication signal according to the B-channel single-edge VS synchronization signal, generate B-channel image coordinate information according to the B-channel coordinate flag signal and the B-channel single-edge HS synchronization signal, and generate a write instruction according to the B-channel image coordinate information and the B-channel single-edge DE synchronization signal.

5. The FPGA-based stereoscopic image display system according to claim 2, characterized in that: The processing module includes an image recovery unit, a storage control unit and a color gamut conversion unit; The image recovery unit is used to recover the image synchronization information and the bit width of the image data according to the A-channel image coordinate information, and generate a read instruction at the same time; The storage control unit is used to parse the write instruction and the read instruction to read the B-path single-edge data signal in the YUV format stored in the write storage space into the read storage space; The color gamut conversion unit is used to convert the A-channel single-edge data signal in the YUV format generated by the A-channel image source acquisition unit into the A-channel image signal in the RGB format, and convert the B-channel single-edge data signal in the YUV format in the read storage space into the B-channel image signal in the RGB format; and is also used to determine whether the A-channel image signal and the B-channel image signal meet a preset condition, and select to output the A-channel image signal or the B-channel image signal according to the determination result; The image restoration unit is further used to receive the image signal output by the color gamut conversion unit, and output a stereoscopic image signal after adding synchronization information to the image signal.

6. The FPGA-based stereoscopic image display system according to claim 2, characterized in that: The storage control unit includes a command arbitration circuit, a read and write data state machine, a control signal generation circuit, a memory controller and a DDR physical layer; The command arbitration circuit is used to receive a write instruction and a read instruction, and start the read / write data state machine according to the write instruction or the read instruction in a first-in-first-out arbitration manner; The read / write data state machine is used to generate address information and read / write commands for controlling the DDR physical layer according to a write instruction or a read instruction; The control signal generating circuit is used to generate a read address signal and a read enable signal according to a write instruction; It is also used to generate a write address signal and a write enable signal according to a read instruction; The memory controller is used to send data signals in the write storage space to the DDR particles through the DDR physical layer using address signals, read and write commands, read address signals and read enable signals; and is also used to read data signals from the DDR particles through the DDR physical layer and write them into the read storage space using address signals, read and write commands, write address signals and write enable signals.

7. A 3D image display method based on FPGA, applied to the 3D image display system based on FPGA as claimed in any one of claims 1 to 6, characterized in that: The FPGA-based stereoscopic image display method comprises: Respectively receive channel A image source signal and channel B image source signal; Obtain the A-channel single-edge data signal in YUV format from the A-channel image source signal, and generate the A-channel image coordinate information and read instruction; Obtaining a B-channel single-edge data signal in a YUV format from a B-channel image source signal, and generating a storage indication signal and a write instruction; The B-channel single-edge data signal in the YUV format is stored in the write storage space according to the storage indication signal and the write instruction; Parse the read instruction and the write instruction to read the B-channel single-edge data signal in the YUV format stored in the write storage space into the read storage space via the DDR particles; Convert the single-edge data signal of A channel in YUV format into the image signal of A channel in RGB888 format, and convert the single-edge data signal of B channel in YUV format in the read storage space into the image signal of B channel in RGB888 format; Determine whether the A-channel image signal and the B-channel image signal meet the preset conditions, and select to output the A-channel image signal or the B-channel image signal according to the determination result; After adding synchronization information to the output image signal, a stereoscopic image signal is output.

8. The FPGA-based stereoscopic image display method according to claim 7, characterized in that: The method of obtaining a single-edge data signal of channel A in a YUV format from a channel A image source signal and generating the coordinate information of channel A image comprises: By using IDDR, the A-channel image data signal is converted from a double-edge data signal to a clock single-edge data signal, and then spliced ​​to obtain the A-channel single-edge data signal in YUV format; By using IDDR, the A-channel DE synchronization signal, the A-channel VS synchronization signal and the A-channel HS synchronization signal are respectively converted from double-edge data signals to clock single-edge data signals, and then respectively processed by OR operation to obtain the A-channel single-edge DE synchronization signal, the A-channel single-edge VS synchronization signal and the A-channel single-edge HS synchronization signal; Detect the rising edge of the single-edge VS synchronization signal of channel A according to the sampling clock to generate a coordinate mark signal of channel A; The A-channel image coordinate information is generated according to the A-channel coordinate mark signal and the A-channel single-edge HS synchronization signal.

9. The FPGA-based stereoscopic image display method according to claim 7, characterized in that: The method for obtaining a B-channel single-edge data signal in a YUV format from a B-channel image source signal and generating a storage indication signal and a write instruction comprises: Using IDDR, the B-channel image data signal is converted from a double-edge data signal to a clock single-edge data signal, and then spliced ​​to obtain a B-channel single-edge data signal in a YUV format; By using IDDR, the B-channel DE synchronization signal, the B-channel VS synchronization signal and the B-channel HS synchronization signal are respectively converted from double-edge data signals to clock single-edge data signals, and then respectively processed by OR operation to obtain the B-channel single-edge DE synchronization signal, the B-channel single-edge VS synchronization signal and the B-channel single-edge HS synchronization signal; Detect the rising edge of the single-edge VS synchronization signal of the B-way according to the sampling clock to generate the B-way coordinate mark signal and the storage indication signal; Generate B-channel image coordinate information according to the B-channel coordinate mark signal and the B-channel single-edge HS synchronization signal; Generate a write instruction based on the B-channel image coordinate information and the B-channel single-edge DE synchronization signal.

10. The FPGA-based stereoscopic image display method according to claim 7, characterized in that: The method for parsing the read instruction and the write instruction to read the B-path single-edge data signal in the YUV format stored in the write storage space into the read storage space via the DDR particles includes: Receive write instructions and read instructions; According to the first-in-first-out arbitration method, a read address signal and a read enable signal are generated according to the write instruction; Read the data signal from the write storage space according to the read address signal and the read enable signal, and send the read data signal to the DDR particle through the DDR physical layer according to the address signal and the read and write command; According to the first-in-first-out arbitration method, a write address signal and a write enable signal are generated according to the read instruction; According to the address signal and the read / write command, the data signal is read from the DDR particle through the DDR physical layer, and according to the write address signal and the write enable signal, the read data signal is written into the read storage space.

11. The FPGA-based stereoscopic image display method according to claim 8, characterized in that: Before converting the A-channel single-edge data signal in the YUV format into the A-channel image signal in the RGB888 format, the FPGA-based stereoscopic image display method further includes: Obtain the initial coordinate position of the currently executed image row according to the image coordinate information of path A; Read the B-channel single-edge data signal 2 lines ahead of the currently executed image line.

12. The FPGA-based stereoscopic image display method according to claim 7, characterized in that: The method of judging whether the A-channel image signal and the B-channel image signal meet preset conditions and selecting to output the A-channel image signal or the B-channel image signal according to the judgment result comprises: Determine whether the R channel value, B channel value and G channel value in the B-channel image signal are all greater than the first preset channel threshold. If so, output the B-channel image signal. Otherwise, determine whether the R channel value, B channel value and G channel value in the A-channel image signal are all greater than the second preset channel threshold. If so, output the A-channel image signal. Otherwise, output the default blue background image.

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