Ramp signal generator, and image sensor and electronic device including the same

Abstract

The invention provides a ramp signal generator, and an image sensor and an electronic device including the same. The ramp signal generator includes: a resistor connected between an output node outputting a ramp signal that increases or decreases at a constant slope and a first power supply node receiving a first power supply voltage; and a plurality of current units. A cell current flows through each of the plurality of current cells and to a first power supply node or a resistor. The plurality of current cells includes a first current cell. The first current cell includes: a first transistor connected between the first switching node and the output node through which the cell current flows to the resistor; a second transistor connected between the first switching node and a first power supply node through which the cell current flows to the first power supply node; and a negative feedback circuit maintaining a constant voltage at the first switching node.

Description

[0001] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0132704 filed on October 5, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] Apparatus and devices consistent with the present disclosure relate to a semiconductor circuit, and more particularly, to a ramp signal generator generating a ramp signal whose level increases or decreases at a specific slope, and an image sensor and an electronic device including the ramp signal generator. Background Art

[0003] A ramp signal is a signal whose level increases or decreases at a constant slope. An electronic device can detect data using a ramp signal. For example, in an image sensor, an analog-to-digital converter can convert a pixel signal into a digital value by sampling a pixel signal generated in response to a photocharge generated by a photosensitive device on a ramp signal. The linearity of the ramp signal is essential for the accuracy of data detection. Summary of the invention

[0004] One aspect is to provide a ramp signal generator having improved integral nonlinearity (INL) performance, and an image sensor and an electronic device including the same.

[0005] According to one aspect of one or more embodiments, a ramp signal generator is provided, the ramp signal generator comprising: a resistor connected between an output node outputting a ramp signal increasing or decreasing at a constant slope and a first power supply node configured to receive a first power supply voltage; and a plurality of current cells, each of which a cell current flows to the first power supply node or the resistor, the plurality of current cells including at least one first current cell. The at least one first current cell comprises: a first transistor connected between a first switch node and an output node, the cell current flows to the resistor through the first transistor; a second transistor connected between the first switch node and the first power supply node, the cell current flows to the first power supply node through the second transistor; and a negative feedback circuit, which maintains a constant voltage at the first switch node by controlling the gate terminal of the first transistor based on the voltage of the first switch node.

[0006] According to another aspect of one or more embodiments, an image sensor is provided, the image sensor comprising: a pixel array comprising a plurality of pixels; a ramp signal generating circuit configured to generate a ramp signal, the level of the ramp signal decreasing at a constant slope; and an analog-to-digital conversion circuit configured to convert a pixel signal provided from the pixel array into a pixel value based on the ramp signal. The ramp signal generating circuit comprises: a load resistor connected between a ground and an output node, the ramp signal being output to the output node, and a plurality of current cells, each of which provides a cell current to the load resistor during a reset period and provides the cell current to the ground during a set period. Each of the plurality of current cells comprises: a first transistor connected between a switch node and an output node, the cell current flowing to the load resistor through the first transistor, a second transistor connected between the switch node and the ground, the cell current flowing to the ground through the second transistor, and a negative feedback circuit, which controls a gate terminal of the first transistor based on a voltage of the switch node so that the first transistor operates in a saturation region.

[0007] According to another aspect of one or more embodiments, there is provided an electronic device, the electronic device comprising: a ramp signal generator, comprising a plurality of current cells and a load resistor, the ramp signal generator being configured to control the plurality of current cells to reduce the amount of current flowing through the load resistor, and generating a ramp signal, the level of the ramp signal increasing or decreasing at a specific slope; and a main circuit, configured to perform at least one predefined function by detecting data based on the ramp signal. Each of the plurality of current cells comprises: a first transistor connected between a switch node and an output node, through which a cell current flows to the load resistor during a reset period, a second transistor connected between the switch node and ground, through which the cell current flows to the ground during a set period, and a negative feedback circuit, which controls a gate terminal of the first transistor based on a voltage of the switch node so that the first transistor operates in a saturation region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Various embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram illustrating an image sensor according to an embodiment.

[0010] Figure 2 is a circuit diagram showing a ramp signal generator according to an embodiment.

[0011] Figure 3A and Figure 3B is a circuit diagram showing a current cell according to an embodiment.

[0012] Figure 4Ais a diagram showing a logic circuit for generating a control signal provided to a current cell according to an embodiment, and Figure 4B is a timing diagram of control signals according to an embodiment.

[0013] Figure 5A and Figure 5B are circuit diagrams illustrating operations in a reset phase and a set phase, respectively, of a current cell according to some embodiments.

[0014] Figure 6 is a circuit diagram showing a current cell according to a comparative example.

[0015] Fig. 7A is a circuit diagram showing the operation of a ramp signal generator including a current unit according to a comparative example, and Figure 7B is a timing diagram of a ramp signal of a voltage and current unit of a switch node according to a comparative example.

[0016] Fig. 8A is a circuit diagram showing a negative feedback loop according to an embodiment when a current unit according to an embodiment operates in a reset phase, and Figure 8B is a timing diagram of a ramp signal of a voltage and current unit of a switch node according to an embodiment.

[0017] Fig.9A and Fig. 9B Graphs comparing changes in integral nonlinearity (INL) characteristics of a current cell according to an embodiment and a current cell according to a comparative example, respectively.

[0018] Fig.10 is a circuit diagram showing a current cell according to an embodiment.

[0019] Fig.11 is a circuit diagram showing a current cell according to an embodiment.

[0020] Fig.12 is a circuit diagram showing a ramp signal generator according to an embodiment.

[0021] Fig.13 is a schematic block diagram of an electronic device according to an embodiment.

[0022] Fig.14 is a block diagram schematically illustrating an electronic device including an image sensor according to an embodiment. DETAILED DESCRIPTION

[0023] Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings.

[0024] Figure 1 is a block diagram showing an image sensor 100 according to an embodiment.

[0025] Reference Figure 1 , the image sensor 100 may be installed in an electronic device having an image or light sensing function. For example, the image sensor 100 may be installed on an electronic device such as a camera, a smart phone, a wearable device, an Internet of Things (IoT) device, a home appliance, a tablet personal computer (tablet PC), a personal digital assistant (PDA), a portable multimedia player (PMP), a navigation, a drone, an advanced driver assistance system (ADAS), etc. In some embodiments, the image sensor 100 may be installed on an electronic device provided as a component in a vehicle, furniture, a manufacturing facility, a door, various measuring devices, etc.

[0026] Reference Figure 1 , the image sensor 100 may include a pixel array 110, a row driver 120, an analog-to-digital conversion (ADC) circuit 130, a ramp signal generator 140, a data bus 160, a timing controller 170, and a signal processor 180. The row driver 120, the ADC circuit 130, and the ramp signal generator 140 may be referred to as a readout circuit.

[0027] The pixel array 110 includes a plurality of row lines RL, a plurality of column lines CL, and a plurality of pixels PX connected to the plurality of row lines RL and the plurality of column lines CL and arranged in rows and columns. In some embodiments, the plurality of pixels PX may be active pixel sensors (APS).

[0028] In one embodiment, the pixels PX arranged in the same column may be connected to the same column line CL. However, the embodiment is not limited thereto, and the pixels PX arranged in the same column may be connected to different column lines CL according to the arrangement of the pixels PX. Each pixel PX may output a pixel signal PXS (e.g., a pixel voltage) through the corresponding column line CL.

[0029] Each pixel PX can detect light using a photoelectric conversion device and output an image signal as an electrical signal according to the detected light. The photoelectric conversion device may be a light sensing device made of an organic material or an inorganic material (such as a photodiode (inorganic photodiode), an organic photo film, a perovskite photodiode, a phototransistor, a photogate, or a pinned photodiode). Hereinafter, a photodiode as a photoelectric conversion element will be described as an example.

[0030] A microlens for focusing light may be arranged above each of the plurality of pixels PX, or above each of the pixel groups consisting of adjacent pixels PX. A color filter for emitting light in a specific spectral region may be arranged above each of the plurality of pixels PX, and each of the plurality of pixels PX may detect light in a specific spectral region from light received through the microlens based on the corresponding color filter. For example, the pixel array 110 may include a red pixel for converting light in a red spectral region into an electrical signal, a green pixel for converting light in a green spectral region into an electrical signal, and a blue pixel for converting light in a blue spectral region into an electrical signal. However, embodiments are not limited thereto, and the pixel array 110 may further include white pixels, or the pixel array 110 may include pixels according to different color combinations (such as cyan pixels, yellow pixels, green pixels, and magenta pixels).

[0031] In one embodiment, the pixel PX may operate in a plurality of conversion gain modes. For example, the pixel PX may operate in a high conversion gain (HCG) mode and may operate in a low conversion gain (LCG) mode. The pixel PX may output an HCG pixel signal (reset signal and image signal) in the HCG mode and may output an LCG pixel signal (reset signal and image signal) in the LCG mode.

[0032] In one embodiment, the pixel PX may operate in the HCG mode under a low illumination environment and in the LCG mode under a high illumination environment. In one embodiment, the pixel PX may operate in the HCG mode in a first frame and in the LCG mode in a second frame continuous with the first frame. In one embodiment, the pixel PX may operate in the HCG mode and the LCG mode in a time-division manner within one frame.

[0033] In one embodiment, the pixel PX may include a plurality of photodiodes (eg, a first photodiode and a second photodiode). The light receiving regions of the plurality of photodiodes may be the same or different. In one embodiment, the pixel PX may have a pixel structure in which the plurality of photodiodes share a floating diffusion node.

[0034] The row driver 120 drives the pixel array 110 in units of one row or a plurality of rows. The row driver 120 may decode a row control signal (e.g., a row address) received from the timing controller 170, and select at least one row to be read out from among a plurality of rows of the pixel array 110 in response to the decoded row control signal.

[0035] The row driver 120 may provide a control signal (e.g., a selection signal, a transfer control signal, a conversion control signal, a switch signal, etc.) to the selected at least one row through the row line RL. The pixels PX included in the pixel row selected by the selection signal provided from the row driver 120 output pixel signals (e.g., pixel voltages).

[0036] The ramp signal generator 140 (also referred to as a ramp signal generating circuit) may generate a ramp signal RAMP (or a ramp voltage) whose level increases (rises) or decreases (falls) at a constant slope. The slope of the ramp signal RAMP may vary according to the analog gain setting. The ramp signal RAMP may be provided to the ADC circuit 130 as a reference voltage.

[0037] The ramp signal generator 140 according to an embodiment may include a plurality of current units and load resistors (see Figure 2 ). The ramp signal generator 140 may also include a bias circuit (not shown) for driving a plurality of current cells. Each of the plurality of current cells may generate a cell current, flow the cell current to a load resistor, or flow the cell current to a first power supply node to which a first power supply voltage (e.g., a ground voltage) is provided. The plurality of current cells may include a switching transistor configured to provide the cell current to the load resistor. In some embodiments, the plurality of current cells may include a negative feedback circuit configured to constantly maintain the voltage of the switching node by controlling the gate voltage of the switching transistor based on the voltage of the first terminal of the switching transistor (e.g., the voltage of the switching node), so that the switching transistor operates in a saturation region. In one embodiment, the negative feedback circuit may be implemented as a single-stage amplifier. Since the switching transistor always operates in the saturation region, the voltage of the switching node may not be changed even if the voltage of the output node from which the ramp signal is output changes. Details of the ramp signal generator 140 will be referred to later. Figures 2 to 12 is described.

[0038] The ADC circuit 130 may convert a plurality of pixel signals PXS (e.g., a plurality of pixel voltages) provided from the pixel array 110 into a plurality of pixel values ​​based on the ramp signal RAMP provided from the ramp signal generator 140. The ADC circuit 130 may include a plurality of comparators (COMP) 131 and a plurality of counters (CNT) 132. In one embodiment, the ADC circuit 130 may further include a plurality of buffers (not shown) for buffering the ramp signal RAMP.

[0039] The ADC circuit 130 may convert each of the plurality of pixel signals PXS into a pixel value in a correlated double sampling (CDS) method, and the plurality of comparators (COMP) 131 may be referred to as a CDS circuit. Each of the plurality of comparators (COMP) 131 may compare the pixel signal PXS received through the column line CL with the ramp signal RAMP and output a comparison result signal. When the ramp signal RAMP whose level decreases at a certain slope becomes the same as the pixel signal PXS or is less than the pixel signal PXS, the comparator (COMP) 131 may output a comparison result signal transitioning from a first level (e.g., logic high) to a second level (e.g., logic low).

[0040] The comparator (COMP) 131 may sample and hold a reset signal provided from the pixel PX according to a correlated double sampling (CDS) method, and may sample a signal obtained by adding the reset signal received from the pixel PX to the image signal. The comparator (COMP) 131 may output a first comparison result signal corresponding to the reset signal, and may output a second comparison result signal corresponding to the image signal.

[0041] The counter (CNT) 132 may generate a pixel signal obtained by subtracting a reset signal from the image signal by counting a period until a time point at which the comparison result signal output from the comparator (COMP) 131 transitions from a first level to a second level. In one embodiment, the counter (CNT) 132 may generate a reset value by counting the first comparison result signal, generate an image value by counting the second comparison result signal, and generate a pixel value PXD by subtracting the reset value from the image value.

[0042] The data bus 160 may temporarily store the pixel value PXD received from the ADC circuit 130, and then output the pixel value PXD to the signal processor 180 (or an external device of the image sensor 100, for example, an application processor). In one embodiment, the data bus 160 may provide the pixel value to the signal processor 180 in units of at least one row of the pixel array 110. The data bus 160 may include a plurality of column memories and a column decoder, and the plurality of pixel values ​​stored in the plurality of column memories may be output as the image data IDTA under the control of the column decoder.

[0043] The timing controller 170 may control the operation and operation timing of the row driver 120 , the ADC circuit 130 , the ramp signal generator 140 , and the data bus 160 by outputting a timing control signal to each of the row driver 120 , the ADC circuit 130 , the ramp signal generator 140 , and the data bus 160 .

[0044] The signal processor 180 may perform image processing on the received image data IDTA. For example, the signal processor 180 may change the data pattern of the pixel values ​​of the received image data IDTA (e.g., change the original data into a red, green, blue (RGB) pattern), or perform signal processing (such as one or more of noise reduction processing, gain control, waveform shaping processing, interpolation processing, white balance processing, gamma processing, edge emphasis processing, merging, reduction, image quality compensation, etc.) on the received image data IDTA. Image quality compensation may include signal processing (such as one or more of black level compensation, lens shading compensation, crosstalk compensation, and bad pixel compensation). In one embodiment, the signal processor 180 may generate a high dynamic range (HDR) image by merging first image data and second image data having different brightness.

[0045] The image data IDTA processed by the image signal processor 180 may be sent to an external processor. For example, the external processor may be a host processor of an electronic device on which the image sensor 100 is mounted. For example, the external processor may be an application processor of a mobile terminal. The image sensor 100 may send the image data IDTA to the external processor according to a data communication method based on a set interface (e.g., a mobile industry processor interface (MIPI)). The external processor may perform image processing on the received image data IDTA. In one embodiment, the external processor may receive first image data and second image data having different brightness as the image data IDTA, and generate an HDR image by merging the first image data and the second image data.

[0046] When the switching transistor operates in the triode region at the beginning of the ramp period in which the ramp signal generator 140 performs the ramp operation, the voltage of the switch node may change according to the change of the ramp signal, and the change of the voltage of the switch node may cause an error in the ramp signal, thereby degrading the integral nonlinearity (INL) characteristic of the ramp signal. In other words, the linearity of the ramp signal may be degraded at the beginning of the ramp period.

[0047] However, in the ramp signal generator 140 according to some embodiments, even at the beginning of the ramp period, the switch transistor of the current unit operates in the saturation region, so that even if the ramp signal changes, the voltage of the switch node does not change. Therefore, the INL characteristic of the ramp signal can be improved. Since the INL characteristic of the ramp signal is improved, even if the image sensor 100 operates at a high speed, the degradation of the image quality of the generated image can be prevented.

[0048] Figure 2 is a circuit diagram showing the ramp signal generator 140 according to an embodiment.

[0049] Reference Figure 2, the ramp signal generator 140 may include a plurality of current units 10 and a load resistor R L The ramp signal generator 140 may further include a bias circuit that provides a bias voltage for driving the plurality of current cells 10 .

[0050] Load resistor R L can be connected to the output node N from which the ramp signal RAMP is output O The first power supply node N P1 The first power supply voltage VSS may be applied to the first power supply node N P1 In one embodiment, the first power supply voltage VSS may be a ground voltage, and the first power supply node N P1 May be referred to as ground or ground node.

[0051] The plurality of current cells 10 may include current cells 10_1 to 10_N, where N is a positive integer equal to or greater than 5, and the current cells 10_1 to 10_N may generate the same cell current. Each of the current cells 10_1 to 10_N may include a current source CS and a switch element SD. Each of the plurality of current cells 10 may be connected to a first power supply node N P1 , the second power supply node N P2 and output node N O A second power supply voltage (or positive power supply voltage) VDDA different from the first power supply voltage VSS may be applied to the second power supply node N P2 In one embodiment, the second power supply voltage VDDA may be higher than the first power supply voltage VSS. Hereinafter, description will be made under the assumption that the second power supply voltage VDDA is higher than the first power supply voltage VSS (eg, ground voltage). However, the embodiment is not limited thereto, and in some embodiments, the first power supply node N P1 The voltage of the second power supply node N P2 In the following description, in the case where there is no need to distinguish the amount of the corresponding current cells among the current cells 10_1 to 10_N, the current cell will be referred to as the current cell 10 .

[0052] The switching element SD may provide the cell current generated in the current cell 10 to the load resistor R L or the first power supply node N P1 The switch element SD may be implemented using at least two transistors. For example, one of the at least two transistors may be turned on to provide the cell current to the load resistor R L , and the other of the at least two transistors may be turned on to supply the cell current to the first power supply node N P1 The current cell 10 may provide the cell current to the load resistor R during the reset phase (or reset period). L, and the cell current may be supplied to the first power supply node N during the set phase (or set period) P1 .

[0053] The current source CS may generate a cell current or a bias current for generating the cell current.

[0054] When the ramp signal generator 140 performs the ramp operation, the plurality of current cells 10 may be sequentially changed from the reset phase to the set phase, and thus, the current flowing through the load resistor R L The amount of current can be reduced, thereby reducing the level of the ramp signal RAMP.

[0055] According to the embodiment (see Figure 3A and Figure 3B ), at least one of the plurality of current cells 10 may be implemented as a first current cell, and the first current cell may include a negative feedback circuit for maintaining a constant voltage of a switch node. In some embodiments, all of the plurality of current cells 10 may be implemented as a first current cell.

[0056] Figure 3A and Figure 3B is a circuit diagram showing a first current unit according to an embodiment.

[0057] Reference Figure 3A , the first current unit 20 may include a current source CS, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, and a plurality of switches (e.g., including a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4). In one embodiment, the first transistor T1 to the fourth transistor T4 may be implemented as (or include) a P-type transistor (e.g., a P-type metal oxide semiconductor field effect transistor (MOSFET)). In one embodiment, the first switch SW1 to the fourth switch SW4 may be implemented as a transistor. For example, Figure 3B As shown in , the first switch SW1 and the second switch SW2 may be implemented with P-type transistors, and for example, may be implemented with the seventh transistor T7 and the eighth transistor T8, respectively; the third switch SW3 and the fourth switch SW4 may be implemented with N-type transistors, and for example, may be implemented by the fifth transistor T5 and the sixth transistor T6, respectively. However, the embodiment is not limited thereto, and in some embodiments, the first switch SW1 and the second switch SW2 may be implemented as N-type transistors, and the third switch SW3 and the fourth switch SW4 may be implemented as P-type transistors. In one embodiment, the first switch SW1 to the fourth switch SW4 may be implemented as transmission gates.

[0058] In the following, reference is made to Figure 3BAs described above, it is assumed that the first switch SW1 and the second switch SW2 are implemented as P-type transistors, and the third switch SW3 and the fourth switch SW4 are implemented as N-type transistors.

[0059] The first transistor T1 and the second transistor T2 may be referred to as a first switching transistor and a second switching transistor, respectively. The first transistor T1 is connected to a switching node N SW With output node N O and can be turned on to provide the cell current to the load resistor R L For example, the first transistor T1 may be turned on to allow the cell current to flow to the resistor R L , so that the cell current flows through the first transistor T1 to the resistor R L The second transistor T2 is connected to the switch node N SW The first power supply node N P1 and can be turned on to provide the cell current to the first power supply node N P1 (ie, ground). For example, the second transistor T2 may be turned on to allow the cell current to flow directly to the first power node N P1 , so that the cell current flows to the first power supply node N through the second transistor T2 P1 .

[0060] The third transistor T3 may be referred to as a bias transistor and may be connected to the second power supply node N P2 With switch node N SW The second power supply voltage VDDA may be applied to the first terminal of the third transistor T3. In other words, the first terminal of the third transistor T3 may be configured to receive the second power supply voltage VDDA. The third transistor T3 may generate a cell current I based on the bias voltage VB. CELL .

[0061] The fifth transistor T5 to the eighth transistor T8 are control transistors for controlling the first transistor T1 and the second transistor T2. The fifth transistor T5 is connected to the second power supply node N P2 The fifth transistor T5 may be turned on or off in response to the first control signal SLB. The fifth transistor T5 may be turned on in response to the first control signal SLB of a first level (e.g., a low level) to apply the second power supply voltage VDDA to the gate terminal of the first transistor T1. The first transistor T1 may be turned off in response to the second power supply voltage VDDA applied to its gate terminal.

[0062] The sixth transistor T6 is connected to the second power supply node N P2The sixth transistor T6 is connected between the gate terminal of the second transistor T2 and the gate terminal of the second transistor T2, and can be turned on or off in response to the second control signal SL. The second control signal SL is a complementary signal of the first control signal SLB. The sixth transistor T6 can be turned on in response to the second control signal SL of the first level (e.g., low level) to apply the second power supply voltage VDDA to the gate terminal of the second transistor T2. The second transistor T2 can be turned off in response to the second power supply voltage VDDA applied to its gate terminal.

[0063] The seventh transistor T7 is connected to the bias node N B The seventh transistor T7 may be turned on or off in response to the first control signal SLB of the second level (eg, high level) to bias the bias node N1. B The voltage of the bias node N is provided to the gate terminal of the first transistor T1. The first transistor T1 may be based on the bias node N B The voltage is turned on to transfer the cell current I CELL Provided to the load resistor R L .

[0064] The eighth transistor T8 is connected to the bias node N B The eighth transistor T8 is connected between the gate terminal of the second transistor T2 and the gate terminal of the second transistor T2, and can be turned on or off in response to the second control signal SL. The eighth transistor T8 can be turned on in response to the second control signal SL of the second level (eg, high level) to bias the bias node N B The voltage of the bias node N is provided to the gate terminal of the second transistor T2. The second transistor T2 can be based on the bias node N B The voltage is turned on to transfer the cell current I CELL Provided to the first power supply node N P1 .

[0065] The fourth transistor T4 and the current source CS may operate as a single-stage amplifier. The fourth transistor T4 may be connected to the second power supply node N P2 With bias node N B and its gate terminal can be connected to the switch node N SW The current source CS is connected to the bias node N B The first power supply node N P1 In some embodiments, the fourth transistor T4 and the current source CS operating as a single-stage amplifier are based on the switch node N SW In some embodiments, the voltage of the bias node N B The voltage of may be provided to the gate terminal of the first transistor as the output of the single-stage amplifier.

[0066] The fourth transistor T4, the current source CS and the seventh transistor T7 can operate as a negative feedback circuit 25. The fourth transistor T4 is based on the switch node N SW The voltage (hereinafter referred to as the first voltage) is used to control the bias node N B The voltage (hereinafter referred to as the second voltage) is adjusted (e.g., in response to the state of the fourth transistor T4), the seventh transistor T7 is turned on to provide the second voltage to the gate terminal of the first transistor T1, and thus the first transistor T1 is controlled based on the second voltage so that the switch node N SW Since the fourth transistor T4, the seventh transistor T7 and the first transistor T1 form a negative loop, the switch node N SW The first voltage of can be maintained at a constant level. In other words, the negative feedback circuit 25 can perform a voltage regulation function of the first voltage. The first transistor T1 can operate as a source follower and can operate in a saturation region. The first transistor T1 has a high output impedance, and the high output impedance can help to alleviate the switching node N SW The first voltage changes.

[0067] Figure 4A is a diagram showing a logic circuit for generating a control signal provided to a current cell according to an embodiment, and Figure 4B is a timing diagram of control signals according to an embodiment.

[0068] The logic circuit 141 may be arranged in Figure 1 The ramp signal generator 140 may generate a signal provided to the ramp signal generator 140. Figure 3A and Figure 3B The control signal of the current unit 20.

[0069] Reference Figure 4A , the logic circuit 141 may include a latch LC, and the latch LC may generate a first control signal SLB and a second control signal SL based on a reset signal RESET and a set signal SET.

[0070] Reference Figure 4B, the reset signal RESET may be switched between a first level (e.g., logic low) and a second level (e.g., logic high) at time point t1, and the latch LC may generate a first control signal SLB of a second level and a second control signal SL of a first level in response to a rising (or falling) edge of the reset signal RESET. Thereafter, at time point t2, the set signal SET may be switched between a first level and a second level, and the latch LC may generate a first control signal SLB of a first level and a second control signal SL of a second level in response to a rising (or falling) edge of the set signal SET. The period from time point t1 to time point t2 may be referred to as a reset phase, and the period after time point t2 may be referred to as a set phase.

[0071] The first level (low level) of each of the first control signal SLB and the second control signal SL may be level-shifted to the first power supply voltage ( Figure 3A and Figure 3B The voltage level of VSS in the first power supply voltage is shifted to the second power supply voltage ( Figure 3A and Figure 3B The voltage level of VDDA in the

[0072] Reference Figure 4B The first control signal SLB and the second control signal SL described above may be provided to Figure 3B The levels of the first control signal SLB and the second control signal SL may be based on Figure 3A The types of the first to fourth switches SW1 to SW4 in FIG. Figure 3B Differently, when the first switch SW1 and the second switch SW2 are implemented as N-type transistors and the third switch SW3 and the fourth switch SW4 are implemented as P-type transistors, the latch LC can generate a first control signal SLB of a first level and a second control signal SL of a second level in the reset phase, and generate a first control signal SLB of a second level and a second control signal SL of a first level in the set phase.

[0073] For ease of explanation, Figure 4A , the logic circuit 141 is shown as including a latch LC, but the logic circuit 141 may include corresponding Figure 2 For example, one of the N latches LC may be provided for each of the N current cells.

[0074] The logic circuit 141 may operate based on the clock signal CLK, and a period from a rising time point (e.g., t1) of the reset signal RESET to a rising time point (e.g., t2) of the set signal SET may correspond to one cycle (or half cycle) of the clock signal CLK. In some embodiments, the logic circuit 141 may continuously shift the initial reset signal RESET and the initial set signal SET by one cycle (or half cycle) of the clock signal CLK over time to generate the reset signal RESET and the set signal SET provided to each of the N latches LC. The N current cells 10_1 to 10_N may be sequentially changed from a reset phase to a set phase according to the corresponding reset signal RESET and the set signal SET, and thus, the level of the ramp signal RAMP may decrease.

[0075] The period (or frequency) of the clock signal CLK can be related to Figure 1 The period (or frequency) of the count clock signal used by the counter (CNT) 132 is the same, and the counter (CNT) 132 may increase the count value whenever the ramp signal RAMP decreases. In other words, the ramp signal generating circuit 140 operates based on the clock signal CLK, the counter (CNT) 132 operates based on the count clock signal, and the operating frequency of the ramp signal generating circuit 140 and the operating frequency of the counter (CNT) 132 may be the same.

[0076] Figure 5A and Figure 5B is a circuit diagram illustrating operations in a reset phase and a set phase of a current cell according to an embodiment.

[0077] Reference Figure 5A In the reset phase, the fifth transistor T5 is turned off in response to the first control signal SLB of the second level H, and the eighth transistor T8 is turned off in response to the second control signal SL of the first level L. The sixth transistor T6 can be turned on in response to the second control signal SL of the first level L to provide the second power supply voltage VDDA to the gate terminal of the second transistor T2. The second transistor T2 can be turned off in response to the second power supply voltage VDDA. The seventh transistor T7 can be turned on in response to the first control signal SLB of the second level H to bias the bias node N B The second voltage is provided to the gate terminal of the first transistor T1. The first transistor T1 can be turned on based on the second voltage to reduce the cell current I CELL Provided to the load resistor R L As mentioned above Figure 3B As described, the switch node N SW , the fourth transistor T4, the seventh transistor T7 and the first transistor T1 may form a negative feedback loop, and the switch node N SWThe first voltage of can remain unchanged and maintain a constant level. The first transistor T1 can operate in a saturation region and can have a high output impedance. Therefore, even if the level of the ramp signal RAMP changes (eg, the level decreases), the first voltage does not change and can maintain a constant level.

[0078] Reference Figure 5B , in the set phase, the sixth transistor T6 is turned off in response to the second control signal SL of the second level H, and the seventh transistor T7 is turned off in response to the first control signal SLB of the first level L. The fifth transistor T5 can be turned on in response to the first control signal SLB of the first level L to provide the second power supply voltage VDDA to the gate terminal of the first transistor T1. The first transistor T1 can be turned off in response to the second power supply voltage VDDA. The eighth transistor T8 can be turned on in response to the second control signal SL of the second level H to bias the bias node N B The second voltage is provided to the gate terminal of the second transistor T2. The second transistor T2 can be turned on based on the second voltage to reduce the cell current I CELL Provided to the first power supply node N P1 In the set phase, the switch node N SW , the fourth transistor T4, the eighth transistor T8 and the second transistor T2 form a negative feedback loop, and the switch node N SW The first voltage may be kept constant.

[0079] Figure 6 is a circuit diagram showing a current cell according to a comparative example.

[0080] Reference Figure 6 , according to the embodiment of Figure 3A and / or Figure 3B The second current unit 30 of the comparative example of the first current unit 20 may include first to fourth transistors T1 to T4.

[0081] The first transistor T1 and the second transistor T2 may be referred to as a first switching transistor and a second switching transistor, respectively. The first transistor T1 is connected to a switching node N SW With output node N O The first transistor T1 may be turned on to transfer the cell current I CELL Provided to the load resistor R L The second transistor T2 is connected to the switch node N SW The first power supply node N P1 The second transistor T2 may be turned on or off in response to the first control signal SLB. CELL Provided to the first power supply node NP1 .

[0082] The third transistor T3 and the fourth transistor T4 may be connected in series at the second power supply node N. P2 With switch node N SW and can generate a cell current I based on the first bias voltage VB1 and the second bias voltage VB2 CELL .

[0083] Fig. 7A is a circuit diagram showing the operation of a ramp signal generator including a current unit according to a comparative example, and Figure 7B is a timing diagram of a ramp signal of a voltage and current unit of a switch node according to a comparative example.

[0084] Reference Fig. 7A , the ramp signal generator 140′ may include N units 30_1 to 30_N, and the N units 30_1 to 30_N may be implemented as the second current unit 30 according to the comparative example (see Figure 6 ). Parasitic capacitor C P A switch node N may be formed at each of the N units 30_1 to 30_N. SW Place.

[0085] The N cells 30_1 to 30_N may be sequentially changed from the reset phase to the set phase, and thus the level of the ramp signal RAMP may be reduced. For example, the first to Nth cells 30_1 to 30_N may be sequentially changed from the reset phase to the set phase.

[0086] Refer to Figure 7B , before the ramp operation of the ramp signal generator 140', for example, before the time point t1, the first to Nth cells 30_1 to 30_N may operate in a reset phase and may provide a cell current to the load resistor R L The ramp operation starts from the time point t1, and the first to Nth cells 30_1 to 30_N may be sequentially changed from the reset phase to the set phase.

[0087] like Fig. 7A As shown in FIG. 1 , at the start of the ramp operation, the first cell 30_1 and the second cell 30_2 may operate in a set phase, and the third cell 30_3 to the Nth cell 30_N may operate in a reset phase. The first cell 30_1 and the second cell 30_2 may provide the cell current to the first power supply node N P1 , and the third unit 30_3 to the Nth unit 30_N can provide the unit current to the load resistor R L When the ramp operation starts, the level of the ramp signal RAMP can flow through the load resistor R Ldecreases with the decrease of the current.

[0088] like Figure 7B As shown in FIG. 1 , the first transistor T1 of the second unit (eg, the third unit 30_3 to the Nth unit 30_N) in the reset phase operates in the triode region, and as the level of the ramp signal RAMP decreases, the switch node N SW The first voltage V SW Also decreases. Since the switch node N SW The first voltage V SW is also reduced, thus charging the parasitic capacitor C P The charge in the resistor is discharged and flows through the load resistor R L Therefore, an error occurs in the level of the ramp signal RAMP. Figure 7B As shown in , the level of the ramp signal RAMP may decrease nonlinearly in the initial period of the ramp operation from the time point t1 to the time point t2, and may be higher than the level of the ideal ramp signal RAMP. As a result, the ramp signal RAMP shows nonlinearity in the INL measurement interval (or INL measurement region or INL measurement period), and thus the INL characteristics may be degraded.

[0089] Thereafter, as the ramp signal RAMP is further reduced, the first transistor T1 may operate in the saturation region from time point t2. Therefore, after time point t2, even if the voltage of the ramp signal RAMP changes as the output impedance of the first transistor T1 increases, the switch node N SW The first voltage V SW Therefore, after time point t2, no parasitic capacitor C P The discharge of the ramp signal RAMP can be linearly reduced.

[0090] However, as described above, in the case including the second current unit ( Figure 6 In the ramp signal generator 140' of FIG30), at the beginning of the ramp operation (ie, from time point t1 to time point t2), an error occurs in the ramp signal, thereby degrading the INL characteristic. P As the capacitance of the ramp signal generator 140 increases, the degradation of the INL characteristic may be aggravated, and as the operating frequency of the ramp signal generator 140' (eg, the frequency of the clock signal) becomes higher, the degradation of the INL characteristic may be aggravated. In some embodiments, the set phase may end at time point t3.

[0091] Fig. 8A is a circuit diagram showing a negative feedback loop according to an embodiment when a current unit according to an embodiment operates in a reset phase, and Figure 8Bis a timing diagram of a ramp signal of a voltage and current unit of a switch node according to an embodiment.

[0092] The first current unit 20 according to the embodiment may be implemented as Figure 3A and / or Figure 3B The first current unit 20, and Fig. 8A The transistor not shown in the figure is in the off state.

[0093] Reference Fig. 8A , during the reset phase, the switch node N SW , the fourth transistor T4, the bias node N B , the seventh transistor T7 and the first transistor T1 form a negative feedback loop, and the first transistor T1 can operate in a saturation region.

[0094] like Figure 8B As shown in , the first transistor T1 may always operate in the saturation region. For example, the first transistor T1 may operate in the saturation region in the reset phase and the set phase. Even in the initial phase of the ramp operation (i.e., starting from the time point t1), since the first transistor T1 provided in the first current unit 20 in the reset phase operates in the saturation region, even if the level of the ramp signal RAMP is reduced, the switch node N SW The voltage of the parasitic capacitor ( Fig. 7A C P ) can form a switch node N in the first current unit 20 SW However, due to the switch node N SW The voltage of the ramp signal RAMP does not change, so there is no voltage drop due to the parasitic capacitor C P Therefore, the ramp signal RAMP shows linearity in the INL measurement period of the ramp signal RAMP, and the INL characteristic can be improved.

[0095] Fig.9A and Fig. 9B is a graph comparing changes in INL characteristics of a current cell according to an embodiment and a current cell according to a comparative example. Fig.9A shows a change in the INL characteristic according to an increase in the capacitance of the parasitic capacitor of the switch node of the current cell, and Fig. 9B A change in the INL characteristic according to an increase in the frequency of the clock signal is shown.

[0096] Reference Fig.9A , the horizontal axis represents the parasitic capacitor C P The vertical axis represents INL.

[0097] In the first current cell CS1 according to the embodiment, although the capacitance of the parasitic capacitor increases, the INL characteristic is almost unchanged. In contrast, the INL characteristic of the second current cell CS2 according to the comparative example may deteriorate as the capacitance of the parasitic capacitor increases. Therefore, it can be seen that the INL characteristic of the second current cell CS2 according to the comparative example is degraded due to the increase in the capacitance of the parasitic capacitor. P The INL characteristic of the first current unit CS1 according to the embodiment is hardly affected by the discharge of the parasitic capacitor C P The impact of discharge.

[0098] Reference Fig. 9B , the horizontal axis represents Figure 4A The frequency of the clock signal CLK is Freq., and the frequency may be several GHz (gigahertz). The vertical axis represents INL. Fig. 9B A change in the INL characteristic according to a change in the frequency of the clock signal is shown under the condition that no load capacitor exists.

[0099] As the frequency of the clock signal increases, the INL characteristic may deteriorate. Compared with the first current cell CS1 according to the embodiment, the INL characteristic of the second current cell CS2 according to the comparative example may be significantly reduced. For example, when the INL characteristic is deteriorated by about 0.3 least significant bits (LSBs) as the frequency of the clock signal increases in the first current cell CS1 according to the embodiment, the INL characteristic of the second current cell CS2 according to the comparative example may be deteriorated by 1 LSB or more as the frequency of the clock signal increases. Therefore, the first current cell CS1 according to the embodiment may have an improved INL characteristic in high-speed operation.

[0100] As described above, the first current unit CS1 according to the embodiment can have a large output impedance by operating the first switching transistor T1 in the saturation region and generating a unit current based on a gain-boosted cascade method including a negative feedback loop circuit. Therefore, the INL characteristic of the ramp signal RAMP is not affected by the parasitic capacitor, and the INL characteristic can be improved in high-speed operation. In some embodiments, unlike the second current unit CS2, the first current unit CS1 may have a single bias transistor. Since the number of transistor stacks is reduced, the ramp signal generator 140 including the first current unit CS1 can operate at a low voltage. Therefore, even during high-speed operation, the image sensor ( Figure 1 100 in ) can also improve image quality and reduce power consumption.

[0101] Fig.10 is a circuit diagram showing a current cell according to an embodiment.

[0102] Fig.10 The first current unit 20a is Figure 3A and Figure 3B 1 is a modified example of the first current unit 20. Therefore, for the sake of brevity, redundant explanations will be omitted and differences will be mainly explained.

[0103] Reference Fig.10 , the first control signal SLB may be applied to the gate terminal of the second transistor T2. The second transistor T2 may be turned off in response to the first control signal SLB of the second level in the reset phase, and may be turned on in response to the first control signal SLB of the first level in the set phase.

[0104] As reference Figure 5A As described, in the reset phase, the second transistor T2 is turned off and the first transistor T1 is turned on to reduce the cell current I CELL Provided to the load resistor R L , and the first transistor T1, the fourth transistor T4 and the seventh transistor T7 can form a negative feedback loop. In the setting phase, the first transistor T1 is turned off, and the second transistor T2 is turned on to convert the cell current I CELL Directly supplied to the first power supply node N P1 (e.g., ground). Different from Figure 5B Description, in Fig.10 In the first current unit 20a, a negative feedback loop may not be formed in the setting phase. Since the first transistor T1 is turned off in the setting phase, even if the level of the ramp signal RAMP is reduced, the switch node N SW The voltage will not be affected.

[0105] Fig.11 is a circuit diagram showing a current cell according to an embodiment.

[0106] Fig.11 The first current unit 20b is Figure 3A and Figure 3B 1 is a modified example of the first current unit 20. Therefore, for the sake of brevity, redundant explanations will be omitted and differences will be mainly explained.

[0107] Reference Fig.11 , the first current unit 20b may include a plurality of third transistors, for example, two third transistors T3-1 and T3-2. The two third transistors T3-1 and T3-2 may generate a unit current based on the first bias voltage VB1 and the second bias voltage VB2, respectively. As the number of transistor stacks increases, the output impedance of the first current unit 20b may increase.

[0108] Fig.12is a circuit diagram showing a ramp signal generator according to an embodiment.

[0109] Fig.12 The ramp signal generator 140a is Figure 2 Therefore, for the sake of brevity, redundant explanations will be omitted and differences will be mainly explained.

[0110] Reference Fig.12 , the ramp signal generator 140a may include a plurality of current units (eg, current units 10_1 to 10_N), and at least one current unit may be implemented as a first current unit ( Figure 3A and Figure 3B 20 of 10, or Fig.10 20a in the above, or Fig.11 20b), and at least another current unit may be implemented as a second current unit ( Figure 6 of 30).

[0111] For example, Fig.12 As shown in , the current units 10_1 and 10_2 may be implemented as a second current unit (current unit 2) 30, and the current units 10_3 to 10_N may be implemented as a first current unit (current unit 1) 20. The current units 10_1 and 10_2 may be changed from the reset phase to the set phase earlier than the current units 10_3 to 10_N. For example, the current units 10_1 and 10_2 may be in the set phase at the initial phase of the ramp period, and the current units 10_3 to 10_N may be in the reset phase at the initial phase of the ramp period. The first transistor T1 provided in each of the current units 10_3 to 10_N may operate in a saturation region, and even when the level of the ramp signal RAMP is reduced, the switch node N SW The voltage of can also be kept constant. Therefore, the linearity of the ramp signal RAMP is maintained and the INL characteristic can be improved.

[0112] Fig.13 is a schematic block diagram of an electronic device according to an embodiment.

[0113] The electronic device 200 may represent any device configured to perform a desired function using electrical energy, and may be referred to as an electrical system. For example, the electronic device 200 may be composed of a semiconductor chip manufactured by a semiconductor process, a module including a board and at least one semiconductor chip mounted on the board, or two or more modules communicating with each other. In some embodiments, the electronic device 200 may be a unit used independently (such as a mobile phone), or a component of an entire system (such as a vehicle).

[0114] Reference Fig.13, the electronic device 200 may include a ramp signal generator 210 and a main circuit 220 .

[0115] The ramp signal generator 210 may be implemented as Figure 1 , Figure 2 and Fig.12 The ramp signal generator 210 may include a load resistor and a plurality of current units, at least one or all of the plurality of current units may include a negative feedback loop circuit, and even if the level of the ramp signal RAMP is reduced, the voltage of the switch node may not change. Therefore, the ramp signal RAMP has linearity, and the INL characteristic may be improved.

[0116] The main circuit 220 may be designed to provide at least one of a function provided by the electronic device 200 and a main function provided by the electronic device 200. The main circuit 220 may output the function provided by the electronic device 200 to the outside as an output signal OUT. For example, the main circuit 220 may include an analog circuit (such as an analog filter, an amplifier, etc.), a digital circuit that processes a digital signal, or a circuit that processes a mixed signal (such as an analog-to-digital converter or a digital-to-analog converter).

[0117] According to an embodiment, the main circuit 220 may perform a predefined function by detecting data based on the ramp signal RAMP. For example, the main circuit 220 may be a CDS circuit that performs correlated double sampling (CDS) on data based on the ramp signal RAMP, or an analog-to-digital conversion circuit including a CDS function. In some embodiments, the main circuit 220 may provide various functions using a ramp signal RAMP whose level has a constant slope and gradually increases or decreases.

[0118] Fig.14 is a block diagram schematically illustrating an electronic device including an image sensor according to an embodiment.

[0119] Reference Fig.14 , the electronic device 1000 may include an image sensor 1100 and an application processor (AP) 1200. The electronic device 1000 may also include various sensors (such as an illumination sensor, a communication module, etc.).

[0120] The AP 1200 may provide a control signal CIT for controlling the operation of the image sensor 1100 to the image sensor 1100. The transmission of the control signal CIT may be performed based on, for example, an interface based on an inter-integrated circuit (I2C). The control signal CIT may further include configuration data of the image sensor 1100 (such as a lens shading correction value, a crosstalk coefficient, an analog gain, a digital gain, a frame rate setting value, etc.).

[0121] The image sensor 1100 may generate image data IDTA by photographing an object based on a received control signal. The image data IDTA may include a static image and a dynamic image. The image sensor 1100 may perform signal processing (such as one or more of image quality compensation, merging, and reduction) on the image data IDTA, and the image quality compensation may include, for example, signal processing (such as one or more of black level compensation, lens shading compensation, crosstalk compensation, and bad pixel compensation).

[0122] Reference Figure 1 The image sensor 100 described above may be applied as the image sensor 1100. The ramp signal generator ( Figure 1 140) may include a load resistor and a plurality of current cells that provide a cell current to the load resistor or a first power supply node (eg, ground), and at least some or all of the plurality of current cells may be implemented as a first current cell ( Figure 3A and Figure 3B 20 of 20 Fig.10 20a or Fig.11 20b in FIG. 20b). Therefore, the INL characteristic of the ramp signal RAMP can be improved, and the degradation of the INL characteristic of the ramp signal RAMP can be improved when the ramp signal generator 140 operates at a high speed. Therefore, even if the image sensor 1100 operates at a high speed, the image quality of the image data IDTA generated by the image sensor 1100 can be prevented from being degraded.

[0123] For example, when the frame rate of the image sensor 1100 increases, or the image sensor 1100 generates a first image and a second image having different brightness for generating a high dynamic range (HDR) image in one frame, the ramp signal generator 140 may operate at a high speed. When the INL characteristic of the ramp signal RAMP is degraded during the high-speed operation of the ramp signal generator 140, the image quality of the image generated by the image sensor 1100 may be degraded. However, as described above, the ramp signal generator 140 according to the embodiment does not degrade the INL characteristic of the ramp signal RAMP even during the high-speed operation, and therefore, the image quality can be prevented from being degraded.

[0124] The image sensor 1100 may transmit the image data IDTA or the signal-processed image data IDTA to the AP 1200. In one embodiment, the image sensor 1100 may transmit a plurality of pieces of image data having different brightness (eg, image data IDTA including first image data and second image data) to the AP 1200.

[0125] The transmission of the image data IDTA may be performed using, for example, a camera serial interface (CSI) based on a mobile industry processor interface (MIPI), but the embodiment is not limited thereto.

[0126] The application processor 1200 may perform image processing (such as one or more of bad pixel correction, 3A adjustment including auto focus correction, auto white balance, and auto exposure, noise reduction, sharpening, gamma control, mosaic reordering, demosaicing, and resolution scaling (video / preview)) on the received image data IDTA.

[0127] In some embodiments, the application processor 1200 may generate a high dynamic range (HDR) image based on a plurality of image data having different brightness, such as first image data and second image data.

[0128] Although various embodiments have been particularly shown and described with reference to the drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A ramp signal generator, comprising: a resistor connected between an output node outputting a ramp signal that increases or decreases at a constant slope and a first power supply node configured to receive a first power supply voltage; as well as a plurality of current cells, a cell current flows through each of the plurality of current cells and flows to a first power supply node or a resistor, the plurality of current cells including at least one first current cell, Wherein, each of the at least one first current unit comprises: a first transistor connected between the first switch node and the output node, the cell current flowing to the resistor through the first transistor; a second transistor connected between the first switch node and the first power supply node, the cell current flowing to the first power supply node through the second transistor; and The negative feedback circuit maintains a constant voltage at the first switch node by controlling the gate terminal of the first transistor based on the voltage of the first switch node.

2. The ramp signal generator according to claim 1, wherein: The negative feedback circuit includes: a load transistor including a first terminal connected to a second power supply node configured to receive a second power supply voltage, a second terminal connected to a bias node, and a gate terminal connected to the first switch node; a current source connected between the bias node and the first power supply node; a first switch connected to the bias node and the gate terminal of the first transistor, the first switch being turned on or off based on a first control signal; and A second switch is connected to the bias node and the gate terminal of the second transistor, and the second switch is turned on or off based on a second control signal which is a complementary signal of the first control signal.

3. The ramp signal generator according to claim 2, wherein: Each of the at least one first current unit further includes: a bias transistor connected between the second power supply node and the first switch node, the bias transistor generating a cell current; a third switch connected between the second power supply node and the gate terminal of the first transistor, the third switch being turned on based on the first control signal to turn off the first transistor; and The fourth switch is connected between the second power supply node and the gate terminal of the second transistor, and is turned on based on the second control signal to turn off the second transistor.

4. The ramp signal generator according to claim 3, wherein: In the reset phase, the second transistor is turned off, and the first transistor is turned on to supply the cell current to the resistor.

5. The ramp signal generator according to claim 4, wherein: The first transistor operates in a saturation region.

6. The ramp signal generator according to claim 4, wherein: In a set phase following the reset phase, the first transistor is turned off, and the second transistor is turned on to supply the cell current to the first power supply node.

7. The ramp signal generator according to claim 6, wherein: In the reset phase, the first switch and the fourth switch are turned on, and the second switch and the third switch are turned off, and In the set phase, the first switch and the fourth switch are turned off, and the second switch and the third switch are turned on.

8. The ramp signal generator according to claim 2, wherein: The first power supply voltage is less than the second power supply voltage, and Each of the first transistor and the second transistor includes a P-type transistor.

9. The ramp signal generator according to claim 1, wherein: The plurality of current cells are sequentially changed from a reset phase to a set phase, and The first transistor provided in the at least one first current cell in a reset phase among the plurality of current cells operates in a saturation region and supplies a cell current to a resistor.

10. The ramp signal generator according to claim 1, wherein: Each of the plurality of current cells includes a first current cell.

11. The ramp signal generator according to claim 1, wherein: The plurality of current cells include the at least one first current cell and at least one second current cell, wherein each of the at least one second current cell includes: a bias transistor connected between a second power supply node configured to receive a second power supply voltage and the second switch node, the bias transistor generating a cell current; a third transistor connected between the second switch node and the first terminal of the resistor, the cell current flowing to the resistor through the third transistor; and The fourth transistor is connected between the second switch node and the first power supply node, and the cell current flows to the first power supply node through the fourth transistor.

12. The ramp signal generator according to claim 11, wherein: The level of the ramp signal decreases as the plurality of current cells are sequentially changed from a reset phase to a set phase; In the reset phase, the first transistor and the third transistor are turned on, and the second transistor and the fourth transistor are turned off; In the set phase, the second transistor and the fourth transistor are turned on, and the first transistor and the third transistor are turned off; and The at least one second current cell is changed to the set phase earlier than the at least one first current cell.

13. An image sensor, comprising: A pixel array comprising a plurality of pixels; a ramp signal generating circuit configured to generate a ramp signal, the level of the ramp signal decreasing at a constant slope; as well as The analog-to-digital conversion circuit is configured to convert a pixel signal provided from the pixel array into a pixel value based on the ramp signal, Wherein, the ramp signal generating circuit comprises: A load resistor, connected between ground and the output node, to which the ramp signal is output, and a plurality of current cells, each supplying a cell current to a load resistor during a reset period and supplying a cell current to a ground during a set period, and Wherein, each of the plurality of current units comprises: a first transistor connected between the switch node and the output node, through which the cell current flows to the load resistor; a second transistor connected between the switch node and ground, the cell current flowing to the ground through the second transistor, and The negative feedback circuit controls the gate terminal of the first transistor based on the voltage of the switch node so that the first transistor operates in a saturation region.

14. The image sensor according to claim 13, wherein: The negative feedback circuit includes: a third transistor including a first terminal configured to receive a positive supply voltage, a second terminal connected to a bias node, and a gate terminal connected to the switch node; a current source connected between the bias node and ground; a fourth transistor connected to the bias node and the gate terminal of the first transistor, the fourth transistor being turned on or off based on the first control signal; and A fifth transistor is connected to the bias node and a gate terminal of the second transistor, and the fifth transistor is turned on or off based on a second control signal which is a complementary signal of the first control signal.

15. The image sensor according to claim 13, wherein: The negative feedback circuit is further configured to control the gate terminal of the first transistor based on the voltage of the switch node to keep the voltage of the switch node constant.

16. The image sensor according to claim 13, wherein: Each of the plurality of current cells further comprises: a sixth transistor connected between the switch node and a power supply node configured to receive a positive power supply voltage, the sixth transistor being configured to generate a cell current; a seventh transistor connected between the power supply node and the gate terminal of the first transistor, the seventh transistor being configured to turn off the first transistor by providing a positive power supply voltage to the gate terminal of the first transistor during a set phase; and An eighth transistor is connected between the power node and the gate terminal of the second transistor, and is turned on based on a second control signal of a second level during a reset phase to turn off the second transistor by supplying a positive power voltage to the gate terminal of the second transistor.

17. The image sensor according to claim 13, wherein: The plurality of current cells are sequentially changed from a reset phase to a set phase to reduce a level of a ramp signal.

18. An electronic device comprising: a ramp signal generator including a plurality of current cells and a load resistor, the ramp signal generator being configured to control the plurality of current cells to reduce an amount of current flowing through the load resistor, and to generate a ramp signal, a level of the ramp signal increasing or decreasing at a specific slope; as well as a main circuit configured to perform at least one predefined function by detecting data based on the ramp signal, Wherein, each of the plurality of current units comprises: a first transistor connected between the switch node and the output node, through which the cell current flows to the load resistor during a reset period, a second transistor connected between the switch node and ground, through which the cell current flows to ground during the set period, and The negative feedback circuit controls the gate terminal of the first transistor based on the voltage of the switch node so that the first transistor operates in a saturation region.

19. The electronic device according to claim 18, wherein: The negative feedback circuit includes: An amplifier including a single stage based on voltage control of a switch node; and A switch is turned on during the reset period, the switch being configured to provide the output of the amplifier to the gate terminal of the first transistor.

20. The electronic device according to claim 19, wherein: Amplifiers include: a third transistor including a first terminal configured to receive a positive supply voltage, a second terminal connected to a bias node, and a gate terminal connected to the switch node; and A current source connected between the bias node and ground, and The voltage of the bias node is provided to the gate terminal of the first transistor as the output of the amplifier.

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