Spin-orbit moment magnetic memory and preparation method thereof

Abstract

The invention provides a spin-orbit moment magnetic memory and a preparation method thereof, and the preparation method comprises the steps: forming a lamination unit and a dielectric layer wrapping the lamination unit on a substrate, the lamination unit comprises a magnetic tunnel junction and an SOT layer, and the dielectric layer comprises a top dielectric sub-layer and a side dielectric sub-layer; forming a photoetching processing layer on the dielectric layer; patterning the photoetching processing layer to form an electric interconnection groove; etching the dielectric layer according to the patterned photoetching processing layer to expose the upper surface of the SOT layer or expose the side wall of the SOT layer; depositing a conductive material to form a conductive layer covering the dielectric layer; and planarizing the conductive layer to enable the conductive layer to form at least two mutually independent conductive structures. According to the invention, the manufacturing cost of the bottom pinning type SOT-MRAM can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a spin-orbit moment magnetic memory and a preparation method thereof. Background Art

[0002] Spin-orbit torque magnetic RAM (SOT-MRAM) has the advantages of non-volatility, high speed, high reliability, and low power consumption, and is a storage device with great development potential.

[0003] The SOT-MRAM device unit consists of a spin-orbit torque providing (SOT) layer and a magnetic tunnel junction. The magnetic tunnel junction includes a free layer, a tunneling layer, a reference layer, a pinning layer, etc. Usually, the SOT-MRAM device unit adopts a top pinning structure, but it faces the problems of short circuit and damage of the magnetic tunnel junction and over-etching of the spin-orbit torque providing layer during preparation, making the preparation of the spin-orbit torque magnetic memory difficult and the yield is low. The use of a bottom pinning structure, that is, a structure in which the spin-orbit torque providing layer is arranged above the magnetic tunnel junction, is conducive to solving the above problems.

[0004] However, one of the difficulties currently faced by the bottom pinned structure is that the process of forming the electrical interconnection of the spin-orbit moment providing layer requires two photolithography steps to form conductive grooves and through-holes through a hard mask respectively, thereby realizing the electrical coupling between the conductive layer and the SOT layer. The increase in the number of photolithography steps makes the production cost of the bottom pinned SOT-MRAM higher.

[0005] Therefore, how to reduce the number of photolithography times and thus reduce the production cost of bottom pinned SOT-MRAM has become a difficult problem that needs to be solved urgently. Summary of the invention

[0006] To solve the above problems, the present invention provides a spin-orbit moment magnetic memory and a method for preparing the same, wherein a dielectric layer is etched through a photolithography processing layer to form a conductive structure electrically coupled to a SOT layer, thereby reducing the number of photolithography times and the manufacturing cost of a bottom pinned SOT-MRAM.

[0007] In a first aspect, the present invention provides a method for preparing a spin-orbit moment magnetic memory, comprising:

[0008] A stacking unit and a dielectric layer covering the stacking unit are formed on a substrate, wherein the stacking unit includes, from bottom to top, a magnetic tunnel junction and a SOT layer, and the dielectric layer includes, a top dielectric sublayer overlapping the SOT layer in the up-down direction and a side dielectric sublayer located on the periphery of the stacking unit;

[0009] forming a photolithography processing layer on the dielectric layer;

[0010] Patterning the photolithography processing layer to form at least two mutually independent electrical interconnection grooves on the photolithography processing layer; wherein each electrical interconnection groove overlaps with a portion of the top dielectric sublayer and a portion of the side dielectric sublayer in the up-down direction, or each electrical interconnection groove overlaps with a portion of the side dielectric sublayer in the up-down direction, and the sidewall of the electrical interconnection groove overlaps with the sidewall of the SOT layer in the up-down direction;

[0011] Etching the dielectric layer according to the patterned photolithography process layer, so that when the electrical interconnection trench overlaps with a portion of the top dielectric sublayer and a portion of the side dielectric sublayer in the up-down direction, respectively, the upper surface of the SOT layer is exposed, and when the electrical interconnection trench overlaps with a portion of the side dielectric sublayer in the up-down direction, and the sidewall of the electrical interconnection trench overlaps with the sidewall of the SOT layer in the up-down direction, the sidewall of the SOT layer is exposed;

[0012] Depositing a conductive material to form a conductive layer covering the dielectric layer;

[0013] The conductive layer is planarized so that the conductive layer forms at least two mutually independent conductive structures.

[0014] Optionally, before the step of depositing a conductive material to form a conductive layer covering the dielectric layer, the method further comprises:

[0015] Removing the patterned photolithography layer;

[0016] The material of the photolithography processing layer includes: photoresist material, metal hard mask material or dielectric hard mask material.

[0017] Optionally, when the material of the photolithography processing layer is an insulating material, the step of planarizing the conductive layer so that the conductive layer forms at least two mutually independent conductive structures includes:

[0018] The conductive layer is planarized to expose the photolithographic processing layer or the top dielectric sublayer.

[0019] Optionally, when the material of the photolithography processing layer is a conductive material, the step of planarizing the conductive layer so that the conductive layer forms at least two mutually independent conductive structures includes:

[0020] The conductive layer is planarized to expose the top dielectric sublayer.

[0021] Optionally, the step of forming a stacking unit and a dielectric layer covering the stacking unit on a substrate includes:

[0022] Depositing a stacked structure, a first preliminary dielectric layer and a hard mask layer in sequence on a substrate, wherein the stacked structure is used to form a SOT layer and a magnetic tunnel junction;

[0023] Patterning the hard mask layer, and etching the first preliminary dielectric layer and the stacked structure according to the patterned hard mask layer to form a top dielectric sublayer, a SOT layer, and a magnetic tunnel junction;

[0024] Depositing a second preliminary dielectric layer covering the magnetic tunnel junction;

[0025] The second preliminary dielectric layer is planarized to remove the hard mask layer and obtain a side dielectric sub-layer.

[0026] Optionally, the step of depositing a second preliminary dielectric layer covering the magnetic tunnel junction includes:

[0027] Depositing in sequence a first preliminary dielectric sublayer and a second preliminary dielectric sublayer covering the magnetic tunnel junction;

[0028] The step of etching the dielectric layer according to the patterned photolithography processing layer includes:

[0029] The first preliminary dielectric sub-layer is etched, and the etching stop position of the first preliminary dielectric sub-layer is higher than the lower surface of the SOT layer.

[0030] Optionally, the material of the hard mask layer includes: at least one of tantalum, titanium, tantalum nitride and titanium nitride;

[0031] The shape of the patterned hard mask layer includes: circle, oval, rectangle, diamond or triangle;

[0032] The material of the first preliminary dielectric sub-layer includes silicon nitride, and the material of the second preliminary dielectric sub-layer includes silicon oxide.

[0033] Optionally, the step of etching the dielectric layer according to the patterned photolithography processing layer includes:

[0034] According to the patterned photolithography processing layer, the dielectric layer is etched by reactive ion etching or ion beam etching.

[0035] Optionally, the material of the top dielectric sublayer includes at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon oxycarbide.

[0036] In a second aspect, the present invention provides a spin-orbit torque magnetic memory, and the spin-orbit torque magnetic memory is obtained by using any of the methods described above.

[0037] The spin-orbit moment magnetic memory and its preparation method provided by the embodiment of the present invention can realize the conductive interconnection of the SOT layer by patterning the photolithography processing layer by photolithography, and etching the dielectric layer according to the patterned photolithography processing layer, thereby simplifying the process flow and reducing the production cost of the bottom pinned SOT-MRAM. At the same time, the wire structure is realized by the first hard mask, which can effectively control the contact area between the conductive structure and the SOT layer, and ensure that the current density flowing through the SOT layer is large enough. In addition, retaining part or all of the top dielectric sublayer in the etched dielectric layer can avoid damage to the effective part of the SOT layer covered by the top dielectric sublayer. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figures 1 to 10 They are schematic structural diagrams of a spin-orbit moment magnetic memory at various stages of preparing the spin-orbit moment magnetic memory according to an embodiment of the present application;

[0040] Fig.11 A schematic structural diagram of a spin-orbit torque magnetic memory in a process of preparing the spin-orbit torque magnetic memory according to an embodiment of the present application;

[0041] Fig.12 A schematic structural diagram of a spin-orbit torque magnetic memory during the process of preparing the spin-orbit torque magnetic memory according to an embodiment of the present application;

[0042] Fig.13 A schematic structural diagram of a spin-orbit torque magnetic memory during the process of preparing the spin-orbit torque magnetic memory according to an embodiment of the present application;

[0043] Fig.14 and Fig.15 All of them are schematic structural diagrams of a spin-orbit moment magnetic memory at different stages of preparing the spin-orbit moment magnetic memory according to an embodiment of the present application;

[0044] in, Figure 2 , Figure 5 , Figure 7 , Fig.10 and Fig.14 Schematic top views of the spin-orbit moment magnetic memory at different stages of preparing the spin-orbit moment magnetic memory; Figure 1 , Figure 3 , Figure 4 , Figure 6 , Figure 8 , Fig. 9 , Fig.11 , Fig.12 and Fig.13 They are schematic cross-sectional views of a spin-orbit torque magnetic memory at different stages of preparing the spin-orbit torque magnetic memory.

[0045] Reference numerals:

[0046] 1. stacked unit; 11. magnetic tunnel junction; 12. SOT layer; 2. dielectric layer; 21. top dielectric sublayer; 22. second preliminary dielectric layer; 221. first preliminary dielectric sublayer; 222. second preliminary dielectric sublayer; 23. side dielectric sublayer; 3. photolithography processing layer; 31. electrical interconnection groove; 4. hard mask layer; 5. conductive layer; 51. conductive structure; 6. substrate. DETAILED DESCRIPTION

[0047] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0049] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0050] It should be noted that when an element is referred to as being "fixedly connected" to another element, it may be directly on the other element or there may also be a central element. When an element is considered to be "connected" to another element, it may be directly connected to the other element or there may be a central element at the same time. In contrast, when an element is referred to as being "directly on" another element, there is no intermediate element. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0051] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0052] In a first aspect, the present invention provides a method for preparing a spin-orbit moment magnetic memory, the method comprising steps S101 to S106:

[0053] Step S101: forming a laminated unit 1 and a dielectric layer 2 covering the laminated unit 1 on a substrate 6, see Figure 1 and Figure 2 .

[0054] Among them, combined Figure 3 The stacking unit 1 includes, from bottom to top, a magnetic tunnel junction 11 and a SOT layer 12. The dielectric layer 2 includes: a top dielectric sublayer 21 overlapping the SOT layer 12 in the up-down direction and a side dielectric sublayer 23 located on the side of the stacking unit 1. The side dielectric sublayer 23 is flush with the upper surface of the top dielectric sublayer 21. It can be understood that the stacking unit 1 is a storage bit in the spin-orbit moment magnetic memory.

[0055] Further, combined with Figure 3 The step of forming a stacking unit 1 and a dielectric layer 2 covering the stacking unit 1 on a substrate 6 includes:

[0056] A stacked structure, a first preliminary dielectric layer 2, and a hard mask layer 4 are sequentially deposited on a substrate 6. The hard mask layer 4 is patterned, and the first preliminary dielectric layer 2 and the stacked structure are etched according to the patterned hard mask layer 4 to form a top dielectric sublayer 21, a SOT layer 12, and a magnetic tunnel junction 11; a second preliminary dielectric layer 22 covering the magnetic tunnel junction 11 is deposited; and the second preliminary dielectric layer 22 is planarized to remove the hard mask layer 4 to obtain a side dielectric sublayer 23.

[0057] Among them, the stacked structure is used to form the SOT layer 12 and the magnetic tunnel junction 11; the material of the top dielectric sublayer 21, that is, the first preliminary dielectric layer 2 includes: at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon oxycarbide, but is not limited to this; the material of the hard mask layer 4 includes but is not limited to: tantalum, titanium, tantalum nitride and titanium nitride, etc., and the shape of the patterned hard mask layer 4 includes: circular, elliptical, rectangular, diamond or triangular, but is not limited to this.

[0058] In this embodiment, the magnetic tunnel junction 11 includes from bottom to top: an antiferromagnetic pinning layer, a reference layer, a tunneling layer and a free layer, and the free layer is in contact with the SOT layer 12; the material of the first preliminary dielectric layer 2 is a low-k dielectric material, which is not specifically limited in this embodiment.

[0059] Step S102 : forming a photolithography processing layer 3 on the dielectric layer 2 .

[0060] The material of the photolithography processing layer 3 includes: a photoresist material, a metal hard mask material or a dielectric hard mask material, which is not specifically limited in this embodiment.

[0061] Step S103: patterning the photolithography processing layer 3 to form at least two mutually independent electrical interconnection grooves 31 on the photolithography processing layer 3, see Figure 4 and Figure 5 .

[0062] It should be noted that, due to the different materials of the photolithography processing layer 3, the specific patterning process of step S103 is also different.

[0063] Taking the material of the photolithography processing layer 3 as a dielectric hard mask material as an example, step S103 includes steps S1031 to S1034. Specifically,

[0064] Step S1031: coating, i.e. coating the photoresist evenly on the upper surface of the photoresist processing layer 3; Step S1032: exposure, exposing the photoresist according to the mask, and the exposed photoresist hardens and remains on the photoresist processing layer 3; Step S1033: stripping, the unexposed photoresist is cleaned and removed; Step S1034: etching the photoresist processing layer 3, i.e. etching the photoresist processing layer 3 so that the part covered by the photoresist is retained and the other part is removed.

[0065] Therefore, in step S103, the order of pattern transfer is: mask→photoresist→photolithography processing layer 3. The process corresponding to the first transfer is photolithography, and the second transfer is etching. When the material of the photolithography processing layer 3 is a photoresist material, only the photolithography step needs to be performed, and this embodiment will not be described in detail.

[0066] In this embodiment, there are two electrical interconnection grooves 31, that is, two electrical interconnection grooves 31 are opened on one magnetic tunnel junction 11. The two electrical interconnection grooves 31 are arranged opposite to each other, and each electrical interconnection groove 31 overlaps part of the top dielectric sublayer 21 and part of the side dielectric sublayer 23 in the up and down direction.

[0067] The shape of the horizontal cross section of the electrical interconnection groove 31 may be a rectangle, a trapezoid, a fan ring, etc. In the present embodiment, the shape of the horizontal cross section of the electrical interconnection groove 31 is a rectangle.

[0068] Step S104: Etching the dielectric layer 2 according to the patterned photolithography processing layer 3 to expose the upper surface of the SOT layer 12, see Figure 6 and Figure 7 .

[0069] It should be noted that in step S104, in addition to exposing the upper surface of the SOT layer 12, the sidewall of the SOT layer 12 may also be exposed. Specifically, the stop position of etching the dielectric layer 2 may be caused by the etching process or by different etching rates of the dielectric layers 2.

[0070] Combination Fig.11 For example, in the process of over-etching the dielectric layer 2, an appropriate amount of over-etching is allowed, thereby exposing the sidewall of the SOT layer 12. This not only increases the tolerance of the etching process and reduces the difficulty of preparing the spin-orbit moment magnetic memory, but also increases the contact area between the subsequent conductive structure 51 and the SOT layer 12, ensuring the stability of the performance of the spin-orbit moment magnetic memory.

[0071] Combination Fig.12 For another example, the side dielectric sublayer 23 is composed of an inner and outer multilayer structure, and the etching rate of the inner layer in contact with the SOT layer 12 in the side dielectric sublayer 23 is controlled to be greater than the etching rate of the outer dielectric layer 2, or after the upper surface of the corresponding part of the SOT layer 12 is exposed, the inner layer in the side dielectric sublayer 23 is additionally selectively etched, that is, the etching rate of the inner layer in the side dielectric sublayer 23 is greater than the etching rate of other materials.

[0072] In an optional embodiment, in combination Fig.11 , Fig.12 and Fig.13 ,in, Fig.11 is a schematic structural diagram of a conductive structure 51 formed in an over-etched state of the dielectric layer 2; Fig.12 A schematic structural diagram of forming a conductive structure 51 when the etching rate of the first preliminary dielectric sub-layer 221 is greater than the etching rate of the second preliminary dielectric sub-layer 222; Fig.13This is a schematic structural diagram of forming a conductive structure 51 when the etching rate of the first preliminary dielectric sub-layer 221 is lower than the etching rate of the second preliminary dielectric sub-layer 222 .

[0073] The step of depositing the second preliminary dielectric layer 22 covering the magnetic tunnel junction 11 includes: sequentially depositing a first preliminary dielectric sublayer 221 and a second preliminary dielectric sublayer 222 covering the magnetic tunnel junction 11 .

[0074] The step of etching the dielectric layer 2 according to the patterned photolithography processing layer 3 includes: etching the first preliminary dielectric sublayer 221 , and the etching stop position of the first preliminary dielectric sublayer 221 is higher than the lower surface of the SOT layer 12 .

[0075] The etching rates of the first preliminary dielectric sublayer 221 and the second preliminary dielectric sublayer 222 may be the same or different. In this optional embodiment, the material of the first preliminary dielectric sublayer 221 includes silicon nitride, and the material of the second preliminary dielectric sublayer 222 includes silicon oxide, but this is not limited thereto.

[0076] In an optional embodiment, the step of etching the dielectric layer 2 according to the patterned photolithography processing layer 3 includes: etching the dielectric layer 2 by reactive ion etching or ion beam etching according to the patterned photolithography processing layer 3. In this optional embodiment, the reactive ion etching or ion beam etching is not described in detail.

[0077] Step S105: depositing a conductive material to form a conductive layer 5 covering the dielectric layer 2, see Figure 8 .

[0078] It should be noted that when the photolithography processing layer 3 is a metal hard mask material, it can be used as a part of the conductive layer 5, so that the patterned photolithography processing layer 3 can be removed in step S106, or before performing step S105. When the photolithography processing layer 3 is a dielectric hard mask or photoresist material, it can be used as a part of the top dielectric sublayer 21, so that the patterned photolithography processing layer 3 can be removed in step S106, or before performing step S105, or it can be directly retained for separating different conductive structures 51 after step S106.

[0079] In this embodiment, the photolithography processing layer 3 is a dielectric hard mask, and its material is at least one of silicon nitride and silicon oxide, but is not limited thereto. Before depositing a conductive material to form a conductive layer 5 covering the dielectric layer 2, the method further includes: removing the patterned photolithography processing layer 3.

[0080] In an optional embodiment, when the material of the photolithography processing layer 3 is an insulating material, such as at least one of a photoresist material and a dielectric hard mask material, the step of planarizing the conductive layer 5 so that the conductive layer 5 forms at least two independent conductive structures 51 includes: planarizing the conductive layer 5 to expose the photolithography processing layer 3 or the top dielectric sublayer 21.

[0081] In an optional embodiment, when the material of the photolithography processing layer 3 is a conductive material, such as a metal hard mask material, the step of planarizing the conductive layer 5 so that the conductive layer 5 forms at least two independent conductive structures 51 includes: planarizing the conductive layer 5 to expose the top dielectric sublayer 21.

[0082] Step S106: planarize the conductive layer 5 so that the conductive layer 5 forms at least two mutually independent conductive structures 51, see Fig. 9 and Fig.10 .

[0083] In this embodiment, the conductive layer 5 is planarized until the top dielectric sublayer 21 is exposed, that is, the stop position of the planarized conductive layer 5 does not exceed the lower surface of the top dielectric sublayer 21 .

[0084] It should be noted that after executing step S106 , a dielectric material covering the conductive structure 51 and the second preliminary dielectric layer 22 may be deposited to form a protective layer; the conductive structure 51 is connected to the write circuit in the spin-orbit moment magnetic memory through the protective layer.

[0085] The method for preparing the spin-orbit moment magnetic memory provided in this embodiment patterns the photolithography processing layer 3 by photolithography, and etches the dielectric layer 2 according to the patterned photolithography processing layer 3, so that the conductive interconnection of the SOT layer 12 can be achieved by only one photolithography process, which simplifies the process flow and reduces the production cost of the bottom pinned SOT-MRAM. At the same time, the wire structure is realized by the first hard mask, which can effectively control the contact area between the conductive structure 51 and the SOT layer 12, and ensure that the current density flowing through the SOT layer 12 is large enough. In addition, retaining part or all of the top dielectric sublayer 21 in the etched dielectric layer 2 can avoid damage to the effective part of the SOT layer 12 covered by the top dielectric sublayer 21.

[0086] In a second aspect, an embodiment of the present invention provides a method for preparing a spin-orbit moment magnetic memory. Based on the method for preparing a spin-orbit moment magnetic memory provided in the first aspect, the preparation method in this embodiment includes steps S201 to S206:

[0087] Step S201: forming a laminated unit 1 and a dielectric layer 2 covering the laminated unit 1 on a substrate 6, see Figure 1 .

[0088] Step S202 : forming a photolithography processing layer 3 on the dielectric layer 2 .

[0089] Step S203: patterning the photolithography processing layer 3 to form at least two mutually independent electrical interconnection grooves 31 on the photolithography processing layer 3, see Fig.14 and Fig.15 .

[0090] Each electrical interconnection trench 31 only overlaps a portion of the side dielectric sublayer 23 along the up-down direction, and the sidewall of the electrical interconnection trench 31 overlaps the sidewall of the SOT layer 12 along the up-down direction.

[0091] Step S204: Etching the dielectric layer 2 according to the patterned photolithography processing layer 3 to expose the sidewall of the SOT layer 12, see Fig.14 .

[0092] Step S205 : depositing a conductive material to form a conductive layer 5 covering the dielectric layer 2 .

[0093] Step S206: planarize the conductive layer 5 so that the conductive layer 5 forms at least two mutually independent conductive structures 51, see Fig.15 .

[0094] The method for preparing the spin-orbit moment magnetic memory provided in the second aspect is different from that in the first aspect in that the specific implementation methods of the two process steps are different, as follows:

[0095] The first process different from the first aspect is that the electrical interconnection trench 31 formed in step S203 is relative to the top dielectric sublayer 21. In this embodiment, the electrical interconnection trench 31 formed by the patterned photolithography process layer 3 overlaps with a portion of the first preliminary dielectric sublayer 221 and a portion of the second preliminary dielectric sublayer 222 in the vertical direction.

[0096] The second process is different from the first process in that the etching position of step S204 is different, and only the sidewall of the SOT layer 12 is exposed. It can be understood that the second process is different from the first process due to the first process, and this embodiment will not be described in detail.

[0097] In a third aspect, an embodiment of the present invention provides a spin-orbit torque magnetic memory, and the spin-orbit torque magnetic memory is obtained by using any of the methods described above.

[0098] The spin-orbit moment magnetic memory provided by the present embodiment has a small number of photolithography times and a simple manufacturing process, thereby reducing the manufacturing cost of the spin-orbit moment magnetic memory.

[0099] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0100] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for preparing a spin-orbit moment magnetic memory, characterized in that: include: A stacked unit (1) and a dielectric layer (2) covering the stacked unit (1) are formed on a substrate (6); the stacked unit (1) comprises, from bottom to top, a magnetic tunnel junction (11) and a SOT layer (12); the dielectric layer (2) comprises a top dielectric sublayer (21) overlapping the SOT layer (12) in the up-down direction and a side dielectric sublayer (23) located around the stacked unit (1); forming a photolithography processing layer (3) on the dielectric layer (2); The photolithography processing layer (3) is patterned to form at least two mutually independent electrical interconnection grooves (31) on the photolithography processing layer (3); wherein each of the electrical interconnection grooves (31) overlaps with a portion of the top dielectric sublayer (21) and a portion of the side dielectric sublayer (23) along the up-down direction, or each of the electrical interconnection grooves (31) overlaps with a portion of the side dielectric sublayer (23) along the up-down direction, and the sidewalls of the electrical interconnection grooves (31) overlap with the sidewalls of the SOT layer (12) along the up-down direction; The dielectric layer (2) is etched according to the patterned photolithography processing layer (3) so that when the electrical interconnection groove (31) overlaps with a part of the top dielectric sublayer (21) and a part of the side dielectric sublayer (23) in the up-down direction, respectively, the upper surface of the SOT layer (12) is exposed, or when the electrical interconnection groove (31) overlaps with a part of the side dielectric sublayer (23) in the up-down direction and the side wall of the electrical interconnection groove (31) overlaps with the side wall of the SOT layer (12) in the up-down direction, the side wall of the SOT layer (12) is exposed; Depositing a conductive material to form a conductive layer (5) covering the dielectric layer (2); The conductive layer (5) is planarized so that the conductive layer (5) forms at least two mutually independent conductive structures (51).

2. The method according to claim 1, characterized in that Before the step of depositing a conductive material to form a conductive layer (5) covering the dielectric layer (2), the method further comprises: removing the patterned photolithography processing layer (3); The material of the photolithography processing layer (3) includes: photoresist material, metal hard mask material or dielectric hard mask material.

3. The method according to claim 1, characterized in that When the material of the photolithography processing layer (3) is an insulating material, the step of planarizing the conductive layer (5) so that the conductive layer (5) forms at least two mutually independent conductive structures (51) comprises: The conductive layer (5) is planarized to expose the photolithography processing layer (3) or the top dielectric sublayer (21).

4. The method according to claim 1, characterized in that: When the material of the photolithography processing layer (3) is a conductive material, the step of planarizing the conductive layer (5) so that the conductive layer (5) forms at least two mutually independent conductive structures (51) comprises: The conductive layer (5) is planarized to expose the top dielectric sublayer (21).

5. The method according to claim 1, characterized in that The step of forming a stacked unit (1) on a substrate (6) and a dielectric layer (2) covering the stacked unit (1) comprises: A stacked structure, a first preliminary dielectric layer (2) and a hard mask layer (4) are sequentially deposited on the substrate (6), wherein the stacked structure is used to form the SOT layer (12) and the magnetic tunnel junction (11); Patterning the hard mask layer (4), and etching the first preliminary dielectric layer (2) and the stacked structure according to the patterned hard mask layer (4) to form the top dielectric sublayer (21), the SOT layer (12), and the magnetic tunnel junction (11); Depositing a second preliminary dielectric layer (22) covering the magnetic tunnel junction (11); The second preliminary dielectric layer (22) is planarized to remove the hard mask layer (4) and obtain the side dielectric sublayer (23).

6. The method according to claim 5, characterized in that The step of depositing a second preliminary dielectric layer (22) covering the magnetic tunnel junction (11) comprises: sequentially depositing a first preliminary dielectric sublayer (221) and a second preliminary dielectric sublayer (222) covering the magnetic tunnel junction (11); The step of etching the dielectric layer (2) according to the patterned photolithography processing layer (3) comprises: The first preliminary dielectric sublayer (221) is etched, and the etching stop position of the first preliminary dielectric sublayer (221) is higher than the lower surface of the SOT layer (12).

7. The method according to claim 5, characterized in that The material of the hard mask layer (4) includes: at least one of tantalum, titanium, tantalum nitride and titanium nitride; The shape of the patterned hard mask layer (4) includes: circle, ellipse, rectangle, diamond or triangle; The material of the first preliminary dielectric sublayer (221) includes silicon nitride, and the material of the second preliminary dielectric sublayer (222) includes silicon oxide.

8. The method according to claim 1, characterized in that The step of etching the dielectric layer (2) according to the patterned photolithography processing layer (3) comprises: According to the patterned photolithography processing layer (3), the dielectric layer (2) is etched by reactive ion etching or ion beam etching.

9. The method according to claim 1, characterized in that: The material of the top dielectric sublayer (21) includes at least one of silicon oxide, silicon nitride, silicon oxynitride and silicon oxycarbide.

10. A spin-orbit moment magnetic memory, characterized in that: The spin-orbit torque magnetic memory is prepared by the method according to any one of claims 1 to 9.

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