LED light emitting diode and preparation method thereof

Abstract

The present invention discloses an LED light-emitting diode and a preparation method thereof, and relates to the technical field of an LED chip. The LED light-emitting diode comprises an epitaxial layer placed on a substrate; a current blocking layer placed on the epitaxial layer; a transparent conductive layer placed on the current blocking layer; a metal electrode layer placed above the transparent conductive layer; the current blocking layer forms a raised morphology by etching. The morphology uses a mask to expose a wafer coated with photoresist. After exposure, a developer is used to remove the photoresist in the exposed area to form a pattern corresponding to the mask pattern. An etching process is used to etch away the current blocking layer removed from the top layer of the wafer through the photoresist opening to form a raised morphology. While retaining the original current blocking operation, the core particle light-emitting area is increased to achieve a higher light-emitting efficiency of the chip.

Description

Technical Field

[0001] This invention relates to the technical field of LED chips, specifically LED light-emitting diodes and their fabrication methods. Background Technology

[0002] In the design and manufacturing of LED chips, adding a current blocking layer (CBL) can cut off the current, causing it to flow entirely into the transparent conductive layer (TCL), and then through the TCL into the GaN layer directly beneath it. Without a current blocking layer, some current flows into the TCL and then into the GaN layer, while some flows directly into the GaN layer and quantum well for light emission. The light emitted from the quantum well is largely blocked by the electrodes; this light is either reflected or absorbed. A significant portion of the reflected light is also absorbed after multiple reflections within the chip, resulting in very little light actually escaping. With the addition of a current blocking layer, the current flowing directly into the P-GaN layer directly beneath the P-pad is blocked, allowing all the current to diffuse directly through the transparent conductive layer to the effective light-emitting area. This increases the current density in the effective light-emitting area, improves current utilization, and ultimately enhances the chip's brightness.

[0003] In existing technologies, CB-SiO2 with P-GaN or N-GaN contacts is commonly used as a current-blocking layer in P- or N-PAD designs, but its light-transmitting properties are often overlooked. Patent CN103311382B discloses an LED chip and its fabrication method. This method primarily uses a sol-gel process to prepare a porous SiO2 film as a current-blocking layer. This improves upon the P-GaN damage caused by plasma during PECVD deposition of silicon dioxide in existing technologies, which leads to increased operating voltage and fails to reduce light absorption at the P-electrode. Due to the presence of the porous SiO2 film, light emitted from the quantum well is reflected and refracted multiple times, with some light escaping from the side of the current-blocking layer, reducing P-electrode light absorption and thus improving chip brightness. However, the sol-gel method is difficult to control in terms of morphology, and the fabrication process is not stable enough, resulting in poor process repeatability. Summary of the Invention

[0004] To address the issues of limited light emission and low light emission efficiency in existing chip solutions, this invention provides an LED light-emitting diode and its fabrication method. By optimizing the morphology of the current blocking layer, the light-emitting area of ​​the chip is increased while retaining its original current blocking function, thereby achieving higher light emission efficiency. The technical solution is as follows.

[0005] An LED light-emitting diode, comprising: An epitaxial layer placed on a substrate; A current blocking layer placed on the epitaxial layer; A transparent conductive layer placed on the current blocking layer; A metal electrode layer positioned above the transparent conductive layer; The current blocking layer is etched to form a raised morphology.

[0006] Furthermore, the outermost layer is an insulating protective layer.

[0007] Furthermore, the epitaxial layer includes N-GaN, quantum well, and P-GaN, and the epitaxial layer is etched to expose N-GaN; the transparent conductive layer is ITO.

[0008] Furthermore, the current blocking layer is SiO2 or SiNx, and the thickness of the current blocking layer is 500~5000 Å.

[0009] Furthermore, the protrusion has a stepped or yurt-like shape.

[0010] Furthermore, the metal electrode layer comprises an adhesion layer, a structural layer, and a conductive layer. The adhesion layer is selected from Cr, Ni, and Ti; the structural layer is selected from Al, Cr, Ti, Pt, and Ni; and the conductive layer is selected from Cu, Al, Sn, and AuSn.

[0011] A method for fabricating an LED light-emitting diode, comprising the following steps: (1) An epitaxial layer is prepared on a substrate; (2) A current blocking layer is prepared on the epitaxial layer, and then a photoresist is coated on the surface of the current blocking layer. The wafer coated with photoresist is exposed using a mask. After exposure, the photoresist in the exposed area is removed using a developer to form a pattern corresponding to the mask pattern. The current blocking layer removed through the photoresist opening on the top layer of the wafer is etched away using an etching process to form a raised morphology. (3) Deposit a transparent conductive layer on the current blocking layer; (4) Fabrication of a metal electrode layer on a transparent conductive layer: (5) Prepare an insulating protective layer for the outermost layer.

[0012] Furthermore, the mask template has circular or elliptical holes.

[0013] Furthermore, the diameter of the hole is 8µm to 50µm, and the distance between the holes is 5µm to 100µm.

[0014] Furthermore, the etching process is either wet etching or dry etching.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The chip is designed with hole-shaped, elliptical, or other irregular shapes. The hole diameter is controlled between 8um and 50um, and the spacing between holes is controlled between 5 and 100um. The pattern is created by photolithography, and the CB-SiO2 stepped or yurt-shaped morphology is formed by etching. While retaining the original current blocking operation, the chip light-emitting area is increased, resulting in higher chip light emission efficiency.

[0016] The manufacturing process described in this application is mature and can improve the light extraction efficiency of LED chips. Attached Figure Description

[0017] Figure 1 This is a structural diagram of existing technology; Figure 2 This is a structural diagram of the present invention; Figure 3 This is a magnified view of a portion of the image.

[0018] 1 is the substrate, 2 is the epitaxial layer, 3 is the current blocking layer (protrusion), 4 is the transparent conductive layer, 5 is the metal electrode layer, and 6 is the insulating protective layer. Detailed Implementation

[0019] The technical solution of the present invention will be further explained below with reference to the accompanying drawings.

[0020] The concept of "above" or "on top" in this invention refers to a spatial concept. For example, an epitaxial layer placed on a substrate is not limited to the epitaxial layer being in direct contact with the substrate; it may also include a buffer layer between the substrate and the epitaxial layer.

[0021] The technical solution of the present invention is as follows Figure 2 As shown, an LED light-emitting diode includes the following structure: An epitaxial layer 2 is disposed above the substrate 1, and a current blocking layer 3 is disposed above the epitaxial layer 2. The current blocking layer 3 is etched to form a raised morphology. A transparent conductive layer 4 is disposed above the current blocking layer 3. A metal electrode layer 5 is disposed above the transparent conductive layer 4. The outermost layer of the LED light-emitting diode is an insulating protective layer 6, which exposes the electrode solder joints.

[0022] The epitaxial layer 2 comprises N-GaN, a quantum well, and P-GaN, and the epitaxial layer 2 is etched to expose the N-GaN. The current blocking layer 3 is SiO2 or SiNx. The transparent conductive layer 4 is ITO.

[0023] The method for preparing an LED light-emitting diode includes the following steps: (1) An epitaxial layer 2 is prepared on the substrate 1, and the bottom layer of the epitaxial layer 2 is exposed by etching; (2) A current blocking layer 3 is prepared above the epitaxial layer 2, and then a layer of photoresist is coated on the surface of the current blocking layer 3. A photomask is used to expose the wafer coated with photoresist. After exposure, the photoresist in the exposed area is removed by the developer to form a pattern corresponding to the photomask pattern. The current blocking layer 3 to be removed is etched away through the photoresist opening on the top layer of the wafer to form a raised morphology. The thickness of the SiO2 or SiNx is 500~5000 Å. The photomask has circular or elliptical holes. The diameter of the holes is 8µm~50µm, and the spacing between the holes is 5~100µm. The etching process is wet etching or dry etching. The morphology is stepped or yurt-like. (The morphology is as follows...) Figure 3 As shown.

[0024] (3) Deposit a transparent conductive layer 4 on the epitaxial layer 2; (4) Fabricate a metal electrode layer 5 on the transparent conductive layer 4: (5) Prepare an insulating protective layer 6 on the outermost layer to expose the electrode solder joints.

[0025] The transparent conductive layer 4 is ITO, allowing for lateral current propagation on the P-GAN surface. Metal electrodes are fabricated on the epitaxial layer 2, including metal fingers through which current propagates laterally on the surface of the transparent conductive layer 4. The structure comprises an adhesion layer, a structural layer, and a conductive layer. The adhesion layer is selected from Cr, Ni, and Ti; the structural layer is selected from Al, Cr, Ti, Pt, and Ni; and the conductive layer is selected from Cu, Au, Sn, and AuSn. An insulating protective layer 6 is fabricated on the chip surface, exposing the P / N electrode solder joints.

[0026] Existing technologies such as Figure 1 As shown, unlike the embodiments described above, CB-SiO2 is only used as the current blocking layer 3 and does not produce a stepped or yurt-like morphology through etching, which would result in a certain degree of brightness loss. After testing, taking a 28*48mil chip as an example, with a test current of 60mA and using probe testing technology, the probe contacts the LED chip electrode to perform electrical measurements. The test current was set to 60mA, and the brightness output was 159.0mW, which was used as a comparison benchmark. Example

[0027] Based on the aforementioned embodiments, the SiO2 thickness is 2000 Å to 3000 Å, with circular holes of 8-24 μm diameter and a spacing of 15-30 μm, exhibiting a stepped morphology. All other parameters are the same as described above.

[0028] After testing, taking a 28*48mil chip as an example, using probe testing technology, the probe contacts the LED chip electrode to perform electrical measurements. With a test current of 60mA, the brightness output is 162.19mW, while the original process brightness output is 159.0mW, meaning the brightness can be increased by 2.19mW. Example

[0029] Based on the aforementioned embodiments, the SiO2 thickness is 2000 Å to 3000 Å, elliptical holes are used, the hole diameter is 8 to 24 μm, the hole spacing is 30 to 50 μm, and the morphology is stepped. All other parameters are the same as those described above.

[0030] After testing, taking a 28*48mil chip as an example, using probe testing technology, the probe contacts the LED chip electrode to perform electrical measurements. With a test current of 60mA, the brightness output is 160.60 mW, while the original process brightness output is 159.0mW, meaning the brightness can be increased by 1.60mW. Example

[0031] Based on the aforementioned embodiments, the SiO2 thickness is 2000 Å to 3000 Å, with circular holes of 8 to 24 μm in diameter and 50 to 100 μm in spacing, exhibiting a stepped morphology. All other parameters are the same as those described above.

[0032] After testing, taking a 28*48mil chip as an example, using probe testing technology, the probe contacts the LED chip electrode to perform electrical measurements. With a test current of 60mA, the brightness output is 160.05mW, while the original process brightness output is 159.0mW, meaning the brightness can be increased by 1.05mW. Example

[0033] Based on the aforementioned embodiments, the SiO2 thickness is 2000 Å to 3000 Å, with circular holes, a hole spacing of 15 to 30 μm, a hole diameter of 24 to 36 μm, and a stepped morphology. All other parameters are the same as those described above.

[0034] Taking a 28*48mil chip as an example, using probe testing technology, the probe contacts the LED chip electrode to perform electrical measurements. The test current is set to 60mA, and the brightness output is 161.70 mW. The original process brightness output is 159.0mW, so the brightness can be increased by 1.70mW. Example

[0035] Based on the aforementioned embodiments, the SiO2 thickness is 2000 Å to 3000 Å, with circular holes, a hole spacing of 15 to 30 μm, a hole diameter of 36 to 50 μm, and a stepped morphology. All other parameters are the same as those described above.

[0036] After testing, taking a 28*48mil chip as an example, using probe testing technology, the probe contacts the LED chip electrode to perform electrical measurements. With a test current of 60mA, the brightness output is 160.43mW, while the original process brightness output is 159.0mW, meaning the brightness can be increased by 1.43mW. Example

[0037] Based on the aforementioned embodiments, the SiO2 thickness is 500 Å to 2000 Å, with circular holes, a hole spacing of 15 to 30 μm, a hole diameter of 24 to 36 μm, and a stepped morphology. All other parameters are the same as those described above.

[0038] After testing, taking a 28*48mil chip as an example, using probe testing technology, the probe contacts the LED chip electrode to perform electrical measurements. With a test current of 60mA, the brightness output is 160.21mW, while the original process brightness output is 159.0mW, meaning the brightness can be increased by 1.21mW. Example

[0039] Based on the aforementioned embodiments, the SiO2 thickness is 3000~5000 Å, with circular holes, a hole spacing of 15~30 μm, a hole diameter of 24~36 μm, and a yurt-like morphology. All other parameters are the same as those described above.

[0040] Taking a 28*48mil chip as an example, using probe testing technology, the probe contacts the LED chip electrode to perform electrical measurements. The test current is set to 60mA, and the brightness output is 160.19mW, while the original process brightness output is 159.0mW, so the brightness can be increased by 1.19mW.

[0041] Table 1 Test parameters and results for each embodiment type LOP (brightness) / mW VF (voltage) / V WD (dominant wavelength) / nm Example 1 162.19 2.689 455.37 Example 2 160.60 2.686 455.39 Example 3 160.05 2.683 455.45 Example 4 161.70 2.688 455.40 Example 5 160.43 2.685 455.43 Example 6 160.21 2.684 455.40 Example 7 160.19 2.683 455.38 The comparative analysis in Table 1 shows that Example 1 is the optimal example. All other examples show varying degrees of brightness improvement.

Claims

1. An LED light emitting diode, characterized in that: Include: an epitaxial layer disposed on a substrate; a current blocking layer disposed on the epitaxial layer; a transparent conductive layer disposed on the current blocking layer; A metal electrode layer disposed on the transparent conductive layer; The current blocking layer is formed into a protruding morphology by etching.

2. The LED light emitting diode according to claim 1, characterized in that: The outermost layer of the LED light emitting diode is an insulating protective layer.

3. The LED light emitting diode according to claim 1, characterized in that: The epitaxial layer includes N-GaN, quantum wells, and P-GaN. The epitaxial layer is etched to expose the N-GaN. The transparent conductive layer is ITO.

4. The LED light emitting diode according to claim 1, characterized in that: The current blocking layer is SiO2 or SiNx, and the thickness of the current blocking layer is 500-5000A.

5. The LED light emitting diode according to claim 1, characterized in that: The protrusion has a step-like or yurt-like shape.

6. The LED light emitting diode according to claim 1, characterized in that: The metal electrode layer comprises an adhesion layer, a structural layer and a conductive layer. The adhesion layer is selected from Cr, Ni and Ti; the structural layer is selected from Al, Cr, Ti, Pt and Ni; and the conductive layer is selected from Cu, Au, Sn and AuSn.

7. A method for preparing an LED light emitting diode, characterized in that: The preparation of the LED light emitting diode according to any one of claims 1 to 6 comprises the following steps: (1) Preparing an epitaxial layer on a substrate; (2) preparing a current blocking layer on the epitaxial layer, then coating a layer of photoresist on the surface of the current blocking layer, using a mask to expose the wafer coated with the photoresist, after exposure, using a developer to remove the photoresist in the exposed area to form a pattern corresponding to the mask pattern, and using an etching process to etch the current blocking layer removed from the top layer of the wafer through the photoresist opening to form a raised morphology; (3) depositing a transparent conductive layer on the current blocking layer; (4) Preparing a metal electrode layer on the transparent conductive layer.

8. The method for preparing an LED light emitting diode according to claim 7, characterized in that: The mask plate has circular or elliptical holes.

9. The method for preparing an LED light emitting diode according to claim 8, characterized in that: The diameter of the holes is 8um-50um, and the distance between the holes is 5-100um.

10. The method for preparing an LED light emitting diode according to claim 7, characterized in that: The etching process is wet etching or dry etching.

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