Corticoelectroencephalogram electrode array and preparation method thereof

Abstract

The invention discloses a cortical electroencephalogram electrode array and a preparation method thereof.The cortical electroencephalogram electrode array comprises a top polymer insulating layer, a middle metal layer and a bottom polymer insulating layer, the top polymer insulating layer is provided with small holes used for exposing electrode points and welding spots, the middle metal layer comprises an electrode array, and the bottom polymer insulating layer is provided with small holes used for exposing the electrode points and the welding spots. And the shape of the electrode array is matched with the shape of the surface of the nearly whole cortex. The electrode array can collect brain wave signals of a certain behavior in a near-full cortex range.

Description

Technical Field

[0001] The invention belongs to the technical field of implantable electrode manufacturing, and in particular relates to a cortical electroencephalogram electrode array and a preparation method thereof. Background Art

[0002] With the development of medicine, neuroscience and brain-computer interface technology, the demand for large-scale, multi-dimensional recording of neuronal activities is increasing. Implantable electrocorticography (ECoG) electrode arrays can instantly capture high-frequency action potentials of neurons, with extremely high temporal resolution and strong spatial resolution. They are a useful tool for diagnosing epilepsy in the medical field, and with the development of neural electrical stimulation and optogenetics research, they are expected to promote a new paradigm of brain photoelectric stimulation in clinical practice.

[0003] The invention patent application with publication number CN118592963A discloses an ECoG electrode and a method for preparing the same. The implantable electrode of the present invention includes a flexible support layer, an electrode metal layer and a packaging layer, wherein the electrode metal layer includes an electrode contact array area, a pad area and a conductive wire; the electrode contact array area contains one or more electrode contacts, and the pad area contains one or more solder joints; each of the electrode contacts and a corresponding solder joint is connected by a conductive wire to form a connection path, and different connection paths are electrically isolated from each other. The present invention arranges different materials on the exposed surfaces of the electrode contacts and solder joints so that different materials can give full play to their respective advantages, which not only optimizes the electrode performance, but also helps to maintain the consistency of signal transmission. At the same time, the manufacturing process required for the electrode is relatively simple, the cost is lower, and it is more environmentally friendly.

[0004] The invention patent application with the publication number CN107157478A discloses a multi-channel cortical electroencephalogram acquisition system based on capacitive electrodes, which is used to realize ECoG signal acquisition; the invention includes a capacitive array microelectrode, a front impedance conversion module, an analog amplifier circuit module, an AD conversion module, a main control chip, a computer host computer and a mobile power supply; the capacitive array microelectrode couples the cortical electroencephalogram signal, and after the impedance conversion by the front impedance conversion module, the signal is amplified and processed by the analog amplifier circuit module, and then the data is converted by the AD conversion module and transmitted to the main control chip, and the main control chip forms a data packet and transmits it to the computer host computer via a serial port for display and analysis. The present invention uses a capacitive array microelectrode to collect ECoG signals, which has the characteristics of small stimulation and high spatial resolution, and can realize multi-channel parallel high-precision acquisition of ECoG signals, filter out high-frequency signals, and completely extract cortical electroencephalograms.

[0005] However, the subdural cortical electrodes (ECoG) disclosed in the above patent application are basically square or rectangular, and can only record local brain areas. It is impossible to monitor the dynamic network of the entire cortex of a mouse with a certain behavior. The electrode shapes disclosed in the prior art are regular shapes, but the brain surface of a mouse is irregular, so some areas cannot be covered and cause signal loss. Summary of the invention

[0006] The present invention provides a cortical electroencephalogram electrode array, which can collect brain wave signals of a certain behavior in a nearly entire cortical surface range.

[0007] The present invention provides a cortical electroencephalogram electrode array, comprising a top polymer insulating layer, an intermediate metal layer and a bottom polymer insulating layer, wherein the top polymer insulating layer is provided with small holes for exposing electrode points and welding points;

[0008] The middle metal layer comprises an electrode array, and the shape of the electrode array matches the shape of the nearly entire cortical surface.

[0009] Preferably, the shape of the electrode array is matched with the shape of the nearly entire cortical surface by the following method, including:

[0010] Two-photon microscopy or nuclear magnetic resonance imaging is used to image nearly the entire cortex, and the dimensional data of the electrode array are obtained through the dimensional data of the nearly entire cortical surface imaging map, so that the shape of the electrode array matches the shape of the nearly entire cortical surface.

[0011] Through the above method, the electrode array provided by the present invention can form a corresponding shape based on the irregular image of the nearly entire cortical surface. Since the present invention arranges electrode points in the nearly entire cortex, compared with the arrangement of electrode points in part of the brain region in the prior art, the electrode point arrangement has a smaller tolerance space. Based on the irregular image of the nearly entire cortical surface obtained first, the present invention can reasonably arrange electrode points on the nearly entire cortex with a smaller tolerance space, thereby covering the brain wave information of each brain region. The near-cortical surface provided by the present invention can be understood as including the surface of each brain region, but some edge areas of the whole brain are not included. The reason is that in the anatomical structure of the mouse cerebral cortex, a small part of the cortex is curled downward and is not directly above the brain surface. This part of the cortex cannot be exposed in actual craniotomy, thus limiting the coverage of the flexible electrode in this small part of the cortex.

[0012] Preferably, relatively dense electrode points are arranged in brain areas with higher functional density, and relatively sparse electrode points are arranged in brain areas with lower functional density.

[0013] The specific embodiment of the present invention arranges electrode points with different densities in different brain regions based on the density of functions performed by each brain region. The denser the functions performed in the brain region, the denser the electrode points are arranged. The limited number of electrode channels can be used to collect as much EEG information of the key brain regions as possible, thereby enriching the whole brain cortical network connection.

[0014] Preferably, when the shape of the electrode array matches the shape of the nearly entire cortical surface of the mouse, the spacing between the electrode points arranged in the prefrontal cortex and the cerebellar cortex is smaller than the spacing between the electrode points arranged in the motor cortex and the somatosensory cortex.

[0015] Since the prefrontal cortex and cerebellar cortex of mice are relatively important, that is, they are brain areas with relatively dense functions, the corresponding motor cortex and somatosensory cortex occupy a larger area but perform relatively single functions. Therefore, based on the density of functions, the present invention arranges more densely packed electrode points in the prefrontal cortex and cerebellar cortex, that is, the spacing between the electrode points is smaller than the spacing between the electrode points arranged in the motor cortex and somatosensory cortex.

[0016] Preferably, the spacing between the electrode points arranged in the prefrontal cortex and the cerebellar cortex is 200-600 μm, and the spacing between the electrode points arranged in the motor cortex and the somatosensory cortex is 600-1200 μm.

[0017] The present invention controls the spacing between the electrode points arranged in the prefrontal cortex and the cerebellar cortex, so that relatively dense electrode points can be arranged in small areas such as the prefrontal cortex and the cerebellar cortex, thereby realizing the observation of dense functional columns.

[0018] Preferably, the end of the electrode point is in an arc shape. In the prior art, when the electrode is buried, the sharp edges and corners are easy to scratch the cortex. In the present invention, the end of the electrode point is in an arc shape, which causes less damage to the cerebral cortex.

[0019] Preferably, the intermediate metal layer also includes a soldering pad and a wire, the soldering pad includes a plurality of soldering points, each soldering point is connected to a corresponding electrode point through a wire, each soldering point is welded to a PCB, and the brain wave signal is transmitted to an external device through the PCB.

[0020] Preferably, the materials of the top polymer insulating layer and the bottom polymer insulating layer are respectively flexible transparent materials, and the flexible transparent material is parylene-c.

[0021] Preferably, the intermediate metal layer is an ITO flexible material.

[0022] The present invention also provides a method for preparing the electrocortical electroencephalogram electrode array, which is characterized by comprising:

[0023] depositing an aluminum sacrificial layer on a silicon wafer substrate;

[0024] Depositing a parylene-c layer on the aluminum sacrificial layer;

[0025] Coating photoresist on the parylene-c layer, obtaining an intermediate metal layer pattern through masking, exposure, and development, and then depositing and removing the photoresist to obtain the intermediate metal layer, wherein the pattern of the intermediate metal layer is a pattern of an electrode array, a wire, and a pad, the pattern of the electrode array is consistent with a nearly full cortical surface imaging map, and the arrangement pattern of each electrode point in the electrode array is adapted to the density of the functions of each brain region;

[0026] Depositing a parylene-c layer on the intermediate metal layer and the substrate;

[0027] Photolithography and dry etching are used to open holes for electrodes and solder joints;

[0028] Photolithography and dry etching were used to etch out the outline of the cortical EEG electrode array and remove excess parylene-c material;

[0029] The aluminum sacrificial layer was etched away by chemical etching to obtain the electrocorticogram electrode array.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] The shape of the electrode array provided by the present invention matches the shape of the nearly entire cortical surface, so that the shape of the electrode array can cover nearly the entire cortex, thereby enabling the collection of brain wave signals of various brain regions under a certain behavior and avoiding the phenomenon of signal loss due to the inability to cover some areas. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of the structure of an electrocorticogram electrode array provided in a specific embodiment of the present invention;

[0033] Figure 2 A circuit layout diagram of an intermediate metal layer provided in a specific embodiment of the present invention;

[0034] Figure 3 An imaging diagram of the nearly entire cortical surface of a mouse provided in a specific embodiment of the present invention;

[0035] Figure 4 A shape diagram of an electrode array designed based on the size data of an imaging diagram of a nearly entire cortical surface of a mouse provided in a specific embodiment of the present invention;

[0036] Figure 5 A flow chart of a method for preparing a cortical electroencephalogram electrode array provided in a specific embodiment of the present invention.

[0037] Among them, there are a top polymer insulating layer 2, a middle metal layer 1, an electrode array 1-1, an electrode point 1-1-1, a wire 1-2, a pad 1-3, a solder point 1-3-1, and a bottom polymer insulating layer 3. DETAILED DESCRIPTION

[0038] The prior art often focuses on the impact of a certain brain area on a certain behavior, and thus only detects brain wave signals in a certain brain area, but ignores the fact that various brain areas are interconnected. The present invention achieves coverage of various brain areas by matching the shape of the electrode with the shape of nearly the entire cortex, and can detect the EEG signals of various brain areas under a certain behavior.

[0039] A specific embodiment of the present invention provides a cortical electroencephalogram electrode array, such as Figure 1 As shown, it includes a top polymer insulating layer 2, an intermediate metal layer 1 and a bottom polymer insulating layer 3. The intermediate metal layer 1 is wrapped by the top polymer insulating layer 2 and the bottom polymer insulating layer 3. The top polymer insulating layer is provided with small holes for exposing electrode points and welding points. The intermediate metal layer, as shown Figure 2 The method comprises an electrode array 1-1, a wire 1-2 and a pad 1-3. The shape of the electrode array 1 matches the shape of the nearly entire cortical surface. The nearly entire cortical surface shape is obtained by imaging the nearly entire cortex through a two-photon microscope or magnetic resonance imaging. The nearly entire cortex provided in the specific embodiment of the present invention can be understood as being close to or covering most areas of the cerebral cortex. The specific embodiment of the present invention constructs the shape of the electrode array based on the shape of the nearly entire cortex. In the case of a small fault tolerance space, it is possible to arrange various electrode points on the nearly entire cortex, so as to detect brain wave signals of various brain regions under a certain behavior and provide information support for the connection between various brain regions.

[0040] The electrode array provided in a specific embodiment of the present invention includes multiple electrode points 1-1-1, and the pad 1-3 includes multiple welding points 1-3-1. Each electrode point 1-1-1 is connected to the corresponding welding point 1-3-1 through a wire 1-2, and each welding point 1-3-1 is welded to the PCB, and the brain wave signal is transmitted to the external device through the PCB.

[0041] In the specific embodiment of the present invention, when arranging the electrode points, the electrode points are arranged more densely in the brain area with higher function density, and the electrode points are arranged more sparsely in the brain area with lower function density. It can be understood that the meaning of function density is that this brain area is involved in regulating multiple functions. By using the above arrangement of electrode points, the EEG information of the key brain area can be collected as much as possible with a limited number of electrode channels, thereby enriching the whole brain cortical network connection.

[0042] In a specific embodiment, the specific steps of obtaining the shape of a 64-channel ECoG electrode array based on the data size of the nearly entire cortical surface of a mouse are as follows:

[0043] like Figure 3 and Figure 4 As shown, the present invention first uses a two-photon microscope to image nearly the entire cortex of a standard C57 experimental mouse to obtain a nearly entire cortical surface image of the mouse, and designs the specific size of the electrode array based on the size data of the nearly entire cortical surface image of the mouse, such as Figure 3 A and C, the electrodes are densely arranged in the frontal cortex area in the front and the cerebellar cortex area in the back, such as Figure 3 In B, the electrodes are arranged relatively sparsely in the middle somatosensory cortex and motor cortex, and no electrodes are arranged on the central sagittal vein. There is no signal on the surface of the blood vessels, and once the blood vessel wall is damaged by the electrode, it will cause severe intracranial hemorrhage and affect the function of the electrode.

[0044] Specifically, the spacing between the electrodes arranged in the prefrontal cortex and the cerebellar cortex is 200-600 μm, and the spacing between the electrodes arranged in the motor cortex and the somatosensory cortex is 600-1200 μm.

[0045] The end of the electrode point provided in the specific embodiment of the present invention is in an arc shape. When the existing electrode is buried, the sharp edges and corners of the end are easy to scratch the cortex. The specific embodiment of the present invention uses the arc-shaped end to reduce the loss of the cortex.

[0046] In a specific embodiment, the diameter of the electrode point sampled in this embodiment is 100 microns, which is suitable for the recording and observation size of the rhesus monkey functional column. The electrode arrangement position provided in the specific embodiment of the sampling invention is an electrode array specially designed based on the 7T nuclear magnetic resonance imaging of the experimental monkey functional column and the experimental purpose. This electrode array can realize for the first time the simultaneous recording of electrical signals, optical imaging or stimulation, and functional nuclear magnetic resonance imaging of a single functional column and other experimental requirements.

[0047] The top polymer insulating layer and the bottom polymer insulating layer provided in the specific embodiment of the present invention are made of flexible transparent materials, the flexible transparent material is parylene-c, and the middle metal layer is ITO flexible material. The present invention uses transparent flexible materials to obtain a full-cortical electroencephalogram electrode array that combines conductivity, permeability, flexibility and biocompatibility.

[0048] A specific embodiment of the present invention also provides a method for preparing the electrocortical electroencephalogram electrode array, comprising:

[0049] (1) Figure 5As shown in 5-1, first prepare a 4-inch silicon wafer as substrate a. In order to ensure the quality of subsequent processes, the silicon wafer must be strictly cleaned. The specific operation is: ultrasonic vibration in acetone for 5 minutes to remove organic pollutants, ultrasonic vibration in isopropanol again for 5 minutes to further clean the surface, then rinse with ultrapure water and blow dry with nitrogen. Finally, place the silicon wafer in an oven at 105°C for 4 minutes to ensure that it is completely dry and no moisture remains.

[0050] (2) Figure 5 As shown in Figure 5-2, a 100nm thick aluminum film b is deposited on a silicon wafer substrate using a magnetron sputtering device as a sacrificial layer. The reason for choosing aluminum is that it has good adhesion to the silicon wafer and is not easy to fall off; at the same time, aluminum also has good adhesion to the parylene-C film c, and can be easily removed by chemical corrosion in subsequent steps, so it is one of the ideal sacrificial layer materials. In addition, the thickness of the aluminum layer has been optimized to provide sufficient structural support without affecting the deposition quality of subsequent layers. This layer plays a key role in the final device release, allowing the transparent flexible electrode to be completely peeled off from the silicon wafer substrate without damaging the electrode itself.

[0051] (3) Figure 5 As shown in 5-3, a layer of parylene-C film c with a thickness of 5 μm is deposited on the aluminum sacrificial layer using an evaporation device. Parylene-C film c is one of the preferred insulating materials in the present invention due to its high transparency, excellent insulation and sealing properties, and strong flexibility. The deposition process of parylene-C film c requires highly precise control of temperature and pressure to ensure that the film evenly covers the entire surface of the silicon wafer without pinholes or other defects. The parylene-C film c formed in this step is not only the base of the subsequent intermediate metal layer, but also plays an important role in protecting the internal circuit from environmental factors in the final product.

[0052] (4) Figure 5As shown in 5-4, a 5350 photoresist is used to form the desired intermediate metal layer pattern on the parylene-C layer c through masking, alignment exposure and development and other photolithography processes. The pattern includes an electrode array 1, a wire 2 and a pad 3. Then, a 150nm thick indium tin oxide (ITO) d is deposited in the above pattern area using a magnetron sputtering device. This is a common transparent conductive material. After the deposition is completed, the sample is placed in acetone for ultrasonic vibration for 5 minutes to peel off the remaining photoresist, thereby obtaining a patterned ITO intermediate metal layer d. The pattern of the intermediate metal layer is the pattern of the electrode array, the wire and the pad. The pattern of the electrode array is consistent with the imaging map of the nearly entire cortical surface. The arrangement pattern of each electrode point in the electrode array is adapted to the density of the function of each brain region. This process requires special attention to the selection of photoresist and the uniformity of coating, because they directly determine the accuracy and reliability of the final conductor layer pattern. In addition, the thickness of the ITO layer is also carefully designed to balance the relationship between transparency and conductivity to ensure optimal optical and electrical performance.

[0053] (5) Figure 5 As shown in 5-5, the evaporation equipment is used again to deposit another 5μm thick parylene-C film c on the entire device (including the newly formed intermediate metal layer and the original substrate). This layer of parylene-C film c mainly plays the role of insulation and sealing, protecting the internal structure from the external environment. This step repeats the previous parylene-C film c deposition process, but this time it is to encapsulate the already formed conductor layer to prevent it from being damaged during subsequent processing or actual application. Similarly, strict control of deposition conditions ensures the quality of the film, so that the final product has excellent durability and stability.

[0054] (6) Figure 5 As shown in 5-6, in order to construct the ITO electrode point 1-1-1 and the ITO solder joint 1-3-1 in the device, a photolithography process is required to form the required opening pattern. In this step, 4620 photoresist is used as a mask for dry etching, and the thickness after spin coating is 9μm, which is used to protect the unexposed area. Then, the inductively coupled plasma (ICP) etching technology is applied to accurately open the metal contact and metal pad. The chemical reaction and physical bombardment generated by the plasma are used to effectively remove the 5μm parylene-C layer c covering the ITO electrode point 1-1-1 and the ITO solder joint 1-3-1.

[0055] (7) Figure 5As shown in Figures 5-7, in order to construct the device's outline, another photolithography process is required to form the desired outline pattern. Similarly, 4620 photoresist is used as a mask for dry etching, and the thickness after spin coating is 9μm to protect the unexposed area. ICP etching technology is applied again to accurately etch the excess parylene-C layer c, remove the first and second layers of the parylene-C layer c with a total thickness of 10μm that are not covered by the photoresist, and finally form a complete device shape.

[0056] (8) Figure 5 As shown in Figures 5-8, after all the above steps are completed, the aluminum sacrificial layer b needs to be removed by chemical etching to completely release the transparent flexible electrode from the silicon wafer a substrate. Select a suitable etching solution (such as a diluted hydrochloric acid solution) and perform etching under appropriate conditions to ensure that the aluminum layer is completely removed without damaging the electrode structure. This release process is a key step in the manufacture of transparent flexible electrode arrays, which determines the flexibility and implantability of the final product. By finely controlling the etching time and conditions, it can be ensured that the electrode array is smoothly separated from the substrate to form an independent functional component.

[0057] (9) The last step is to connect the transparent flexible electrode to the PCB board. Use conductive silver paste to match the pads (1-3) of the transparent flexible electrode to the pads of the PCB board one by one and conduct them. The specific operation is: apply an appropriate amount of conductive silver paste on the pads of the PCB board, and then accurately align the pads of the transparent flexible electrode with the pads of the PCB board to fit. After the assembly is placed in a 150°C environment and heated and cured for 20 minutes, the connection between the electrode array and the PCB board (2-1) is completed. In order to ensure the stability and waterproofness of the connection part, the connection position is sealed with UV light-curing glue and cured under UV light. This connection step requires not only precise alignment of each pad, but also ensuring the quality of the conductive silver paste and UV light-curing glue to achieve reliable and lasting electrical connection and mechanical fixation.

Claims

1. A cortical electroencephalogram electrode array, characterized in that It comprises a top polymer insulating layer, a middle metal layer and a bottom polymer insulating layer, wherein the top polymer insulating layer is provided with small holes for exposing electrode points and welding points; The middle metal layer comprises an electrode array, and the shape of the electrode array matches the shape of the nearly entire cortical surface.

2. The electrocorticogram electrode array according to claim 1, characterized in that: The shape of the electrode array is made to match the shape of the nearly entire cortical surface by the following methods, including: Two-photon microscopy or nuclear magnetic resonance imaging is used to image nearly the entire cortex, and the dimension data of the electrode array are obtained through the dimension data of the nearly entire cortical surface imaging map, so that the shape of the electrode array matches the shape of the nearly entire cortical surface.

3. The electrocorticogram electrode array according to claim 1, characterized in that: The electrodes are arranged more densely in brain areas with higher functional density, and more sparsely in brain areas with lower functional density.

4. The full-cortical EEG electrode array according to claim 1, characterized in that: When the shape of the electrode array matches the shape of the nearly entire cortical surface of the mouse, the spacing between the electrode points arranged in the prefrontal cortex and the cerebellar cortex is smaller than the spacing between the electrode points arranged in the motor cortex and the somatosensory cortex.

5. The full-cortical EEG electrode array according to claim 4, characterized in that: The spacing between the electrodes in the prefrontal cortex and cerebellar cortex was 200-600 μm, and the spacing between the electrodes in the motor cortex and somatosensory cortex was 600-1200 μm.

6. The electrocorticogram electrode array according to claim 1, characterized in that: The end of the electrode point is in an arc shape.

7. The full-cortical EEG electrode array according to claim 1, characterized in that: The intermediate metal layer also includes a soldering pad and a wire. The soldering pad includes a plurality of soldering points. Each soldering point is connected to a corresponding electrode point through a wire. Each soldering point is welded to a PCB, and the brain wave signal is transmitted to an external device through the PCB.

8. The full-cortical EEG electrode array according to claim 1, characterized in that: The materials of the top polymer insulating layer and the bottom polymer insulating layer are respectively flexible transparent materials, and the flexible transparent material is parylene-c.

9. The full-cortical EEG electrode array according to claim 1, characterized in that: The intermediate metal layer is made of ITO transparent material.

10. A method for preparing a cortical electroencephalogram electrode array according to any one of claims 1 to 9, characterized in that: include: depositing an aluminum sacrificial layer on a silicon wafer substrate; Depositing a parylene-c layer on the aluminum sacrificial layer; Coating photoresist on the parylene-c layer, obtaining an intermediate metal layer pattern through masking, exposure, and development, and then depositing to obtain the intermediate metal layer, wherein the pattern of the intermediate metal layer is a pattern of an electrode array, a wire, and a pad, wherein the pattern of the electrode array is consistent with an imaging diagram of a nearly entire cortical surface, and the arrangement pattern of each electrode point in the electrode array is adapted to the density of the functions of each brain region; Depositing a parylene-c layer on the intermediate metal layer and the substrate; Photolithography and dry etching are used to open holes for electrodes and solder joints; Photolithography and dry etching were used to etch out the outline of the cortical EEG electrode array and remove excess parylene-c material; The aluminum sacrificial layer was etched away by chemical etching to obtain the electrocorticogram electrode array.

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