Dry and wet electrode dual-purpose electroencephalogram impedance detection device and method
The dry and wet electrode brain impedance detection device, designed with independent analog switching circuits and high-precision integrated circuits, solves the problems of dry electrode noise interference and wet electrode signal attenuation, realizes the versatility of the device and improves signal quality, reduces costs and ensures signal stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-09
- Publication Date
- 2026-03-13
AI Technical Summary
Existing dry electrode EEG acquisition equipment is susceptible to external noise interference and has poor versatility. Wet electrode acquisition is susceptible to noise interference during long-distance transmission, and the two types of electrode acquisition equipment are difficult to be compatible, resulting in poor equipment versatility and high replacement costs. The integration of existing impedance detection circuits with EEG acquisition circuits leads to severe signal interference.
Design a brain impedance detection device that can be used for both dry and wet electrodes. Through independent analog switching circuits and impedance measurement circuits, it realizes flexible switching between dry and wet electrodes and signal conditioning. High-precision integrated circuits and physical isolation design are used to reduce noise interference. Multilayer PCB structure and standard interface are used to realize plug-and-play between the device and equipment.
It achieves compatibility between dry and wet electrodes with the same device, reduces equipment procurement and maintenance costs, improves signal quality and versatility, ensures signal stability and long-term equipment reliability, and is suitable for EEG acquisition needs in multiple scenarios.
Smart Images
Figure CN121647699A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of brain-computer interface technology, and in particular to a brain electrical impedance detection device and method that can use both dry and wet electrodes. Background Technology
[0002] Dry electrode-based EEG acquisition technology has greatly facilitated the application of brain-computer interfaces in everyday scenarios. However, due to the high contact impedance of dry electrodes, the system is prone to external noise ingress and signal quality degradation caused by changes in contact state. To address this issue, existing solutions have incorporated a pre-amplified active driving conditioning circuit to increase the input impedance and load-carrying capacity of the acquisition circuit, thereby improving signal quality. However, such devices often place the active driving circuit at the electrode terminals, significantly increasing the cost of consumables and reducing the versatility of the sensing device.
[0003] Another essential function in EEG acquisition is the detection of input impedance of the acquisition electrodes. Input impedance reflects the contact condition between the electrodes and the scalp. Good contact is an important indicator for ensuring high-quality and complete signal. However, the impedance detection function requires the electrodes and amplifier to work together, which severely limits the versatility of EEG caps and amplifiers. Summary of the Invention
[0004] The purpose of this invention is to provide a brain electrical impedance detection device and method applicable to both wet and dry electrodes. By designing the data driving function and impedance detection function separately, and isolating the design of the EEG amplifier and EEG cap, the device allows for arbitrary combination of the EEG cap and amplifier, significantly reducing the cost of EEG acquisition equipment. Simultaneously, by introducing an independent driving circuit module, EEG amplification equipment that was previously only applicable to wet electrodes can now be used with dry electrodes while maintaining signal quality. This greatly expands the versatility of EEG equipment.
[0005] To achieve the above objectives, the following technical solution is adopted: In a first aspect, the present invention provides a brain electrical impedance detection device that can be used with both dry and wet electrodes, comprising an EEG electrode interface, a multi-channel 2:1 analog switch circuit, a 10:1 analog switch circuit, a multi-channel buffer drive circuit, an impedance measurement circuit, an impedance measurement interface, and an EEG transmission interface; wherein: The multi-channel active electrode output terminal, 1-channel reference electrode output terminal, and 1-channel bias electrode output terminal of the EEG electrode interface are electrically connected to the input terminals of multiple 2:1 analog switch circuits, and the EEG electrode interface is compatible with the access of dry electrodes and wet electrodes. The first output of each 2:1 analog switch circuit is electrically connected to the input of one buffer drive circuit. In the second output of each 2:1 analog switch circuit, the impedance channels corresponding to multiple active electrodes and the impedance channel corresponding to one bias electrode are electrically connected to the eight active electrode impedance inputs and one bias electrode impedance input of the 10:1 analog switch circuit. At the same time, the second output of one 2:1 analog switch circuit leads out one impedance calibration channel, which is electrically connected to the calibration channel input of the 10:1 analog switch circuit. The output terminal of the 10:1 analog switch circuit is electrically connected to the first signal input terminal of the impedance measurement circuit, and the second output terminal of the 2:1 analog switch circuit corresponding to the reference electrode is directly electrically connected to the second signal input terminal of the impedance measurement circuit. The output of the multi-channel buffer drive circuit is electrically connected to the multi-channel EEG signal input of the EEG transmission interface one by one. The control signal terminal and data signal terminal of the impedance measurement circuit are electrically connected to the control signal terminal and data signal terminal of the impedance measurement interface, respectively, and the power supply terminal of the impedance measurement circuit is electrically connected to the power supply terminal of the impedance measurement interface. The power supply terminals of the 2:1 analog switch circuit, 10:1 analog switch circuit, buffer drive circuit, and impedance measurement circuit are all electrically connected to the external power supply module, and the grounding terminals are all electrically connected to the common ground terminal of the device. The 2:1 analog switch circuit is used to switch the single electrode signal between the impedance channel and the EEG channel. The 10:1 analog switch circuit is used to realize the time-division switching output of multiple impedance signals. The impedance measurement circuit is used to complete impedance calibration and electrode-scalp contact impedance measurement. The buffer drive circuit is used to drive and condition high internal resistance EEG signals. The impedance measurement interface and EEG transmission interface are used to realize the connection and signal transmission between the device and external EEG acquisition equipment.
[0006] Preferably, in the above-mentioned brain electrical impedance detection device that can be used for both dry and wet electrodes, the 2:1 analog switch circuit includes a three-channel 2:1 analog switch chip and an electrostatic diode; wherein: The three-channel 2:1 analog switch chip has its D1, D2, and D3 terminals shorted to form a common input terminal, its S1A, S2A, and S3A terminals shorted to form a first output terminal, its S1B, S2B, and S3B terminals shorted to form a second output terminal, and its SEL3, SEL2, and SEL1 terminals shorted to form a control terminal. The input terminal of the electrostatic diode is electrically connected to the corresponding electrode output terminal of the EEG electrode interface, and the output terminal of the electrostatic diode is electrically connected to the node after shorting the common input terminal of the three-channel 2:1 analog switch chip. The first output terminal is connected to the input terminal of the buffer drive circuit after being connected in series with a resistor. The second output terminal is connected to the corresponding input terminal of the 10:1 analog switch circuit or impedance measurement circuit after being connected in series with a resistor. The control terminal is connected to the common ground terminal after being connected in series with a pull-down resistor. The AVDD terminal and AVSS terminal of the three-channel 2:1 analog switch chip are connected to the power supply terminal respectively. The AVDD terminal is connected to the common ground terminal after being connected in parallel with the first decoupling capacitor, and the AVSS terminal is connected to the common ground terminal after being connected in parallel with the second decoupling capacitor.
[0007] Preferably, in the above-mentioned brain electrical impedance detection device that can be used for both dry and wet electrodes, the buffer drive circuit includes a buffer; wherein: The four input terminals of the buffer are shorted to form the input terminals of the buffer drive circuit, which are electrically connected to the first output terminal of the 2:1 analog switch circuit; the four output terminals of the buffer are connected in series with a resistor to form the output terminals of the buffer drive circuit, and the output terminals of the buffer drive circuit are electrically connected to the corresponding input terminals of the EEG transmission interface. The buffer is electrically connected to the power supply terminal. The +VS terminal of the buffer is connected in parallel with two third decoupling capacitors and then connected to the common ground terminal. The -VS terminal of the buffer is connected in parallel with two third decoupling capacitors and then connected to the common ground terminal.
[0008] Preferably, in the above-mentioned brain electrical impedance detection device that can be used for both dry and wet electrodes, the 10:1 analog switch circuit includes two 8:1 analog switch chips and an inverter, wherein the two 8:1 analog switch chips are respectively the first switch chip and the second switch chip, wherein: In the first switch chip, terminals S1-S8 are respectively connected to the first two impedance channels of the eight active electrodes, terminal S3 is connected to the bias electrode impedance channel, and terminal S4 is connected to the impedance calibration channel. Terminals S5-S8 are shorted and then connected to the common ground. In the second switch chip, terminals S1-S6 are shorted and then connected to the common ground. Terminals S7-S8 are respectively connected to the last six impedance channels of the eight active electrodes. The common output terminals of the two 8:1 analog switch chips are shorted to form the output terminal of a 10:1 analog switch circuit, which is electrically connected to the first signal input terminal of the impedance measurement circuit. In the four digital control signals output by the external MCU, the lower three bits are electrically connected to the channel selection terminals of the two 8:1 analog switch chips respectively; the highest bit is directly connected to the enable terminal of the second switch chip, and after being inverted by an inverter, it is electrically connected to the enable terminal of the first switch chip.
[0009] Preferably, in the above-mentioned brain electrical impedance detection device that can be used for both dry and wet electrodes, the impedance measurement circuit includes a high-precision impedance measurement integrated circuit, an active crystal oscillator module, an analog switch chip, and a calibration resistor; wherein: The output terminal of the active crystal oscillator module is electrically connected to the clock input terminal of the impedance measurement integrated circuit; the excitation signal output terminal of the impedance measurement integrated circuit is electrically connected to the first common input terminal of the analog switch chip. The analog switch chip's D1-D3 terminals are shorted to form a first common input terminal, and its S1A-S3A terminals are shorted to form a first output terminal. The first output terminal is electrically connected to one end of a calibration resistor, and the other end of the calibration resistor is connected to a common ground terminal. The analog switch chip's S1B-S3B terminals are shorted to form a second output terminal, which is electrically connected to the second output terminal of the 2:1 analog switch circuit corresponding to the reference electrode. The analog switch chip's SEL1-SEL3 terminals are shorted to form a control terminal, which is electrically connected to the control signal terminal of an external MCU. The signal acquisition input terminal of the impedance measurement integrated circuit is electrically connected to the output terminal of the 10:1 analog switch circuit, and the feedback resistor terminal of the impedance measurement integrated circuit is connected in series with a feedback resistor and then connected to the common ground terminal.
[0010] Preferably, the above-mentioned brain electrical impedance detection device that can be used for both dry and wet electrodes also includes a PCB board, wherein the PCB board includes a top layer, a GND layer, a power layer, and a bottom layer arranged sequentially from top to bottom; wherein: The components of the 2:1 analog switch circuit, buffer drive circuit, 10:1 analog switch circuit, and impedance measurement circuit are all soldered on the top and bottom layers. The 2:1 analog switch circuit and buffer drive circuit corresponding to each electrode adopt a symmetrical layout, and the pins of adjacent components are electrically connected through PCB wires. The signal wires of the EEG channel are laid on the top layer, and the top layer wires and the adjacent GND layer form a common ground reference plane; the signal wires of the impedance channel and the switch control signal wires are laid on the bottom layer, and the bottom layer wires are isolated from the adjacent power supply layer. The power layer is divided into a positive power area and a negative power area, which are electrically connected to the positive power terminals and negative power terminals of the top and bottom layer components through PCB vias, respectively; the GND layer is a complete copper foil plane, which is electrically connected to the ground terminals of the top and bottom layer components through PCB vias.
[0011] Preferably, in the above-mentioned brain electrical impedance detection device that can be used for both dry and wet electrodes, both the impedance measurement interface and the brain electrical transmission interface adopt a female connector; wherein: The VBUS and GND pins of the female connector serve as the positive and negative DC power supply terminals of the impedance measurement interface, respectively, and are electrically connected to the power supply terminal and common ground terminal of the impedance measurement circuit. The D+ and D- pins of the female connector serve as the positive and negative transmission terminals of the analog switch control signal, respectively, and are electrically connected to the control terminals of the 2:1 analog switch circuit and the 10:1 analog switch circuit. The CC1 and CC2 pins of the female connector serve as the SDA and SCL terminals of the I2C bus, respectively, and are electrically connected to the I2C data terminal and the I2C clock terminal of the impedance measurement circuit. The VBUS and GND pins of the female connector serve as the positive and negative DC power supply terminals of the EEG transmission interface, respectively, and are electrically connected to the power supply terminal and common ground terminal of the buffer drive circuit. The 10 data pins of the female connector are electrically connected to the output terminals of the 10 buffer drive circuits, respectively, for transmitting the conditioned EEG signals.
[0012] Secondly, the present invention provides a brain electrical impedance detection method that can use both dry and wet electrodes, based on the brain electrical impedance detection device that can use both dry and wet electrodes as described above, the method comprising: Dry or wet electrodes are soldered to the EEG electrode interface using flexible wires. After the device is powered on, it waits for the EEG acquisition device to send the working mode command; If the received instruction is in normal mode, the 2:1 analog switch circuit is switched to the EEG channel. The EEG signal is conditioned by the buffer drive circuit and then transmitted to the EEG acquisition device. The mode is continuously monitored to see if it changes. If the received instruction is in impedance measurement mode, the 2:1 analog switch circuit and the 10:1 analog switch circuit are switched to the impedance calibration channel to complete impedance calibration and obtain the impedance gain coefficient. Then, the 10:1 analog switch circuit is switched in a time-division manner to complete the impedance measurement between the 8 active electrodes, the 1 bias electrode and the reference electrode in sequence. After completing all impedance channel measurements, wait for the new operating mode command and execute the corresponding operation.
[0013] Preferably, in the above-mentioned brain impedance detection method using both dry and wet electrodes, in the normal mode, the command states of the 2:1 analog switch circuit control ports cnt6-cnt1 are in a preset first state, the 10:1 analog switch circuit control ports cnt10-cnt7 are in any state, and the impedance measurement integrated circuit is in a power-off mode; in the impedance calibration mode, the command states of the 2:1 analog switch circuit control ports are in a preset second state, the command states of the 10:1 analog switch circuit control ports are in a preset third state, and the impedance measurement integrated circuit is in a working mode; in the impedance measurement mode, the command states of the 2:1 analog switch circuit control ports are in a preset fourth state, the command states of the 10:1 analog switch circuit control ports are in a preset fifth state, and the impedance measurement integrated circuit is in a working mode.
[0014] Preferably, in the above-mentioned brain electrical impedance detection method using both dry and wet electrodes, the method further includes a host computer processing step for impedance data, wherein the host computer processing step for impedance data includes: Acquire impedance data from 10 channels; The 10 impedance data are parsed, their validity is verified, and outliers are filtered. The original data and processing results are saved. Based on the processing results, an EEG topography map is displayed on the front-end interface, and the electrode impedance status is indicated by a three-color grading system, with different electrode impedance statuses corresponding to different degrees of contact. The beneficial effects of this invention are reflected in: 1) In existing technologies, dry electrode acquisition relies on complex rigid-flexible active electrode structures, while wet electrode acquisition is susceptible to noise interference during long-distance transmission. Furthermore, the acquisition devices corresponding to the two types of electrodes are difficult to integrate, resulting in poor device versatility and high replacement costs. This invention utilizes a 10-channel independent 2:1 analog switch circuit design to achieve flexible switching of single-electrode signals between impedance and EEG channels. Combined with the EEG electrode interfaces for dry and wet electrodes, the same device can be directly connected to either dry or wet electrodes. Simultaneously, the buffer drive circuit conditions high-internal-resistance EEG signals, avoiding noise feed into dry electrode signals and solving the signal attenuation problem during long-distance transmission of wet electrodes. This allows for EEG acquisition needs to be met in different scenarios without equipment replacement, significantly reducing users' equipment procurement and maintenance costs.
[0015] 2) Existing EEG devices with impedance detection often integrate the impedance detection circuit and the EEG acquisition circuit into one unit. The switching network built with discrete components is prone to introducing digital noise, and the complex wiring leads to severe signal interference. This invention utilizes a 10:1 analog switching circuit and a high-precision integrated chip AD5934 impedance measurement architecture. On the one hand, it leverages the characteristics of the AD5934, which integrates a frequency generator, ADC, and DFT, to replace traditional discrete circuits, reducing the number of chip types, simplifying the circuit structure, and lowering the difficulty of PCB layout. On the other hand, it physically isolates the impedance detection circuit from the EEG transmission circuit. The impedance channel signal is routed separately on the bottom layer with the power layer as a reference, while the EEG channel signal is routed on the top layer with the complete GND layer as a reference. The crosstalk noise between the two types of signals is significantly reduced, ensuring the accuracy of impedance measurement and avoiding interference of the impedance detection module to the EEG signal, thereby improving the signal-to-noise ratio of the acquired EEG signal.
[0016] 3) This invention improves overall stability through multiple redundancy and optimized design. Specifically, the 2:1 analog switch circuit uses three single-pole double-throw switches in parallel, reducing the switch on-resistance to below 5Ω and improving channel switching reliability to 99.9%. The buffer drive circuit adopts a four-channel buffer parallel architecture, reducing the voltage noise density to half that of a single-channel buffer, ensuring distortion-free transmission of high internal resistance EEG signals. At the same time, all analog chips are equipped with a 0.1uF + 4.7uF decoupling capacitor combination at the power supply end, and the pre-protection design of the electrostatic diode can withstand ±15kV contact discharge, improving the device's anti-interference capability in complex electromagnetic environments and meeting the reliability requirements of clinical-grade EEG acquisition.
[0017] 4) This invention enables plug-and-play functionality between the device and EEG acquisition equipment via a standardized USB Type-C interface, eliminating the need for complex wiring. It also features a three-level communication protocol: normal mode, impedance calibration mode, and impedance measurement mode. Automatic mode switching is achieved via control codes, eliminating the need for manual circuit parameter adjustments. The accompanying host computer system supports BLE low-power Bluetooth connectivity, receiving 10 channels of impedance data in real time and displaying it as an EEG topography map and a three-color graded alarm (green / yellow / red corresponding to different contact levels). Operators can quickly assess electrode contact status, significantly reducing equipment setup time, making it particularly suitable for everyday use by non-professionals.
[0018] 5) This invention employs a four-layer PCB stack, providing a stable reference plane for EEG signals through a complete GND layer, and dividing the power supply layer into two independent regions to avoid power supply crosstalk. Simultaneously, the electrode leads are secured to the PCB using nylon cable ties to prevent solder joint detachment due to stress. This structural design ensures that the circuit parameter drift is controlled within ±2% during long-term use, guaranteeing the long-term stability of the system performance and meeting the long-term usage requirements of various scenarios such as home use, research, and clinical applications. Attached Figure Description
[0019] Figure 1 This is an overall circuit diagram of a brain electrical impedance detection device that can be used with both dry and wet electrodes, provided in an embodiment of the present invention. Figure 2 A circuit diagram of a 2:1 analog switch circuit provided in an embodiment of the present invention; Figure 3 A circuit diagram of a buffer drive circuit provided in an embodiment of the present invention; Figure 4 A circuit diagram of a 10:1 analog switch circuit provided for an embodiment of the present invention; Figure 5 A circuit diagram of an impedance measurement circuit provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the PCB stack-up provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the assembly of the device provided in the embodiment of the present invention; Figure 8 A flowchart of a brain electrical impedance detection method using both dry and wet electrodes provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the host computer startup interface provided in an embodiment of the present invention; Figure 10 A schematic diagram of the host computer working interface (suspended electrode) provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the host computer working interface (with electrodes) provided in an embodiment of the present invention. Detailed Implementation
[0020] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.
[0021] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0022] Example 1: The existing background technology and remaining problems of current EEG acquisition devices are as follows: 1) For dry electrode applications, the current best approach is to use a rigid-flexible active electrode structure. This involves using a rigid FR4 board to condition the high-internal-resistance EEG signal via a high-input-impedance buffer drive circuit, and then transmitting the signal to the EEG acquisition device via a flexible board. While this structure is effective, it is complex and costly. Crucially, once the structure is finalized, the relative positions of the electrodes are fixed and cannot be changed, resulting in poor flexibility. For wet electrode applications, the most common approach is to directly connect to the EEG acquisition device for processing. This is simple and low-cost, but the high internal resistance of the EEG signal source makes it susceptible to noise interference during long-distance transmission, leading to poor signal integrity and consequently, poor signal quality, directly impacting the final application results. Therefore, a compromise is needed between these two common design schemes. The goal is to reduce the complexity and cost of the rigid-flexible active electrode structure while avoiding the poor signal quality issues caused by direct long-distance EEG signal transmission. A full-board FR4 material design is recommended to achieve the dual functionality of dry and wet electrodes.
[0023] 2) Currently, there are EEG acquisition devices with impedance detection capabilities on the market. The impedance detection circuit is directly integrated into the EEG acquisition device, often employing a discrete circuit architecture such as a switching network + DAC + conditioning circuit + ADC. This results in a wide variety of chips, complex circuit structures, and numerous interwoven analog and digital signals, increasing the difficulty of PCB layout and routing, and inevitably introducing digital noise interference, affecting the quality of the EEG signal. High-precision impedance measurement integrated circuits, such as AD5934 and AD5933, are now available that integrate a frequency generator, current-voltage conversion conditioning, analog-to-digital converter (ADC), and discrete Fourier transform (DFT) into a single unit specifically for bioconductivity analysis and impedance measurement. These are simple and convenient to control, directly obtaining impedance information. This not only reduces the complexity of the original impedance detection circuit and the difficulty of MCU acquisition and processing but also effectively reduces the impact of circuit noise interference on the EEG signal. Furthermore, separating the impedance detection circuit from the EEG acquisition device and integrating it with the front-end signal conditioning circuit can further reduce noise interference from the switching network and mitigate signal integrity issues caused by long-distance transmission. This is also an important purpose of this design.
[0024] Based on this, embodiments of the present invention provide a brain electrical impedance detection device that can be used with both dry and wet electrodes, such as... Figure 1As shown, the dual-purpose dry and wet electrode brain impedance detection device includes an EEG electrode interface 10, a multi-channel 2:1 analog switch circuit 20, a 10:1 analog switch circuit 30, a multi-channel buffer drive circuit 40, an impedance measurement circuit 50, an impedance measurement interface 60, and an EEG transmission interface 70. The multi-channel active electrode output, one reference electrode output, and one bias electrode output of the EEG electrode interface 10 are electrically connected to the input terminals of the multi-channel 2:1 analog switch circuit 20, and the EEG electrode interface 10 is compatible with both dry and wet electrodes. The first input of each 2:1 analog switch circuit 20... The output terminal is electrically connected to the input terminal of the 1-channel buffer drive circuit 40. In the second output terminal of each 2:1 analog switch circuit 20, the impedance channels corresponding to multiple active electrodes and the impedance channel corresponding to one bias electrode are electrically connected one-to-one with the 8 active electrode impedance input terminals and 1 bias electrode impedance input terminal of the 10:1 analog switch circuit 30. At the same time, the second output terminal of one 2:1 analog switch circuit 20 leads out one impedance calibration channel, which is electrically connected to the calibration channel input terminal of the 10:1 analog switch circuit 30. The output terminal of the 10:1 analog switch circuit 30 is connected to the first signal input terminal of the impedance measurement circuit 50. Electrical connections are established: the second output terminal of the 2:1 analog switch circuit 20 corresponding to the reference electrode is directly connected to the second signal input terminal of the impedance measurement circuit 50; the output terminal of the multi-channel buffer drive circuit 40 is electrically connected to the multi-channel EEG signal input terminals of the EEG transmission interface 70; the control signal terminal and data signal terminal of the impedance measurement circuit 50 are electrically connected to the control signal terminal and data signal terminal of the impedance measurement interface 60, respectively, and the power supply terminal of the impedance measurement circuit 50 is electrically connected to the power supply terminal of the impedance measurement interface 60; the 2:1 analog switch circuit 20, the 10:1 analog switch circuit 30, and the buffer drive circuit 40 are all electrically connected. The power supply terminals of circuit 40 and impedance measurement circuit 50 are both electrically connected to the external power supply module, and the grounding terminals are both electrically connected to the common ground terminal of the device. The 2:1 analog switch circuit 20 is used to switch the single electrode signal between the impedance channel and the EEG channel. The 10:1 analog switch circuit 30 is used to realize the time-division switching output of multiple impedance signals. The impedance measurement circuit 50 is used to complete impedance calibration and electrode-scalp contact impedance measurement. The buffer drive circuit 40 is used to drive and condition the high internal resistance EEG signal. The impedance measurement interface 60 and the EEG transmission interface 70 are used to realize the connection between the device and the external EEG acquisition equipment and signal transmission.
[0025] In this embodiment, taking the time-sharing control function of impedance measurement and EEG signal-driven modulation of 8 active electrodes, 1 reference electrode, and 1 bias electrode as an example, such as... Figure 1As shown, the eight active electrodes are represented by C1 to C8, the reference electrode by C9, the bias electrode by C10, the impedance channels of the eight active electrodes, one reference electrode, and one bias electrode by C1A to C10A, the EEG channels of the eight active electrodes, one reference electrode, and one bias electrode by C1B to C10B, and cnt1 to cnt10 represent ten switching control signals.
[0026] Specifically, dry or wet electrodes are connected to the device via EEG electrode interface 10. Each electrode signal passes through a 2:1 analog switch circuit 20, enabling switching control between 10 impedance channels and 10 EEG channels. Eight active electrode impedance channels, one bias electrode impedance channel, and one impedance calibration channel are connected to a 10:1 analog switch circuit 30 for 10-to-1 switching; the reference electrode impedance channel and impedance calibration channel are switched between 2 and 1 via the 2:1 analog switch circuit 20; the selected channels are connected to both ends of the impedance measurement circuit, which performs impedance calibration and measurement functions. The 10 electrode EEG channels are driven and conditioned by a buffer drive circuit 40, achieving high internal resistance characteristics for EEG signal driving.
[0027] The impedance measurement interface 60 includes analog switch control signals, I2C bus interface signals, and a DC power supply. The EEG transmission interface 70 includes an EEG signal channel with 8 active electrodes, 1 bias electrode, and 1 reference electrode, as well as a DC power supply. Both the impedance measurement interface 60 and the EEG transmission interface 70 can use a universal standard USB Type-C female connector, which is reversible and has good shielding.
[0028] In some embodiments, such as Figure 2As shown, the 2:1 analog switch circuit 20 consists of a three-channel 2:1 analog switch chip TMUX1133PWR, an ESD diode KPESD3V3S1BL, and resistive and capacitive components. The input terminal of the ESD diode KPESD3V3S1BL is electrically connected to the corresponding electrode output terminal of the EEG electrode interface 10. The output terminal of the ESD diode is electrically connected to the node formed by shorting the D1, D2, and D3 terminals (common input terminal) of the analog switch chip TMUX1133PWR. Shorting the D1, D2, and D3 terminals of the analog switch chip TMUX1133PWR forms the common input terminal; shorting the S1A, S2A, and S3A terminals forms the first output terminal (EEG channel); and shorting the S1B, S2B, and S3B terminals forms the second output terminal (EEG channel). The output terminal (impedance channel) is formed by shorting SEL3, SEL2, and SEL1. The first output terminal (EEG channel) is connected in series with a 51Ω resistor R40 and then electrically connected to the input terminal of the buffer drive circuit 40. The second output terminal (impedance channel) is connected in series with a 51Ω resistor R49 and then electrically connected to the corresponding input terminal of the 10:1 analog switch circuit 30 or impedance measurement circuit 50. The control terminal is connected in series with a 10kΩ pull-down resistor R50 and then electrically connected to the common ground terminal AGND. The AVDD terminal (positive power supply) and VSS terminal (negative power supply) of the analog switch chip are electrically connected to the +2.5V and -2.5V power supply terminals, respectively. The AVDD terminal is connected in parallel with a 0.1uF decoupling capacitor and then connected to the common ground terminal. The AVSS terminal is connected in parallel with a 0.1uF decoupling capacitor and then connected to the common ground terminal.
[0029] Each electrode signal passes through a 2:1 analog switch circuit 20 to switch between the impedance channel and the EEG channel. To mitigate the hazards of electrostatic discharge (ESD) to the head, ESD diodes are added to the common input terminals D1 / D2 / D3 of the three-channel 2:1 analog switch chip TMUX1133 to protect the analog switches from ESD damage. In this 2:1 analog switch circuit 20, the D1, D2, and D3 terminals of the TMUX1133 are shorted together, the S1A, S2A, and S3A terminals are shorted together, the S1B, S2B, and S3B terminals are shorted together, and the SEL3, SEL2, and SEL1 terminals are shorted together. This means that each electrode signal is connected in parallel through three single-pole double-throw switches, enabling the switching between the impedance measurement channel and the EEG transmission channel. This redundant circuitry improves the reliability of channel switching and reduces the switch on-resistance, minimizing its impact on the EEG signal. Both the EEG channel and the impedance channel are connected in series with a 51Ω resistor (R40 and R49). This is to ensure impedance matching on the signal transmission link, prevent signal reflection, contribute to signal integrity, and effectively suppress noise interference. To prevent interference and uncertainty caused by floating pins, a 10kΩ pull-down resistor R50 is added to the control terminals SEL3 / SEL2 / SEL1 of the TMUX1133. A 0.1uF decoupling capacitor is placed on both the positive and negative power supply terminals of the TMUX1133 to effectively filter out high-frequency interference in the power supply and stabilize the power supply voltage.
[0030] In some embodiments, considering that EEG signals with high internal resistance are prone to signal attenuation and interference during transmission, a buffer drive circuit with high input impedance is designed to address this issue. For example... Figure 3 As shown, the buffer drive circuit 40 consists of a four-channel unity-gain buffer AD8244 and resistive and capacitive components. The four input terminals of the buffer AD8244 are shorted to form the input terminals of the buffer drive circuit 40, which are electrically connected to the first output terminal (EEG channel) of the 2:1 analog switch circuit 20. The four output terminals of the buffer are each connected in series with a 51Ω resistor to form the output terminals of the buffer drive circuit 40, which are electrically connected to the corresponding input terminals of the EEG transmission interface 70. The +VS terminal (positive power supply) of the buffer AD8244 is electrically connected to the +2.5V power supply terminal AVDD, and the -VS terminal (negative power supply) is electrically connected to the -2.5V power supply terminal AVSS. A 0.1uF decoupling capacitor C10 and a 4.7uF decoupling capacitor C11 are connected in parallel to the +VS terminal before connecting to the common ground terminal. Similarly, a 0.1uF decoupling capacitor C12 and a 4.7uF decoupling capacitor C13 are connected in parallel to the -VS terminal before connecting to the common ground terminal.
[0031] It should be noted that the AD8244 is a four-channel unity-gain buffer with a maximum bias current of 2pA, current noise of 0.8fA, voltage noise of 0.4uVpp, and an input impedance of 10TΩ. Therefore, even with a source impedance in the MΩ range, it will not produce input errors due to load effects. The device's output resistance is essentially zero, and its output voltage has a high load-carrying capacity. The circuit uses a parallel structure of four buffers to isolate and buffer one channel of EEG signal. This structure reduces the voltage noise density, lowering the effective noise value to half that of a single-channel buffer, thus improving the signal-to-noise ratio. A small 51Ω resistor is placed at each buffer output pin to prevent additional current flow caused by slight differences between the outputs. 0.1uF and 4.7uF decoupling capacitors are placed at the positive and negative power supply terminals of the AD8244, effectively filtering out high-frequency interference in the power supply and stabilizing the power supply voltage.
[0032] In some embodiments, such as Figure 4As shown, the 10:1 analog switch circuit 30 consists of two 8:1 analog switch chips TMUX1108, an inverter SN74AUP1G14DCKR, and resistive and capacitive components; wherein: in the first TMUX1108 (low 8 channels), the S1-S8 terminals are respectively connected to the first two impedance channels of the 8 active electrodes, the S3 terminal to the bias electrode impedance channel, and the S4 terminal to the impedance calibration channel, and the S5-S8 terminals are shorted and connected to the common ground terminal; the second TMUX1108... The S1-S6 terminals of the UX1108 (high 8 channels) are shorted and connected to the common ground terminal. The S7-S8 terminals are electrically connected to the last 6 impedance channels of the 8 active electrodes, respectively. The D terminals (common output terminals) of the two TMUX1108 chips are shorted to form the output terminal of the 10:1 analog switch circuit 30, which is electrically connected to the first signal input terminal of the impedance measurement circuit 50. Among the 4 digital control signals (cnt7-cnt10) output by the external MCU, the lower 3 bits (cnt7-cnt9) are... Each of the two TMUX1108 chips is electrically connected to its corresponding A0, A1, and A2 terminals (channel selection terminals). The highest bit signal (cnt10) is directly connected to the EN terminal (enable terminal) of the second TMUX1108 chip, and after being inverted by an inverter SN74AUP1G14DCKR, it is electrically connected to the EN terminal of the first TMUX1108 chip. A 10kΩ pull-down resistor is connected in series with each of the EN terminals and A0-A2 terminals of both TMUX1108 chips, and then connected to a common ground. The VDD terminal (positive power supply) of the two TMUX1108 chips is electrically connected to the +2.5V power supply terminal, and the VSS terminal (negative power supply) is electrically connected to the -2.5V power supply terminal. Both the VDD and VSS terminals are connected in parallel with a 0.1uF decoupling capacitor and then connected to the common ground terminal. The VCC terminal (positive power supply) of the inverter SN74AUP1G14DCKR is electrically connected to the +3.3V power supply terminal, and the GND terminal (ground terminal) is connected to the common ground terminal. The VCC terminal is connected in parallel with a 0.1uF decoupling capacitor and then connected to the common ground terminal.
[0033] The impedance measurement function operates in two steps. The first step measures the calibration resistor to obtain the impedance gain coefficient. The second step involves time-division multiplexing the measurements between the active electrode, bias electrode, and reference electrode, and then using the impedance gain coefficient to obtain the impedance value. To achieve time-division measurement, the 10 signals (8 active electrode, 1 bias electrode, and 1 calibration) need to be switched via a 10:1 analog switch circuit. To meet the ±2.5V power supply requirement, two 8:1 analog switch chips (TMUX1108) were selected and cascaded to form a 16-to-1 switching circuit. Figure 4As shown. The TMUX1108 achieves tri-state control output through the enable terminal EN. Therefore, the common terminal D of each switch is cascaded together. The switch S terminals are sequentially connected to the impedance paths of 8 active electrodes, 1 bias electrode, and 1 calibration channel. The unused high 6 channels are directly shorted to GND to avoid interference caused by floating. The lower 3 bits of the 4 digital signals are cascaded to control the analog switches A2, A1, and A0. The highest digital signal directly controls the enable terminal EN of the high 8 channels of analog switches. The highest digital signal is also converted into a control signal by the inverter SN74AUP1G14DCKR and connected to the enable terminal EN of the low 8 channels of analog switches, thereby controlling the 4-bit digital signal to change from 0000 to 1001, realizing the time-division switching output of 10 signals.
[0034] To ensure impedance matching in the signal transmission link and prevent signal reflection, a 51Ω resistor is connected in series in each of the 8 active electrode impedance channels and the 1 bias electrode impedance channel. To prevent interference and uncertainty caused by floating pins, a 10kΩ pull-down resistor is added to the enable pin EN and the control pins A2, A1, and A0 of the TMUX1108.
[0035] Both the positive and negative power supply terminals of the TMUX1108 and SN74AUP1G14DCKR have 0.1uF decoupling capacitors, which can effectively filter out high-frequency interference in the power supply and stabilize the power supply voltage.
[0036] In some embodiments, such as Figure 5As shown, the impedance measurement circuit 50 is based on the high-precision impedance measurement integrated circuit AD5934, and is composed of an active crystal oscillator module, a three-channel 2:1 analog switch chip TMUX1133PWR (for reference electrode switching), and a calibration resistor R142. The output of the active crystal oscillator module is electrically connected to the SCLK terminal (clock input) of the AD5934, providing the AD5934 with its operating clock. The VOUT terminal (excitation signal output) of the AD5934 is electrically connected to the first common input terminal of the TMUX1133PWR for reference electrode switching. The D1-D3 terminals of the TMUX1133PWR are shorted to form the first common input terminal, and the S1A-S3A terminals are shorted to form the first output terminal, which is electrically connected to one end of the calibration resistor R142. The other end of the calibration resistor R142 is connected to the common ground terminal. The S1B-S3B terminals are shorted to form the second output terminal, which corresponds to the second output of the 2:1 analog switch circuit 20. The reference electrode impedance channel is electrically connected; the SEL1-SEL3 terminals are shorted to form a control terminal, which is electrically connected to the control signal terminal of the external MCU; the VIN terminal (signal acquisition input terminal) of AD5934 is electrically connected to the output terminal (first signal input terminal) of the 10:1 analog switch circuit 30, and the RFB terminal (feedback resistor terminal) of AD5934 is connected to the common ground terminal after being connected in series with a 10kΩ feedback resistor; the SDA terminal (I2C data terminal) and SCL terminal (I2C clock terminal) of AD5934 are electrically connected to the I2C data terminal and I2C clock terminal of the impedance measurement interface 60, respectively; the VDD terminal (positive power supply) of AD5934 is electrically connected to the +3.3V power supply terminal, the GND terminal (ground terminal) is connected to the common ground terminal, and the VDD terminal is connected to the common ground terminal after being connected in parallel with a 0.1uF decoupling capacitor; the power supply and RC connection method of TMUX1133PWR is used for reference electrode switching, which is consistent with the power supply and RC connection method of 2:1 analog switch circuit 20.
[0037] The brain impedance detection process of this device is a dynamic test of the skin contact impedance between the active electrode or bias electrode and the reference electrode, and the measured result is a dynamic complex impedance. The main circuit for impedance measurement is as follows: Figure 5 As shown, the AD5934 is a high-precision impedance measurement integrated circuit that integrates a frequency generator, current-voltage conversion conditioning, analog-to-digital converter (ADC), and discrete Fourier transform (DFT). It is widely used in fields such as bioconductivity analysis, impedance spectroscopy, and complex impedance measurement, and is an ideal choice for impedance measurement and analysis.
[0038] Figure 5In the diagram, X2 is an active crystal oscillator module that provides the operating clock for the AD5934. The VOUT pin of the AD5934 outputs the excitation signal to the path under test, while the VIN and RFB pins receive the current in the path under test, convert it into a voltage signal, and complete the AD acquisition and DFT process internally to obtain impedance information. The AD5934 has an I2C bus interface, through which it can communicate with an external MCU.
[0039] exist Figure 5 In this design, a three-channel 2:1 analog switch chip, TMUX1133PWR, is used. Firstly, it switches the transmission path of the reference electrode signal between normal operation mode and impedance measurement mode. In normal operation mode, the reference electrode signal REF_IN is output through the S1A and S2A terminals of the switch and connected in series with an impedance matching resistor R140 to the buffer driver AD8244, which generates the required EEG reference signal. In impedance measurement mode, the reference electrode signal REF_IN is connected to the VOUT pin of the AD5934 through the D1 / D2-S1B / S2B / S3B-D3 terminals of the switch, preparing for the measurement of skin contact resistance between the active or bias electrode and the reference electrode. Secondly, in normal operation mode, the calibration resistor R142 is connected to the impedance measurement path to perform impedance measurement calibration.
[0040] Figure 5 A 0.1uF decoupling capacitor is placed at the power supply terminal of the integrated circuit module or chip to effectively filter out high-frequency interference in the power supply and stabilize the power supply voltage.
[0041] In some embodiments, such as Figure 6 As shown, the device also includes a PCB board 80, which adopts a four-layer PCB architecture. The stacking order from top to bottom is top layer 801, GND layer 802, power layer 803, and bottom layer 804. Among them, the components of the 2:1 analog switch circuit 20, buffer drive circuit 40, 10:1 analog switch circuit 30, and impedance measurement circuit 50 are all soldered on the top layer 801 and bottom layer 804. The 2:1 analog switch circuit 20 and buffer drive circuit 40 corresponding to each electrode adopt a symmetrical layout, and the pins of adjacent components are electrically connected through PCB wires. The signal wires of the EEG channel are laid on the top layer 801, and the top layer wires and the adjacent GND layer 802 form a common ground reference plane; the signal wires of the impedance channel and the switch control signal wires are laid on the bottom layer, and the bottom layer wires are isolated from the adjacent power layer 803; the power layer 803 is divided into a +2.5V area and a -2.5V area, which are electrically connected to the positive power terminals and negative power terminals of the components on the top layer 801 and the bottom layer 804 through PCB vias, respectively; the GND layer 802 is a complete copper foil plane, which is electrically connected to the ground terminals of the components on the top layer 801 and the bottom layer 802 through PCB vias.
[0042] In this embodiment, the device is soldered to the EEG electrode interface with a flexible wire and secured to the PCB near the soldering point using nylon cable ties. This ensures good contact and avoids the wire from breaking easily due to stress on the soldering point.
[0043] This PCB board 80 can be manufactured using an FR4 rigid board design, employing a four-layer PCB architecture, such as... Figure 6 As shown, the stack-up order from top to bottom is: top layer 801, GND layer 802, power layer 803, and bottom layer 804. All components are placed on the top layer 801 and bottom layer 804. GND layer 802 is a complete reference ground plane, and power layer 803 is divided into +2.5V and -2.5V sections. Signals from the normal EEG transmission channel are routed on the top layer 801. Because the top layer 801 is adjacent to GND layer 802, it provides a good electrical reference plane for EEG signal transmission, ensuring signal integrity. Signals from the impedance measurement channel and switching network control signals are routed on the bottom layer 804, with the power layer 803 as the adjacent reference plane, effectively reducing noise interference from switching signals to EEG signals.
[0044] The layout and routing design of the pre-amplifier 2:1 switch circuit and buffer drive circuit is as follows: During PCB layout and routing, for each EEG electrode signal, the ESD diode KPESD3V3S1BL is placed as close as possible to the corresponding input pin of the analog switch TMUX1133. The EEG channel output of the analog switch is connected in series with a 51Ω resistor to the input of the buffer driver AD8244, and the routing path is as short as possible. Ten such electrode path switching drive circuits have similar structures and use symmetrical layout and routing, which can effectively improve signal anti-interference capability.
[0045] Further integration Figure 2 As shown, the analog switch TMUX1133 has three 2:1 channels. In order to improve the high reliability of channel switching, reduce the on-resistance of the switch, and reduce the influence of the on-resistance of the switch on-resistance on the EEG signal, the circuit adopts redundancy and uses the three 2:1 switches in parallel.
[0046] Further integration Figure 3 As shown, each EEG signal channel employs a parallel structure of four buffers for isolation and buffering. This structure reduces voltage noise density, lowering the effective noise value to half that of a single-channel buffer, thus improving the signal-to-noise ratio. A small 51Ω resistor is placed at each buffer output pin to prevent additional current flow caused by slight differences between the outputs.
[0047] In some embodiments, both the impedance measurement interface 60 and the EEG transmission interface 70 use a USB Type-C female connector. The VBUS and GND pins of the USB Type-C female connector serve as the positive and negative DC power supply terminals of the impedance measurement interface 60, respectively, and are electrically connected to the power supply terminal and common ground terminal of the impedance measurement circuit 50. The D+ and D- pins of the USB Type-C female connector serve as the positive and negative transmission terminals of the analog switch control signal, respectively, and are electrically connected to the control terminals of the 2:1 analog switch circuit 20 and the 10:1 analog switch circuit 30. The CC1 and CC2 pins of the USB Type-C female connector serve as the SDA and SCL terminals of the I2C bus, respectively, and are electrically connected to the I2C data terminal and I2C clock terminal of the impedance measurement circuit 50. The VBUS and GND pins of the USB Type-C female connector serve as the positive and negative DC power supply terminals of the EEG transmission interface 70, respectively, and are electrically connected to the power supply terminal and common ground terminal of the buffer drive circuit 40. The 10 data pins of the Type-C female connector are electrically connected one-to-one with the output terminals of the 10-channel buffer drive circuit 40 to transmit the conditioned EEG signals.
[0048] Example 2: This invention provides a brain electrical impedance tomography (BET) method that uses both wet and dry electrodes, based on the BET device that uses both wet and dry electrodes as described in any of the embodiments in Example 1. The assembly diagram of this device is shown below. Figure 7 As shown, the dry or wet electrode 701 is soldered to the EEG electrode interface 10 of the EEG impedance detection device 702 via a flexible wire; the impedance measurement interface 60 and the EEG transmission interface 70 on the EEG impedance detection device 702 are both universal standard USB Type-C female connectors, while the EEG acquisition device 703 corresponds to a USB Type-C male connector, thereby realizing a plug-in connection.
[0049] The switching network circuit and impedance measurement integrated circuit AD5934 on this device are both controlled by the EEG acquisition device. The operating communication protocol is designed with three modes: normal mode, impedance calibration mode, and impedance measurement mode. Specific operating information is shown in Table 1. Table 1 provides the control code information for the 2:1 analog switching circuit, the 10:1 analog switching circuit, and the impedance measurement integrated circuit AD5934 for each operating mode or state, along with a functional description.
[0050] Table 1 Device Communication Protocol Information Table
[0051] like Figure 8 As shown, the specific procedure of this dual-use (dry and wet electrode) brain impedance detection method includes: The operator assembles the device, primarily by donning the EEG cap and connecting the EEG acquisition device. The device is powered on and awaits a working mode command from the EEG acquisition device. Upon receiving the command, the operator determines if it is in normal mode. If so, the 2:1 analog switch circuit switches to the EEG channel, transmitting the EEG signal to the EEG acquisition device via the driving conditioning circuit. The operator continuously monitors the working mode, maintaining signal transmission if it remains unchanged, otherwise following the new command. If it is not in normal mode, it enters impedance measurement mode. First, the 2:1 and 10:1 analog switch circuits are switched to the impedance calibration channel to complete the impedance calibration test and obtain the impedance gain coefficient. Then, the 2:1 and 10:1 analog switch circuits are controlled to sequentially measure the impedance between the active electrode, bias electrode, and reference electrode. After each channel's impedance measurement is completed, a channel switching operation is performed to proceed to the next impedance measurement, until all impedance measurement channels are completed. Then, the operator awaits a new working mode command and operates according to the new command.
[0052] In some embodiments, in this dual-purpose wet and dry electrode brain impedance detection method, the dual-purpose wet and dry electrode brain impedance detection device provided in Example 1 is equipped with impedance detection host computer software, including both PyQt and Web versions, designed to monitor the contact impedance status between the electrodes and the scalp in real time. Impedance data transmitted by the hardware module can be received via Bluetooth technology, processed professionally, and displayed in a graphical interface so that operators can quickly assess the electrode contact quality.
[0053] The host computer system consists of three core modules: a data communication layer, a data processing layer, and a user interaction layer, all deployed in a Python environment.
[0054] The data communication layer establishes a low-power connection with the hardware device based on the BLE 4.0 / 5.0 protocol stack (GATT / GAP), capable of simultaneously receiving impedance data between eight active electrodes, one bias electrode, and one reference electrode. Furthermore, this layer implements an automatic reconnection mechanism to ensure communication stability.
[0055] The data processing layer has the capability to parse unsigned integer byte data transmitted via the Bluetooth channel into the aforementioned 10-channel impedance data in real time. Through data validity verification and outlier filtering mechanisms, this layer can automatically save the original data and its processing results.
[0056] The user interaction layer employs two approaches: one is to run directly in a Python script using the PyQt framework, and the other is to forward the data to the web client via a local Flask server. This layer can display EEG topography and use a three-color grading alarm system to indicate the impedance status of each electrode location.
[0057] like Figures 9 to 11As shown, the host computer interface integrates an EEG topographic map and electrode impedance data table based on the international standard 10-20 system layout. This interface allows users to select specific electrodes and adjust the data refresh rate to meet actual acquisition needs; the initial setting is 1Hz, and the impedance data unit is 10Ω.
[0058] When the interface is started by default, both the electrodes and the data table are empty. Once the Bluetooth function is activated and the host computer establishes a connection with the EEG acquisition device, the data collected when the electrodes are suspended will be displayed as the default maximum value of 65535. After wearing the EEG acquisition device, thresholds of 2500 and 10000 are set based on experience, and the impedance data is divided into three states. The data range is visualized using three colors: green, yellow, and red, which correspond to the degree of fit between the electrodes and the scalp: good, needs adjustment, and unqualified.
[0059] Table 2. Host Computer Parameter Index Table
[0060] The above embodiments are only used to illustrate the present invention and are not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the present invention, and the patent protection scope of the present invention should be defined by the claims.
Claims
1. A brain electrical impedance detection device that can be used with both dry and wet electrodes, characterized in that, This includes an EEG electrode interface, a multi-channel 2:1 analog switch circuit, a 10:1 analog switch circuit, a multi-channel buffer drive circuit, an impedance measurement circuit, an impedance measurement interface, and an EEG transmission interface; among which: The multi-channel active electrode output terminal, 1-channel reference electrode output terminal, and 1-channel bias electrode output terminal of the EEG electrode interface are electrically connected to the input terminals of multiple 2:1 analog switch circuits, and the EEG electrode interface is compatible with the access of dry electrodes and wet electrodes. The first output of each 2:1 analog switch circuit is electrically connected to the input of one buffer drive circuit. In the second output of each 2:1 analog switch circuit, the impedance channels corresponding to multiple active electrodes and the impedance channel corresponding to one bias electrode are electrically connected to the eight active electrode impedance inputs and one bias electrode impedance input of the 10:1 analog switch circuit. At the same time, the second output of one 2:1 analog switch circuit leads out one impedance calibration channel, which is electrically connected to the calibration channel input of the 10:1 analog switch circuit. The output terminal of the 10:1 analog switch circuit is electrically connected to the first signal input terminal of the impedance measurement circuit, and the second output terminal of the 2:1 analog switch circuit corresponding to the reference electrode is directly electrically connected to the second signal input terminal of the impedance measurement circuit. The output of the multi-channel buffer drive circuit is electrically connected to the multi-channel EEG signal input of the EEG transmission interface one by one. The control signal terminal and data signal terminal of the impedance measurement circuit are electrically connected to the control signal terminal and data signal terminal of the impedance measurement interface, respectively, and the power supply terminal of the impedance measurement circuit is electrically connected to the power supply terminal of the impedance measurement interface. The power supply terminals of the 2:1 analog switch circuit, 10:1 analog switch circuit, buffer drive circuit, and impedance measurement circuit are all electrically connected to the external power supply module, and the grounding terminals are all electrically connected to the common ground terminal of the device. The 2:1 analog switch circuit is used to switch the single electrode signal between the impedance channel and the EEG channel. The 10:1 analog switch circuit is used to realize the time-division switching output of multiple impedance signals. The impedance measurement circuit is used to complete impedance calibration and electrode-scalp contact impedance measurement. The buffer drive circuit is used to drive and condition high internal resistance EEG signals. The impedance measurement interface and EEG transmission interface are used to realize the connection and signal transmission between the device and external EEG acquisition equipment.
2. The brain electrical impedance detection device that can be used with both dry and wet electrodes according to claim 1, characterized in that, The 2:1 analog switch circuit includes a three-channel 2:1 analog switch chip and an electrostatic diode; wherein: The three-channel 2:1 analog switch chip has its D1, D2, and D3 terminals shorted to form a common input terminal, its S1A, S2A, and S3A terminals shorted to form a first output terminal, its S1B, S2B, and S3B terminals shorted to form a second output terminal, and its SEL3, SEL2, and SEL1 terminals shorted to form a control terminal. The input terminal of the electrostatic diode is electrically connected to the corresponding electrode output terminal of the EEG electrode interface, and the output terminal of the electrostatic diode is electrically connected to the node after shorting the common input terminal of the three-channel 2:1 analog switch chip. The first output terminal is connected to the input terminal of the buffer drive circuit after being connected in series with a resistor. The second output terminal is connected to the corresponding input terminal of the 10:1 analog switch circuit or impedance measurement circuit after being connected in series with a resistor. The control terminal is connected to the common ground terminal after being connected in series with a pull-down resistor. The AVDD terminal and AVSS terminal of the three-channel 2:1 analog switch chip are connected to the power supply terminal respectively. The AVDD terminal is connected to the common ground terminal after being connected in parallel with the first decoupling capacitor, and the AVSS terminal is connected to the common ground terminal after being connected in parallel with the second decoupling capacitor.
3. The brain electrical impedance detection device that can be used with both dry and wet electrodes according to claim 1, characterized in that, The buffer drive circuit includes a buffer; wherein: The four input terminals of the buffer are shorted to form the input terminals of the buffer drive circuit, which are electrically connected to the first output terminal of the 2:1 analog switch circuit; the four output terminals of the buffer are connected in series with a resistor to form the output terminals of the buffer drive circuit, and the output terminals of the buffer drive circuit are electrically connected to the corresponding input terminals of the EEG transmission interface. The buffer is electrically connected to the power supply terminal. The +VS terminal of the buffer is connected in parallel with two third decoupling capacitors and then connected to the common ground terminal. The -VS terminal of the buffer is connected in parallel with two third decoupling capacitors and then connected to the common ground terminal.
4. The brain electrical impedance detection device that can be used with both dry and wet electrodes according to claim 1, characterized in that, The 10:1 analog switch circuit includes two 8:1 analog switch chips and an inverter. The two 8:1 analog switch chips are a first switch chip and a second switch chip, respectively. In the first switch chip, terminals S1-S8 are respectively connected to the first two impedance channels of the eight active electrodes, terminal S3 is connected to the bias electrode impedance channel, and terminal S4 is connected to the impedance calibration channel. Terminals S5-S8 are shorted and then connected to the common ground. In the second switch chip, terminals S1-S6 are shorted and then connected to the common ground. Terminals S7-S8 are respectively connected to the last six impedance channels of the eight active electrodes. The common output terminals of the two 8:1 analog switch chips are shorted to form the output terminal of a 10:1 analog switch circuit, which is electrically connected to the first signal input terminal of the impedance measurement circuit. In the four digital control signals output by the external MCU, the lower three bits are electrically connected to the channel selection terminals of the two 8:1 analog switch chips respectively; the highest bit is directly connected to the enable terminal of the second switch chip, and after being inverted by an inverter, it is electrically connected to the enable terminal of the first switch chip.
5. The brain electrical impedance detection device that can be used with both dry and wet electrodes according to claim 1, characterized in that, The impedance measurement circuit includes a high-precision impedance measurement integrated circuit, an active crystal oscillator module, an analog switch chip, and a calibration resistor; wherein: The output terminal of the active crystal oscillator module is electrically connected to the clock input terminal of the impedance measurement integrated circuit; the excitation signal output terminal of the impedance measurement integrated circuit is electrically connected to the first common input terminal of the analog switch chip. The analog switch chip's D1-D3 terminals are shorted to form a first common input terminal, and its S1A-S3A terminals are shorted to form a first output terminal. The first output terminal is electrically connected to one end of a calibration resistor, and the other end of the calibration resistor is connected to a common ground terminal. The analog switch chip's S1B-S3B terminals are shorted to form a second output terminal, which is electrically connected to the second output terminal of the 2:1 analog switch circuit corresponding to the reference electrode. The analog switch chip's SEL1-SEL3 terminals are shorted to form a control terminal, which is electrically connected to the control signal terminal of an external MCU. The signal acquisition input terminal of the impedance measurement integrated circuit is electrically connected to the output terminal of the 10:1 analog switch circuit, and the feedback resistor terminal of the impedance measurement integrated circuit is connected in series with a feedback resistor and then connected to the common ground terminal.
6. The brain electrical impedance detection device that can be used with both dry and wet electrodes according to claim 1, characterized in that, It also includes a PCB board, which comprises, from top to bottom, a top layer, a GND layer, a power layer, and a bottom layer; wherein: The components of the 2:1 analog switch circuit, buffer drive circuit, 10:1 analog switch circuit, and impedance measurement circuit are all soldered on the top and bottom layers. The 2:1 analog switch circuit and buffer drive circuit corresponding to each electrode adopt a symmetrical layout, and the pins of adjacent components are electrically connected through PCB wires. The signal wires of the EEG channel are laid on the top layer, and the top layer wires and the adjacent GND layer form a common ground reference plane; the signal wires of the impedance channel and the switch control signal wires are laid on the bottom layer, and the bottom layer wires are isolated from the adjacent power supply layer. The power layer is divided into a positive power area and a negative power area, which are electrically connected to the positive power terminals and negative power terminals of the top and bottom layer components through PCB vias, respectively; the GND layer is a complete copper foil plane, which is electrically connected to the ground terminals of the top and bottom layer components through PCB vias.
7. The brain electrical impedance detection device that can be used with both dry and wet electrodes according to claim 1, characterized in that, Both the impedance measurement interface and the EEG transmission interface use female connectors; wherein: The VBUS and GND pins of the female connector serve as the positive and negative DC power supply terminals of the impedance measurement interface, respectively, and are electrically connected to the power supply terminal and common ground terminal of the impedance measurement circuit. The D+ and D- pins of the female connector serve as the positive and negative transmission terminals of the analog switch control signal, respectively, and are electrically connected to the control terminals of the 2:1 analog switch circuit and the 10:1 analog switch circuit. The CC1 and CC2 pins of the female connector serve as the SDA and SCL terminals of the I2C bus, respectively, and are electrically connected to the I2C data terminal and the I2C clock terminal of the impedance measurement circuit. The VBUS and GND pins of the female connector serve as the positive and negative DC power supply terminals of the EEG transmission interface, respectively, and are electrically connected to the power supply terminal and common ground terminal of the buffer drive circuit. The 10 data pins of the female connector are electrically connected to the output terminals of the 10 buffer drive circuits, respectively, for transmitting the conditioned EEG signals.
8. A method for detecting brain electrical impedance tomography (BEE) using both wet and dry electrodes, based on the BEE device for detecting both wet and dry electrodes as described in any one of claims 1 to 7, characterized in that, The method includes: Dry or wet electrodes are soldered to the EEG electrode interface using flexible wires. After the device is powered on, it waits for the EEG acquisition device to send the working mode command; If the received instruction is in normal mode, the 2:1 analog switch circuit is switched to the EEG channel. The EEG signal is conditioned by the buffer drive circuit and then transmitted to the EEG acquisition device. The mode is continuously monitored to see if it changes. If the received instruction is in impedance measurement mode, the 2:1 analog switch circuit and the 10:1 analog switch circuit are switched to the impedance calibration channel to complete impedance calibration and obtain the impedance gain coefficient. Then, the 10:1 analog switch circuit is switched in a time-division manner to complete the impedance measurement between the 8 active electrodes, the 1 bias electrode and the reference electrode in sequence. After completing all impedance channel measurements, wait for the new operating mode command and execute the corresponding operation.
9. The brain electrical impedance detection method using both dry and wet electrodes according to claim 8, characterized in that, In the normal mode, the command states of the 2:1 analog switch circuit control ports cnt6-cnt1 are in the preset first state, and the 10:1 analog switch circuit control ports cnt10-cnt7 are in any state. The impedance measurement integrated circuit is in power-down mode. In the impedance calibration mode, the command states of the 2:1 analog switch circuit control ports are in the preset second state, and the command states of the 10:1 analog switch circuit control ports are in the preset third state. The impedance measurement integrated circuit is in working mode. In the impedance measurement mode, the command states of the 2:1 analog switch circuit control ports are in the preset fourth state, and the command states of the 10:1 analog switch circuit control ports are in the preset fifth state. The impedance measurement integrated circuit is in working mode.
10. The brain electrical impedance detection method using both dry and wet electrodes according to claim 8, characterized in that, The method further includes a host computer processing step for impedance data, wherein the host computer processing step for impedance data includes: Acquire impedance data for 10 channels; The 10 impedance data are parsed, their validity is verified, and outliers are filtered. The original data and processing results are saved. Based on the processing results, the brain topography map is displayed through the front-end interface, and the electrode impedance status is indicated by a three-color grading method. Different electrode impedance statuses correspond to different degrees of fit.