Package test method based on power supply pin distribution

Abstract

The invention provides a packaging test method based on power supply pin distribution, which belongs to the technical field of chip testing, and comprises the following steps: sorting and analyzing the number of power supply pins of all DDR (Double Data Rate) chips, dividing four paths of power supplies of a board card into multiple paths through an analog switch, and supplying power to a single power supply channel of the chip; each path of power supply channel is connected with a path of PMU channel, and FVMI and FIMV tests are carried out through the PMU channels; the single power supply channel is composed of a power supply channel and a PMU channel, and the PMU channel is composed of a PMU channel and a grounding channel; and according to a test requirement, a channel connected with the chip is controlled. According to the invention, four paths of power supplies of the board card are divided into multiple paths through the analog switch, so that power can be effectively supplied to a single power supply channel of the chip, and reasonable distribution of the power supplies is realized. And each power supply channel is connected with a PMU channel, so that FVMI and FIMV test channels are constructed, and specific test requirements are met.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a packaging testing method based on power pin allocation. Background Art

[0002] The existing chip power channel packaging test method has the following problems:

[0003] Test equipment and cost:

[0004] Expensive equipment: Chip packaging and testing equipment is expensive. For example, the construction of IC packaging and testing laboratories is often difficult for universities to undertake independently and needs to be built together with enterprises. This limits some research institutions and small enterprises from carrying out chip power channel packaging and testing.

[0005] High cost: During the testing process, such as electrostatic discharge (ESD) testing, professional testing equipment and tools are required. The purchase and maintenance costs of these equipment are high, which increases the overall cost of testing.

[0006] Testing technology and methods:

[0007] Technical limitations: With the continuous development of chip packaging technology, such as smaller packaging pitch and higher density, the design and manufacture of test tools such as test sockets have become very difficult. Traditional testing methods may not be able to meet the testing requirements of new packaging forms.

[0008] Single method: The current testing methods mainly focus on electrical performance testing, and the testing methods for the reliability and stability of chip power channels in actual working environments are not perfect enough.

[0009] Test standards and specifications:

[0010] Inconsistent standards: Different chip manufacturers and testing organizations may adopt different testing standards and specifications, resulting in poor comparability and consistency of test results.

[0011] Incomplete specifications: For some new chip power channel packaging forms, the relevant test specifications and standards are not yet complete, and there is a lack of clear test requirements and method guidance.

[0012] Therefore, there is an urgent need in the art for a technical solution that can adapt to a variety of DDR chip power pins for packaging and testing.

[0013] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0014] The purpose of the present invention is to provide a method capable of adapting to a variety of DDR chip power pins for packaging testing.

[0015] To achieve the above object, the present invention provides the following solutions:

[0016] A package testing method based on power pin assignment, comprising:

[0017] The number of power pins of all DDR chips is sorted and analyzed, and the 4-way power supply of the board is divided into multiple ways through analog switches to supply power to the single power channel of the chip;

[0018] Connect a PMU channel to each power channel, and perform FVMI and FIMV tests through the PMU channel; a single power channel consists of a power channel and a PMU channel, and a PMU channel consists of a PMU channel and a ground channel; control the channel connected to the chip according to test requirements.

[0019] Optional power channel package test items include:

[0020] Test the diode between power supply and ground, test short circuit within power supply group and open circuit between power supply groups.

[0021] Optionally, the diode between the test power supply and the ground is specifically:

[0022] All power groups except the one under test are left hanging;

[0023] Send negative current to each power supply group to read back the voltage test;

[0024] If the power pack is short-circuited to the ground, the test result will be -0.1~0.1V;

[0025] If the diode between the power pack and the ground is damaged or broken, the test result will be greater than the normal value.

[0026] Optionally, the short circuit in the testing power supply group is specifically:

[0027] Connect a single pin of the power bank to ground;

[0028] Sending a positive current to read back the voltage to the other pins of the power supply group except the ground pin;

[0029] The power pins in the same group are turned on, so the pin under test should be connected to the ground power pin and grounded. The test result should be -0.1~0.1V;

[0030] On the contrary, if the power pin in the power group is not conducting, the result is open.

[0031] Optionally, the open circuit test between power supply groups is as follows:

[0032] All power supply groups except the one under test are grounded;

[0033] When the diode between the power supply and the ground is tested intact, send a negative current to the power supply group under test and read back the voltage test; if the short circuit test result between the power supply groups is -0.1~0.1V.

[0034] Optionally, the number of channels of the power supply channel is:

[0035] The first power supply has 40 channels; the second power supply has 32 channels; the third power supply has 24 channels; and the fourth power supply has 16 channels.

[0036] Compared with the prior art, the present invention has the following beneficial effects:

[0037] The present invention provides a packaging test method based on power pin allocation, which solves the problem of sorting and analyzing the number of power pins of a DDR chip, and helps to better understand the power supply requirements of the chip. By utilizing the 4-way power supply of the board and dividing it into multiple ways through an analog switch, the single power supply channel of the chip can be effectively powered, thereby realizing the reasonable distribution of power. The PMU channel is connected to each power supply channel, and a channel for FVMI and FIMV testing is constructed to meet specific test requirements. The composition structure of a single power supply channel and a PMU channel is clarified, providing a theoretical basis for the construction of power supply and test channels. The control connection can control the channel connected to the chip according to the test requirements, thereby improving the flexibility and pertinence of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0039] Figure 1 A schematic diagram of a single power supply channel structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0041] The purpose of the present invention is to provide a technical solution capable of adapting to a variety of DDR chip power pins for packaging testing.

[0042] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0043] Embodiment 1:

[0044] This embodiment provides a packaging test method based on power pin allocation, including:

[0045] The number of power pins of all DDR chips is sorted and analyzed, and the 4-way power supply of the board is divided into multiple ways through analog switches to supply power to the single power channel of the chip;

[0046] Connect a PMU channel to each power channel, and perform FVMI and FIMV tests through the PMU channel; a single power channel consists of a power channel and a PMU channel, and a PMU channel consists of a PMU channel and a ground channel; control the channel connected to the chip according to test requirements.

[0047] In one embodiment, the power channel package test items include:

[0048] Test the diode between power supply and ground, test short circuit within power supply group and open circuit between power supply groups.

[0049] In one embodiment, the diode between the test power supply and the ground is specifically:

[0050] All power groups except the one under test are left hanging;

[0051] Send negative current to each power supply group to read back the voltage test;

[0052] If the power pack is short-circuited to the ground, the test result will be -0.1~0.1V;

[0053] If the diode between the power pack and the ground is damaged or broken, the test result will be greater than the normal value.

[0054] In one embodiment, the short circuit in the testing power supply group is specifically:

[0055] Connect a single pin of the power bank to ground;

[0056] Sending a positive current to read back the voltage to the other pins of the power supply group except the ground pin;

[0057] The power pins in the same group are turned on, so the pin under test should be connected to the ground power pin and grounded. The test result should be -0.1~0.1V;

[0058] On the contrary, if the power pin in the power group is not conducting, the result is open.

[0059] In one embodiment, the open circuit test between power supply groups is specifically as follows:

[0060] All power supply groups except the one under test are grounded;

[0061] When the diode between the power supply and the ground is tested intact, send a negative current to the power supply group under test and read back the voltage test; if the short circuit test result between the power supply groups is -0.1~0.1V.

[0062] In one embodiment, Figure 1 The single power supply channel structure shown in the figure has the following channel number:

[0063] The first power supply has 40 channels; the second power supply has 32 channels; the third power supply has 24 channels; and the fourth power supply has 16 channels.

[0064] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0065] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A packaging test method based on power pin allocation, characterized in that: include: The number of power pins of all DDR chips is sorted and analyzed, and the 4-way power supply of the board is divided into multiple ways through analog switches to supply power to the single power channel of the chip; Connect a PMU channel to each power channel and perform FVMI and FIMV tests through the PMU channel; The single power supply channel consists of a power supply channel and a PMU channel, and the PMU channel consists of a PMU channel and a ground channel; Control the channels to which the chip is connected according to test requirements.

2. The packaging test method based on power pin allocation according to claim 1, characterized in that: Power channel package test items include: Test the diode between power supply and ground, test short circuit within power supply group and open circuit between power supply groups.

3. The packaging test method based on power pin allocation according to claim 2, characterized in that: The diode between the test power supply and the ground is specifically: All power groups except the one under test are left hanging; Send negative current to each power supply group to read back the voltage test; If the power pack is short-circuited to the ground, the test result will be -0.1~0.1V; If the diode between the power pack and the ground is damaged or broken, the test result will be greater than the normal value.

4. The packaging test method based on power pin allocation according to claim 2, characterized in that: The short circuit in the test power supply group is specifically: Connect a single pin of the power bank to ground; Sending a positive current to read back the voltage to the other pins of the power supply group except the ground pin; The power pins in the same group are turned on, so the pin under test should be connected to the ground power pin and grounded. The test result should be -0.1~0.1V; On the contrary, if the power pin in the power group is not conducting, the result is open.

5. The packaging test method based on power pin allocation according to claim 2, characterized in that: The open circuit test between power supply groups is as follows: All power supply groups except the one under test are grounded; When the diode between the power supply and the ground is tested intact, send a negative current to the power supply group under test and read back the voltage test; if the short circuit test result between the power supply groups is -0.1~0.1V.

6. The packaging test method based on power pin allocation according to claim 1, characterized in that: The number of channels of the power supply channel is: The first power supply has 40 channels; the second power supply has 32 channels; the third power supply has 24 channels; and the fourth power supply has 16 channels.

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