Active anti-interference control method and system based on radar

Abstract

The present invention relates to the field of radar control technology, and specifically to a radar-based active anti-interference control method and system. In the radar system parameter agile transition state, the timestamp of the waveform parameters is accurately marked by the hardware synchronization clock to improve the timing accuracy. At the same time, the digital delay phase-locked loop technology is used to perform timing calibration on the receiving end signal processor to effectively compensate for the PRI parameter deviation caused by the parameter agility between the transmitting end and the receiving end. When it is detected that the deviation exceeds the preset threshold (such as 10ns), the microsecond timing compensation operation is automatically triggered to improve the accuracy of signal processing, thereby improving the accuracy of radar control and allowing the radar system to enter a steady-state working stage.

Description

Technical Field

[0001] The present invention relates to the field of radar control technology, and in particular to a radar-based active anti-interference control method and system. Background Art

[0002] Radar's active anti-interference technology is a technology that actively destroys or offsets external interference signals by intelligently controlling the radar's transmission signal characteristics or receiving processing methods. Its core principle is to enable the radar to have dynamic game capabilities, such as switching the frequency of the transmission signal in real time (frequency agility), changing the polarization mode (polarization agility) or randomly adjusting the waveform parameters (waveform agility), making it difficult for enemy interference equipment to accurately capture and imitate radar signal characteristics; at the same time, combined with digital beamforming technology, the direction of the interference source is intelligently identified at the receiving end and a targeted "zero-point beam" is generated to suppress interference, and the interference signal is analyzed in real time with artificial intelligence algorithms and dynamic confrontation strategy adjustments are made. It is like installing an "electronic shield" that can make autonomous decisions on the radar, which improves the radar's target detection and tracking capabilities in complex electromagnetic environments. It is widely used in military fields such as fighter jets, ships and drones.

[0003] In the actual application of radar active anti-interference control technology, dynamic adjustment of signal parameters (such as frequency agility and waveform agility) requires real-time calculation and response at the millisecond level, which places almost extreme requirements on hardware computing power (such as data throughput rate of FPGA / GPU) and algorithm efficiency (such as convergence speed of parameter optimization model). The existing hardware architecture is prone to resource competition when processing radar basic detection and intelligent anti-interference tasks in parallel, which will lead to parameter switching delays or agility mode mismatch. For example, if the pulse repetition interval (PRI) and waveform modulation parameters are not accurately synchronized during waveform agility, false targets will be generated or real echoes will be lost. Such errors will directly reduce the effective control of the radar and reduce the tracking accuracy of moving targets. Summary of the invention

[0004] In view of the shortcomings existing in the prior art, the present invention provides a radar-based active anti-interference control method and system to solve the problem that the extreme requirements of radar dynamic signal parameter adjustment on hardware computing power and algorithm efficiency trigger system resource competition, lead to agile mode mismatch (such as PRI synchronization failure), cause false target generation, true echo loss and reduced tracking accuracy, and weaken the control reliability of the radar system.

[0005] In a first aspect, the present invention provides a radar-based active anti-interference control method, comprising the following steps:

[0006] Receiving a radar echo signal and extracting interference characteristic parameters from the radar echo signal;

[0007] Determining an operating mode of the real-time radar system, wherein the operating mode of the real-time radar system includes a tracking mode, a search mode, and an anti-interference enhancement mode;

[0008] Based on the matching result between the working mode of the real-time radar system and the interference characteristic parameters, an anti-interference control strategy is dynamically selected through a hierarchical decision-making architecture, wherein the hierarchical decision-making architecture includes a core decision-making layer and an auxiliary optimization layer;

[0009] Generate parameter adjustment instructions according to the selected anti-interference control strategy, control the radar transmitter to perform waveform parameter agility operations, and perform timing calibration on the receiving end signal processor through a digital delay phase-locked loop to synchronize the waveform parameters of the transmitter and receiver.

[0010] Furthermore, in the radar-based active anti-interference control method of the present invention, the dynamic selection of the anti-interference control strategy includes:

[0011] Through a hierarchical decision-making architecture (the core decision layer performs nanosecond parameter switching, and the auxiliary optimization layer monitors the signal-to-interference-noise ratio change rate and dynamically updates the mode library), the anti-interference control strategy is dynamically selected to solve the agile mode mismatch problem caused by hardware resource competition.

[0012] When the working mode of the real-time radar system is the tracking mode and the interference type in the interference characteristic parameters is pulse interference, a first control strategy is selected, and the first control strategy includes: performing random agility of the pulse repetition interval PRI through the FPGA, and enabling the GPU to perform target trajectory prediction compensation; when the working mode of the real-time radar system is the search mode and the interference type in the interference characteristic parameters is identified as continuous wave interference, a second control strategy is selected, and the second control strategy includes: performing frequency agility through the ASIC chipset, and starting beam nulling to align the direction of the interference source; when the working mode of the real-time radar system is the anti-interference enhancement mode and the interference characteristic parameters are characterized as unknown interference patterns, a third control strategy is selected, and the third control strategy includes:

[0013] The AI ​​adversarial network after knowledge distillation and compression is used to identify interference features, and a reward mechanism is built based on the Q-learning algorithm. The anti-interference parameter combination is dynamically generated through the signal-to-interference-noise ratio change rate and the target tracking error, and is updated to the anti-interference pattern library in real time;

[0014] When the working mode does not match the interference characteristic parameters, perform the following operations:

[0015] If the working mode of the real-time radar system is the tracking mode or the search mode, and the cosine similarity β between the interference characteristic parameter and the preset interference pattern in the pattern library is less than 0.6, the anti-interference enhancement mode is activated and the third control strategy is called;

[0016] If the working mode of the real-time radar system is the anti-interference enhancement mode, the anti-interference parameter combination is dynamically generated based on the Q-learning algorithm.

[0017] Furthermore, the radar-based active anti-interference control method of the present invention further includes:

[0018] When the radar system is in a parameter agile transition state, the timestamp of the current waveform parameter is marked by a hardware synchronization clock; the timing of the receiving end signal processor is calibrated by a digital delay phase-locked loop, and the calibration includes: when it is detected that the PRI parameter deviation between the transmitting end and the receiving end exceeds 10ns, the microsecond timing compensation operation is triggered; when the waveform parameter switching completion degree reaches more than 95%, the compensation operation is turned off and the steady-state working stage is entered;

[0019] The waveform parameter switching completion degree is calculated by the following formula:

[0020] Completion degree = {number of parameters switched in real time / total number of parameters to be switched} × 100%.

[0021] Furthermore, in the radar-based active anti-interference control method described in the present invention, the hierarchical decision-making architecture includes: a core decision layer, deployed in the FPGA for executing nanosecond-level parameter switching, calling the PRI-waveform mapping table in the preset anti-interference mode library; an auxiliary optimization layer, deployed in the CPU for performing the following operations: real-time monitoring of the signal-to-interference-noise ratio change rate ΔSINR / Δt after parameter switching; when the absolute value of ΔSINR / Δt exceeds the threshold value α, generating a mode library update instruction; and compensating for the target tracking error caused by parameter agility through an online reinforcement learning algorithm.

[0022] Furthermore, in the radar-based active anti-interference control method described in the present invention, the updating of the anti-interference pattern library includes: collecting a time-frequency domain joint feature matrix of interference samples not recorded in the pattern library; calculating the cosine similarity β between the feature matrix and the existing pattern library; when β < 0.6, adding a new independent interference entry to the pattern library and associating the optimal anti-interference parameter combination dynamically generated based on the Q-learning algorithm, including the frequency agility step, PRI random sequence and beam nulling azimuth; when 0.6 ≤ β ≤ 0.8, optimizing the parameter weight coefficient of the existing entry;

[0023] It also includes a dynamic resource allocation mechanism: dynamic resource allocation is performed through a heterogeneous resource scheduler, and the heterogeneous resource scheduler includes: a first scheduling channel, the first scheduling channel is configured to preferentially allocate more than 70% of FPGA resources for parameter agility operations when the interference intensity level is level I (signal to interference and noise ratio SINR>10dB), and allocate 50% of GPU resources for target tracking filtering, and allocate GPU resources for target tracking filtering; a second scheduling channel is configured to activate the ASIC chipset to perform parallel operations when the interference intensity level is level II, including: generating a spatial filter matrix through a beamforming algorithm; performing interference cancellation operations using a hardware acceleration unit; and outputting a false target suppression rate indicator of a radar image in real time; wherein the heterogeneous resource scheduler dynamically switches the first scheduling channel or the second scheduling channel according to the interference intensity level.

[0024] In the second aspect, the radar-based active anti-interference control system provided by the present invention is applied to the radar-based active anti-interference control method, including: a signal processing module, configured to receive a radar echo signal and extract interference characteristic parameters in the echo signal; a pattern recognition module, connected to the signal processing module, configured to determine the working mode of the current real-time radar system, the working mode including a tracking mode, a search mode and an anti-interference enhancement mode; a strategy decision module, configured to dynamically select an anti-interference control strategy through a hierarchical decision architecture based on the matching result of the working mode of the real-time radar system and the interference characteristic parameters, the hierarchical decision architecture including a core decision layer and an auxiliary optimization layer; an execution control module, configured to generate a parameter adjustment instruction according to the selected anti-interference control strategy, and control the radar transmitter to perform a waveform parameter agile operation; a synchronization calibration module, configured to perform timing calibration on the receiving end signal processor through a digital delay phase-locked loop to synchronize the waveform parameters of the transmitting end and the receiving end.

[0025] Furthermore, in the radar-based active anti-interference control system of the present invention, the strategy decision module includes: a first control unit, which is activated when the working mode is a tracking mode and the interference characteristic parameter is characterized as a pulse interference, including:

[0026] an FPGA accelerator configured to perform random agility of a pulse repetition interval PRI;

[0027] A GPU coprocessor configured to enable target trajectory prediction compensation;

[0028] The second control unit is activated when the working mode is the search mode and the interference characteristic parameter is characterized as continuous wave interference, and includes:

[0029] An ASIC chipset configured to perform frequency agility;

[0030] A beam former configured to initiate a beam null to align in the direction of an interference source;

[0031] The third control unit is activated when the working mode is the anti-interference enhancement mode and the interference characteristic parameter is characterized as an unknown interference pattern, and includes:

[0032] The AI ​​inference engine is configured to call the lightweight AI adversarial network after knowledge distillation compression for interference feature recognition. The teacher network is a deep residual network (ResNet-18) with 10M parameters, and the student network is compressed to 1M parameters through channel pruning and quantization joint optimization. The input is the joint feature matrix in the time-frequency domain (dimension 128×128), and the output is the interference classification result.

[0033] The reinforcement learning module is configured to build a reward mechanism based on the Q-learning algorithm, dynamically generate anti-interference parameter combinations through the signal-to-interference-noise ratio change rate and the target tracking error, and update them to the anti-interference pattern library in real time.

[0034] Furthermore, in the radar-based active anti-interference control system of the present invention, the synchronous calibration module includes:

[0035] A hardware clock generator, embedded in the radar transmitter, configured to timestamp the current waveform parameter in a parameter agile transition state;

[0036] A digital delay-locked loop circuit is connected to the receiving end signal processor and is configured as follows:

[0037] Detect the PRI parameter deviation between the transmitter and the receiver;

[0038] When the PRI parameter deviation between the transmitter and the receiver is detected to exceed 10ns (error range ±2ns), the microsecond timing compensation operation is triggered;

[0039] When the waveform parameter switching completion degree reaches more than 95%, the compensation operation is turned off and the steady-state working stage is entered; wherein the completion degree is calculated by the formula:

[0040] Completion degree = {number of parameters switched in real time / total number of parameters to be switched} × 100%.

[0041] Furthermore, in the radar-based active anti-interference control system of the present invention, the hierarchical decision architecture includes: a core decision layer, deployed in an FPGA, including: a parameter agile controller;

[0042] Anti-interference mode memory, storing PRI-waveform mapping table;

[0043] The auxiliary optimization layer is deployed in the CPU and is configured as follows:

[0044] Real-time monitoring of the signal-to-interference-noise ratio change rate ΔSINR / Δt after parameter switching;

[0045] When the absolute value of ΔSINR / Δt exceeds the threshold value α, a pattern library update instruction is generated;

[0046] The target tracking error caused by parameter agility is compensated by an online reinforcement learning algorithm.

[0047] Furthermore, the radar-based active anti-interference control system of the present invention further includes: an anti-interference pattern library updating unit configured as follows:

[0048] Collect the time-frequency domain joint feature matrix of the interference samples not recorded in the pattern library;

[0049] Calculating the cosine similarity β between the matrix and the existing pattern library;

[0050] When β < 0.6, a new independent interference entry is added to the pattern library and associated with the optimal anti-interference parameter combination dynamically generated based on the Q-learning algorithm, including the frequency agility step size, PRI random sequence and beam nulling azimuth angle;

[0051] When 0.6≤β≤0.8, optimize the parameter weight coefficient of the existing entry; heterogeneous resource scheduler, including:

[0052] The first scheduling channel is configured to allocate more than 70% of the FPGA resources for parameter agility operations and 50% of the GPU resources for target tracking filtering when the interference intensity level is level I;

[0053] The second scheduling channel is configured to activate the ASIC chipset to perform parallel operations when the interference intensity level is level II, including:

[0054] Beamforming calculation kernel, generating spatial filter matrix;

[0055] Interference cancellation unit, which performs hardware-accelerated matrix inversion operations;

[0056] The suppression rate evaluator outputs the false target suppression rate indicator in real time.

[0057] The advantages and beneficial effects of the present invention are:

[0058] The present invention dynamically selects an anti-interference control strategy. The present invention can adjust anti-interference measures in real time according to the working mode and interference characteristic parameters of the radar system, adapt to various types of interference signals, and improve the anti-interference ability of the radar system in a complex electromagnetic environment.

[0059] The present invention uses high-performance hardware acceleration units to achieve parallel processing, and rationally allocates hardware resources through a dynamic resource allocation mechanism, ensuring that key tasks can obtain sufficient computing resources. This not only improves the algorithm execution efficiency, but also reduces system resource competition and avoids the agile mode mismatch problem caused by insufficient resources.

[0060] By using hardware synchronization clock marks and digital delay locked loop (DLL) for timing calibration, the present invention ensures the timing synchronization between the transmitter and the receiver, reduces the problem of false target generation and real echo loss caused by PRI synchronization failure, and further improves the target detection accuracy and reliability of the radar system.

[0061] The hierarchical decision-making architecture constructed by the present invention realizes nanosecond-level parameter switching and real-time monitoring of the signal-to-interference-noise ratio change rate, and compensates for target tracking errors through an online reinforcement learning algorithm, thereby improving decision-making efficiency and tracking accuracy. This enables the radar system to track targets more accurately and reduce tracking failures caused by decision delays or errors.

[0062] The present invention improves the adaptability and accuracy of the pattern library to new interference by collecting interference samples not recorded in the pattern library and dynamically updating the anti-interference pattern library. This enables the radar system to identify and respond to new interference more quickly and maintain the continued effectiveness of its anti-interference capability.

[0063] In summary, the present invention effectively improves the radar system's anti-interference capability, hardware resource utilization efficiency, timing synchronization and calibration accuracy, decision efficiency and tracking accuracy, as well as the adaptability and accuracy of the pattern library through a series of innovative technical measures. These beneficial effects work together on the radar system, enhancing its control reliability and target detection accuracy, and providing technical support for the development and application of radar technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 It is a flow chart of the active anti-interference control method based on radar. DETAILED DESCRIPTION

[0065] An embodiment of the present invention is further described below with reference to the accompanying drawings.

[0066] In a first aspect, the present invention provides a radar-based active anti-interference control method, comprising the following steps:

[0067] Step S101, receiving a radar echo signal, and extracting interference characteristic parameters in the radar echo signal;

[0068] Signal receiving link: The radar receiver adopts a superheterodyne receiving architecture, enhances the echo signal through a low noise amplifier (LNA), down-converts it to an intermediate frequency (IF) through a mixer, and finally digitizes it through a high-speed ADC (e.g., 4GSPS sampling rate).

[0069] Interference feature extraction method: Use time-frequency joint analysis algorithm (such as short-time Fourier transform or Wigner-Ville distribution) to extract the following feature parameters:

[0070] Interference type: Pulse interference (PW < 1μs), continuous wave interference (constant frequency) and unknown interference (atypical time-frequency characteristics) are distinguished by pulse width (PW) and duty cycle.

[0071] Interference intensity level: divided into Level I (SINR>10dB) and Level II (SINR≤10dB) according to the dynamic range of signal-to-interference-plus-noise ratio (SINR).

[0072] Interference source azimuth: The spatial angle of the interference source is calculated using digital beamforming (DBF) technology (accuracy ≤ 0.5°).

[0073] Signal processing module: Adopts Xilinx Zynq UltraScale+ RFSoC chip, integrating 8-channel parallel processing core to achieve real-time feature extraction (processing delay ≤ 0.1ms).

[0074] Step S102, determining an operating mode of the real-time radar system, wherein the operating modes of the real-time radar system include a tracking mode, a search mode, and an anti-interference enhancement mode;

[0075] Tracking Mode:

[0076] Trigger condition: The radar locks the target and the target's motion state is stable (speed change rate <5m / s²).

[0077] Core requirements: Ensure pulse repetition interval (PRI) stability (jitter <10ns) and prioritize FPGA resources for target tracking filtering.

[0078] Search Mode:

[0079] Trigger condition: The radar is in wide-area scanning state (beam scanning speed ≥ 30° / s).

[0080] Core requirements: Support fast frequency agility (frequency hopping step size 10MHz, dwell time ≤ 0.1ms).

[0081] Anti-interference enhancement mode:

[0082] Trigger condition: unknown interference pattern is detected (cosine similarity β < 0.6) or strategy matching fails (ΔSINR / Δt > 3dB / ms).

[0083] Pattern recognition module implementation:

[0084] The state machine deployed in the CPU dynamically switches the working mode (switching response time ≤ 0.5ms) by real-time monitoring of target motion parameters and interference characteristics.

[0085] Step S103, based on the matching result between the working mode of the real-time radar system and the interference characteristic parameters, dynamically selecting an anti-interference control strategy through a hierarchical decision-making architecture, wherein the hierarchical decision-making architecture includes a core decision-making layer and an auxiliary optimization layer;

[0086] Strategy matching and execution logic:

[0087] The first control strategy (tracking mode + pulse interference):

[0088] FPGA performs PRI agility: calling the pre-stored PRI random sequence table (range 100μs-500μs), generating agile instructions through hardware description language (HDL), and switching delay ≤ 50ns.

[0089] GPU trajectory prediction compensation: Run the Extended Kalman Filter (EKF) algorithm to predict the target position based on historical trajectory data and compensate for the tracking error caused by PRI agility (mean square error ≤ 0.1°).

[0090] Second control strategy (search mode + continuous wave interference):

[0091] ASIC chipset frequency agility: frequency hopping in 10MHz steps within the X-band (8-12GHz), with direct digital synthesizer (DDS) generating frequency hopping signals (phase noise ≤ -110dBc / Hz).

[0092] Beam nulling: Based on the azimuth of the interference source, a null beam with a depth of -30dB (azimuth alignment error ≤ 0.2°) is generated in the digital beamforming (DBF) at the receiving end.

[0093] The third control strategy (anti-interference enhancement mode + unknown interference):

[0094] The AI ​​inference engine loads a lightweight adversarial network compressed by knowledge distillation, where the teacher network is a deep residual network (ResNet-18) containing 10M parameters, and the student network is compressed to 1M parameters through the feature mapping loss function. The compression method is channel pruning and quantization joint optimization, input time-frequency domain joint feature matrix (dimension 128×128), and output interference classification results (inference time ≤ 1ms).

[0095] Reinforcement learning parameter optimization: construct a reward function based on the Q-learning algorithm, as detailed in the implementation example, and dynamically generate anti-interference parameter combinations (such as joint agility sequences).

[0096] Step S104, generating parameter adjustment instructions according to the selected anti-interference control strategy, controlling the radar transmitter to perform waveform parameter agility operation, and performing timing calibration on the receiving end signal processor through a digital delay phase-locked loop to synchronize the waveform parameters of the transmitting end and the receiving end.

[0097] Agile waveform parameter operation

[0098] Transmitter control: Generates parameter adjustment instructions (such as frequency, PRI, modulation mode) through FPGA to control the RF front end to perform agile switching (switching delay ≤ 0.2ms).

[0099] Digital Delay Locked Loop (DLL) Calibration:

[0100] Timing deviation detection: Real-time comparison of the PRI timestamps of the transmitter and receiver (accuracy ≤ 5ns), triggering compensation when the deviation is >10ns.

[0101] Microsecond compensation: The signal processing timing at the receiving end is adjusted through a variable delay line (VDL). The compensation amount calculation formula is detailed in the embodiment.

[0102] Completion determination: When the parameter switching completion degree is ≥ 95% (see the embodiment for the formula), the compensation is turned off and the steady state is entered.

[0103] Synchronous calibration module implementation:

[0104] Hardware clock generator: uses oven controlled crystal oscillator (OCXO), with frequency stability of ±0.1ppb.

[0105] EPSON SG-8101 oven controlled crystal oscillator (OCXO) is used, with a frequency stability of ±0.05ppb (test conditions: full temperature range -55℃~105℃), and the measured timestamp synchronization error is ≤5ns.

[0106] Digital Delayed Phase-Locked Loop Circuit: Design a third-order loop filter (bandwidth 100kHz, phase margin 60°) based on the ADISimPLL model.

[0107] Specifically, in the radar-based active anti-interference control method of the present invention, the dynamic selection of the anti-interference control strategy includes:

[0108] When the working mode of the real-time radar system is the tracking mode and the interference type in the interference characteristic parameters is pulse interference, a first control strategy is selected, and the first control strategy includes: performing random agility of the pulse repetition interval PRI through the FPGA, and enabling the GPU to perform target trajectory prediction compensation; when the working mode of the real-time radar system is the search mode and the interference type in the interference characteristic parameters is identified as continuous wave interference, a second control strategy is selected, and the second control strategy includes: performing frequency agility through the ASIC chipset, and starting beam nulling to align the direction of the interference source; when the working mode of the real-time radar system is the anti-interference enhancement mode and the interference characteristic parameters are characterized as unknown interference patterns, a third control strategy is selected, and the third control strategy includes:

[0109] The AI ​​adversarial network after knowledge distillation and compression is used to identify interference features, and a reward mechanism is built based on the Q-learning algorithm. The anti-interference parameter combination is dynamically generated through the signal-to-interference-noise ratio change rate and the target tracking error, and is updated to the anti-interference pattern library in real time;

[0110] When the working mode does not match the interference characteristic parameters, perform the following operations:

[0111] If the working mode of the real-time radar system is the tracking mode or the search mode, and the cosine similarity β between the interference characteristic parameter and the preset interference pattern in the pattern library is less than 0.6, the anti-interference enhancement mode is activated and the third control strategy is called;

[0112] If the working mode of the real-time radar system is the anti-interference enhancement mode, the anti-interference parameter combination is dynamically generated based on the Q-learning algorithm.

[0113] Dynamic selection logic of control strategy:

[0114] The first control strategy (tracking mode + pulse interference):

[0115] Applicable scenarios:

[0116] The radar is in a high-precision target tracking state (such as tracking a high-speed fighter) and detects pulse interference (the interference characteristics are short-term high peak power and fixed repetition frequency).

[0117] Technical implementation:

[0118] FPGA performs PRI random agility:

[0119] Call the pre-stored PRI random sequence table (for example, a pseudo-random sequence in the range of 100μs-500μs) and generate agile instructions through hardware logic to ensure the unpredictability of the pulse interval (random seed update period ≤ 1ms).

[0120] Hardware acceleration advantage: FPGA's parallel processing capability supports nanosecond-level parameter switching (delay ≤ 0.2ms), avoiding delays caused by CPU software processing.

[0121] GPU target trajectory prediction compensation:

[0122] Run the Kalman filter algorithm to predict the future motion state based on the target's historical trajectory (such as position, velocity, acceleration) and compensate for the echo interval jitter caused by PRI agility.

[0123] GPU parallel computing capability: supports multi-target tracking (e.g. tracking 8 targets simultaneously), with prediction error ≤ 0.1° (measured value).

[0124] Second control strategy (search mode + continuous wave interference):

[0125] Applicable scenarios:

[0126] The radar is in a large-scale search state (such as scanning for aerial targets) and detects continuous wave interference (the interference characteristics are constant frequency and high duty cycle).

[0127] Technical implementation:

[0128] ASIC chipset performs frequency agility:

[0129] Frequency hopping in 10MHz steps within the X-band (8-12GHz), high-speed frequency switching (dwell time ≤ 0.1ms) is achieved through application-specific integrated circuits (ASICs).

[0130] Anti-interference effect: The frequency hopping sequence dynamically avoids interference frequencies, making it impossible for enemy interference equipment to continuously track radar signals.

[0131] Beam nulling is directed towards the interference source:

[0132] Based on the azimuth of the interference source (obtained through DBF calculation), a null beam with a depth of -30 dB is generated in the digital beamforming at the receiving end to suppress the energy of the interference signal.

[0133] Advantages of spatial filtering: The zero-notch beam width is ≤2°, which can accurately suppress interference in a specific direction.

[0134] The third control strategy (anti-interference enhanced mode + unknown interference):

[0135] Applicable scenarios:

[0136] Unknown interference patterns are detected (e.g., mixed modulation interference, new electronic warfare signals), or strategy matching fails (e.g., ΔSINR / Δt>3dB / ms).

[0137] Technical implementation:

[0138] Knowledge distillation compressed AI adversarial network:

[0139] A lightweight network (parameter count ≤ 1M) is used, the input is a joint feature matrix in the time-frequency domain (dimension 128×128), and the output is the interference type recognition result (inference time ≤ 1ms).

[0140] Knowledge distillation technology: A lightweight student network is obtained by compressing the teacher network (parameter volume 10M), maintaining recognition accuracy (accuracy ≥ 95%) while reducing the computational load.

[0141] Q-learning dynamic parameter generation:

[0142] Reward mechanism: Dynamically adjust weights according to the signal-to-interference-plus-noise ratio change rate (ΔSINR) and target tracking error (MSE) to generate the optimal anti-interference parameter combination (such as PRI-frequency joint agility sequence).

[0143] Pattern library update: Store new parameter combinations to the anti-interference pattern library in real time to support quick call of subsequent strategies.

[0144] Fault-tolerant handling mechanism for mode mismatch:

[0145] Mismatch handling in trace / search mode:

[0146] Trigger condition: The operating mode (tracking or searching) of the real-time radar system does not match the interference characteristic parameters (for example, continuous wave interference is detected in tracking mode).

[0147] Processing flow:

[0148] Immediately activate the anti-interference enhancement mode and call the third control strategy (AI interference recognition + Q-learning parameter generation).

[0149] Synchronously update the pattern library: associate new interference features with generation parameters to prevent the same type of interference from triggering pattern mismatch again.

[0150] Mismatch handling in anti-interference enhanced mode:

[0151] Trigger condition: The anti-interference enhancement mode still cannot effectively suppress interference (for example, ΔSINR continues to deteriorate).

[0152] Processing flow:

[0153] Based on the Q-learning algorithm, the reward function weight is optimized online (for example, the weight coefficient α of ΔSINR is increased) and the parameter combination is regenerated.

[0154] Perform multiple rounds of iterative optimization until the signal-to-interference-noise ratio is stable (ΔSINR / Δt < 1dB / ms).

[0155] Control strategy execution example:

[0156] Example 1 (tracking mode + pulse interference): FPGA reads the next pulse interval (such as 320μs) from the PRI random sequence table, and GPU predicts the next moment position based on the target historical position (coordinates x, y, z) to compensate for the tracking offset caused by agility.

[0157] Example 2 (search mode + continuous wave interference): The ASIC chipset jumps the frequency from 9.2 GHz to 9.3 GHz, and the beamformer generates a null beam in the azimuth direction of 45° to suppress the interference signal in this direction.

[0158] Example 3 (anti-interference enhancement mode + unknown interference): The AI ​​adversarial network identifies the non-periodic peak features in the time-frequency matrix, Q-learning generates joint agility parameters of PRI = 200μs and frequency = 10.1GHz, and stores the combination in the pattern library.

[0159] Specifically, the radar-based active anti-interference control method of the present invention further includes:

[0160] When the radar system is in a parameter agile transition state, the timestamp of the current waveform parameter is marked by a hardware synchronization clock; the timing of the receiving end signal processor is calibrated by a digital delay phase-locked loop, and the calibration includes: when it is detected that the PRI parameter deviation between the transmitting end and the receiving end exceeds 10ns, the microsecond timing compensation operation is triggered; when the waveform parameter switching completion degree reaches more than 95%, the compensation operation is turned off and the steady-state working stage is entered;

[0161] The waveform parameter switching completion degree is calculated by the following formula:

[0162] Completion degree = {number of parameters switched in real time / total number of parameters to be switched} × 100%.

[0163] Definition of parameter agility transition state:

[0164] Trigger condition: The instantaneous stage when the radar system performs waveform parameter agility operations (such as frequency, PRI, and modulation mode switching).

[0165] Technical challenges: The waveform parameter switching between the transmitter and receiver may lead to timing asynchrony due to hardware delays or differences in signal transmission paths, causing false targets or loss of real echoes.

[0166] Hardware sync clock markers:

[0167] Implementation:

[0168] Clock source: Oven controlled crystal oscillator (OCXO) is used as the hardware clock generator, with a frequency stability of ≤±0.1ppb, making the timestamp accuracy ≤5ns.

[0169] Marking mechanism: At the moment when the parameter agility instruction is issued (such as the rising edge / falling edge of the transmitter trigger signal), the timestamp of the current waveform parameter is recorded through the Precision Time Protocol (PTP) and embedded in the transmission signal frame header.

[0170] Digital Delay Locked Loop (DLL) Calibration:

[0171] Deviation Detection:

[0172] The signal processor at the receiving end parses the timestamp embedded by the transmitting end in real time and compares it with the local clock.

[0173] When the PRI parameter deviation between the transmitter and the receiver is detected to be greater than 10ns, it is determined to be a timing out of sync.

[0174] Microsecond compensation operation:

[0175] Compensation trigger: The timing of the signal processing pipeline at the receiving end is adjusted through the variable delay line (VDL) of the DLL, and the compensation amount is dynamically calculated based on the absolute value of the deviation.

[0176] Compensation termination condition: When the waveform parameter switching completion degree is ≥95%, the compensation operation is turned off and the system enters the steady-state working stage.

[0177] Determination of steady-state working stage:

[0178] Completion calculation logic:

[0179] Switched parameters: refers to the waveform parameters (such as frequency, PRI) that have been successfully loaded and effective at the transmitter.

[0180] Total number of parameters to be switched: dynamically determined according to the current anti-interference strategy (for example, switching 3 frequency points + 2 PRI values, the total number is 5).

[0181] Steady-state flag: Completion ≥ 95% indicates that parameter switching is nearly complete. Continuing compensation may introduce overshoot errors, so DLL compensation is turned off.

[0182] Additional technical details:

[0183] Hardware implementation:

[0184] OCXO clock module:

[0185] Model example: EPSON SG-8101, phase noise ≤ -150dBc / Hz @10kHz offset.

[0186] Timestamp embedding method: The timestamp is written into the reserved field of the signal frame header through the FPGA hardware description language (HDL).

[0187] Digital Delay Locked Loop (DLL) Circuit:

[0188] The ADISimPLL model from Analog Devices was used, configured as a third-order loop filter with bandwidth = 100kHz and phase margin = 60° to ensure compensation stability.

[0189] Compensation delay range: 0-10μs (step accuracy 1ns).

[0190] Calibration process:

[0191] Timestamp synchronization: The transmitter marks the timestamp at the moment of parameter agility, and the receiver parses and records the local timestamp.

[0192] Deviation calculation: Calculate the timestamp difference Δt between the transmitter and receiver in real time.

[0193] Compensation trigger: If Δt>10ns, DLL starts compensation and generates compensation amount according to Δt×damping coefficient (K_damp=0.8).

[0194] Completion monitoring: The parameter switching progress is counted every 1ms, and compensation is turned off when it reaches 95%.

[0195] Performance indicators:

[0196] Timing synchronization accuracy: PRI deviation between the transmitter and the receiver in steady state is <2ns.

[0197] Compensation response time: The delay from detecting deviation to completing compensation is ≤ 1μs.

[0198] System stability: Phase jitter introduced by compensation operation ≤ 0.1° RMS.

[0199] Timing calibration example:

[0200] Parameter agility trigger: When the radar switches from tracking mode to search mode, the frequency needs to be jumped from 9.2GHz to 9.3GHz, and the PRI needs to be adjusted from 200μs to 150μs.

[0201] Timestamp: At the moment the jump instruction is issued (t=0ms), the transmitter records the timestamp through OCXO and embeds it into the signal frame header.

[0202] Deviation detection and compensation:

[0203] The receiving end detects a timestamp deviation of Δt=15ns at t=0.1ms, triggering DLL compensation and adjusting the receiving end timing by Δt×0.8=12ns.

[0204] The completion degree is updated every 0.1ms, and compensation is turned off when both the frequency and PRI are switched successfully (completion degree = 100%).

[0205] Steady-state operation: The system enters the search mode steady-state, the timing deviation is <2ns, and the beam scanning is performed normally.

[0206] Specifically, the radar-based active anti-interference control method described in the present invention, the hierarchical decision-making architecture includes: a core decision-making layer, deployed in the FPGA for executing nanosecond-level parameter switching, calling the PRI-waveform mapping table in the preset anti-interference mode library; an auxiliary optimization layer, deployed in the CPU for performing the following operations: real-time monitoring of the signal-to-interference-noise ratio change rate ΔSINR / Δt after parameter switching; when the absolute value of ΔSINR / Δt exceeds the threshold value α, generating a mode library update instruction; and compensating for the target tracking error caused by parameter agility through an online reinforcement learning algorithm.

[0207] The core logic of the hierarchical decision-making architecture:

[0208] The purpose of architectural layering:

[0209] Core decision layer (FPGA): dedicated to performing high real-time, low-latency hardware-level operations (such as nanosecond-level parameter switching) to ensure instant response of anti-interference control.

[0210] Auxiliary optimization layer (CPU): responsible for dynamically monitoring system performance, optimizing anti-interference strategies, and making up for the lack of flexibility of pure hardware logic.

[0211] Collaboration mechanism: FPGA and CPU exchange data through high-speed buses (such as PCIe), realizing the division of labor mode of "fast hardware execution + dynamic software optimization".

[0212] Additional technical details:

[0213] Core decision layer (FPGA) implementation:

[0214] Nanosecond parameter switching:

[0215] Hardware logic design: The state machine is written in hardware description language (HDL) to directly control the RF front-end parameter registers, with a switching delay of ≤0.2ms.

[0216] PRI-waveform mapping table: pre-stored in the FPGA's on-chip BRAM (Block RAM), storing the optimal parameter combinations (such as PRI range and frequency hopping sequence) under different interference scenarios.

[0217] Table 1 below is an example of a PRI-waveform mapping table:

[0218] Table 1 is the PRI-waveform mapping table:

[0219]

[0220] Anti-interference mode library call:

[0221] According to the real-time interference characteristic parameters (such as β value) index mapping table, FPGA reads the parameters from the table and loads them to the transmitter.

[0222] Auxiliary optimization layer (CPU) functions:

[0223] Signal to Interference and Noise Ratio Change Rate Monitoring (ΔSINR / Δt):

[0224] Monitoring frequency: Sample the SINR value every 1 ms and calculate the change rate (unit: dB / ms).

[0225] Threshold trigger mechanism:

[0226] The preset threshold value α=3dB / ms, when |ΔSINR / Δt|>α, the current strategy is determined to be invalid and a pattern library update instruction is generated.

[0227] Online Reinforcement Learning Compensation:

[0228] Algorithm selection: Asynchronous advantage Actor-Critic (A3C) algorithm is used to optimize the target tracking filter parameters in real time.

[0229] Compensation logic:

[0230] Collect tracking error data (such as position deviation and speed deviation) caused by parameter agility.

[0231] The compensation coefficients are generated through the A3C model to dynamically adjust the process noise covariance matrix of the Kalman filter.

[0232] Output the compensated target trajectory to ensure the mean square error is ≤ 0.15°.

[0233] Pattern library update instruction generation:

[0234] The new interference characteristics are associated with the optimized parameter combination and written into the mapping table storage area of ​​the FPGA through the bus.

[0235] Hierarchical decision making example:

[0236] Scenario: The radar detects pulse interference (β=0.4) in tracking mode. The core decision layer calls the parameter combination of PRI=300μs and frequency=9.5GHz from the FPGA mapping table and switches.

[0237] Monitoring and Optimization:

[0238] The CPU detects that ΔSINR / Δt=-4.2dB / ms (exceeding α=3dB / ms) and determines that the current strategy is invalid.

[0239] The online reinforcement learning model generates compensation coefficients to adjust the process noise covariance of the Kalman filter from Q = 0.1 to Q = 0.05.

[0240] Pattern library update: Associate the interference feature of β=0.4 with the optimized parameter combination (PRI=280μs, frequency=9.6GHz) and update it to the FPGA mapping table.

[0241] Specifically, in the radar-based active anti-interference control method described in the present invention, the updating of the anti-interference pattern library includes: collecting the time-frequency domain joint feature matrix of the interference samples not recorded in the pattern library; calculating the cosine similarity β between the feature matrix and the existing pattern library; when β < 0.6, adding a new independent interference entry to the pattern library and associating the optimal anti-interference parameter combination dynamically generated based on the Q-learning algorithm, including the frequency agility step, PRI random sequence and beam nulling azimuth; when 0.6 ≤ β ≤ 0.8, optimizing the parameter weight coefficient of the existing entry;

[0242] It also includes a dynamic resource allocation mechanism: dynamic resource allocation is performed through a heterogeneous resource scheduler, and the heterogeneous resource scheduler includes: a first scheduling channel, configured to preferentially allocate FPGA resources for parameter agility operations when the interference intensity level is level I, and allocate GPU resources for target tracking filtering; a second scheduling channel, configured to activate the ASIC chipset to perform parallel operations when the interference intensity level is level II, including: generating a spatial filter matrix through a beamforming algorithm; performing interference cancellation operations using a hardware acceleration unit; and outputting a false target suppression rate indicator of a radar image in real time; wherein the heterogeneous resource scheduler dynamically switches the first scheduling channel or the second scheduling channel according to the interference intensity level;

[0243] Parameter switching delay ≤ 0.2ms, maximum timing synchronization error < 10ns;

[0244] Through FPGA hardware logic testing (Xilinx Kintex-7), the average delay from the generation of parameter switching instructions to the loading of them into the RF front end is 0.18ms (standard deviation ±0.02ms), meeting the requirement of ≤0.2ms; after calibration with a constant temperature crystal oscillator (OCXO) and a digital delay phase-locked loop, the measured maximum value of the PRI synchronization error between the transmitter and the receiver is 8.5ns (test conditions: interference intensity level II, temperature -40℃~85℃).

[0245] The probability of false target generation is reduced by 60% to 70%, and the mean square error of target tracking is ≤ 0.15°;

[0246] In a simulated interference scenario (mixed pulse interference + continuous wave interference), after using an ASIC chipset to perform beam nulling to align with the interference source, the probability of generating false targets dropped from the baseline value of 32% to 9.8% (a decrease of 69.4%). In real field tests, the false target suppression rate averaged 65.2% (standard deviation ±2.7%).

[0247] The policy generation response time in unknown interference mode is ≤ 3ms.

[0248] Anti-interference pattern library update mechanism:

[0249] Technical process:

[0250] Interference sample collection not recorded in the pattern library:

[0251] Data source: The radar echo signal is captured in real time, sampled by a high-speed ADC to generate a time domain signal, which is converted into a joint feature matrix in the time and frequency domains through short-time Fourier transform (STFT).

[0252] Matrix dimension: The feature matrix dimension is 128×128, including parameters such as time-frequency energy distribution and instantaneous frequency.

[0253] Cosine similarity calculation (β):

[0254] Dimensionality reduction: Principal component analysis (PCA) is used to compress the feature matrix to 32 dimensions to reduce computational complexity.

[0255] Similarity calculation: Compare the cosine similarity β (value range [-1,1]) between the compressed feature vector and the existing entries in the pattern library.

[0256] Pattern library update logic:

[0257] β<0.6: It is determined to be a new type of interference. A new independent entry is added and associated with the optimal parameter combination (such as frequency hopping sequence + null direction).

[0258] Parameter combination generation: Dynamically generate joint agility sequences of PRI, frequency, and modulation mode through reinforcement learning (such as Q-learning).

[0259] 0.6 ≤ β ≤ 0.8: It is determined to be a known interference variant, the weight coefficient of the existing entry is optimized (learning rate η=0.01), and the parameter priority is adjusted.

[0260] Additional technical details:

[0261] Feature extraction hardware: Xilinx RFSoC chip is used to achieve real-time time-frequency analysis (processing delay ≤ 0.1ms).

[0262] Pattern library storage: The anti-interference pattern library is stored in the FPGA off-chip DDR4 memory, supporting high-speed reading and writing (bandwidth ≥ 20GB / s).

[0263] Dynamic resource allocation mechanism:

[0264] The first dispatch channel (interference intensity level I):

[0265] Applicable scenarios: low interference intensity (signal-to-interference-plus-noise ratio SINR ≥ 10dB).

[0266] Resource allocation strategy:

[0267] FPGA resource allocation: ≥70% of the logic cells are used for parameter agility operations (such as PRI randomization and frequency hopping), ensuring that the switching delay is ≤0.2ms.

[0268] GPU resource allocation: 50% of the CUDA cores are used to run the Kalman filter algorithm to compensate for the target tracking error (mean square error ≤ 0.15°).

[0269] Performance advantage: Prioritizes core anti-interference tasks and reduces resource competition by 60%.

[0270] Second scheduling channel (interference intensity level II):

[0271] Applicable scenarios: high interference intensity (SINR<10dB).

[0272] ASIC Chipset Activation:

[0273] Beamforming algorithm: Generates spatial filter matrix based on Grassmann manifold optimization, with null depth ≥-30dB, to suppress signals in the direction of interference sources.

[0274] Interference cancellation operation: Cholesky decomposition hardware acceleration is performed through a customized ASIC, with a throughput of ≥1Gops and real-time output of false target suppression rate indicators (reduced by 60% to 70%).

[0275] Parallel Operations:

[0276] The beamforming calculation core and the interference cancellation unit run synchronously, and the resource utilization rate is ≥85%.

[0277] Dynamic switching logic:

[0278] Switching conditions:

[0279] Level I → Level II: When SINR continues to deteriorate (ΔSINR / Δt < -3dB / ms) and lasts for 10ms.

[0280] Level II → Level I: When SINR recovers to ≥10dB and remains stable for 20ms.

[0281] Switching response time: Mode switching delay ≤ 0.5ms to avoid task interruption.

[0282] Resource allocation implementation example:

[0283] Level I interference scenario:

[0284] The FPGA allocates 75% of resources to perform frequency agility (9.2GHz→9.3GHz), and the GPU allocates 50% of resources to run the extended Kalman filter with a tracking error of ≤0.12°.

[0285] Level II interference scenario:

[0286] ASIC activates the beamforming calculation core to generate a spatial filter matrix with a null angle of 45°, and the false target suppression rate is increased to 68%. The interference cancellation unit is accelerated by Cholesky decomposition hardware, and the calculation time is ≤50μs.

[0287] In the second aspect, the radar-based active anti-interference control system provided by the present invention is applied to the radar-based active anti-interference control method, including: a signal processing module, configured to receive a radar echo signal and extract interference characteristic parameters in the echo signal; a pattern recognition module, connected to the signal processing module, configured to determine the working mode of the current real-time radar system, the working mode including a tracking mode, a search mode and an anti-interference enhancement mode; a strategy decision module, configured to dynamically select an anti-interference control strategy through a hierarchical decision architecture based on the matching result of the working mode of the real-time radar system and the interference characteristic parameters, the hierarchical decision architecture including a core decision layer and an auxiliary optimization layer; an execution control module, configured to generate a parameter adjustment instruction according to the selected anti-interference control strategy, and control the radar transmitter to perform a waveform parameter agile operation; a synchronization calibration module, configured to perform timing calibration on the receiving end signal processor through a digital delay phase-locked loop to synchronize the waveform parameters of the transmitting end and the receiving end.

[0288] Furthermore, in the radar-based active anti-interference control system of the present invention, the strategy decision module includes: a first control unit, which is activated when the working mode is a tracking mode and the interference characteristic parameter is characterized as a pulse interference, including:

[0289] an FPGA accelerator configured to perform random agility of a pulse repetition interval PRI;

[0290] A GPU coprocessor configured to enable target trajectory prediction compensation;

[0291] The second control unit is activated when the working mode is the search mode and the interference characteristic parameter is characterized as continuous wave interference, and includes:

[0292] An ASIC chipset configured to perform frequency agility;

[0293] A beam former configured to initiate a beam null to align in the direction of an interference source;

[0294] The third control unit is activated when the working mode is the anti-interference enhancement mode and the interference characteristic parameter is characterized as an unknown interference pattern, and includes:

[0295] The AI ​​inference engine is configured to call the AI ​​adversarial network after knowledge distillation compression to perform interference feature recognition;

[0296] The reinforcement learning module is configured to build a reward mechanism based on the Q-learning algorithm, dynamically generate anti-interference parameter combinations through the signal-to-interference-noise ratio change rate and the target tracking error, and update them to the anti-interference pattern library in real time.

[0297] Furthermore, in the radar-based active anti-interference control system of the present invention, the synchronous calibration module includes:

[0298] A hardware clock generator, embedded in the radar transmitter, configured to timestamp the current waveform parameter in a parameter agile transition state;

[0299] A digital delay-locked loop circuit is connected to the receiving end signal processor and is configured as follows:

[0300] Detect the PRI parameter deviation between the transmitter and the receiver;

[0301] When the deviation exceeds 10ns, a microsecond timing compensation operation is triggered;

[0302] When the waveform parameter switching completion degree reaches more than 95%, the compensation operation is turned off and the steady-state working stage is entered; wherein the completion degree is calculated by the formula:

[0303] Completion degree = {number of parameters switched in real time / total number of parameters to be switched} × 100%.

[0304] Further, in the radar-based active anti-interference control system of the present invention, the hierarchical decision architecture includes: a core decision layer, deployed in the FPGA, including: a parameter agile controller, configured to perform nanosecond-level parameter switching;

[0305] Anti-interference mode memory, storing PRI-waveform mapping table;

[0306] The auxiliary optimization layer is deployed in the CPU and is configured as follows:

[0307] Real-time monitoring of the signal-to-interference-noise ratio change rate ΔSINR / Δt after parameter switching;

[0308] When the absolute value of ΔSINR / Δt exceeds the threshold value α, a pattern library update instruction is generated;

[0309] The target tracking error caused by parameter agility is compensated by an online reinforcement learning algorithm.

[0310] Furthermore, the radar-based active anti-interference control system of the present invention further includes: an anti-interference pattern library updating unit configured as follows:

[0311] Collect the time-frequency domain joint feature matrix of the interference samples not recorded in the pattern library;

[0312] Calculating the cosine similarity β between the matrix and the existing pattern library;

[0313] When β < 0.6, a new independent interference entry is added to the pattern library and associated with the optimal anti-interference parameter combination dynamically generated based on the Q-learning algorithm, including the frequency agility step size, PRI random sequence and beam nulling azimuth angle;

[0314] When 0.6≤β≤0.8, optimize the parameter weight coefficient of the existing entry; heterogeneous resource scheduler, including:

[0315] The first scheduling channel is configured to allocate more than 70% of the FPGA resources for parameter agility operations and 50% of the GPU resources for target tracking filtering when the interference intensity level is level I;

[0316] The second scheduling channel is configured to activate the ASIC chipset to perform parallel operations when the interference intensity level is level II, including:

[0317] Beamforming calculation kernel, generating spatial filter matrix;

[0318] Interference cancellation unit, which performs hardware-accelerated matrix inversion operations;

[0319] Suppression rate evaluator, which outputs false target suppression rate indicators in real time;

[0320] Wherein, the system satisfies:

[0321] Parameter switching delay ≤ 0.2ms, maximum timing synchronization error < 10ns;

[0322] The probability of false target generation is reduced by 60% to 70%, and the mean square error of target tracking is ≤ 0.15°;

[0323] Based on the extended Kalman filter algorithm (EKF), the high-speed fighter target (speed ≥ 2 Mach) is tracked, and the measured mean square error is 0.12° (test time 10 minutes, interference intensity level I); in the anti-interference enhanced mode, the maximum mean square error is ≤0.13°, meeting the requirement of ≤0.15°.

[0324] The policy generation response time in unknown interference mode is ≤ 3ms.

[0325] Embodiment 1:

[0326] like Figure 1 As shown, this embodiment specifically implements the active anti-interference control method based on radar, including the following steps:

[0327] Signal reception and feature extraction:

[0328] The radar receiver captures the echo signal through a superheterodyne receiving link, and inputs it into the signal processing module after sampling by a high-speed ADC (analog-to-digital converter).

[0329] The signal processing module uses a time-frequency joint analysis algorithm (such as short-time Fourier transform) to extract interference characteristic parameters, including interference type (pulse / continuous wave / unknown), interference intensity level (Level I / Level II), interference source azimuth, etc.

[0330] Working mode determination:

[0331] The mode recognition module dynamically switches the working mode according to the radar's current mission requirements and target tracking status:

[0332] Tracking mode: used for high-precision target tracking, giving priority to pulse repetition interval (PRI) stability;

[0333] Search mode: used for wide-range target scanning, supporting fast frequency agility;

[0334] Anti-interference enhanced mode: automatically activated when unknown interference is detected or strategy matching fails.

[0335] Dynamic selection of anti-interference strategy:

[0336] The first control strategy (tracking mode + pulse interference):

[0337] The FPGA loads the preset PRI random agility parameter table to generate a randomized pulse interval sequence (range: 100μs-500μs, random seed update period ≤1ms);

[0338] The GPU executes the Kalman filter algorithm in parallel to predict the target position based on historical trajectory data and compensate for the tracking error caused by PRI agility.

[0339] Second control strategy (search mode + continuous wave interference):

[0340] The ASIC chipset invokes the frequency agility instruction set to hop frequencies in the X-band in 10MHz steps (dwell time ≤ 0.1ms);

[0341] The beamformer generates a null beam with a depth of -30dB in the receive-side digital beamforming (DBF) according to the azimuth of the interference source.

[0342] The third control strategy (anti-interference enhancement mode + unknown interference):

[0343] The AI ​​inference engine loads a lightweight adversarial network (parameter quantity ≤ 1M) compressed by knowledge distillation, and identifies interference patterns through a joint feature matrix in the time and frequency domains;

[0344] The reinforcement learning module uses the Q-learning algorithm to construct the reward function:

[0345] Reward function formula (dynamic selection of anti-interference strategy);

[0346]

[0347] Symbol definition:

[0348] R: Reward value in reinforcement learning, used to evaluate the effectiveness of the anti-interference strategy

[0349] α: weight coefficient of signal to interference plus noise ratio change rate (ΔSINR), which is set to 0.7 in the embodiment.

[0350] ΔSINR: The real-time change rate of Signal-to-Interference-plus-Noise Ratio (in dB / ms). It reflects the degree of improvement of the anti-interference strategy on signal quality.

[0351] β: target tracking mean square error The weight coefficient of is 0.3 in the embodiment.

[0352] : Mean Squared Error of target tracking, in units of angle squared, used to quantify the effect of parameter agility on tracking accuracy.

[0353] Timing calibration and parameter synchronization:

[0354] Hardware clock marking: The transmitter uses PTP (Precision Time Protocol) to mark the timestamp at the moment of parameter agility change (rising edge / falling edge), with an accuracy of ≤5ns.

[0355] Digital Delay Locked Loop (DLL) Calibration:

[0356] The signal processor at the receiving end monitors the PRI parameters at the transmitting end in real time. When the deviation exceeds 10ns, the microsecond compensation of the DLL is triggered.

[0357]

[0358] Symbol definition:

[0359] Δt: The timing deviation that needs to be compensated, in microseconds (μs).

[0360] : The waveform parameter timestamp marked by the transmitter is generated by the hardware clock generator with an accuracy of ≤5ns.

[0361] : The waveform parameter timestamp detected by the receiving end is captured in real time by a digital delay-locked loop (DLL).

[0362] : Damping coefficient, which is 0.8 in the embodiment, is used to suppress overshoot oscillation and ensure compensation stability.

[0363] Waveform parameter switching completion calculation formula:

[0364]

[0365] When the completion rate is ≥95%, the compensation is turned off and the system enters a steady state.

[0366] Symbol definition:

[0367] : The number of waveform parameters that have been successfully switched, such as frequency, PRI, modulation mode, etc.

[0368] : The total number of waveform parameters that need to be switched is dynamically calculated by the core decision layer (FPGA) based on the anti-interference pattern library.

[0369] Dynamic resource allocation is performed through heterogeneous resource schedulers:

[0370] When the interference intensity level is level I (SINR ≥ 10dB):

[0371] Allocate more than 70% of FPGA resources for parameter agility operations (such as PRI random agility and frequency hopping);

[0372] Allocate 50% of the GPU resources to run the extended Kalman filter algorithm to compensate for the target tracking error (mean square error ≤ 0.15°).

[0373] When the interference intensity level is II (SINR<10dB):

[0374] Activate ASIC chipset to perform parallel operations:

[0375] The beamforming calculation kernel generates a spatial filter matrix with a null depth of ≥-30dB;

[0376] The interference cancellation unit performs Cholesky decomposition hardware acceleration with a throughput of ≥1 Gops.

[0377] Output false target suppression rate indicator in real time (reduced by 60% to 70%).

[0378] Pattern library update implementation:

[0379] Interference sample collection not recorded in the pattern library:

[0380] The time-frequency domain joint feature matrix (dimension 128×128) of the interference signal is collected and generated by short-time Fourier transform (STFT);

[0381] Cosine similarity β calculation:

[0382] PCA is used to reduce the dimension of the feature matrix to 32 dimensions, and the cosine similarity β between it and the existing entries in the pattern library is calculated;

[0383] Pattern library update logic:

[0384] If β<0.6:

[0385] Added independent entries in the pattern library, associated with the best anti-interference parameter combination (such as frequency hopping sequence + nulling direction);

[0386] Generate parameter weight coefficients through the Q-learning algorithm (learning rate η=0.01);

[0387] If 0.6≤β≤0.8:

[0388] Optimize the parameter weight coefficients of existing entries and adjust the priority.

[0389] Hierarchical decision making and resource scheduling:

[0390] Core decision layer (FPGA):

[0391] Call the PRI-waveform mapping table (stored in on-chip BRAM) to perform nanosecond parameter switching (delay ≤ 0.2ms);

[0392] Secondary optimization layer (CPU):

[0393] Real-time monitoring of the signal-to-interference-noise ratio change rate:

[0394] when When , the pattern library is updated;

[0395] The tracking error is compensated by online reinforcement learning (online Q value update frequency ≥ 1kHz) to ensure that the mean square error is ≤ 0.15°.

[0396] Based on the A3C algorithm (Asynchronous Advantage Actor-Critic), 100 sets of historical interference scenarios were trained. After compensation, the mean square error of target tracking was reduced from 0.25° to 0.11°, and the compensation efficiency was improved by 56%.

[0397] Pattern library dynamic updates:

[0398] The dimension of the joint feature matrix in the time-frequency domain of the interference samples not recorded in the pattern library is 128×128. After PCA dimension reduction, the cosine similarity β with the existing pattern library is calculated:

[0399] If β<0.6, add independent entries and associate parameter combinations (e.g., frequency hopping sequence + nulling orientation);

[0400] By collecting the time-frequency domain feature matrices of 100 groups of known interference samples (including pulse interference and continuous wave interference), the cosine similarity β is calculated after PCA dimensionality reduction. The statistical results show that the β mean of the same type of interference is ≥0.75, and the β mean of the different types of interference is ≤0.45 (confidence interval 95%), so β<0.6 is set as the threshold for adding new interference items.

[0401] If 0.6≤β≤0.8, adjust the weight coefficient of the existing entry (learning rate η=0.01).

[0402] Embodiment 2:

[0403] This embodiment specifically includes:

[0404] Signal processing module:

[0405] Adopt Xilinx Zynq UltraScale+ RFSoC chip, integrated with 4GSPS ADC, to realize interference feature parameter extraction (time-frequency analysis parallel computing channels ≥ 8 channels).

[0406] Policy decision module:

[0407] First control unit:

[0408] FPGA (Xilinx Kintex-7) is equipped with PRI agile controller, supporting 100ns-level parameter switching;

[0409] GPU (NVIDIA Jetson AGX Xavier) runs the trajectory prediction model (LSTM network, number of hidden layer nodes = 64).

[0410] Second control unit:

[0411] ASIC chipset (customized frequency agile engine) supports 8-channel parallel frequency hopping, with switching time ≤50μs;

[0412] The beamformer uses an adaptive algorithm based on Grassmann manifold, and the null generation delay is ≤200μs.

[0413] Synchronous calibration module:

[0414] The hardware clock generator uses OCXO (oven-controlled crystal oscillator, stability ±0.1ppb);

[0415] The digital delay-locked loop (ADISimPLL model) is configured as a third-order loop filter with bandwidth = 100kHz and phase margin = 60°.

[0416] Heterogeneous resource scheduler:

[0417] Level I Disturbance Dispatch:

[0418] FPGA resource allocation ≥ 70% (for parameter agility), GPU resource allocation 50% (for running the extended Kalman filter);

[0419] Level II Disruption Dispatch:

[0420] The ASIC chipset activates the beamforming computing core (matrix operation acceleration ratio ≥ 10 times), and the interference cancellation unit performs Cholesky decomposition hardware acceleration (throughput ≥ 1Gops);

[0421] System performance indicators:

[0422] The probability of false target generation decreased by 65% ​​(measured value: 63.2% to 68.5%).

[0423] The strategy generation response time is ≤2.8ms (measured average: 2.6ms).

[0424] Aiming at the problem of system resource competition caused by the extreme requirements of radar dynamic signal parameter adjustment on hardware computing power and algorithm efficiency, the present invention effectively solves the key problems such as agile mode mismatch (such as PRI synchronization failure), false target generation, true echo loss and tracking accuracy degradation through the following innovative technical means, thereby improving the control reliability and anti-interference performance of the radar system:

[0425] Dynamic anti-interference control strategy matching mechanism:

[0426] Background: When traditional radar systems dynamically adjust waveform parameters (such as frequency, PRI), mismatch between strategy and interference type leads to resource waste and response delay.

[0427] Solution:

[0428] Mode and interference matching logic: Dynamically select the optimal control strategy based on the radar operating mode (tracking / searching / anti-interference enhancement) and real-time interference characteristics (pulse interference, continuous wave interference, unknown interference).

[0429] Tracking mode + pulse interference: FPGA executes PRI random agility (100μs-500μs), and GPU compensates for target trajectory error in parallel to avoid tracking interruption.

[0430] Search Mode + CW Jammer: The ASIC chipset performs high-speed frequency agility (10MHz steps) and the beamformer generates a -30dB null-notch beam to suppress jammers.

[0431] Anti-interference enhanced mode + unknown interference: The AI ​​inference engine identifies interference features, reinforcement learning dynamically generates anti-interference parameter combinations, and updates the pattern library in real time.

[0432] Hierarchical decision-making architecture and hardware resource optimization:

[0433] Problem background: Hardware resource competition causes parameter switching delays, leading to agile mode mismatch (for example, PRI and frequency are not synchronized).

[0434] Solution:

[0435] Core decision layer (FPGA):

[0436] Deploy nanosecond-level parameter switching logic to directly control the RF front-end registers, with a switching delay of ≤0.2ms.

[0437] Call the pre-stored PRI-waveform mapping table to support simultaneous loading of multiple parameters (such as frequency + PRI + modulation mode).

[0438] Secondary optimization layer (CPU):

[0439] Monitor the signal-to-interference-to-noise ratio change rate (ΔSINR / Δt) in real time, and trigger the pattern library update when it exceeds the threshold (3dB / ms).

[0440] Through Monte Carlo simulation tests, when the absolute value of ΔSINR / Δt is greater than 3dB / ms, the probability that the target tracking error exceeds 0.2° increases to 85%, so α=3dB / ms is set as the strategy failure trigger threshold.

[0441] The target tracking filter parameters are dynamically adjusted through online reinforcement learning algorithms (such as A3C) to compensate for the trajectory error caused by agility.

[0442] High-precision timing synchronization and calibration mechanism:

[0443] Problem background: The timing asynchrony between the transmitter and the receiver causes the PRI parameter deviation to be greater than 10ns, which leads to false targets.

[0444] Solution:

[0445] Hardware clock marking: Uses a constant temperature crystal oscillator (OCXO) to generate a high-precision timestamp (error ≤ 5ns) and embeds it into the transmission signal frame header.

[0446] Digital Delay Locked Loop (DLL) Calibration:

[0447] Detect the PRI deviation between the transmitter and the receiver in real time and trigger microsecond compensation (compensation amount = deviation × damping coefficient 0.8).

[0448] When the waveform parameter switching completion degree is ≥95%, compensation is turned off and the system enters a steady state.

[0449] Technical effect: Maximum timing synchronization error <10ns, compensation response time ≤1μs, effectively eliminating false targets.

[0450] Anti-interference pattern library dynamic update and resource allocation:

[0451] Problem background: New interference causes the pattern library to fail, and static resource allocation intensifies resource competition.

[0452] Solution:

[0453] Pattern library update mechanism:

[0454] The time-frequency domain feature matrix (128×128) of the new interference is collected, and the cosine similarity β with the existing pattern library is calculated after PCA dimensionality reduction.

[0455] When β is less than 0.6, new independent entries are added and associated parameter combinations are associated; when 0.6≤β≤0.8, the weights of existing entries are optimized (learning rate 0.01).

[0456] Dynamic Resource Scheduler:

[0457] Level I interference: Allocate FPGA ≥ 70% resources to perform parameter agility and GPU ≥ 50% resources to run target tracking filtering.

[0458] Level II interference: Activate the ASIC chipset to perform beamforming and interference cancellation, with matrix operation acceleration ratio ≥ 10 times.

[0459] The key terms involved in the technical solution of the invention are explained as follows:

[0460] Dynamically select anti-interference control strategy:

[0461] Definition: A technical means of switching the optimal anti-interference measures in real time based on the matching results of the radar's real-time working mode (tracking mode, search mode, anti-interference enhancement mode) and interference characteristic parameters (such as interference type and intensity level). Specific implementation:

[0462] The first control strategy (tracking mode + pulse interference):

[0463] The FPGA performs random agility of the pulse repetition interval (PRI) from 100μs to 500μs, ensuring the unpredictability of the pulse interval;

[0464] The GPU runs the Kalman filter algorithm in parallel to compensate for the target tracking error caused by PRI agility (mean square error ≤ 0.15°).

[0465] Second control strategy (search mode + continuous wave interference):

[0466] ASIC chipset performs frequency agility (10MHz step, dwell time ≤ 0.1ms);

[0467] The beamformer generates a -30dB deep null beam to accurately suppress the direction of the interference source.

[0468] The third control strategy (anti-interference enhancement mode + unknown interference):

[0469] Call a lightweight AI adversarial network (parameter quantity ≤ 1M) to identify interference features;

[0470] Based on the Q-learning algorithm, anti-interference parameter combinations (such as joint agility sequences) are dynamically generated and updated to the pattern library in real time.

[0471] Digital Delay-Locked Loop (DLL):

[0472] Definition: A circuit that uses a hardware synchronized clock and a variable delay line (VDL) to achieve timing alignment between the transmitter and receiver. Technical function:

[0473] Timing deviation detection: real-time comparison of the transmitter timestamp and the receiver local clock, with an accuracy of ≤5ns;

[0474] Microsecond compensation: When the PRI parameter deviation is detected to be greater than 10ns, the compensation operation is triggered (compensation amount = deviation × damping coefficient 0.8);

[0475] Steady-state judgment: When the waveform parameter switching completion degree is ≥95%, the compensation is turned off and the steady-state working stage is entered.

[0476] Hierarchical decision-making architecture:

[0477] Definition: A collaborative processing architecture that divides the anti-interference control task into a hardware acceleration layer (FPGA) and a software optimization layer (CPU). Technical details:

[0478] Core decision layer (FPGA):

[0479] Perform nanosecond-level parameter switching (delay ≤ 0.2ms) and call the pre-stored PRI-waveform mapping table (storing the correspondence between interference scenarios and parameter combinations);

[0480] Directly control RF front-end registers to avoid software processing delays.

[0481] Secondary optimization layer (CPU):

[0482] Monitor the signal-to-interference-to-noise ratio change rate (ΔSINR / Δt) in real time, and trigger the pattern library update when |ΔSINR / Δt|>3dB / ms;

[0483] The target tracking filter parameters are dynamically adjusted through online reinforcement learning algorithms (such as A3C) to compensate for trajectory errors.

[0484] Anti-interference pattern library dynamic update:

[0485] Definition: A knowledge base for dynamically optimizing anti-interference parameter combinations based on new interference characteristics. Update logic:

[0486] Feature extraction: The time-frequency domain joint matrix (128×128) of the interference samples is collected and reduced to 32 dimensions by PCA;

[0487] Similarity calculation: Calculate the cosine similarity β with the existing entries (range [-1,1]);

[0488] Update rules:

[0489] β<0.6: add independent entries and associate parameter combinations (such as frequency hopping sequence + nulling direction);

[0490] 0.6≤β≤0.8: Optimize the weight coefficient of existing entries (learning rate η=0.01).

[0491] Heterogeneous resource scheduler:

[0492] Definition: A scheduling module that dynamically allocates hardware resources based on the interference intensity level. Scheduling strategy:

[0493] Level I interference (SINR ≥ 10dB):

[0494] FPGA allocates ≥70% of resources to execute parameter agility;

[0495] The GPU allocates 50% of resources to run the target tracking filter.

[0496] Level II interference (SINR<10dB):

[0497] Activate the ASIC chipset to perform parallel operations (beamforming + interference cancellation);

[0498] Achieve throughput ≥ 1 Gops through hardware acceleration units such as the Cholesky decomposition engine.

[0499] Waveform parameter agility operation:

[0500] Definition: Dynamically adjust the parameters of the radar transmission signal (such as frequency, PRI, modulation mode) to destroy the synchronization of the interference signal. Technical indicators:

[0501] Switching delay: ≤0.2ms (FPGA hardware acceleration);

[0502] Synchronization error: <10ns (guaranteed by DLL calibration);

[0503] False target suppression rate: decreased by 60% to 70% (measured value).

[0504] AI adversarial network after knowledge distillation compression:

[0505] Definition: An interference recognition model that compresses a large teacher network (10M parameters) into a lightweight student network (≤1M parameters) through knowledge distillation technology. Technical effect:

[0506] Inference speed: ≤1ms (meeting real-time requirements);

[0507] Recognition accuracy: ≥95% (consistent with the teacher network).

[0508] Signal to Interference and Noise Ratio Change Rate (ΔSINR / Δt):

[0509] Definition: The change in signal-to-interference-plus-noise ratio (SINR) per unit time, used to evaluate the real-time effectiveness of anti-interference strategies. Application scenarios:

[0510] When |ΔSINR / Δt|>3dB / ms, the current strategy is determined to be invalid, triggering a pattern library update or parameter optimization.

[0511] The technical solution of the present invention solves the problem that the extreme requirements of radar dynamic signal parameter adjustment on hardware computing power and algorithm efficiency trigger system resource competition, resulting in agile mode mismatch (such as PRI synchronization failure), which in turn causes false target generation, loss of true echo and reduced tracking accuracy, thereby weakening the control reliability of the radar system through the following measures:

[0512] According to the radar system's operating mode (tracking mode, search mode, anti-interference enhancement mode) and interference characteristic parameters, the most suitable anti-interference control strategy is dynamically selected. This dynamic adjustment of the strategy can more effectively utilize hardware resources and reduce unnecessary resource competition.

[0513] High-performance hardware acceleration units such as FPGA, GPU and ASIC are used to perform tasks such as parameter agility, target trajectory prediction and compensation, frequency agility, beamforming, etc., to achieve parallel processing at the hardware level.

[0514] Through the dynamic resource allocation mechanism, hardware resources are reasonably allocated according to the interference intensity level to ensure that key tasks (such as parameter agility and target tracking) can obtain sufficient computing resources and reduce the risk of resource competition and agility mode mismatch.

[0515] When the radar system is in a parameter agile transition state, the timestamp of the current waveform parameters is marked by the hardware synchronization clock to ensure the timing synchronization between the transmitter and the receiver.

[0516] A digital delay-locked loop (DLL) is used to perform timing calibration on the signal processor at the receiving end, monitor and compensate the PRI parameter deviation between the transmitting end and the receiving end in real time, and prevent the generation of false targets and loss of real echoes caused by PRI synchronization failure.

[0517] Construct a hierarchical decision-making architecture including a core decision-making layer and an auxiliary optimization layer. The core decision-making layer is responsible for executing nanosecond-level parameter switching and calling the preset anti-interference mode library. The auxiliary optimization layer is responsible for real-time monitoring of the signal-to-interference-noise ratio change rate after parameter switching, and generates mode library update instructions as needed and compensates for target tracking errors through online reinforcement learning algorithms. This hierarchical architecture can effectively reduce system complexity, improve decision-making efficiency, and reduce the decline in tracking accuracy caused by decision delays.

[0518] Collect the time-frequency domain joint feature matrix of interference samples not recorded in the pattern library, calculate its cosine similarity β with the existing pattern library, and dynamically update the anti-interference pattern library according to the value of similarity β. By adding new independent interference entries and optimizing the parameter weight coefficients of existing entries, the adaptability and accuracy of the pattern library to new interference can be improved, and the problem of poor anti-interference effect caused by pattern mismatch can be reduced.

[0519] In summary, the technical solution of the present invention effectively solves the problems caused by the extreme requirements of radar dynamic signal parameter adjustment on hardware computing power and algorithm efficiency through measures such as dynamic selection of anti-interference control strategy, hardware acceleration and resource optimization, timing synchronization and calibration, hierarchical decision-making architecture, and anti-interference pattern library update mechanism, improves the anti-interference capability and target detection accuracy of the radar system, and enhances the control reliability of the radar system.

Claims

1. The active anti-interference control method based on radar is characterized in that: The steps include: Receiving a radar echo signal and extracting interference characteristic parameters from the radar echo signal; Determining an operating mode of the real-time radar system, wherein the operating mode of the real-time radar system includes a tracking mode, a search mode, and an anti-interference enhancement mode; Based on the matching result between the working mode of the real-time radar system and the interference characteristic parameters, an anti-interference control strategy is dynamically selected through a hierarchical decision-making architecture, wherein the hierarchical decision-making architecture includes a core decision-making layer and an auxiliary optimization layer; Generate parameter adjustment instructions according to the selected anti-interference control strategy, control the radar transmitter to perform waveform parameter agility operation, and perform timing calibration on the receiving end signal processor through a digital delay phase-locked loop to synchronize the waveform parameters of the transmitter and the receiver; When the radar system is in a parameter agile transition state, the timestamp of the current waveform parameters is marked by the hardware synchronization clock; A digital delay phase-locked loop is used to perform timing calibration on a signal processor at the receiving end, wherein the calibration includes: triggering a microsecond timing compensation operation when a PRI parameter deviation between the transmitting end and the receiving end is detected to exceed 10ns; When the waveform parameter switching completion degree reaches more than 95%, the compensation operation is turned off and the steady-state working stage is entered; The waveform parameter switching completion degree is calculated by the following formula: Completion degree = {number of parameters switched in real time / total number of parameters to be switched} × 100%.

2. The radar-based active anti-interference control method according to claim 1, characterized in that: The dynamic selection anti-interference control strategy includes: When the working mode of the real-time radar system is the tracking mode and the interference type in the interference characteristic parameters is pulse interference, a first control strategy is selected, and the first control strategy includes: performing random agility of the pulse repetition interval PRI through the FPGA, and enabling the GPU to perform target trajectory prediction compensation; when the working mode of the real-time radar system is the search mode and the interference type in the interference characteristic parameters is identified as continuous wave interference, a second control strategy is selected, and the second control strategy includes: performing frequency agility through the ASIC chipset, and starting beam nulling to align the direction of the interference source; when the working mode of the real-time radar system is the anti-interference enhancement mode and the interference characteristic parameters are characterized as unknown interference patterns, a third control strategy is selected, and the third control strategy includes: The AI ​​adversarial network after knowledge distillation and compression is used to identify interference features, and a reward mechanism is built based on the Q-learning algorithm. The anti-interference parameter combination is dynamically generated through the signal-to-interference-noise ratio change rate and the target tracking error, and is updated to the anti-interference pattern library in real time; When the working mode does not match the interference characteristic parameters, perform the following operations: If the working mode of the real-time radar system is the tracking mode or the search mode, and the cosine similarity β between the interference characteristic parameter and the preset interference pattern in the pattern library is less than 0.6, the anti-interference enhancement mode is activated and the third control strategy is called; If the working mode of the real-time radar system is the anti-interference enhancement mode, the anti-interference parameter combination is dynamically generated based on the Q-learning algorithm.

3. The radar-based active anti-interference control method according to claim 1, characterized in that: The hierarchical decision architecture includes: a core decision layer, which is deployed in the FPGA to execute nanosecond-level parameter switching and call the PRI-waveform mapping table in the preset anti-interference mode library; an auxiliary optimization layer, which is deployed in the CPU to perform the following operations: real-time monitoring of the signal-to-interference-noise ratio change rate ΔSINR / Δt after parameter switching; when the absolute value of ΔSINR / Δt exceeds the threshold value α, generating a mode library update instruction; and compensating the target tracking error caused by parameter agility through an online reinforcement learning algorithm.

4. The radar-based active anti-interference control method according to claim 3, characterized in that: The updating of the anti-interference pattern library includes: collecting a time-frequency domain joint feature matrix of interference samples not recorded in the pattern library; calculating a cosine similarity β between the feature matrix and the existing pattern library; When β is less than 0.6, add independent interference entries to the pattern library and associate them with the optimal anti-interference parameter combination dynamically generated based on the Q-learning algorithm, including frequency agility step size, PRI random sequence and beam nulling azimuth angle; when 0.6≤β≤0.8, optimize the parameter weight coefficients of existing entries; It also includes a dynamic resource allocation mechanism: the dynamic resource allocation mechanism includes executing dynamic resource allocation through a heterogeneous resource scheduler, and the heterogeneous resource scheduler includes: a first scheduling channel, configured to preferentially allocate FPGA resources for parameter agility operations when the interference intensity level is level I, and allocate GPU resources for target tracking filtering; a second scheduling channel, configured to activate the ASIC chipset to perform parallel operations when the interference intensity level is level II, including: generating a spatial filter matrix through a beamforming algorithm; performing interference cancellation operations using a hardware acceleration unit; and outputting a false target suppression rate indicator of a radar image in real time; wherein the heterogeneous resource scheduler dynamically switches the first scheduling channel or the second scheduling channel according to the interference intensity level.

5. A radar-based active anti-interference control system, applied to the radar-based active anti-interference control method according to any one of claims 1 to 4, characterized in that: include: A signal processing module, configured to receive a radar echo signal and extract interference characteristic parameters from the echo signal; A mode recognition module, connected to the signal processing module, configured to determine a current working mode of the real-time radar system, wherein the working mode includes a tracking mode, a search mode, and an anti-interference enhancement mode; A strategy decision module is configured to dynamically select an anti-interference control strategy through a hierarchical decision architecture based on a matching result between the working mode of the real-time radar system and the interference characteristic parameters, wherein the hierarchical decision architecture includes a core decision layer and an auxiliary optimization layer; an execution control module is configured to generate a parameter adjustment instruction according to the selected anti-interference control strategy to control the radar transmitter to perform a waveform parameter agile operation; A synchronization calibration module, configured to perform timing calibration on a signal processor at the receiving end through a digital delay phase-locked loop to synchronize waveform parameters between the transmitting end and the receiving end; The synchronous calibration module comprises: A hardware clock generator, embedded in the radar transmitter, configured to timestamp the current waveform parameter in a parameter agile transition state; A digital delay-locked loop circuit is connected to the receiving end signal processor and is configured as follows: Detect the PRI parameter deviation between the transmitter and the receiver; When the deviation exceeds 10ns, a microsecond timing compensation operation is triggered; When the waveform parameter switching completion degree reaches more than 95%, the compensation operation is turned off and the steady-state working stage is entered; wherein the completion degree is calculated by the formula: Completion degree = {number of parameters switched in real time / total number of parameters to be switched} × 100%.

6. The radar-based active anti-interference control system according to claim 5, characterized in that: The strategy decision module includes: a first control unit, which is activated when the working mode is a tracking mode and the interference characteristic parameter is characterized as a pulse interference, including: an FPGA accelerator configured to perform random agility of a pulse repetition interval PRI; A GPU coprocessor configured to enable target trajectory prediction compensation; The second control unit is activated when the working mode is the search mode and the interference characteristic parameter is characterized as continuous wave interference, and includes: An ASIC chipset configured to perform frequency agility; A beam former configured to initiate a beam null to align in the direction of an interference source; The third control unit activates the anti-interference enhancement mode and calls the third control strategy if the working mode of the real-time radar system is the tracking mode or the search mode, and the cosine similarity β between the interference characteristic parameter and the preset interference pattern in the pattern library is less than 0.6, including: The AI ​​inference engine is configured to call the AI ​​adversarial network after knowledge distillation compression to perform interference feature recognition; The reinforcement learning module is configured to build a reward mechanism based on the Q-learning algorithm, dynamically generate anti-interference parameter combinations through the signal-to-interference-noise ratio change rate and the target tracking error, and update them to the anti-interference pattern library in real time.

7. The radar-based active anti-interference control system according to claim 5, characterized in that: The hierarchical decision architecture includes: a core decision layer, deployed in an FPGA, including: a parameter agile controller, configured to perform nanosecond-level parameter switching; Anti-interference mode memory, storing PRI-waveform mapping table; The auxiliary optimization layer is deployed in the CPU and is configured as follows: Real-time monitoring of the signal-to-interference-noise ratio change rate ΔSINR / Δt after parameter switching; When the absolute value of ΔSINR / Δt exceeds the threshold value α, a pattern library update instruction is generated; The target tracking error caused by parameter agility is compensated by an online reinforcement learning algorithm.

8. The radar-based active anti-interference control system according to claim 7, characterized in that: Also includes: Anti-interference pattern library update unit, configured as: Collect the time-frequency domain joint feature matrix of the interference samples not recorded in the pattern library; Calculating the cosine similarity β between the matrix and the existing pattern library; When β < 0.6, a new independent interference entry is added to the pattern library and associated with the optimal anti-interference parameter combination dynamically generated based on the Q-learning algorithm, including the frequency agility step size, PRI random sequence and beam nulling azimuth angle; When 0.6≤β≤0.8, optimize the parameter weight coefficient of the existing entries; Heterogeneous resource scheduler, including: The first scheduling channel is configured to preferentially allocate FPGA resources for parameter agility operations and allocate GPU resources for target tracking filtering when the interference intensity level is level I; the second scheduling channel is configured to activate the ASIC chipset to perform parallel operations when the interference intensity level is level II, including: generating a spatial filter matrix through a beamforming algorithm; performing interference cancellation operations using a hardware acceleration unit; and outputting a false target suppression rate indicator of a radar image in real time; wherein the heterogeneous resource scheduler dynamically switches between the first scheduling channel or the second scheduling channel according to the interference intensity level.

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