Time synchronization device and method based on Beidou satellite timing signal security isolation

Abstract

The present application discloses a time synchronization device and method based on the security isolation of Beidou satellite timing signals. The device includes: a Beidou signal receiving module, a dual-core processor, a high-precision clock module, and a time slicing coordination module; wherein the dual-core processor includes a security isolation core and a time synchronization core; an isolation bridge is provided between the security isolation core and the time synchronization core; the Beidou signal receiving module is connected to the security isolation core via a dedicated data interface; the high-precision clock module is connected to the time synchronization core via a dedicated clock bus. The physical isolation design of the heterogeneous dual-core processor in the embodiment of the present application realizes the strict separation of timing signal processing and time synchronization functions at the hardware level, effectively blocks potential attack paths, thereby ensuring the security, integrity, and anti-interference capability of timing information at the system architecture level, and can be widely used in the field of computer technology.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a time synchronization device and method based on the secure isolation of Beidou satellite timing signals. Background Art

[0002] As modern society's demand for time synchronization accuracy continues to increase, high-precision time synchronization technology is playing an increasingly important role in critical infrastructure such as power systems, communication networks, and financial transactions. The Beidou Satellite Navigation System, my country's independently developed global satellite navigation system, has become a crucial means of achieving time synchronization in these sectors thanks to its high precision and reliability. In power systems, Beidou timing technology is widely used in smart grid equipment such as phasor measurement units (PMUs) and substation automation systems, providing a precise time reference for stable grid operation and fault location. Furthermore, in communication networks, Beidou timing also provides critical time synchronization support for 5G base stations, data centers, and other facilities.

[0003] However, existing time synchronization devices still face some urgent challenges. Traditional single-core processor architectures struggle to effectively isolate timing signal processing from other system functions, posing a security risk. Single-core architectures often struggle to meet high concurrency and low latency requirements when processing complex timing signals and executing time synchronization algorithms. Most existing systems lack effective task scheduling and resource management mechanisms, making it difficult to fully utilize processor resources. This leads to a significant decrease in system performance under high loads, impacting the accuracy and stability of time synchronization. While the BeiDou system itself boasts high precision, existing time synchronization devices still have room for improvement in signal processing and clock calibration. Under long-term operation and in harsh environments, the performance of existing devices is prone to deterioration, making it difficult to ensure continuous and stable timing services. Summary of the Invention

[0004] In order to solve at least one of the above problems, the main purpose of the embodiments of the present application is to propose a time synchronization device and method based on the secure isolation of Beidou satellite timing signals, which can improve the security, integrity and anti-interference capabilities of various systems.

[0005] To achieve the above objectives, one aspect of an embodiment of the present application provides a time synchronization device based on secure isolation of Beidou satellite timing signals, the device comprising:

[0006] Beidou signal receiving module, dual-core processor, high-precision clock module and time slicing coordination module;

[0007] The dual-core processor includes a security isolation core and a time synchronization core; an isolation bridge is provided between the security isolation core and the time synchronization core;

[0008] The Beidou signal receiving module is connected to the security isolation core through a dedicated data interface;

[0009] The high-precision clock module is connected to the time synchronization core via a dedicated clock bus.

[0010] In some embodiments, the BeiDou signal receiving module includes:

[0011] Beidou satellite signal receiving antenna, low-noise amplifier, bandpass filter, multi-band receiver and high-speed analog-to-digital converter;

[0012] Wherein, the Beidou satellite signal receiving antenna is connected to the low noise amplifier via a coaxial cable;

[0013] An impedance network is provided between the Beidou satellite signal receiving antenna and the low noise amplifier;

[0014] The low noise amplifier is cascade-connected to the bandpass filter via a microstrip line;

[0015] The multi-band receiver is connected to a high-speed analog-to-digital converter via a high-speed digital interface;

[0016] The high-speed analog-to-digital converter is connected to the safety isolation core via a dedicated data interface.

[0017] In some embodiments, the secure isolation core includes:

[0018] CRC check unit, state machine check unit, digital signal processing unit, cache and multiplexer;

[0019] Wherein, the CRC check unit and the state machine check unit are connected in parallel to the digital signal processing unit;

[0020] The cache is connected to the digital signal processing unit via a multi-port interface;

[0021] The multiplexer adopts a cross switch structure;

[0022] The digital signal processing unit is connected to the Beidou signal receiving module through the dedicated data interface;

[0023] The degree-even multiplexer is connected to the isolation bridge;

[0024] The digital signal processing unit is connected to the time slicing coordination module via a control bus.

[0025] In some embodiments, the time synchronization core includes:

[0026] Local clock receiving unit, time deviation calculation unit, digital controlled oscillator, digital phase locked loop circuit and time output interface;

[0027] Wherein, the local clock receiving unit is connected to the high-precision clock module;

[0028] The time deviation calculation unit is connected to the safety isolation core;

[0029] The time deviation calculation unit is connected to the digitally controlled oscillator via a high-speed data channel;

[0030] The output end of the digital controlled oscillator is connected to the input end of the digital phase locked loop;

[0031] The time output interface is connected to the digital phase locked loop circuit and is connected to an external device through an output buffer.

[0032] In some embodiments, the high-precision clock module includes:

[0033] Dual oven-controlled crystal oscillators, backup atomic clock interface, clock switching control circuit, clock output unit;

[0034] Wherein, the dual oven controlled crystal oscillator is isolated from the main circuit board via a low noise power supply and a temperature control loop;

[0035] The clock switching control circuit communicates with the dual-core processor via a high-speed serial interface;

[0036] The clock output unit is connected to the dual oven controlled crystal oscillator and the backup atomic clock interface;

[0037] The clock output unit is connected to the local clock receiving unit of the time synchronization core through a dedicated low-jitter clock channel;

[0038] The clock switching control circuit is connected to the time synchronization core.

[0039] In some embodiments, the time slicing coordination module includes:

[0040] Hardware counters, status registers, task signature lookup tables, hardware priority queues, time-triggered schedulers, programmable timer arrays, DMA controllers, and dual-port RAM;

[0041] wherein the hardware counter and the status register are connected to the time-triggered scheduler via a low-latency bus;

[0042] The task feature lookup table and the hardware priority queue are implemented using on-chip memory;

[0043] The time-triggered scheduler and the programmable timer array work in coordination via an internal high-speed interconnect bus;

[0044] The dual-port RAM is connected to the security isolation core and the time synchronization core via a high-speed data channel;

[0045] The DMA controller is connected to the dual-core processor via a PCIe interface; the DMA controller is also connected to the hardware priority queue via a control signal line;

[0046] The time-triggered scheduler is connected to the time synchronization core via a control bus.

[0047] In some embodiments, the digital phase locked loop comprises:

[0048] High-speed digital phase detector, adjustable digital loop filter, digitally controlled oscillator, and programmable frequency divider;

[0049] wherein the high-speed digital phase detector is connected to the adjustable digital loop filter via a high-speed data channel;

[0050] The digitally controlled oscillator is connected to the programmable frequency divider via a low-jitter clock distribution network.

[0051] In some embodiments, the apparatus further comprises:

[0052] Non-volatile memory, power management unit and multi-interface input and output module;

[0053] The non-volatile memory adopts a dual-backup structure and is connected to the dual-core processor via an independent storage controller;

[0054] The power management unit is connected to each module that needs power supply through a star topology;

[0055] The multi-interface input and output module is connected to the dual-core processor via a high-speed serial interface.

[0056] To achieve the above-mentioned purpose, the embodiment of the present application further provides a time synchronization method based on the above-mentioned time synchronization device based on Beidou satellite timing signal security isolation, the method comprising the following steps:

[0057] Receive an initial timing signal transmitted by a Beidou satellite through a Beidou signal receiving module, digitize the initial timing signal, obtain first timing signal data, and send the first timing signal data to the security isolation core of the dual-core processor;

[0058] receiving the first timing signal data through the security isolation core, performing a security check on the first timing signal data, and sending the checked first timing signal data to the time synchronization core of the dual-core processor;

[0059] Sending local clock information to the time synchronization core through a high-precision clock module;

[0060] Performing time synchronization processing according to the received first timing signal and the local clock information through the time synchronization core;

[0061] The scheduling of the high-precision clock module and the dual-core processor is coordinated by a time slicing coordination module.

[0062] In some embodiments, the method further comprises the following steps:

[0063] Storing the configuration information and log data of the dual-core processor in a non-volatile memory;

[0064] The power management unit is used to supply power to each power-consuming module in the time synchronization device based on the safe isolation of Beidou satellite timing signals;

[0065] The communication between the modules in the time synchronization device based on the safe isolation of Beidou satellite timing signals is realized through a multi-interface input and output module.

[0066] The embodiments of the present application include at least the following beneficial effects: The present application provides a time synchronization device and method based on the secure isolation of Beidou satellite timing signals, which includes a Beidou signal receiving module, a dual-core processor, a high-precision clock module, and a time slicing coordination module; wherein, the dual-core processor includes a secure isolation core and a time synchronization core; an isolation bridge is provided between the secure isolation core and the time synchronization core; the Beidou signal receiving module is connected to the secure isolation core via a dedicated data interface; the high-precision clock module is connected to the time synchronization core via a dedicated clock bus. The device achieves strict separation of timing signal processing and time synchronization functions at the hardware level through the physical isolation design of the heterogeneous dual-core processor, effectively blocking potential attack paths, thereby ensuring the security, integrity, and anti-interference capability of timing information at the system architecture level. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0068] Figure 1 This is a schematic diagram of the overall architecture of a time synchronization device based on safe isolation of Beidou satellite timing signals provided in an embodiment of the present application;

[0069] Figure 2 This is a schematic diagram of the internal structure of the dual-core processor provided in an embodiment of the present application;

[0070] Figure 3 This is a schematic diagram of the time slicing coordination module structure provided in an embodiment of the present application;

[0071] Figure 4 This is a schematic diagram of the steps of the time synchronization method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0072] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are merely examples of devices and methods consistent with some aspects of the embodiments of the present application as detailed in the appended claims.

[0073] Although the system diagrams illustrate functional modules and the flowcharts illustrate a logical sequence, in some cases, the steps shown or described may be performed in a different order than the module divisions in the system or the order in the flowcharts. The terms "first / S100," "second / S200," and the like in the specification, claims, and drawings are used to distinguish similar items and are not necessarily used to describe a specific order or sequence.

[0074] It will be understood that the terms "first", "second", etc. used in this application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0075] The terms "at least one", "plurality", "each", "any", etc. used in this application include "at least one", "two" or more, "plurality" or "each", "any" or "any one", "each" or "any one" as used herein.

[0076] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0078] In related technologies, time synchronization devices still face some urgent problems. Traditional single-core processor architectures make it difficult to effectively isolate timing signal processing from other system functions, posing a security risk. When processing complex timing signals and executing time synchronization algorithms, single-core architectures often struggle to meet high concurrency and low latency requirements. Most existing systems lack effective task scheduling and resource management mechanisms, making it difficult to fully utilize processor resources. This results in a significant decrease in system performance under high load conditions, affecting the accuracy and stability of time synchronization. Although the Beidou system itself has high precision characteristics, existing time synchronization devices still have room for improvement in signal processing and clock calibration. Under long-term operation and in harsh environments, the performance of existing devices is prone to deterioration, making it difficult to ensure continuous and stable timing services.

[0079] In view of this, the embodiments of the present application provide a time synchronization device and method based on the security isolation of Beidou satellite timing signals. This solution achieves strict separation of timing signal processing and time synchronization functions at the hardware level through the physical isolation design of heterogeneous dual-core processors, effectively blocking potential attack paths, thereby ensuring the security, integrity and anti-interference capability of timing information at the system architecture level.

[0080] The present application can be used in many general or special computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, and the like. The present application can be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, and the like that perform specific tasks or implement specific abstract data types. The present application can also be practiced in distributed computing environments in which tasks are performed by remote processing devices connected via a communication network. In a distributed computing environment, program modules can be located in local and remote computer storage media, including storage devices.

[0081] Figure 1 This is a schematic diagram of the overall architecture of the device provided in an embodiment of the present application. The time synchronization device based on the safe isolation of Beidou satellite timing signals includes: a Beidou signal receiving module, a dual-core processor, a high-precision clock module and a time slicing coordination module; each module is integrated on the same mainboard and interconnected through a high-speed data bus; the high-speed data bus adopts a multi-layer PCB design, including but not limited to a signal transmission layer, a power supply layer and a ground plane layer; the Beidou signal receiving module is connected to the safe isolation core in the dual-core processor through a dedicated data interface; the dedicated data interface is a high-speed serial interface, which adopts differential signal transmission technology; a dedicated isolation bridge is provided between the safe isolation core and the time synchronization core, and the isolation bridge adopts optoelectronic isolation technology to achieve physical isolation while ensuring high-speed data transmission; the high-precision clock module is connected to the time synchronization core through a dedicated clock bus, and the dedicated clock bus adopts a star topology; the time slicing coordination module is connected to the dual-core processor through a control bus; the control bus adopts a multi-master and multi-slave architecture to support concurrent communication between modules.

[0082] Furthermore, the various modules in the device of the embodiment of the present application are introduced in detail below. It should be noted that the example mentioned is only one of the implementation methods, and the specific elements and data therein are only used as an example, and the present application does not limit this.

[0083] (1) Beidou signal receiving module.

[0084] The Beidou signal receiving module includes: a Beidou satellite signal receiving antenna, a low-noise amplifier, a bandpass filter, a multi-band receiver, and a high-speed analog-to-digital converter; the receiving antenna is connected to the low-noise amplifier via a coaxial cable, and an impedance matching network is provided between the antenna and the low-noise amplifier; the low-noise amplifier and the bandpass filter are cascaded and implemented via a microstrip line; the multi-band receiver adopts direct RF sampling technology and is connected to the high-speed analog-to-digital converter via a high-speed digital interface; the high-speed analog-to-digital converter is connected to the safety isolation core in the dual-core processor via a dedicated data interface, and is used to transmit digitized Beidou signal data directly to the safety isolation core.

[0085] In some embodiments, for example, the receiving antenna can utilize a circularly polarized microstrip antenna design, operating in the B1I, B1C, and B3I bands, with an antenna gain ≥ 3dBi and an axial ratio < 3dB. The receiving antenna is connected to a low-noise amplifier (LNA) via a 50Ω coaxial cable. A π-type impedance matching network is provided between the two to maximize signal transmission efficiency and minimize the noise figure. The LNA has a noise figure of 0.6dB and a gain of 20dB. The bandpass filter can utilize a design combining SAW (Surface Acoustic Wave) technology and a hairpin resonator structure to achieve signal filtering and interference mitigation. Its center frequencies correspond to the B1I, B1C, and B3I bands, respectively, with 3dB bandwidths of 4MHz and 20MHz, insertion loss <2dB, and out-of-band rejection >40dB. The multi-band receiver utilizes direct RF sampling technology and a high-speed analog-to-digital converter with a sampling rate of 500MSPS and an effective number of bits of 14 bits. It is connected to the digital signal processing unit (FPGA) in the dual-core processor through a high-speed digital interface to achieve digital down-conversion and filtering, and convert the sampled data into baseband I / Q signals.

[0086] (2) Dual-core processor.

[0087] Reference Figure 2 The dual-core processor utilizes a heterogeneous architecture, comprising a safety isolation core and a time synchronization core. A dedicated isolation bridge is installed between the safety isolation core and the time synchronization core. This processor processes digital signals received from the Beidou signal receiving module and implements safety isolation and high-precision time synchronization. The isolation bridge utilizes optoelectronic isolation technology, converting electrical signals into optical signals via optocouplers before transmission and then converting them back into electrical signals, achieving electrical isolation between the safety isolation core and the time synchronization core.

[0088] The security isolation core includes: a CRC check unit, a state machine check unit, a digital signal processing unit, a cache, and a multiplexer; wherein the CRC check unit and the state machine check unit are connected in parallel to the digital signal processing unit, using a high-speed parallel bus; the cache is connected to the digital signal processing unit through a multi-port interface, supporting concurrent reading and writing; the multiplexer adopts a cross switch structure; the digital signal processing unit is connected to the Beidou signal receiving module through the dedicated data interface, for receiving digitized Beidou signal data; the multiplexer is also connected to the isolation bridge, for transmitting data that has passed security inspection to the time synchronization core; the digital signal processing unit is connected to the time slicing coordination module through the control bus, for receiving task scheduling instructions.

[0089] The time synchronization core includes a local clock receiving unit, a time deviation calculation unit, a high-precision digitally controlled oscillator (DCO), a digital phase-locked loop (DPLL) circuit, and a time output interface. The local clock receiving unit utilizes a high-speed differential receiver design, including a clock buffer, a frequency divider, and a phase alignment circuit, for receiving and processing clock signals from a high-precision clock module. The local clock receiving unit is connected to the high-precision clock module to receive a local clock reference signal. The time deviation calculation unit is connected to the security isolation core to receive security-checked Beidou satellite timing signals. The time deviation calculation unit is connected to the DCO via a high-speed data channel. The DPLL circuit is fully digital, with internal units interconnected via a synchronized clock domain. The time output interface supports multiple standard protocols and connects to external devices via a configurable output buffer. The time synchronization core connects to external devices via the time output interface, which supports multiple standard protocols, including IEEE 1588 PTP, IRIG-B, and 1PPS.

[0090] In some embodiments, for example, within the secure isolation core, the CRC check unit can use the CRC-32 IEEE 802.3 polynomial, supporting single-cycle 32-bit data CRC calculations. The state machine check unit utilizes a 7-state Moore-type finite state machine with a clock frequency of 500 MHz. These two units are connected in parallel to the digital signal processing unit using a 128-bit wide, 500 MHz high-speed parallel bus. The digital signal processing unit is implemented based on a high-performance FPGA, supporting complex real-time signal processing algorithms. The cache utilizes a four-channel interleaved structure with a total capacity of 1MB and is connected to the digital signal processing unit via four 32-bit wide, 1 GHz multi-port interfaces. The multiplexer utilizes a 64×64 full crossbar switch structure with an insertion loss of <0.5 dB and an isolation of >80 dB. In the specific implementation of the secure isolation core, the digital signal processing unit first receives digital timing signal data from the Beidou signal receiving module via a dedicated data interface. The digital signal processing unit then transmits the data to the CRC check unit and the state machine check unit via a high-speed parallel bus. The CRC check unit performs CRC-32 IEEE802.3 check calculations, while the state machine check unit uses a 7-state Moore-type finite state machine running at a 500MHz clock frequency to perform data status checks. The checked data is uniformly processed by the digital signal processing unit and stored in a high-speed cache. The cache uses a multi-port interface to enable concurrent read and write operations. The data is then transmitted to the time synchronization core via an isolation bridge through a crossbar-based multiplexer. During this process, the digital signal processing unit maintains a connection to the time-slicing coordination module via a control bus, receiving and responding to task scheduling instructions.

[0091] In some embodiments, for example, within the time synchronization core, various units work together to achieve high-precision time synchronization. The time deviation calculation unit uses fixed-point arithmetic and supports 64-bit precision. Its basic processing flow is as follows: first, it compares the security-checked timing signal data with the local clock information to calculate the deviation between the local time and the Beidou satellite time. It then generates a control signal based on this deviation and transmits it in real time to the DCO and DPLL circuits via a high-speed data channel. The digitally controlled oscillator (DCO) is based on a fractional-N phase-locked loop (PLL) structure, with a frequency resolution of 0.01Hz and a phase noise better than -130dBc / Hz at 1kHz offset. The DCO receives control signals from the PLL unit and dynamically adjusts its output frequency to compensate for the detected time deviation. The DCO output serves as the reference clock for the DPLL, while the DPLL feedback signal is used to further fine-tune the DCO output, ultimately achieving stable clock synchronization.

[0092] Furthermore, the DPLL circuit is fully digitally implemented, comprising a high-speed digital phase detector, an adjustable digital loop filter, a digitally controlled oscillator, and a programmable frequency divider. The high-speed digital phase detector utilizes a parallel processing architecture with a resolution of 1 ps and is connected to the adjustable digital loop filter via a high-speed data channel. The adjustable digital loop filter can adaptively adjust the loop bandwidth within a range of 1 Hz to 1 kHz, dynamically optimizing system performance based on current time synchronization requirements. The digitally controlled oscillator in the DPLL utilizes multi-bit quantization technology and is connected to the programmable frequency divider via a low-jitter clock distribution network. The programmable frequency divider dynamically adjusts the division ratio based on system requirements, enabling the DPLL to adapt to varying input frequencies and output requirements. The entire DPLL circuit utilizes a synchronous design approach, with each unit synchronized via a clock tree network, ensuring circuit stability and reliability. The DPLL is able to quickly lock onto and track input signals while maintaining extremely low phase noise and jitter.

[0093] Furthermore, the time output interface directly connects to the DPLL circuit and supports multiple standard protocols such as IEEE 1588 PTP, IRIG-B, and 1PPS. A configurable output buffer provides level conversion and impedance matching to ensure output signal integrity. Output jitter is controlled within 100ps peak-to-peak, and rise time is <1ns (10%-90%), providing highly accurate time synchronization signals for external devices.

[0094] (3) High-precision clock module.

[0095] The high-precision clock module includes: a dual oven-controlled crystal oscillator (DOCXO), a backup atomic clock interface, a clock switching control circuit, and a clock output unit; the DOCXO is isolated from the main circuit board by a low-noise power supply and temperature control loop; the backup atomic clock interface uses differential signal transmission and supports hot plugging; the clock switching control circuit is implemented using FPGA and communicates with the dual-core processor through a high-speed serial interface; the clock output unit is connected to the DOCXO and the backup atomic clock interface to output the selected clock signal; the clock output unit is connected to the local clock receiving unit of the time synchronization core through a dedicated low-jitter clock channel to provide a local clock reference for the time synchronization core; the clock switching control circuit is also connected to the time synchronization core to receive clock source switching instructions and feedback the switching status.

[0096] The clock switching control circuit is configured to achieve seamless switching of the backup atomic clock, wherein the switching process achieves phase continuity through a phase accumulator and a digital filter, and the switching control signal is transmitted through an optical coupler to ensure electrical isolation between the main clock source and the backup clock source.

[0097] In some embodiments, the high-precision clock module exemplarily includes a dual oven-controlled crystal oscillator (DOCXO), a backup atomic clock interface, and a clock switching control circuit. The module is connected to the dual-core processor via a dedicated clock bus, using a star topology to minimize clock skew.

[0098] The DOCXO uses Wenzel Associates' Ultra-Performance SC series, offering performance indicators such as frequency stability better than 5×10^-13 / day and phase noise better than -130dBc / Hz at 1Hz offset. To ensure the DOCXO's stable operation, the following measures were taken: a Linear Technology LT3045 linear regulator provides a low-noise power supply with a noise density of <0.8nV / √Hz at 10kHz, effectively suppressing the impact of power supply noise on DOCXO performance. A proportional-integral-derivative (PID) algorithm is used in the temperature control loop, achieving a temperature control accuracy of ±0.01°C, ensuring the DOCXO's stability across various ambient temperatures. An elastic support structure is used between the DOCXO and the main circuit board to further reduce the impact of external mechanical vibration on the DOCXO and improve overall stability.

[0099] The design of the backup atomic clock interface takes the following aspects into consideration: LVDS differential signal transmission technology is used to support 10MHz reference frequency input, ensuring signal integrity and anti-interference capabilities; the interface circuit design is compatible with 3.3V / 2.5V / 1.8V logic levels, enhancing system flexibility and compatibility; an integrated 8kV human body model standard ESD protection circuit improves the reliability and durability of the interface; and integrated hot-swap control logic with a response time of <100μs facilitates system maintenance and upgrades.

[0100] The clock switching control circuit is implemented based on a Xilinx Artix-7 XC7A50T FPGA and has the following features: It communicates with the dual-core processor via a high-speed serial interface (above 3.125Gbps) with a latency of <1μs, ensuring fast response and precise control. It uses a phase accumulator and a digital filter to achieve phase continuity. The phase accumulator has a resolution of 1ps, and the digital filter uses a 256-order FIR structure to ensure a phase continuity error of <1ns. The switching control signal is transmitted via a Broadcom ACPL-M61L optocoupler, providing a 5kV isolation voltage and a transmission delay of <20ns, effectively ensuring electrical isolation between the primary and backup clock sources.

[0101] The dedicated clock bus for the high-precision clock module utilizes a star topology, specifically implemented as follows: It uses differential LVPECL (Low Voltage Positive Emitter Random Logic) signaling, improving signal immunity and transmission quality. The master clock source is located at the center of the star structure, connected to the two cores of the dual-core processor and other modules requiring high-precision clocks via equal-length differential pairs. The length of each clock line is strictly controlled, with a maximum length difference of no more than 0.5mm, ensuring synchronized clock signal arrival at all modules. The differential pairs utilize 100Ω impedance control, and the termination matching network uses a parallel 50Ω resistor to ground to minimize signal reflections and distortion. Buffers are provided at each clock signal branch point to maintain signal integrity and minimize the effects of fan-out loading.

[0102] Through this design, the high-precision clock module achieves clock signal edge jitter control within 1ps RMS, providing a reliable foundation for the system's high-precision time synchronization. This design not only ensures high clock signal accuracy and low jitter, but also improves system reliability and stability in complex environments.

[0103] (4) Time slicing coordination module.

[0104] The time-slicing coordination module is implemented based on FPGA and includes: hardware counters, status registers, time-triggered scheduler, programmable timer array, DMA controller and dual-port RAM. The time-slicing coordination module also has a task feature lookup table and a hardware priority queue. Among them, the hardware counters and status registers are connected to the time-triggered scheduler through a low-latency bus; the task feature lookup table and hardware priority queue are implemented using on-chip memory and support parallel access; the time-triggered scheduler and programmable timer array work together through an internal high-speed interconnection bus; the DMA controller is connected to the dual-core processor through the PCIe interface to achieve high-speed data transmission. The time-triggered scheduler is connected to the safety isolation core and time synchronization core through the control bus, connected to the hardware counter and status register through the low-latency bus, and works in conjunction with the programmable timer array through the internal high-speed interconnection bus; the programmable timer array receives clock signals and control instructions from the time-triggered scheduler through the internal high-speed interconnection bus; the dual-port RAM is connected to the safety isolation core and time synchronization core through a high-speed data channel for temporary storage and exchange of data; the DMA controller is connected to the dual-core processor through the PCIe interface to achieve high-speed data transmission, and is connected to the hardware priority queue through the control signal line to receive data transmission priority instructions; the time synchronization core receives clock signals from the high-precision clock module through a dedicated clock bus, and provides processed clock signals and synchronization information to the time-triggered scheduler through the control bus.

[0105] In some embodiments, for example, the time-slicing coordination module can be implemented on a Xilinx Kintex UltraScale+ XCKU5P FPGA development board, operating at a 500MHz clock frequency. This module connects to a dual-core processor via a control bus using the AXI4 protocol, supporting a multi-master, multi-slave architecture. The bus width is 128 bits, and the operating frequency is 250MHz, providing up to 4GB / s of bandwidth for concurrent communication between modules. The core function of the time-slicing coordination module is to achieve efficient task allocation and resource scheduling, thereby improving overall system performance.

[0106] This module includes several key components, including a 64-bit high-precision hardware counter with a resolution of 2ns and a maximum counting time exceeding 1000 years. A Gray code structure is used to ensure reliability when multiple bits are flipped simultaneously. The 128 32-bit status registers utilize a dual-port architecture, supporting simultaneous read and write operations with a read latency of less than 3ns and a write latency of less than 5ns. The task feature lookup table is implemented using a content-addressable memory (CAM) with a capacity of 4K x 64 bits. It supports 256 different task types, has a lookup time of less than 5ns, and consumes less than 0.5W. The hardware priority queue, based on a heap data structure, supports eight levels of priority and can manage 1024 tasks simultaneously. Using a parallel comparator array, enqueue / dequeue operations have a latency of less than 10ns.

[0107] The time-triggered scheduler uses a hybrid algorithm of polling and shortest job first. The scheduling period is configurable, with a minimum of 10μs. It supports dynamic time slice allocation, ranging from 100μs to 10ms in 1μs increments. The programmable timer array contains 64 independent high-precision timers with a resolution of 10ns, supporting single-shot and periodic trigger modes, with a maximum timing range of 1 hour. The DMA controller supports 8 independent channels, each with a maximum transfer rate of 10GB / s. It uses a descriptor linked list structure and supports scatter-gather transfer mode. The dual-port RAM uses 18Mb of high-speed SRAM with an access latency of less than 2ns, supporting true dual-port simultaneous read and write without conflicts.

[0108] The module's internal interconnection utilizes an efficient bus architecture. Hardware counters and status registers connect to the FPGA core via an AXI4-Lite bus (32-bit width, 250MHz clock), with single-shot read and write latency less than 20ns. The task signature lookup table and hardware priority queue are implemented using on-chip FPGA block RAM, supporting two parallel accesses per clock cycle and a total bandwidth of 64GB / s. The time-triggered scheduler and programmable timer array work together via an AXI4-Stream bus (128-bit width, 500MHz clock), providing internal data transfer capabilities of up to 64GB / s. The DMA controller connects to the dual-core processor via a PCIe Gen4 x8 interface, offering a theoretical maximum bandwidth of 64GB / s and an actual sustained transfer rate exceeding 50GB / s.

[0109] In addition, in some embodiments, the device of the present application also includes a non-volatile memory, a power management unit, and a multi-interface input / output module; wherein the non-volatile memory adopts a dual backup structure and is connected to the dual-core processor through an independent storage controller; the power management unit adopts multi-stage DC-DC conversion and provides independent and isolated power supply for each module through a star topology; the multi-interface input / output module supports a configurable protocol stack and communicates with the dual-core processor through a high-speed serial interface.

[0110] It should be noted that the examples introduced above are merely examples. In actual applications, other elements with similar functions and appropriate numerical ranges can be used to implement the present invention, and this application does not impose any restrictions on this.

[0111] In summary, the time synchronization device based on the secure isolation of Beidou satellite timing signals according to the embodiment of the present application has the following beneficial effects:

[0112] 1. Improved security of Beidou satellite timing signal processing: This invention utilizes a dual-core processor architecture and physically isolates the security isolation core from the time synchronization core through a dedicated isolation bridge. The isolation bridge utilizes optoelectronic isolation technology, ensuring high-speed data transmission while achieving physical isolation and effectively preventing potential security threats.

[0113] 2. Optimized resource scheduling efficiency: The time-slicing coordination module is implemented based on FPGA and includes components such as hardware counters, hardware priority queues, and time-triggered schedulers, which significantly improves the system's real-time task processing capabilities and resource utilization efficiency.

[0114] 3. Achieved efficient inter-module communication: The high-speed data bus with multi-layer PCB design and the control bus with multi-master and multi-slave architecture support concurrent communication between modules, improving the overall data transmission efficiency of the system.

[0115] 4. Improved time synchronization accuracy: The high-precision clock module utilizes a dual oven-controlled crystal oscillator (DOCXO) and a backup atomic clock interface, combined with a digital phase-locked loop (DPLL) circuit to achieve high-precision time synchronization. The DPLL circuit's loop bandwidth is adaptively adjustable from hertz to kilohertz, further optimizing synchronization performance.

[0116] Reference Figure 4 Another aspect of the embodiment of the present application further provides a time synchronization method based on the above-mentioned time synchronization device based on Beidou satellite timing signal security isolation, the method comprising the following steps S100~S500:

[0117] Step S100, receiving an initial timing signal transmitted by a Beidou satellite through a Beidou signal receiving module, digitizing the initial timing signal, obtaining first timing signal data, and sending the first timing signal data to a secure isolation core of a dual-core processor;

[0118] Step S200: receiving the first timing signal data through the security isolation core, performing a security check on the first timing signal data, and sending the checked first timing signal data to the time synchronization core of the dual-core processor;

[0119] Step S300, sending local clock information to the time synchronization core through a high-precision clock module;

[0120] Step S400, performing time synchronization processing by the time synchronization core according to the received first timing signal and the local clock information;

[0121] Step S500: Coordinate the scheduling of the high-precision clock module and the dual-core processor through a time slicing coordination module.

[0122] In some embodiments, the method may further include but is not limited to the following steps S600 to S800:

[0123] Step S600, storing the configuration information and log data of the dual-core processor in a non-volatile memory;

[0124] Step S700, powering each power-consuming module in the time synchronization device based on the Beidou satellite timing signal security isolation through the power management unit;

[0125] Step S800: realizing communication among various modules in the time synchronization device based on the secure isolation of Beidou satellite timing signals through a multi-interface input and output module.

[0126] It can be understood that the beneficial effects achieved by the above method embodiment are the same as the beneficial effects achieved by the above device embodiment.

[0127] The embodiments described in the embodiments of this application are intended to more clearly illustrate the technical solutions of the embodiments of this application and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will appreciate that with the evolution of technology and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0128] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of the present application, and may include more or fewer steps than shown in the figures, or a combination of certain steps, or different steps.

[0129] The system embodiment described above is merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0130] Those skilled in the art will appreciate that all or some of the steps, systems, devices, and functional modules / units in the methods disclosed above may be implemented as software, firmware, hardware, or appropriate combinations thereof.

[0131] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0132] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0133] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the system embodiments described above are merely schematic. For example, the division of the above units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0134] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0135] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0136] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and includes multiple instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of various embodiments of the present application. The aforementioned storage medium includes: various media that can store programs, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0137] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but are not intended to limit the scope of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and essence of the present invention should be within the scope of the present invention.

Claims

1. A time synchronization device based on the secure isolation of Beidou satellite timing signals, characterized in that: The device comprises: Beidou signal receiving module, dual-core processor, high-precision clock module and time slicing coordination module; The dual-core processor includes a security isolation core and a time synchronization core; an isolation bridge is provided between the security isolation core and the time synchronization core; The Beidou signal receiving module is connected to the security isolation core through a dedicated data interface; The high-precision clock module is connected to the time synchronization core via a dedicated clock bus; The time slicing coordination module is connected to the dual-core processor via a control bus.

2. The device according to claim 1, characterized in that The Beidou signal receiving module includes: Beidou satellite signal receiving antenna, low-noise amplifier, bandpass filter, multi-band receiver and high-speed analog-to-digital converter; Wherein, the Beidou satellite signal receiving antenna is connected to the low noise amplifier via a coaxial cable; An impedance network is provided between the Beidou satellite signal receiving antenna and the low noise amplifier; The low noise amplifier is cascade-connected to the bandpass filter via a microstrip line; The multi-band receiver is connected to a high-speed analog-to-digital converter via a high-speed digital interface; The high-speed analog-to-digital converter is connected to the safety isolation core via a dedicated data interface.

3. The device according to claim 1, characterized in that The security isolation core includes: CRC check unit, state machine check unit, digital signal processing unit, cache and multiplexer; Wherein, the CRC check unit and the state machine check unit are connected in parallel to the digital signal processing unit; The cache is connected to the digital signal processing unit via a multi-port interface; The multiplexer adopts a cross switch structure; The digital signal processing unit is connected to the Beidou signal receiving module through the dedicated data interface; The multiplexer is connected to the isolation bridge; The digital signal processing unit is connected to the time slicing coordination module via a control bus.

4. The device according to claim 1, characterized in that The time synchronization core includes: Local clock receiving unit, time deviation calculation unit, digital controlled oscillator, digital phase locked loop circuit and time output interface; Wherein, the local clock receiving unit is connected to the high-precision clock module; The time deviation calculation unit is connected to the safety isolation core; The time deviation calculation unit is connected to the digitally controlled oscillator via a high-speed data channel; The output end of the digital controlled oscillator is connected to the input end of the digital phase locked loop; The time output interface is connected to the digital phase locked loop circuit and is connected to an external device through an output buffer.

5. The device according to claim 1, characterized in that The high-precision clock module includes: Dual oven-controlled crystal oscillators, backup atomic clock interface, clock switching control circuit, clock output unit; Wherein, the dual oven controlled crystal oscillator is isolated from the main circuit board via a low noise power supply and a temperature control loop; The clock switching control circuit communicates with the dual-core processor via a high-speed serial interface; The clock output unit is connected to the dual oven controlled crystal oscillator and the backup atomic clock interface; The clock output unit is connected to the local clock receiving unit of the time synchronization core through a dedicated low-jitter clock channel; The clock switching control circuit is connected to the time synchronization core.

6. The device according to claim 1, characterized in that The time slicing coordination module includes: Hardware counters, status registers, task signature lookup tables, hardware priority queues, time-triggered schedulers, programmable timer arrays, DMA controllers, and dual-port RAM; wherein the hardware counter and the status register are connected to the time-triggered scheduler via a low-latency bus; The task feature lookup table and the hardware priority queue are implemented using on-chip memory; The time-triggered scheduler and the programmable timer array work in coordination via an internal high-speed interconnect bus; The dual-port RAM is connected to the security isolation core and the time synchronization core via a high-speed data channel; The DMA controller is connected to the dual-core processor via a PCIe interface; the DMA controller is also connected to the hardware priority queue via a control signal line; The time-triggered scheduler is connected to the time synchronization core via a control bus.

7. The device according to claim 4, characterized in that The digital phase locked loop comprises: High-speed digital phase detector, adjustable digital loop filter, digitally controlled oscillator, and programmable frequency divider; wherein the high-speed digital phase detector is connected to the adjustable digital loop filter via a high-speed data channel; The digitally controlled oscillator is connected to the programmable frequency divider via a low-jitter clock distribution network.

8. The device according to any one of claims 1 to 7, characterized in that The device further comprises: Non-volatile memory, power management unit and multi-interface input and output module; The non-volatile memory adopts a dual-backup structure and is connected to the dual-core processor via an independent storage controller; The power management unit is connected to each module that needs power supply through a star topology; The multi-interface input and output module is connected to the dual-core processor via a high-speed serial interface.

9. The time synchronization method based on the time synchronization device for secure isolation of Beidou satellite timing signals according to claim 1 is characterized in that: The method comprises the following steps: Receive an initial timing signal transmitted by a Beidou satellite through a Beidou signal receiving module, digitize the initial timing signal, obtain first timing signal data, and send the first timing signal data to the security isolation core of the dual-core processor; receiving the first timing signal data through the security isolation core, performing a security check on the first timing signal data, and sending the checked first timing signal data to the time synchronization core of the dual-core processor; Sending local clock information to the time synchronization core through a high-precision clock module; Performing time synchronization processing according to the received first timing signal and the local clock information through the time synchronization core; The scheduling of the high-precision clock module and the dual-core processor is coordinated by a time slicing coordination module.

10. The method according to claim 9, characterized in that The method further comprises the following steps: Storing the configuration information and log data of the dual-core processor in a non-volatile memory; The power management unit is used to supply power to each power-consuming module in the time synchronization device based on the safe isolation of Beidou satellite timing signals; The communication between the modules in the time synchronization device based on the safe isolation of Beidou satellite timing signals is realized through a multi-interface input and output module.

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