Turn-back type current limiting protection circuit and low dropout regulator

Abstract

The invention provides a turn-back type current-limiting protection circuit and a low dropout regulator, and belongs to the technical field of integrated circuits, and the turn-back type current-limiting protection circuit is characterized in that a first sampling resistor outputs a first current according to a sampling signal of a load current, a first bias current and a gated second bias current; the second sampling resistor outputs a second current according to the third bias current and the gated fourth bias current; the current comparison network generates a current comparison signal; the common-source amplification module is connected between an output signal of the error amplifier and a grounding end, on-off of the common-source amplification module is controlled by a current comparison signal and a gated low signal, and an output end of the common-source amplification module is connected with a gate driving module of a power tube; the output signal feedback network generates a gating signal according to the input signal, the output signal and the output signal of the error amplifier. The beneficial effects are that constant load current output is realized by detecting the load current change of the power tube and adjusting the grid voltage of the power tube, and the grid voltage clamp of the power tube is positioned at a safe level by utilizing output voltage feedback, so that turn-back type current limiting protection is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a foldback current limiting protection circuit and a low voltage drop linear regulator. Background Art

[0002] With the advancement of science and technology and the changing social demand for technology, electronic product technology has also developed rapidly. This is not only reflected in the performance improvement of traditional electronic products, but also in the emergence of emerging products such as smart phones, wireless mice, laptops and other portable and wearable devices.

[0003] As the main power management chips, low dropout regulator (LDO) power supplies and direct current-direct current (DC-DC) converters are increasingly used in various electronic products. LDO is widely used in application scenarios that require high-precision power supplies due to its low noise, stable output voltage, and simple structure. DC-DC converters are widely used to meet the low power consumption and high-efficiency power conversion requirements of equipment due to their high efficiency, wide input voltage range, and adjustable output.

[0004] However, as the functions of electronic products become increasingly complex and diverse, the application scenarios of power management chips have also become more complex and varied. Customers have also put forward higher and higher requirements. Without increasing the cost of chips, how to simplify circuit design, improve chip load capacity, reduce static power consumption, and improve system stability and reliability has become the focus of research and development. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a foldback current limiting protection circuit; on the other hand, it also provides a low voltage drop linear regulator.

[0006] The technical problem solved by the present invention can be achieved by the following technical solutions: The first aspect of the present invention is to provide a foldback current limiting protection circuit, comprising: a current comparison network, used to compare a first current flowing through a first sampling resistor and a second current flowing through a second sampling resistor, and generate a current comparison signal; wherein the first current is the sum of a sampling signal of a load current sampled from a power tube, a first bias current and a second bias current selected by a selection signal, the second current is the sum of a third bias current and a fourth bias current selected by the selection signal, and the resistance value of the second sampling resistor is different from the resistance value of the first sampling resistor; a common source amplifier module, connected between an error amplifier output signal and a ground terminal, the control end of the common source amplifier module is controlled by the current comparison signal and a low signal selected by the control signal to switch the on-off state, and the output end of the common source amplifier module is connected to the gate drive module of the power tube; an output signal feedback network, used to generate the selection signal according to an input signal, an output signal, and the error amplifier output signal, and to generate the control signal according to the error amplifier output signal.

[0007] Preferably, the resistance of the second sampling resistor is greater than the resistance of the first sampling resistor.

[0008] Preferably, the first bias current accounts for one third of the sum of the first bias current and the second bias current; and / or the second bias current accounts for two thirds of the sum of the first bias current and the second bias current; and / or the third bias current accounts for one third of the sum of the third bias current and the fourth bias current; and / or the fourth bias current accounts for two thirds of the sum of the third bias current and the fourth bias current.

[0009] Preferably, the first bias current is twice the reference current; and / or the second bias current is four times the reference current; and / or the third bias current is twice the reference current; and / or the fourth bias current is four times the reference current.

[0010] Preferably, the sampling signal is generated by a current detection circuit, and the current detection circuit includes: a first PMOS tube, the gate of the first PMOS tube is connected to the gate of the power tube, the source of the first PMOS tube is connected to the input signal through the first sampling resistor, and the drain of the first PMOS tube is used to output the output signal.

[0011] Preferably, the current comparison network includes: a second PMOS tube, the source of which is connected to the input signal through the first sampling resistor; a first NMOS tube, the gate of which is connected to the second bias voltage, the drain of which is connected to the gate and drain of the second PMOS tube, and the source of which is connected to the first bias current; a third PMOS tube, the gate of which is connected to the gate of the second PMOS tube, the source of which is connected to the input signal through the second sampling resistor, and the current comparison signal is output from the drain of the third PMOS tube; a second NMOS tube, the gate of which is connected to the second bias voltage, the drain of which is connected to the drain of the third PMOS tube, and the source of which is connected to the third bias current.

[0012] Preferably, it also includes: a first switch tube, the control end of the first switch tube is connected to the selection signal, the input end of the first switch tube is connected to the first sampling resistor, and the output end of the first switch tube is connected to the second bias current through the first resistor; a second switch tube, the control end of the second switch tube is connected to the selection signal, the input end of the second switch tube is connected to the second sampling resistor, and the output end of the second switch tube is connected to the fourth bias current through the second resistor.

[0013] Preferably, the common-source amplification module includes: a third NMOS tube, the gate of the third NMOS tube is connected to the current comparison signal, the drain of the third NMOS tube is connected to the error amplifier output signal, and the source of the third NMOS tube is connected to the ground terminal; a fourth NMOS tube, the gate of the fourth NMOS tube is connected to the control signal, the drain of the fourth NMOS tube is connected to the current comparison signal, and the source of the fourth NMOS tube is connected to the ground terminal.

[0014] Preferably, the output signal feedback network includes: a fourth PMOS tube, the gate of the fourth PMOS tube is connected to the first bias voltage, the source of the fourth PMOS tube is connected to the input signal, and the drain of the fourth PMOS tube outputs the selection signal; a fifth PMOS tube, the gate of the fifth PMOS tube is connected to the output signal through a third resistor and to the ground terminal through a first capacitor, the source of the fifth PMOS tube is connected to the selection signal, and the drain of the fifth PMOS tube is connected to the ground terminal through a fourth resistor; a fifth NMOS tube, the gate of the fifth NMOS tube is connected to the error amplifier output signal, the drain of the fifth NMOS tube is connected to the fifth bias current, the source of the fifth NMOS tube is connected to the ground terminal, and the control signal is output from the drain of the fifth NMOS tube; a sixth NMOS tube, the gate of the sixth NMOS tube is connected to the control signal, the source of the sixth NMOS tube is connected to the ground terminal, and the drain of the sixth NMOS tube is connected to the selection signal.

[0015] The second aspect of the present invention is to provide a low voltage difference linear regulator, including the above-mentioned foldback current limiting protection circuit, and also including: a power tube, used to generate an output signal lower than the input signal; an error amplifier, the input end of the error amplifier is respectively connected to a reference signal and a feedback signal of the output signal, and the output end of the error amplifier is connected to the error amplifier output signal; a gate drive module, the input end of the gate drive module is connected to the output end of the error amplifier, and the output end of the gate drive module is connected to the gate of the power tube.

[0016] The advantages or beneficial effects of the technical solution of the present invention are: the present invention detects the change of the load current of the power tube, adjusts the gate voltage of the power tube, and realizes the limitation of the output power, especially reduces the static power consumption when the circuit is unloaded or lightly loaded, and realizes constant load current output by adjusting the gate voltage of the power tube in the case of short circuit or overload, and gradually reduces the output current by using the output voltage feedback mechanism, clamps the gate voltage of the power tube at a safe level, realizes the return current limiting protection function, and reduces the power consumption of the chip under heavy load; the circuit has the advantages of simple structure, small chip area, low static power consumption, and low power consumption when the circuit is short-circuited or overloaded, and is suitable for scenarios with low power supply voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A circuit diagram of a current limiting loop in a preferred embodiment of the present invention; Figure 2 A circuit diagram of an output signal feedback network in a preferred embodiment of the present invention; Figure 3 This is a schematic diagram of an application of a low dropout linear regulator LDO in a preferred embodiment of the present invention; Figure 4 FIG. 1 is a schematic diagram of the internal structure of a low dropout linear regulator LDO in a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0019] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0020] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0021] See also Figure 1 , Figure 2 , Figure 3 and Figure 4 In a preferred embodiment of the present invention, based on the above problems existing in the prior art, a foldback current limiting protection circuit is provided, comprising: a current comparison network 100, for comparing a first current flowing through a first sampling resistor R1 and a second current flowing through a second sampling resistor R2, and generating a current comparison signal VCP; wherein the first current is the sum of a sampling signal I1 of a load current sampled from a power tube MP, a first bias current I2, and a second bias current I3 selected by a selection signal PM4_D, the second current is the sum of a third bias current I4 and a fourth bias current I5 selected by a selection signal PM4_D, the resistance value of the second sampling resistor R2 is equal to the first bias current I5, and the resistance value of the second sampling resistor R2 is equal to the first bias current I6. The resistance value of a sampling resistor R1 is different; a common-source amplifier module 200 is connected between the error amplifier output signal C33_MIN and the ground terminal, the control end of the common-source amplifier module 200 is controlled by the current comparison signal VCP and the low signal selected by the control signal PM11_D to switch the on-off state, and the output end of the common-source amplifier module 200 is connected to the gate drive module of the power tube MP; an output signal feedback network 300 is used to generate a selection signal PM4_D according to the input signal VIN, the output signal VOUT, and the error amplifier output signal C33_MIN, and to generate a control signal PM11_D according to the error amplifier output signal C33_MIN.

[0022] Specifically, the embodiment of the present invention is composed of a first sampling resistor R1, a second sampling resistor R2, a current comparison network 100, a common source amplifier module 200 and an output voltage feedback network 300, wherein the first sampling resistor R1, the second sampling resistor R2, the current comparison network 100 and the common source amplifier module 200 constitute a current limiting loop.

[0023] The first current output by the first sampling resistor R1 is superimposed with the fixed first bias current I2 and the second bias current I3 and the sampling signal I1 of the load current from the power tube MP; the second current output by the second sampling resistor R2 is superimposed with the fixed third bias current I4 and the fourth bias current I5. The second bias current I3 and the fourth bias current I5 are both selected by the selection signal PM4_D. When the selection signal PM4_D is at a high level, the second bias current I3 and the fourth bias current I5 are selected at the same time; when the selection signal PM4_D is at a low level, the second bias current I3 and the fourth bias current I5 are disconnected at the same time.

[0024] In the output signal feedback network 300, it is configured as: outputting a selection signal PM4_D according to an input signal VIN in response to a first bias voltage; changing the size of the selection signal PM4_D in response to an output signal VOUT; outputting a control signal PM11_D in response to an error amplifier output signal C33_MIN; and changing the size of the selection signal PM4_D in response to the control signal PM11_D.

[0025] The current comparison network 100 compares the currents flowing through the two sampling resistors to generate a current comparison signal VCP. The common source amplifier module 200 is connected between the error amplifier output signal C33_MIN and the ground terminal, and switches the on-off state under the control of the current comparison signal VCP. At the same time, when the control signal PM11_D is at a high level, the current comparison signal VCP is pulled down to a low level.

[0026] The principle of the circuit shown in the embodiment of the present invention is that when the load is not loaded, the error amplifier output voltage C33_MIN is small, the control signal PM11_D is at a high level, and the current comparison signal VCP is pulled down to a low level; at the same time, because the control signal PM11_D is at a high level, the selection signal PM4_D is pulled down to a low level, and the second bias current I3 and the fourth bias current I5 in the control current limiting loop are disconnected at the same time. At this time, the fixed bias current is the first bias current I2 and the third bias current I4, that is, twice the reference current, recorded as 2Iref, which can reduce the static power consumption when the load is not loaded.

[0027] When the load is light, the gate voltage of the power tube MP is relatively large, and the sampling signal I1 of the load current is relatively small. Since the second sampling resistor R2 is larger than the first sampling resistor R1, at this time, the voltage drop across the first sampling resistor R1 is smaller than the voltage drop across the second sampling resistor R2, and the current comparison signal VCP output by the current comparison network 100 is at a low level. The error amplifier output voltage C33_MIN increases with the increase of the load current, the control signal PM11_D is at a low level, and the selection signal PM4_D is at a high level, and the second bias current I3 and the fourth bias current I5 in the control current limiting loop are selected at the same time. At this time, the fixed bias current is the sum of the first bias current I2 and the second bias current I3, and the sum of the third bias current I4 and the fourth bias current I5, that is, six times the reference current, which is recorded as 6Iref.

[0028] When the load current gradually increases, the voltage drop across the first sampling resistor R1 gradually becomes greater than the voltage drop across the second sampling resistor R2, and the current comparison signal VCP output by the current comparison network 100 is at a high level, entering a fixed current limiting state. At this time, the output voltage feedback network 300 starts to work, the output voltage VOUT decreases, and the selection signal PM4_D is pulled down to a low level, and the second bias current I3 and the fourth bias current I5 in the control current limiting loop are disconnected at the same time. At this time, the magnitude of the bias current changes from 6Iref to 2Iref, and the short-circuit current limiting value becomes 1 / 3 of the fixed current limiting value.

[0029] Since the current comparison signal VCP is at a high level, its voltage is raised through the common source amplifier module 200, thereby raising the gate voltage VPG of the power tube MP. Since the current limiting loop is a closed negative feedback loop, the gate voltage VPG of the power tube MP is finally clamped at a fixed potential, so that the power tube MP outputs a constant load current and performs foldback current limiting.

[0030] As a preferred implementation, the resistance of the second sampling resistor R2 is greater than the resistance of the first sampling resistor R1.

[0031] Specifically, in this embodiment, the first bias current I2 and the sampling signal I1 of the load current are fixedly applied to the first sampling resistor R1 , and the second bias current I3 may be optionally applied to the first sampling resistor R1 .

[0032] Similarly, the third bias current I4 is fixedly applied to the second sampling resistor R2, and the fourth bias current I5 is optionally applied to the second sampling resistor R2.

[0033] The first sampling resistor R1 and the second sampling resistor R2 convert the current signal of their own branch into a voltage signal, realize current comparison at the source of the second PMOS transistor PM2 and the third PMOS transistor PM3 of the current comparison network 100, and output the current comparison signal VCP at the drain of the third PMOS transistor PM3.

[0034] Since R2>R1, when no-load or light-loaded, the voltage drop across the first sampling resistor R1 is smaller than the voltage drop across the second sampling resistor R2, so that the output current comparison signal VCP is low level; and when the load current gradually increases, the voltage drop across the first sampling resistor R1 gradually becomes larger than the voltage drop across the second sampling resistor R2, so that the current comparison signal VCP is flipped to a high level.

[0035] As a preferred embodiment, the first bias current I2 accounts for one third of the sum of the first bias current I2 and the second bias current I3; and / or the second bias current I3 accounts for two thirds of the sum of the first bias current I2 and the second bias current I3; and / or the third bias current I4 accounts for one third of the sum of the third bias current I4 and the fourth bias current I5; and / or the fourth bias current I5 accounts for two thirds of the sum of the third bias current I4 and the fourth bias current I5.

[0036] As a preferred embodiment, the first bias current is twice the reference current; and / or the second bias current is four times the reference current; and / or the third bias current is twice the reference current; and / or the fourth bias current is four times the reference current.

[0037] Specifically, in this embodiment, the first bias current I2 and the third bias current I4 have the same magnitude, which is twice the reference current, ie, 2Iref. Similarly, the second bias current I3 and the fourth bias current I5 have the same magnitude, which is four times the reference current, ie, 4Iref.

[0038] Since the first bias current I2 and the third bias current I4 are fixed bias currents, the second bias current I3 and the fourth bias current I5 are turned on and off at the same time.

[0039] If the second bias current I3 and the fourth bias current I5 are enabled at the same time, the circuit fixed bias current is 6Iref.

[0040] If the second bias current I3 and the fourth bias current I5 are disconnected at the same time, the circuit fixed bias current is 2Iref.

[0041] Therefore, the circuit fixed bias current is switched between 2Iref and 6Iref.

[0042] More specifically, the first bias current I2, the second bias current I3, the third bias current I4 and the fourth bias current I5 are provided by a current mirror module 400, and the current mirror module 400 includes a first transistor NM1, a second transistor NM2, a third transistor NM3, a fourth transistor NM4, a fifth transistor NM5 and a sixth transistor NM6, and the first to sixth transistors are all NMOS tubes.

[0043] The gates of the first to sixth transistors are all connected to the second bias voltage VB2, the source of the first transistor NM1 is connected to the ground terminal, the drain of the first transistor NM1 is connected to the source of the second transistor NM2, and the drain of the second transistor NM2 is connected to the reference current I ref , reference current I ref is an internal reference current, providing a current bias for the circuit; a source of the third transistor NM3 is connected to the ground terminal, and a drain of the third transistor NM3 is used to provide the second bias current I3; a source of the fourth transistor NM4 is connected to the ground terminal, and a drain of the fourth transistor NM4 is used to provide the first bias current I2; a source of the fifth transistor NM5 is connected to the ground terminal, and a drain of the fifth transistor NM5 is used to provide the third bias current I4; a source of the sixth transistor NM6 is connected to the ground terminal, and a drain of the sixth transistor NM6 is used to provide the fourth bias current I5.

[0044] As a preferred embodiment, the sampling signal I1 is generated by a current detection circuit, and the current detection circuit includes: a first PMOS tube PM1, the gate of the first PMOS tube PM1 is connected to the gate of the power tube MP, the source of the first PMOS tube PM1 is connected to the input signal through the first sampling resistor R1, and the drain of the first PMOS tube PM1 is used to output the output signal VOUT.

[0045] Specifically, the sampling signal I1 is the current flowing through the first PMOS transistor PM1.

[0046] As a preferred embodiment, the current comparison network 100 includes: a second PMOS tube PM2, the source of the second PMOS tube PM2 is connected to the input signal VIN through the first sampling resistor R1; a first NMOS tube NM1_LVT, the gate of the first NMOS tube NM1_LVT is connected to the second bias voltage VB2, the drain of the first NMOS tube NM1_LVT is connected to the gate and drain of the second PMOS tube PM2, and the source of the first NMOS tube NM1_LVT is connected to the first bias current I2; a third PMOS tube PM3, the third The gate of the PMOS tube PM3 is connected to the gate of the second PMOS tube PM2, the source of the third PMOS tube PM3 is connected to the input signal VIN through the second sampling resistor R2, and the current comparison signal VCP is output from the drain of the third PMOS tube PM3; the second NMOS tube NM2_LVT, the gate of the second NMOS tube NM2_LVT is connected to the second bias voltage VB, the drain of the second NMOS tube NM2_LVT is connected to the drain of the third PMOS tube PM3, and the source of the second NMOS tube NM2_LVT is connected to the third bias current I4.

[0047] Specifically, in this embodiment, the first sampling resistor R1 and the second sampling resistor R2 convert current into voltage, compare the source voltage of the second PMOS transistor PM2 with the source voltage of the third PMOS transistor PM3, and output a current comparison signal VCP at the drain of the third PMOS transistor PM3.

[0048] The first NMOS tube NM1_LVT and the second NMOS tube NM2_LVT are NMOS tubes, and both are low threshold devices, that is, devices with a low threshold voltage. When the gate-source voltage of the first NMOS tube NM1_LVT and the second NMOS tube NM2_LVT is low, it can ensure that the MOS tube works in the saturation region, so that the entire current comparison network can work normally under a lower power supply voltage, and is suitable for low-voltage LDO.

[0049] As a preferred embodiment, it also includes: a first switch tube NM7, a control end (i.e., a gate) of the first switch tube NM7 is connected to a selection signal PM4_D, an input end (i.e., a drain) of the first switch tube NM7 is connected to a first sampling resistor R1, and an output end (i.e., a source) of the first switch tube NM7 is connected to a second bias current I3 via a first resistor R3.

[0050] Specifically, in this embodiment, the second bias current I3 is controlled by the selection signal PM4_D to control the on / off state of the first switch tube NM7 to achieve selection and disconnection.

[0051] If the selection signal PM4_D is at a low level, the first switch tube NM7 is turned off, and the branch where the second bias current I3 is located is disconnected.

[0052] If the selection signal PM4_D is at a high level, the first switch tube NM7 is turned on, and the branch where the second bias current I3 is located is selected.

[0053] As a preferred embodiment, it also includes: a second switch tube NM8, a control end (i.e., a gate) of the second switch tube NM8 is connected to the selection signal PM4_D, an input end (i.e., a drain) of the second switch tube NM8 is connected to the second sampling resistor R2, and an output end (i.e., a source) of the second switch tube NM8 is connected to the fourth bias current I5 through the second resistor R4.

[0054] Specifically, in this embodiment, the fourth bias current I5 is controlled by the selection signal PM4_D to control the on / off state of the second switch tube NM8 to achieve selection and disconnection.

[0055] If the selection signal PM4_D is at a low level, the second switch tube NM8 is turned off, and the branch where the fourth bias current I5 is located is disconnected.

[0056] If the selection signal PM4_D is at a high level, the second switch tube NM8 is turned on, and the branch where the fourth bias current I5 is located is selected.

[0057] As a preferred embodiment, the common source amplifier module 200 includes: a third NMOS tube NM9, the gate of the third NMOS tube NM9 is connected to the current comparison signal VCP, the drain of the third NMOS tube NM9 is connected to the error amplifier output signal C33_MIN, and the source of the third NMOS tube NM9 is connected to the ground terminal.

[0058] Specifically, in the present embodiment, the third NMOS tube NM9 serves as the second stage of the error amplifier in the LDO, and its input is connected to the error amplifier output signal C33_MIN of the first stage of the error amplifier. The error amplifier output signal C33_MIN is amplified under the control of the current comparison signal VCP, thereby raising the gate voltage of the subsequent power tube MP. Since the current limiting loop is a closed-loop negative feedback loop, the gate voltage VPG of the power tube MP is finally clamped at a fixed potential, so that the power tube MP outputs a constant load current.

[0059] More specifically, the drain of the third NMOS transistor NM9 is connected to the gate drive module of the power transistor MP. The gate drive module can adopt the gate drive circuit in the LDO, which will not be described in detail here.

[0060] As a preferred implementation, it further includes: a fourth NMOS tube NM10, a gate of the fourth NMOS tube NM10 connected to the control signal PM11_D, a drain of the fourth NMOS tube NM10 connected to the current comparison signal VCP, and a source of the fourth NMOS tube NM10 connected to the ground terminal.

[0061] Specifically, in this embodiment, the fourth NMOS transistor NM10 is controlled by the control signal PM11_D to switch the on and off state. When the control signal PM11_D is at a low level, the fourth NMOS transistor NM10 is turned off. When the control signal PM11_D is at a high level, the fourth NMOS transistor NM10 is turned on and pulls the current comparison signal VCP down to a low level.

[0062] As a preferred embodiment, the output signal feedback network 300 includes: a fourth PMOS tube PM4, a gate of the fourth PMOS tube PM4 connected to the first bias voltage VB1, a source of the fourth PMOS tube PM4 connected to the input signal VIN, and a drain of the fourth PMOS tube PM4 outputting a selection signal PM4_D.

[0063] Specifically, in this embodiment, since the first bias voltage VB1 is a constant potential, when the LDO is working, the fourth PMOS transistor PM4 is in a normally-on state, and generates a selection signal PM4_D at its drain after processing the input signal VIN.

[0064] The above VB1 and VB2 are bias voltages, which provide voltage reference points for LDO.

[0065] As a preferred embodiment, the output signal feedback network 300 also includes: a fifth PMOS tube PM5, a gate of the fifth PMOS tube PM5 is connected to the output signal VOUT through a third resistor R5 and is connected to the ground terminal through a first capacitor C1, a source of the fifth PMOS tube PM5 is connected to the selection signal, and a drain of the fifth PMOS tube PM5 is connected to the ground terminal through a fourth resistor R6.

[0066] Specifically, in this embodiment, the third resistor R5, the first capacitor C1, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are used to form an output voltage feedback network, which can respond to changes in the output voltage in a timely manner. Among them, the fourth resistor R6 is a source-level negative feedback resistor, which can improve the output impedance.

[0067] The fifth PMOS transistor PM5 switches between on and off states in response to the control of the output signal VOUT to change the magnitude of the selection signal PM4_D.

[0068] When the load current gradually increases until the current comparison signal VCP flips, it enters a fixed current limiting state. At this time, the output voltage feedback network 300 starts to work, the output signal VOUT decreases, the gate voltage of the fifth PMOS transistor PM5 also decreases, the pull-down of the path where the fifth PMOS transistor PM5 is located is enhanced, and the voltage of the selection signal PM4_D is pulled down, closing the branches where the second bias current I3 and the fourth bias current I5 are located.

[0069] As a preferred embodiment, the output signal feedback network 300 further includes: a fifth NMOS tube NM11, the gate of the fifth NMOS tube NM11 is connected to the error amplifier output signal C33_MIN, the drain of the fifth NMOS tube NM11 is connected to the fifth bias current, the fifth bias current is one third of the reference current, that is, 1 / 3Iref, the source of the fifth NMOS tube NM11 is connected to the ground terminal, and the control signal NM11_D is output from the drain of the fifth NMOS tube NM11.

[0070] Specifically, in the present embodiment, the fifth NMOS transistor NM11 switches between on and off states in response to the control of the error amplifier output signal C33_MIN, and generates a control signal NM11_D at the drain of the fifth NMOS transistor NM11.

[0071] The error amplifier output signal C33_MIN increases as the load current increases. When no-load, the error amplifier output signal C33_MIN is small, and the fifth NMOS transistor NM11 is turned off.

[0072] When the load is light or the load current gradually increases, the fifth NMOS transistor NM11 operates in the subthreshold region, the pull-down is enhanced, and the control signal NM11_D is output as a low level.

[0073] As a preferred implementation, the output signal feedback network 300 further includes: a sixth NMOS tube NM12, a gate of the sixth NMOS tube NM12 connected to the control signal NM11_D, a source of the sixth NMOS tube NM12 connected to the ground terminal, and a drain of the sixth NMOS tube NM12 connected to the selection signal PM4_D.

[0074] Specifically, in this embodiment, the sixth NMOS tube NM12 switches the on-off state in response to the control of the control signal NM11_D to change the magnitude of the selection signal PM4_D. When the control signal NM11_D is at a low level, the sixth NMOS tube NM12 is turned off. When the control signal NM11_D is at a high level, the sixth NMOS tube NM12 is turned on and pulls the selection signal PM4_D down to a low level.

[0075] The present invention proposes a foldback current limiting protection circuit suitable for a low-voltage LDO. First, a power tube MP adopts a PMOS tube. When the circuit is unloaded or lightly loaded, the gate voltage VPG of the power tube MP is relatively high, the sampling signal I1 of the load current is relatively low, and the current limiting loop is turned off, thereby reducing static power consumption. When the circuit is short-circuited or overloaded, the gate voltage VPG of the power tube MP is relatively low, and the sampling signal I1 of the load current is relatively high. At this time, the current comparison signal VCP generated by the current comparison in the current limiting loop is passed through the common source amplifier module of the second stage of the error amplifier to raise the gate voltage of the power tube MP, thereby making the power tube MP output a constant load current.

[0076] Since the circuit has an output voltage feedback network 300, when the output voltage decreases, the output current gradually decreases, and the gate voltage VPG of the power tube MP is clamped at a smaller value, so as to achieve the purpose of short-circuit current limiting and chip protection.

[0077] The fixed current limit value is 6 times the reference current when overloaded, and the short-circuit current limit value is 2 times the reference current when short-circuited, thereby realizing the foldback function. The circuit has the advantages of simple structure, small chip area, and low power consumption when the circuit is short-circuited or overloaded.

[0078] The present invention also provides a low voltage drop linear regulator, including the above-mentioned foldback current limiting protection circuit, such as Figure 3 and Figure 4As shown, it also includes: a power tube MP, which is used to generate an output signal VOUT lower than the input signal VIN; an error amplifier 10, the input end of the error amplifier 10 is respectively connected to the reference signal and the feedback signal of the output signal, and the output end of the error amplifier 10 is connected to the error amplifier output signal C33_MIN; wherein C33_MIN is the error amplifier output voltage of the first stage of the error amplifier, and provides a bias voltage for the current limiting protection circuit; a gate drive module 20, the input end of the gate drive module 20 is connected to the output end of the error amplifier 10, and the output end of the gate drive module 20 is connected to the gate of the power tube MP.

[0079] like Figure 3 The application diagram of the low-dropout linear regulator LDO is shown. The low-dropout linear regulator LDO includes four ports, namely, an input port, an output port, an enable port and a ground port. The input port is used to receive an input signal VIN, the output port is used to output an output signal VOUT, and the enable port is used to receive an enable control signal. The input capacitor C IN Connected between the input signal VIN and the ground terminal, the output capacitor C OUT Connect between the output signal VOUT and the ground.

[0080] like Figure 4 The internal structure diagram of the low-dropout linear regulator LDO is shown. The low-dropout linear regulator LDO may include a power tube MP, an error amplifier 10, a gate drive module 20, a pre-regulator amplifier 30, and a current limiting protection & over-temperature protection 40.

[0081] The pre-regulator amplifier 30 is an operational amplifier, the non-inverting input terminal of the operational amplifier is connected to the reference signal, and the inverting input terminal of the operational amplifier is connected to the voltage-dividing feedback signal of its own output voltage. The voltage-dividing feedback signal is obtained by voltage-dividing resistors R12 and R13.

[0082] The non-inverting input terminal of the error amplifier 10 is connected to the output signal VOUT, the inverting input terminal of the error amplifier 10 is connected to the output terminal of the operational amplifier through the filter resistor R14, the inverting input terminal of the error amplifier 10 and the ground terminal are also connected to the filter capacitor C11, the output terminal of the error amplifier 10 is connected to the input terminal of the gate drive module 20, the output terminal of the gate drive module 20 is connected to the gate of the power tube MP, the source of the power tube MP is connected to the input signal VIN, and the drain of the power tube MP generates the output signal VOUT.

[0083] The low voltage drop linear regulator LDO may also include an inverter INV1, a switch tube Mn and a resistor R11. The gate of the switch tube Mn is connected to the enable control signal through the inverter INV1, the source of the switch tube Mn is connected to the ground terminal, and the drain of the switch tube Mn is connected to the above output signal VOUT through the resistor R11.

[0084] The foldback current limiting protection circuit of the present invention serves as the current limiting protection part.

[0085] In the current limiting loop, the branch current of the fourth transistor NM4 and the fifth transistor NM5 is 2Iref; the sixth transistor NM6 and the seventh transistor NM7 also form a fixed bias current, and the branch current of the sixth transistor NM6 and the seventh transistor NM7 is 4Iref. The current of the first sampling resistor R1 is superimposed with the fixed first bias current I2, the second bias current I3 and the sampling signal I1 that changes with the load current.

[0086] When unloaded, the error amplifier output voltage C33_MIN is small, the fifth NMOS tube NM11 operates in the subthreshold region, and the output control signal NM11_D is high level, which controls the gate voltage of the fourth NMOS tube NM10, so that the fourth NMOS tube NM10 operates in the linear region, and pulls the current comparison signal VCP down to a low level.

[0087] At the same time, since the control signal NM11_D is at a high level, the pull-down of the sixth NMOS tube NM12 is enhanced, so that the sixth NMOS tube NM12 operates in the linear region, and the selection signal PM4_D is pulled down to a low level, and the first switch tube NM7 and the second switch tube NM8 in the current limiting loop are controlled to be cut off, so that the second bias current I3 and the fourth bias current I5 are disconnected at the same time. At this time, the fixed bias current is 2Iref, which can reduce the static power consumption when no-load.

[0088] When the load is light, the gate voltage VPG of the power tube MP is large, and the sampling signal I1 of the load current is small. Since R2>R1, the voltage drop across the first sampling resistor R1 is smaller than the voltage drop across the second sampling resistor R2, the source voltage of the second PMOS tube PM2 is higher than the source voltage of the third PMOS tube PM3, the output current comparison signal VCP is low, and the third NMOS tube NM9 is cut off.

[0089] The error amplifier output voltage C33_MIN increases with the increase of the load current, the fifth NMOS tube NM11 works in the subthreshold region, the pull-down is enhanced, the output control signal NM11_D is low, and the gate voltage of the fourth NMOS tube NM10 is controlled to make the fourth NMOS tube NM10 work in the cut-off region. At this time, the selection signal PM4_D is high, and the first switch tube NM7 and the second switch tube NM8 in the current limiting loop are controlled to be turned on, so that the second bias current I3 and the fourth bias current I5 are simultaneously selected, and the fixed bias current is 6Iref at this time.

[0090] When the load current gradually increases, the source voltage of the second PMOS tube PM2 gradually decreases. When the source voltage of the second PMOS tube PM2 is lower than the source voltage of the third PMOS tube PM3, the output current comparison signal VCP flips to a high level and enters a fixed current limiting state. At this time, the output voltage feedback network 300 starts to work, the output signal VOUT decreases, the gate voltage of the fifth PMOS tube PM5 also decreases, the pull-down of the path where the fifth PMOS tube PM5 is located is enhanced, and the voltage of the selection signal PM4_D is pulled down, closing the branch where the second bias current I3 and the fourth bias current I5 are located. At this time, the magnitude of the bias current changes from 6Iref to 2Iref, and the short-circuit current limiting value becomes 1 / 3 of the fixed current limiting value.

[0091] Since the current comparison signal VCP is at a high level, the voltage of the second-stage common source amplifier module 200 of the error amplifier is raised, thereby raising the gate voltage VPG of the power tube MP. Since the current limiting loop is a closed-loop negative feedback loop, the gate voltage VPG of the power tube MP is finally clamped at a fixed potential, so that the power tube MP outputs a constant load current and performs foldback current limiting.

[0092] The advantages or beneficial effects of adopting the above technical solution are: the present invention detects the change of the load current of the power tube and adjusts the gate voltage of the power tube to achieve the limitation of the output power, especially reducing the static power consumption when the circuit is unloaded or lightly loaded, and adjusting the gate voltage of the power tube in the case of short circuit or overload to achieve constant load current output, and gradually reduces the output current by using the output voltage feedback mechanism, clamps the gate voltage of the power tube at a safe level, realizes the return current limiting protection function, and reduces the power consumption of the chip under heavy load; the circuit has the advantages of simple structure, small chip area, low static power consumption, and low power consumption when the circuit is short-circuited or overloaded, and is suitable for scenarios with low power supply voltage.

[0093] The above are only preferred embodiments of the present invention, and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the contents of this specification and illustrations should be included in the protection scope of the present invention.

Claims

1. A foldback current limiting protection circuit, characterized in that: include: A current comparison network, used for comparing a first current flowing through a first sampling resistor and a second current flowing through a second sampling resistor, and generating a current comparison signal; wherein the first current is the sum of a sampling signal of a load current sampled from a power tube, a first bias current, and a second bias current selected by a selection signal, the second current is the sum of a third bias current and a fourth bias current selected by the selection signal, and the resistance value of the second sampling resistor is different from the resistance value of the first sampling resistor; A common-source amplifier module is connected between the error amplifier output signal and the ground terminal. The control terminal of the common-source amplifier module switches the on-off state under the control of the current comparison signal and the low signal selected by the control signal. The output terminal of the common-source amplifier module is connected to the gate drive module of the power tube; an output signal feedback network is used to generate the selection signal according to the input signal, the output signal, and the error amplifier output signal, and to generate the control signal according to the error amplifier output signal.

2. The foldback current limiting protection circuit according to claim 1, characterized in that: The resistance of the second sampling resistor is greater than the resistance of the first sampling resistor.

3. The foldback current limiting protection circuit according to claim 1, characterized in that: The first bias current accounts for one third of the sum of the first bias current and the second bias current; and / or the second bias current accounts for two thirds of the sum of the first bias current and the second bias current; and / or the third bias current accounts for one third of the sum of the third bias current and the fourth bias current; And / or the fourth bias current accounts for two thirds of the sum of the third bias current and the fourth bias current.

4. The foldback current limiting protection circuit according to claim 1, characterized in that: The first bias current is twice the reference current; and / or the second bias current is four times the reference current; and / or the third bias current is twice the reference current; And / or the fourth bias current is 4 times the reference current.

5. The foldback current limiting protection circuit according to claim 1, characterized in that: The sampling signal is generated by a current detection circuit, which includes: a first PMOS tube, a gate of the first PMOS tube is connected to the gate of the power tube, a source of the first PMOS tube is connected to the input signal through the first sampling resistor, and a drain of the first PMOS tube is used to output the output signal.

6. The foldback current limiting protection circuit according to claim 1, characterized in that: The current comparison network includes: a second PMOS tube, the source of which is connected to the input signal through the first sampling resistor; a first NMOS tube, the gate of which is connected to the second bias voltage, the drain of which is connected to the gate and drain of the second PMOS tube, and the source of which is connected to the first bias current; a third PMOS tube, the gate of which is connected to the gate of the second PMOS tube, the source of which is connected to the input signal through the second sampling resistor, and the current comparison signal is output from the drain of the third PMOS tube; and a second NMOS tube, the gate of which is connected to the second bias voltage, the drain of which is connected to the drain of the third PMOS tube, and the source of which is connected to the third bias current.

7. The foldback current limiting protection circuit according to claim 1, characterized in that: Also includes: A first switch tube, wherein a control end of the first switch tube is connected to the selection signal, an input end of the first switch tube is connected to the first sampling resistor, and an output end of the first switch tube is connected to the second bias current through a first resistor; A second switch tube, wherein a control end of the second switch tube is connected to the selection signal, an input end of the second switch tube is connected to the second sampling resistor, and an output end of the second switch tube is connected to the fourth bias current through a second resistor.

8. The foldback current limiting protection circuit according to claim 1, characterized in that: The common-source amplification module includes: a third NMOS tube, the gate of the third NMOS tube is connected to the current comparison signal, the drain of the third NMOS tube is connected to the error amplifier output signal, and the source of the third NMOS tube is connected to the ground terminal; a fourth NMOS tube, the gate of the fourth NMOS tube is connected to the control signal, the drain of the fourth NMOS tube is connected to the current comparison signal, and the source of the fourth NMOS tube is connected to the ground terminal.

9. The foldback current limiting protection circuit according to claim 1, characterized in that: The output signal feedback network includes: a fourth PMOS tube, a gate of the fourth PMOS tube is connected to a first bias voltage, a source of the fourth PMOS tube is connected to the input signal, and a drain of the fourth PMOS tube outputs the selection signal; a fifth PMOS tube, a gate of the fifth PMOS tube is connected to the output signal through a third resistor and to the ground terminal through a first capacitor, a source of the fifth PMOS tube is connected to the selection signal, and a drain of the fifth PMOS tube is connected to the ground terminal through a fourth resistor; a fifth NMOS tube, a gate of the fifth NMOS tube is connected to the error amplifier output signal, a drain of the fifth NMOS tube is connected to a fifth bias current, a source of the fifth NMOS tube is connected to the ground terminal, and the control signal is output from the drain of the fifth NMOS tube; a sixth NMOS tube, a gate of the sixth NMOS tube is connected to the control signal, a source of the sixth NMOS tube is connected to the ground terminal, and a drain of the sixth NMOS tube is connected to the selection signal.

10. A low voltage dropout linear regulator, characterized in that: It includes the foldback current limiting protection circuit as described in any one of claims 1 to 9, and also includes: a power tube, used to generate an output signal lower than the input signal; an error amplifier, the input end of the error amplifier is respectively connected to a reference signal and a feedback signal of the output signal, and the output end of the error amplifier is connected to the error amplifier output signal; a gate drive module, the input end of the gate drive module is connected to the output end of the error amplifier, and the output end of the gate drive module is connected to the gate of the power tube.

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